drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v13_0.h"
  35 #include "smu13_driver_if_v13_0_0.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "smu_v13_0_0_ppt.h"
  39 #include "smu_v13_0_0_pptable.h"
  40 #include "smu_v13_0_0_ppsmc.h"
  41 #include "nbio/nbio_4_3_0_offset.h"
  42 #include "nbio/nbio_4_3_0_sh_mask.h"
  43 #include "mp/mp_13_0_0_offset.h"
  44 #include "mp/mp_13_0_0_sh_mask.h"
  45
  46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
  47 #include "smu_cmn.h"
  48 #include "amdgpu_ras.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define FEATURE_MASK(feature) (1ULL << feature)
  63 #define SMC_DPM_FEATURE ( \
  64         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  65         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  66         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  67         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  68         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  70
  71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE   0x4000
  72
  73 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
  74 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
  75
  76 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
  77 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
  78
  79 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
  80 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
  81
  82 #define mmMP1_SMN_C2PMSG_75                                                                            0x028b
  83 #define mmMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
  84
  85 #define mmMP1_SMN_C2PMSG_53                                                                            0x0275
  86 #define mmMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
  87
  88 #define mmMP1_SMN_C2PMSG_54                                                                            0x0276
  89 #define mmMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
  90
  91 #define DEBUGSMC_MSG_Mode1Reset 2
  92
  93 /*
  94  * SMU_v13_0_10 supports ECCTABLE since version 80.34.0,
  95  * use this to check ECCTABLE feature whether support
  96  */
  97 #define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION 0x00502200
  98
  99 #define PP_OD_FEATURE_GFXCLK_FMIN                       0
 100 #define PP_OD_FEATURE_GFXCLK_FMAX                       1
 101 #define PP_OD_FEATURE_UCLK_FMIN                         2
 102 #define PP_OD_FEATURE_UCLK_FMAX                         3
 103 #define PP_OD_FEATURE_GFX_VF_CURVE                      4
 104 #define PP_OD_FEATURE_FAN_CURVE_TEMP                    5
 105 #define PP_OD_FEATURE_FAN_CURVE_PWM                     6
 106 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT                7
 107 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET               8
 108 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE            9
 109 #define PP_OD_FEATURE_FAN_MINIMUM_PWM                   10
 110
 111 #define LINK_SPEED_MAX                                  3
 112
 113 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
 114         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
 115         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
 116         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
 117         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
 118         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
 119         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
 120         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
 121         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 122         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 123         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 124         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 125         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 126         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 127         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 128         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 129         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 130         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 131         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 132         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 133         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 134         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 135         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 136         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 137         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 138         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 139         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 140         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 141         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 142         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 143         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 144         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 145         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 146         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 147         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 148         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 149         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 150         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 151         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 152         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,      0),
 153         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,       0),
 154         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,          0),
 155         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 156         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 157         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 158         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 159         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 160         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 161         MSG_MAP(Mode2Reset,                     PPSMC_MSG_Mode2Reset,                      0),
 162         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         0),
 163         MSG_MAP(DFCstateControl,                PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
 164         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 165         MSG_MAP(SetNumBadMemoryPagesRetired,    PPSMC_MSG_SetNumBadMemoryPagesRetired,   0),
 166         MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
 167                             PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,   0),
 168         MSG_MAP(AllowGpo,                       PPSMC_MSG_SetGpoAllow,           0),
 169         MSG_MAP(AllowIHHostInterrupt,           PPSMC_MSG_AllowIHHostInterrupt,       0),
 170         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 171         MSG_MAP(DALNotPresent,          PPSMC_MSG_DALNotPresent,       0),
 172 };
 173
 174 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
 175         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 176         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 177         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 178         CLK_MAP(FCLK,           PPCLK_FCLK),
 179         CLK_MAP(UCLK,           PPCLK_UCLK),
 180         CLK_MAP(MCLK,           PPCLK_UCLK),
 181         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 182         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 183         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 184         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 185         CLK_MAP(DCEFCLK,        PPCLK_DCFCLK),
 186 };
 187
 188 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
 189         FEA_MAP(FW_DATA_READ),
 190         FEA_MAP(DPM_GFXCLK),
 191         FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
 192         FEA_MAP(DPM_UCLK),
 193         FEA_MAP(DPM_FCLK),
 194         FEA_MAP(DPM_SOCCLK),
 195         FEA_MAP(DPM_MP0CLK),
 196         FEA_MAP(DPM_LINK),
 197         FEA_MAP(DPM_DCN),
 198         FEA_MAP(VMEMP_SCALING),
 199         FEA_MAP(VDDIO_MEM_SCALING),
 200         FEA_MAP(DS_GFXCLK),
 201         FEA_MAP(DS_SOCCLK),
 202         FEA_MAP(DS_FCLK),
 203         FEA_MAP(DS_LCLK),
 204         FEA_MAP(DS_DCFCLK),
 205         FEA_MAP(DS_UCLK),
 206         FEA_MAP(GFX_ULV),
 207         FEA_MAP(FW_DSTATE),
 208         FEA_MAP(GFXOFF),
 209         FEA_MAP(BACO),
 210         FEA_MAP(MM_DPM),
 211         FEA_MAP(SOC_MPCLK_DS),
 212         FEA_MAP(BACO_MPCLK_DS),
 213         FEA_MAP(THROTTLERS),
 214         FEA_MAP(SMARTSHIFT),
 215         FEA_MAP(GTHR),
 216         FEA_MAP(ACDC),
 217         FEA_MAP(VR0HOT),
 218         FEA_MAP(FW_CTF),
 219         FEA_MAP(FAN_CONTROL),
 220         FEA_MAP(GFX_DCS),
 221         FEA_MAP(GFX_READ_MARGIN),
 222         FEA_MAP(LED_DISPLAY),
 223         FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
 224         FEA_MAP(OUT_OF_BAND_MONITOR),
 225         FEA_MAP(OPTIMIZED_VMIN),
 226         FEA_MAP(GFX_IMU),
 227         FEA_MAP(BOOT_TIME_CAL),
 228         FEA_MAP(GFX_PCC_DFLL),
 229         FEA_MAP(SOC_CG),
 230         FEA_MAP(DF_CSTATE),
 231         FEA_MAP(GFX_EDC),
 232         FEA_MAP(BOOT_POWER_OPT),
 233         FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
 234         FEA_MAP(DS_VCN),
 235         FEA_MAP(BACO_CG),
 236         FEA_MAP(MEM_TEMP_READ),
 237         FEA_MAP(ATHUB_MMHUB_PG),
 238         FEA_MAP(SOC_PCC),
 239         [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 240         [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 241         [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
 242 };
 243
 244 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
 245         TAB_MAP(PPTABLE),
 246         TAB_MAP(WATERMARKS),
 247         TAB_MAP(AVFS_PSM_DEBUG),
 248         TAB_MAP(PMSTATUSLOG),
 249         TAB_MAP(SMU_METRICS),
 250         TAB_MAP(DRIVER_SMU_CONFIG),
 251         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 252         [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
 253         TAB_MAP(I2C_COMMANDS),
 254         TAB_MAP(ECCINFO),
 255         TAB_MAP(OVERDRIVE),
 256 };
 257
 258 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 259         PWR_MAP(AC),
 260         PWR_MAP(DC),
 261 };
 262
 263 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 264         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 265         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 266         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 267         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 268         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 269         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 270         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 271         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D,             WORKLOAD_PPLIB_WINDOW_3D_BIT),
 272 };
 273
 274 static const uint8_t smu_v13_0_0_throttler_map[] = {
 275         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 276         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 277         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 278         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 279         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 280         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 281         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 282         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 283         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 284         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 285         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 286         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 287         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 288         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 289         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 290         [THROTTLER_GFX_APCC_PLUS_BIT]   = (SMU_THROTTLER_APCC_BIT),
 291         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 292 };
 293
 294 static int
 295 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
 296                                   uint32_t *feature_mask, uint32_t num)
 297 {
 298         struct amdgpu_device *adev = smu->adev;
 299
 300         if (num > 2)
 301                 return -EINVAL;
 302
 303         memset(feature_mask, 0xff, sizeof(uint32_t) * num);
 304
 305         if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
 306                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 307                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
 308         }
 309
 310         if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
 311             !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
 312                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
 313
 314         if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
 315                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 316
 317         /* PMFW 78.58 contains a critical fix for gfxoff feature */
 318         if ((smu->smc_fw_version < 0x004e3a00) ||
 319              !(adev->pm.pp_feature & PP_GFXOFF_MASK))
 320                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
 321
 322         if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
 323                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
 324                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
 325                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
 326         }
 327
 328         if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
 329                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 330
 331         if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
 332                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 333                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 334         }
 335
 336         if (!(adev->pm.pp_feature & PP_ULV_MASK))
 337                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 338
 339         return 0;
 340 }
 341
 342 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
 343 {
 344         struct smu_table_context *table_context = &smu->smu_table;
 345         struct smu_13_0_0_powerplay_table *powerplay_table =
 346                 table_context->power_play_table;
 347         struct smu_baco_context *smu_baco = &smu->smu_baco;
 348         PPTable_t *pptable = smu->smu_table.driver_pptable;
 349         const OverDriveLimits_t * const overdrive_upperlimits =
 350                                 &pptable->SkuTable.OverDriveLimitsBasicMax;
 351         const OverDriveLimits_t * const overdrive_lowerlimits =
 352                                 &pptable->SkuTable.OverDriveLimitsMin;
 353
 354         if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
 355                 smu->dc_controlled_by_gpio = true;
 356
 357         if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) {
 358                 smu_baco->platform_support = true;
 359
 360                 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
 361                         smu_baco->maco_support = true;
 362         }
 363
 364         if (!overdrive_lowerlimits->FeatureCtrlMask ||
 365             !overdrive_upperlimits->FeatureCtrlMask)
 366                 smu->od_enabled = false;
 367
 368         table_context->thermal_controller_type =
 369                 powerplay_table->thermal_controller_type;
 370
 371         /*
 372          * Instead of having its own buffer space and get overdrive_table copied,
 373          * smu->od_settings just points to the actual overdrive_table
 374          */
 375         smu->od_settings = &powerplay_table->overdrive_table;
 376
 377         smu->adev->pm.no_fan =
 378                 !(pptable->SkuTable.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
 379
 380         return 0;
 381 }
 382
 383 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
 384 {
 385         struct smu_table_context *table_context = &smu->smu_table;
 386         struct smu_13_0_0_powerplay_table *powerplay_table =
 387                 table_context->power_play_table;
 388
 389         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 390                sizeof(PPTable_t));
 391
 392         return 0;
 393 }
 394
 395 #ifndef atom_smc_dpm_info_table_13_0_0
 396 struct atom_smc_dpm_info_table_13_0_0 {
 397         struct atom_common_table_header table_header;
 398         BoardTable_t BoardTable;
 399 };
 400 #endif
 401
 402 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
 403 {
 404         struct smu_table_context *table_context = &smu->smu_table;
 405         PPTable_t *smc_pptable = table_context->driver_pptable;
 406         struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
 407         BoardTable_t *BoardTable = &smc_pptable->BoardTable;
 408         int index, ret;
 409
 410         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 411                                             smc_dpm_info);
 412
 413         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 414                                              (uint8_t **)&smc_dpm_table);
 415         if (ret)
 416                 return ret;
 417
 418         memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
 419
 420         return 0;
 421 }
 422
 423 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu,
 424                                              void **table,
 425                                              uint32_t *size)
 426 {
 427         struct smu_table_context *smu_table = &smu->smu_table;
 428         void *combo_pptable = smu_table->combo_pptable;
 429         int ret = 0;
 430
 431         ret = smu_cmn_get_combo_pptable(smu);
 432         if (ret)
 433                 return ret;
 434
 435         *table = combo_pptable;
 436         *size = sizeof(struct smu_13_0_0_powerplay_table);
 437
 438         return 0;
 439 }
 440
 441 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
 442 {
 443         struct smu_table_context *smu_table = &smu->smu_table;
 444         struct amdgpu_device *adev = smu->adev;
 445         int ret = 0;
 446
 447         if (amdgpu_sriov_vf(smu->adev))
 448                 return 0;
 449
 450         ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
 451                                                 &smu_table->power_play_table,
 452                                                 &smu_table->power_play_table_size);
 453         if (ret)
 454                 return ret;
 455
 456         ret = smu_v13_0_0_store_powerplay_table(smu);
 457         if (ret)
 458                 return ret;
 459
 460         /*
 461          * With SCPM enabled, the operation below will be handled
 462          * by PSP. Driver involvment is unnecessary and useless.
 463          */
 464         if (!adev->scpm_enabled) {
 465                 ret = smu_v13_0_0_append_powerplay_table(smu);
 466                 if (ret)
 467                         return ret;
 468         }
 469
 470         ret = smu_v13_0_0_check_powerplay_table(smu);
 471         if (ret)
 472                 return ret;
 473
 474         return ret;
 475 }
 476
 477 static int smu_v13_0_0_tables_init(struct smu_context *smu)
 478 {
 479         struct smu_table_context *smu_table = &smu->smu_table;
 480         struct smu_table *tables = smu_table->tables;
 481
 482         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 483                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 484         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 485                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 486         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 487                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 488         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 489                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 490         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
 491                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 492         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 493                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 494         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 495                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 496                        AMDGPU_GEM_DOMAIN_VRAM);
 497         SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
 498                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 499         SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
 500                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 501
 502         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 503         if (!smu_table->metrics_table)
 504                 goto err0_out;
 505         smu_table->metrics_time = 0;
 506
 507         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 508         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 509         if (!smu_table->gpu_metrics_table)
 510                 goto err1_out;
 511
 512         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 513         if (!smu_table->watermarks_table)
 514                 goto err2_out;
 515
 516         smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
 517         if (!smu_table->ecc_table)
 518                 goto err3_out;
 519
 520         return 0;
 521
 522 err3_out:
 523         kfree(smu_table->watermarks_table);
 524 err2_out:
 525         kfree(smu_table->gpu_metrics_table);
 526 err1_out:
 527         kfree(smu_table->metrics_table);
 528 err0_out:
 529         return -ENOMEM;
 530 }
 531
 532 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
 533 {
 534         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 535
 536         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 537                                        GFP_KERNEL);
 538         if (!smu_dpm->dpm_context)
 539                 return -ENOMEM;
 540
 541         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 542
 543         return 0;
 544 }
 545
 546 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
 547 {
 548         int ret = 0;
 549
 550         ret = smu_v13_0_0_tables_init(smu);
 551         if (ret)
 552                 return ret;
 553
 554         ret = smu_v13_0_0_allocate_dpm_context(smu);
 555         if (ret)
 556                 return ret;
 557
 558         return smu_v13_0_init_smc_tables(smu);
 559 }
 560
 561 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
 562 {
 563         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 564         struct smu_table_context *table_context = &smu->smu_table;
 565         PPTable_t *pptable = table_context->driver_pptable;
 566         SkuTable_t *skutable = &pptable->SkuTable;
 567         struct smu_13_0_dpm_table *dpm_table;
 568         struct smu_13_0_pcie_table *pcie_table;
 569         uint32_t link_level;
 570         int ret = 0;
 571
 572         /* socclk dpm table setup */
 573         dpm_table = &dpm_context->dpm_tables.soc_table;
 574         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 575                 ret = smu_v13_0_set_single_dpm_table(smu,
 576                                                      SMU_SOCCLK,
 577                                                      dpm_table);
 578                 if (ret)
 579                         return ret;
 580         } else {
 581                 dpm_table->count = 1;
 582                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 583                 dpm_table->dpm_levels[0].enabled = true;
 584                 dpm_table->min = dpm_table->dpm_levels[0].value;
 585                 dpm_table->max = dpm_table->dpm_levels[0].value;
 586         }
 587
 588         /* gfxclk dpm table setup */
 589         dpm_table = &dpm_context->dpm_tables.gfx_table;
 590         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 591                 ret = smu_v13_0_set_single_dpm_table(smu,
 592                                                      SMU_GFXCLK,
 593                                                      dpm_table);
 594                 if (ret)
 595                         return ret;
 596
 597                 /*
 598                  * Update the reported maximum shader clock to the value
 599                  * which can be guarded to be achieved on all cards. This
 600                  * is aligned with Window setting. And considering that value
 601                  * might be not the peak frequency the card can achieve, it
 602                  * is normal some real-time clock frequency can overtake this
 603                  * labelled maximum clock frequency(for example in pp_dpm_sclk
 604                  * sysfs output).
 605                  */
 606                 if (skutable->DriverReportedClocks.GameClockAc &&
 607                     (dpm_table->dpm_levels[dpm_table->count - 1].value >
 608                     skutable->DriverReportedClocks.GameClockAc)) {
 609                         dpm_table->dpm_levels[dpm_table->count - 1].value =
 610                                 skutable->DriverReportedClocks.GameClockAc;
 611                         dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
 612                 }
 613         } else {
 614                 dpm_table->count = 1;
 615                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 616                 dpm_table->dpm_levels[0].enabled = true;
 617                 dpm_table->min = dpm_table->dpm_levels[0].value;
 618                 dpm_table->max = dpm_table->dpm_levels[0].value;
 619         }
 620
 621         /* uclk dpm table setup */
 622         dpm_table = &dpm_context->dpm_tables.uclk_table;
 623         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 624                 ret = smu_v13_0_set_single_dpm_table(smu,
 625                                                      SMU_UCLK,
 626                                                      dpm_table);
 627                 if (ret)
 628                         return ret;
 629         } else {
 630                 dpm_table->count = 1;
 631                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 632                 dpm_table->dpm_levels[0].enabled = true;
 633                 dpm_table->min = dpm_table->dpm_levels[0].value;
 634                 dpm_table->max = dpm_table->dpm_levels[0].value;
 635         }
 636
 637         /* fclk dpm table setup */
 638         dpm_table = &dpm_context->dpm_tables.fclk_table;
 639         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 640                 ret = smu_v13_0_set_single_dpm_table(smu,
 641                                                      SMU_FCLK,
 642                                                      dpm_table);
 643                 if (ret)
 644                         return ret;
 645         } else {
 646                 dpm_table->count = 1;
 647                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 648                 dpm_table->dpm_levels[0].enabled = true;
 649                 dpm_table->min = dpm_table->dpm_levels[0].value;
 650                 dpm_table->max = dpm_table->dpm_levels[0].value;
 651         }
 652
 653         /* vclk dpm table setup */
 654         dpm_table = &dpm_context->dpm_tables.vclk_table;
 655         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
 656                 ret = smu_v13_0_set_single_dpm_table(smu,
 657                                                      SMU_VCLK,
 658                                                      dpm_table);
 659                 if (ret)
 660                         return ret;
 661         } else {
 662                 dpm_table->count = 1;
 663                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 664                 dpm_table->dpm_levels[0].enabled = true;
 665                 dpm_table->min = dpm_table->dpm_levels[0].value;
 666                 dpm_table->max = dpm_table->dpm_levels[0].value;
 667         }
 668
 669         /* dclk dpm table setup */
 670         dpm_table = &dpm_context->dpm_tables.dclk_table;
 671         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
 672                 ret = smu_v13_0_set_single_dpm_table(smu,
 673                                                      SMU_DCLK,
 674                                                      dpm_table);
 675                 if (ret)
 676                         return ret;
 677         } else {
 678                 dpm_table->count = 1;
 679                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 680                 dpm_table->dpm_levels[0].enabled = true;
 681                 dpm_table->min = dpm_table->dpm_levels[0].value;
 682                 dpm_table->max = dpm_table->dpm_levels[0].value;
 683         }
 684
 685         /* lclk dpm table setup */
 686         pcie_table = &dpm_context->dpm_tables.pcie_table;
 687         pcie_table->num_of_link_levels = 0;
 688         for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
 689                 if (!skutable->PcieGenSpeed[link_level] &&
 690                     !skutable->PcieLaneCount[link_level] &&
 691                     !skutable->LclkFreq[link_level])
 692                         continue;
 693
 694                 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
 695                                         skutable->PcieGenSpeed[link_level];
 696                 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
 697                                         skutable->PcieLaneCount[link_level];
 698                 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
 699                                         skutable->LclkFreq[link_level];
 700                 pcie_table->num_of_link_levels++;
 701         }
 702
 703         /* dcefclk dpm table setup */
 704         dpm_table = &dpm_context->dpm_tables.dcef_table;
 705         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
 706                 ret = smu_v13_0_set_single_dpm_table(smu,
 707                                                      SMU_DCEFCLK,
 708                                                      dpm_table);
 709                 if (ret)
 710                         return ret;
 711         } else {
 712                 dpm_table->count = 1;
 713                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 714                 dpm_table->dpm_levels[0].enabled = true;
 715                 dpm_table->min = dpm_table->dpm_levels[0].value;
 716                 dpm_table->max = dpm_table->dpm_levels[0].value;
 717         }
 718
 719         return 0;
 720 }
 721
 722 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
 723 {
 724         int ret = 0;
 725         uint64_t feature_enabled;
 726
 727         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 728         if (ret)
 729                 return false;
 730
 731         return !!(feature_enabled & SMC_DPM_FEATURE);
 732 }
 733
 734 static void smu_v13_0_0_dump_pptable(struct smu_context *smu)
 735 {
 736        struct smu_table_context *table_context = &smu->smu_table;
 737        PPTable_t *pptable = table_context->driver_pptable;
 738        SkuTable_t *skutable = &pptable->SkuTable;
 739
 740        dev_info(smu->adev->dev, "Dumped PPTable:\n");
 741
 742        dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
 743        dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
 744        dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
 745 }
 746
 747 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
 748                                                   bool en)
 749 {
 750         return smu_v13_0_system_features_control(smu, en);
 751 }
 752
 753 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
 754 {
 755         uint32_t throttler_status = 0;
 756         int i;
 757
 758         for (i = 0; i < THROTTLER_COUNT; i++)
 759                 throttler_status |=
 760                         (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
 761
 762         return throttler_status;
 763 }
 764
 765 #define SMU_13_0_0_BUSY_THRESHOLD       15
 766 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
 767                                             MetricsMember_t member,
 768                                             uint32_t *value)
 769 {
 770         struct smu_table_context *smu_table = &smu->smu_table;
 771         SmuMetrics_t *metrics =
 772                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 773         int ret = 0;
 774
 775         ret = smu_cmn_get_metrics_table(smu,
 776                                         NULL,
 777                                         false);
 778         if (ret)
 779                 return ret;
 780
 781         switch (member) {
 782         case METRICS_CURR_GFXCLK:
 783                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 784                 break;
 785         case METRICS_CURR_SOCCLK:
 786                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 787                 break;
 788         case METRICS_CURR_UCLK:
 789                 *value = metrics->CurrClock[PPCLK_UCLK];
 790                 break;
 791         case METRICS_CURR_VCLK:
 792                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 793                 break;
 794         case METRICS_CURR_VCLK1:
 795                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 796                 break;
 797         case METRICS_CURR_DCLK:
 798                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 799                 break;
 800         case METRICS_CURR_DCLK1:
 801                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 802                 break;
 803         case METRICS_CURR_FCLK:
 804                 *value = metrics->CurrClock[PPCLK_FCLK];
 805                 break;
 806         case METRICS_CURR_DCEFCLK:
 807                 *value = metrics->CurrClock[PPCLK_DCFCLK];
 808                 break;
 809         case METRICS_AVERAGE_GFXCLK:
 810                 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
 811                         *value = metrics->AverageGfxclkFrequencyPostDs;
 812                 else
 813                         *value = metrics->AverageGfxclkFrequencyPreDs;
 814                 break;
 815         case METRICS_AVERAGE_FCLK:
 816                 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
 817                         *value = metrics->AverageFclkFrequencyPostDs;
 818                 else
 819                         *value = metrics->AverageFclkFrequencyPreDs;
 820                 break;
 821         case METRICS_AVERAGE_UCLK:
 822                 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
 823                         *value = metrics->AverageMemclkFrequencyPostDs;
 824                 else
 825                         *value = metrics->AverageMemclkFrequencyPreDs;
 826                 break;
 827         case METRICS_AVERAGE_VCLK:
 828                 *value = metrics->AverageVclk0Frequency;
 829                 break;
 830         case METRICS_AVERAGE_DCLK:
 831                 *value = metrics->AverageDclk0Frequency;
 832                 break;
 833         case METRICS_AVERAGE_VCLK1:
 834                 *value = metrics->AverageVclk1Frequency;
 835                 break;
 836         case METRICS_AVERAGE_DCLK1:
 837                 *value = metrics->AverageDclk1Frequency;
 838                 break;
 839         case METRICS_AVERAGE_GFXACTIVITY:
 840                 *value = metrics->AverageGfxActivity;
 841                 break;
 842         case METRICS_AVERAGE_MEMACTIVITY:
 843                 *value = metrics->AverageUclkActivity;
 844                 break;
 845         case METRICS_AVERAGE_SOCKETPOWER:
 846                 *value = metrics->AverageSocketPower << 8;
 847                 break;
 848         case METRICS_TEMPERATURE_EDGE:
 849                 *value = metrics->AvgTemperature[TEMP_EDGE] *
 850                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 851                 break;
 852         case METRICS_TEMPERATURE_HOTSPOT:
 853                 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
 854                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 855                 break;
 856         case METRICS_TEMPERATURE_MEM:
 857                 *value = metrics->AvgTemperature[TEMP_MEM] *
 858                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 859                 break;
 860         case METRICS_TEMPERATURE_VRGFX:
 861                 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
 862                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 863                 break;
 864         case METRICS_TEMPERATURE_VRSOC:
 865                 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
 866                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 867                 break;
 868         case METRICS_THROTTLER_STATUS:
 869                 *value = smu_v13_0_get_throttler_status(metrics);
 870                 break;
 871         case METRICS_CURR_FANSPEED:
 872                 *value = metrics->AvgFanRpm;
 873                 break;
 874         case METRICS_CURR_FANPWM:
 875                 *value = metrics->AvgFanPwm;
 876                 break;
 877         case METRICS_VOLTAGE_VDDGFX:
 878                 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
 879                 break;
 880         case METRICS_PCIE_RATE:
 881                 *value = metrics->PcieRate;
 882                 break;
 883         case METRICS_PCIE_WIDTH:
 884                 *value = metrics->PcieWidth;
 885                 break;
 886         default:
 887                 *value = UINT_MAX;
 888                 break;
 889         }
 890
 891         return ret;
 892 }
 893
 894 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
 895                                              enum smu_clk_type clk_type,
 896                                              uint32_t *min,
 897                                              uint32_t *max)
 898 {
 899         struct smu_13_0_dpm_context *dpm_context =
 900                 smu->smu_dpm.dpm_context;
 901         struct smu_13_0_dpm_table *dpm_table;
 902
 903         switch (clk_type) {
 904         case SMU_MCLK:
 905         case SMU_UCLK:
 906                 /* uclk dpm table */
 907                 dpm_table = &dpm_context->dpm_tables.uclk_table;
 908                 break;
 909         case SMU_GFXCLK:
 910         case SMU_SCLK:
 911                 /* gfxclk dpm table */
 912                 dpm_table = &dpm_context->dpm_tables.gfx_table;
 913                 break;
 914         case SMU_SOCCLK:
 915                 /* socclk dpm table */
 916                 dpm_table = &dpm_context->dpm_tables.soc_table;
 917                 break;
 918         case SMU_FCLK:
 919                 /* fclk dpm table */
 920                 dpm_table = &dpm_context->dpm_tables.fclk_table;
 921                 break;
 922         case SMU_VCLK:
 923         case SMU_VCLK1:
 924                 /* vclk dpm table */
 925                 dpm_table = &dpm_context->dpm_tables.vclk_table;
 926                 break;
 927         case SMU_DCLK:
 928         case SMU_DCLK1:
 929                 /* dclk dpm table */
 930                 dpm_table = &dpm_context->dpm_tables.dclk_table;
 931                 break;
 932         default:
 933                 dev_err(smu->adev->dev, "Unsupported clock type!\n");
 934                 return -EINVAL;
 935         }
 936
 937         if (min)
 938                 *min = dpm_table->min;
 939         if (max)
 940                 *max = dpm_table->max;
 941
 942         return 0;
 943 }
 944
 945 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
 946                                    enum amd_pp_sensors sensor,
 947                                    void *data,
 948                                    uint32_t *size)
 949 {
 950         struct smu_table_context *table_context = &smu->smu_table;
 951         PPTable_t *smc_pptable = table_context->driver_pptable;
 952         int ret = 0;
 953
 954         switch (sensor) {
 955         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 956                 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
 957                 *size = 4;
 958                 break;
 959         case AMDGPU_PP_SENSOR_MEM_LOAD:
 960                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 961                                                        METRICS_AVERAGE_MEMACTIVITY,
 962                                                        (uint32_t *)data);
 963                 *size = 4;
 964                 break;
 965         case AMDGPU_PP_SENSOR_GPU_LOAD:
 966                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 967                                                        METRICS_AVERAGE_GFXACTIVITY,
 968                                                        (uint32_t *)data);
 969                 *size = 4;
 970                 break;
 971         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
 972                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 973                                                        METRICS_AVERAGE_SOCKETPOWER,
 974                                                        (uint32_t *)data);
 975                 *size = 4;
 976                 break;
 977         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 978                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 979                                                        METRICS_TEMPERATURE_HOTSPOT,
 980                                                        (uint32_t *)data);
 981                 *size = 4;
 982                 break;
 983         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 984                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 985                                                        METRICS_TEMPERATURE_EDGE,
 986                                                        (uint32_t *)data);
 987                 *size = 4;
 988                 break;
 989         case AMDGPU_PP_SENSOR_MEM_TEMP:
 990                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 991                                                        METRICS_TEMPERATURE_MEM,
 992                                                        (uint32_t *)data);
 993                 *size = 4;
 994                 break;
 995         case AMDGPU_PP_SENSOR_GFX_MCLK:
 996                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
 997                                                        METRICS_CURR_UCLK,
 998                                                        (uint32_t *)data);
 999                 *(uint32_t *)data *= 100;
1000                 *size = 4;
1001                 break;
1002         case AMDGPU_PP_SENSOR_GFX_SCLK:
1003                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1004                                                        METRICS_AVERAGE_GFXCLK,
1005                                                        (uint32_t *)data);
1006                 *(uint32_t *)data *= 100;
1007                 *size = 4;
1008                 break;
1009         case AMDGPU_PP_SENSOR_VDDGFX:
1010                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1011                                                        METRICS_VOLTAGE_VDDGFX,
1012                                                        (uint32_t *)data);
1013                 *size = 4;
1014                 break;
1015         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1016         default:
1017                 ret = -EOPNOTSUPP;
1018                 break;
1019         }
1020
1021         return ret;
1022 }
1023
1024 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
1025                                                      enum smu_clk_type clk_type,
1026                                                      uint32_t *value)
1027 {
1028         MetricsMember_t member_type;
1029         int clk_id = 0;
1030
1031         clk_id = smu_cmn_to_asic_specific_index(smu,
1032                                                 CMN2ASIC_MAPPING_CLK,
1033                                                 clk_type);
1034         if (clk_id < 0)
1035                 return -EINVAL;
1036
1037         switch (clk_id) {
1038         case PPCLK_GFXCLK:
1039                 member_type = METRICS_AVERAGE_GFXCLK;
1040                 break;
1041         case PPCLK_UCLK:
1042                 member_type = METRICS_CURR_UCLK;
1043                 break;
1044         case PPCLK_FCLK:
1045                 member_type = METRICS_CURR_FCLK;
1046                 break;
1047         case PPCLK_SOCCLK:
1048                 member_type = METRICS_CURR_SOCCLK;
1049                 break;
1050         case PPCLK_VCLK_0:
1051                 member_type = METRICS_AVERAGE_VCLK;
1052                 break;
1053         case PPCLK_DCLK_0:
1054                 member_type = METRICS_AVERAGE_DCLK;
1055                 break;
1056         case PPCLK_VCLK_1:
1057                 member_type = METRICS_AVERAGE_VCLK1;
1058                 break;
1059         case PPCLK_DCLK_1:
1060                 member_type = METRICS_AVERAGE_DCLK1;
1061                 break;
1062         case PPCLK_DCFCLK:
1063                 member_type = METRICS_CURR_DCEFCLK;
1064                 break;
1065         default:
1066                 return -EINVAL;
1067         }
1068
1069         return smu_v13_0_0_get_smu_metrics_data(smu,
1070                                                 member_type,
1071                                                 value);
1072 }
1073
1074 static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
1075                                                 int od_feature_bit)
1076 {
1077         PPTable_t *pptable = smu->smu_table.driver_pptable;
1078         const OverDriveLimits_t * const overdrive_upperlimits =
1079                                 &pptable->SkuTable.OverDriveLimitsBasicMax;
1080
1081         return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1082 }
1083
1084 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
1085                                               int od_feature_bit,
1086                                               int32_t *min,
1087                                               int32_t *max)
1088 {
1089         PPTable_t *pptable = smu->smu_table.driver_pptable;
1090         const OverDriveLimits_t * const overdrive_upperlimits =
1091                                 &pptable->SkuTable.OverDriveLimitsBasicMax;
1092         const OverDriveLimits_t * const overdrive_lowerlimits =
1093                                 &pptable->SkuTable.OverDriveLimitsMin;
1094         int32_t od_min_setting, od_max_setting;
1095
1096         switch (od_feature_bit) {
1097         case PP_OD_FEATURE_GFXCLK_FMIN:
1098                 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1099                 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1100                 break;
1101         case PP_OD_FEATURE_GFXCLK_FMAX:
1102                 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1103                 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1104                 break;
1105         case PP_OD_FEATURE_UCLK_FMIN:
1106                 od_min_setting = overdrive_lowerlimits->UclkFmin;
1107                 od_max_setting = overdrive_upperlimits->UclkFmin;
1108                 break;
1109         case PP_OD_FEATURE_UCLK_FMAX:
1110                 od_min_setting = overdrive_lowerlimits->UclkFmax;
1111                 od_max_setting = overdrive_upperlimits->UclkFmax;
1112                 break;
1113         case PP_OD_FEATURE_GFX_VF_CURVE:
1114                 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1115                 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1116                 break;
1117         case PP_OD_FEATURE_FAN_CURVE_TEMP:
1118                 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1119                 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1120                 break;
1121         case PP_OD_FEATURE_FAN_CURVE_PWM:
1122                 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1123                 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1124                 break;
1125         case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1126                 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1127                 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1128                 break;
1129         case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1130                 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1131                 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1132                 break;
1133         case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1134                 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1135                 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1136                 break;
1137         case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1138                 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1139                 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1140                 break;
1141         default:
1142                 od_min_setting = od_max_setting = INT_MAX;
1143                 break;
1144         }
1145
1146         if (min)
1147                 *min = od_min_setting;
1148         if (max)
1149                 *max = od_max_setting;
1150 }
1151
1152 static void smu_v13_0_0_dump_od_table(struct smu_context *smu,
1153                                       OverDriveTableExternal_t *od_table)
1154 {
1155         struct amdgpu_device *adev = smu->adev;
1156
1157         dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1158                                                      od_table->OverDriveTable.GfxclkFmax);
1159         dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1160                                                    od_table->OverDriveTable.UclkFmax);
1161 }
1162
1163 static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu,
1164                                            OverDriveTableExternal_t *od_table)
1165 {
1166         int ret = 0;
1167
1168         ret = smu_cmn_update_table(smu,
1169                                    SMU_TABLE_OVERDRIVE,
1170                                    0,
1171                                    (void *)od_table,
1172                                    false);
1173         if (ret)
1174                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1175
1176         return ret;
1177 }
1178
1179 static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
1180                                               OverDriveTableExternal_t *od_table)
1181 {
1182         int ret = 0;
1183
1184         ret = smu_cmn_update_table(smu,
1185                                    SMU_TABLE_OVERDRIVE,
1186                                    0,
1187                                    (void *)od_table,
1188                                    true);
1189         if (ret)
1190                 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1191
1192         return ret;
1193 }
1194
1195 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
1196                                         enum smu_clk_type clk_type,
1197                                         char *buf)
1198 {
1199         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1200         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1201         OverDriveTableExternal_t *od_table =
1202                 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1203         struct smu_13_0_dpm_table *single_dpm_table;
1204         struct smu_13_0_pcie_table *pcie_table;
1205         uint32_t gen_speed, lane_width;
1206         int i, curr_freq, size = 0;
1207         int32_t min_value, max_value;
1208         int ret = 0;
1209
1210         smu_cmn_get_sysfs_buf(&buf, &size);
1211
1212         if (amdgpu_ras_intr_triggered()) {
1213                 size += sysfs_emit_at(buf, size, "unavailable\n");
1214                 return size;
1215         }
1216
1217         switch (clk_type) {
1218         case SMU_SCLK:
1219                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1220                 break;
1221         case SMU_MCLK:
1222                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1223                 break;
1224         case SMU_SOCCLK:
1225                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1226                 break;
1227         case SMU_FCLK:
1228                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1229                 break;
1230         case SMU_VCLK:
1231         case SMU_VCLK1:
1232                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1233                 break;
1234         case SMU_DCLK:
1235         case SMU_DCLK1:
1236                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1237                 break;
1238         case SMU_DCEFCLK:
1239                 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1240                 break;
1241         default:
1242                 break;
1243         }
1244
1245         switch (clk_type) {
1246         case SMU_SCLK:
1247         case SMU_MCLK:
1248         case SMU_SOCCLK:
1249         case SMU_FCLK:
1250         case SMU_VCLK:
1251         case SMU_VCLK1:
1252         case SMU_DCLK:
1253         case SMU_DCLK1:
1254         case SMU_DCEFCLK:
1255                 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1256                 if (ret) {
1257                         dev_err(smu->adev->dev, "Failed to get current clock freq!");
1258                         return ret;
1259                 }
1260
1261                 if (single_dpm_table->is_fine_grained) {
1262                         /*
1263                          * For fine grained dpms, there are only two dpm levels:
1264                          *   - level 0 -> min clock freq
1265                          *   - level 1 -> max clock freq
1266                          * And the current clock frequency can be any value between them.
1267                          * So, if the current clock frequency is not at level 0 or level 1,
1268                          * we will fake it as three dpm levels:
1269                          *   - level 0 -> min clock freq
1270                          *   - level 1 -> current actual clock freq
1271                          *   - level 2 -> max clock freq
1272                          */
1273                         if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1274                              (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1275                                 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1276                                                 single_dpm_table->dpm_levels[0].value);
1277                                 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1278                                                 curr_freq);
1279                                 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1280                                                 single_dpm_table->dpm_levels[1].value);
1281                         } else {
1282                                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1283                                                 single_dpm_table->dpm_levels[0].value,
1284                                                 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1285                                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1286                                                 single_dpm_table->dpm_levels[1].value,
1287                                                 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1288                         }
1289                 } else {
1290                         for (i = 0; i < single_dpm_table->count; i++)
1291                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1292                                                 i, single_dpm_table->dpm_levels[i].value,
1293                                                 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1294                 }
1295                 break;
1296         case SMU_PCIE:
1297                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1298                                                        METRICS_PCIE_RATE,
1299                                                        &gen_speed);
1300                 if (ret)
1301                         return ret;
1302
1303                 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1304                                                        METRICS_PCIE_WIDTH,
1305                                                        &lane_width);
1306                 if (ret)
1307                         return ret;
1308
1309                 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1310                 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1311                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1312                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1313                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1314                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1315                                         (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1316                                         (pcie_table->pcie_lane[i] == 1) ? "x1" :
1317                                         (pcie_table->pcie_lane[i] == 2) ? "x2" :
1318                                         (pcie_table->pcie_lane[i] == 3) ? "x4" :
1319                                         (pcie_table->pcie_lane[i] == 4) ? "x8" :
1320                                         (pcie_table->pcie_lane[i] == 5) ? "x12" :
1321                                         (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1322                                         pcie_table->clk_freq[i],
1323                                         (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1324                                         (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1325                                         "*" : "");
1326                 break;
1327
1328         case SMU_OD_SCLK:
1329                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1330                                                          PP_OD_FEATURE_GFXCLK_BIT))
1331                         break;
1332
1333                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1334                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1335                                         od_table->OverDriveTable.GfxclkFmin,
1336                                         od_table->OverDriveTable.GfxclkFmax);
1337                 break;
1338
1339         case SMU_OD_MCLK:
1340                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1341                                                          PP_OD_FEATURE_UCLK_BIT))
1342                         break;
1343
1344                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1345                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1346                                         od_table->OverDriveTable.UclkFmin,
1347                                         od_table->OverDriveTable.UclkFmax);
1348                 break;
1349
1350         case SMU_OD_VDDGFX_OFFSET:
1351                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1352                                                          PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1353                         break;
1354
1355                 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1356                 size += sysfs_emit_at(buf, size, "%dmV\n",
1357                                       od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1358                 break;
1359
1360         case SMU_OD_FAN_CURVE:
1361                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1362                                                          PP_OD_FEATURE_FAN_CURVE_BIT))
1363                         break;
1364
1365                 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1366                 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1367                         size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1368                                                 i,
1369                                                 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1370                                                 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1371
1372                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1373                 smu_v13_0_0_get_od_setting_limits(smu,
1374                                                   PP_OD_FEATURE_FAN_CURVE_TEMP,
1375                                                   &min_value,
1376                                                   &max_value);
1377                 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1378                                       min_value, max_value);
1379
1380                 smu_v13_0_0_get_od_setting_limits(smu,
1381                                                   PP_OD_FEATURE_FAN_CURVE_PWM,
1382                                                   &min_value,
1383                                                   &max_value);
1384                 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1385                                       min_value, max_value);
1386
1387                 break;
1388
1389         case SMU_OD_ACOUSTIC_LIMIT:
1390                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1391                                                          PP_OD_FEATURE_FAN_CURVE_BIT))
1392                         break;
1393
1394                 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1395                 size += sysfs_emit_at(buf, size, "%d\n",
1396                                         (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1397
1398                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1399                 smu_v13_0_0_get_od_setting_limits(smu,
1400                                                   PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1401                                                   &min_value,
1402                                                   &max_value);
1403                 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1404                                       min_value, max_value);
1405                 break;
1406
1407         case SMU_OD_ACOUSTIC_TARGET:
1408                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1409                                                          PP_OD_FEATURE_FAN_CURVE_BIT))
1410                         break;
1411
1412                 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1413                 size += sysfs_emit_at(buf, size, "%d\n",
1414                                         (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1415
1416                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1417                 smu_v13_0_0_get_od_setting_limits(smu,
1418                                                   PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1419                                                   &min_value,
1420                                                   &max_value);
1421                 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1422                                       min_value, max_value);
1423                 break;
1424
1425         case SMU_OD_FAN_TARGET_TEMPERATURE:
1426                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1427                                                          PP_OD_FEATURE_FAN_CURVE_BIT))
1428                         break;
1429
1430                 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1431                 size += sysfs_emit_at(buf, size, "%d\n",
1432                                         (int)od_table->OverDriveTable.FanTargetTemperature);
1433
1434                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1435                 smu_v13_0_0_get_od_setting_limits(smu,
1436                                                   PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1437                                                   &min_value,
1438                                                   &max_value);
1439                 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1440                                       min_value, max_value);
1441                 break;
1442
1443         case SMU_OD_FAN_MINIMUM_PWM:
1444                 if (!smu_v13_0_0_is_od_feature_supported(smu,
1445                                                          PP_OD_FEATURE_FAN_CURVE_BIT))
1446                         break;
1447
1448                 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1449                 size += sysfs_emit_at(buf, size, "%d\n",
1450                                         (int)od_table->OverDriveTable.FanMinimumPwm);
1451
1452                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1453                 smu_v13_0_0_get_od_setting_limits(smu,
1454                                                   PP_OD_FEATURE_FAN_MINIMUM_PWM,
1455                                                   &min_value,
1456                                                   &max_value);
1457                 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1458                                       min_value, max_value);
1459                 break;
1460
1461         case SMU_OD_RANGE:
1462                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1463                     !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1464                     !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1465                         break;
1466
1467                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1468
1469                 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1470                         smu_v13_0_0_get_od_setting_limits(smu,
1471                                                           PP_OD_FEATURE_GFXCLK_FMIN,
1472                                                           &min_value,
1473                                                           NULL);
1474                         smu_v13_0_0_get_od_setting_limits(smu,
1475                                                           PP_OD_FEATURE_GFXCLK_FMAX,
1476                                                           NULL,
1477                                                           &max_value);
1478                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1479                                               min_value, max_value);
1480                 }
1481
1482                 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1483                         smu_v13_0_0_get_od_setting_limits(smu,
1484                                                           PP_OD_FEATURE_UCLK_FMIN,
1485                                                           &min_value,
1486                                                           NULL);
1487                         smu_v13_0_0_get_od_setting_limits(smu,
1488                                                           PP_OD_FEATURE_UCLK_FMAX,
1489                                                           NULL,
1490                                                           &max_value);
1491                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1492                                               min_value, max_value);
1493                 }
1494
1495                 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1496                         smu_v13_0_0_get_od_setting_limits(smu,
1497                                                           PP_OD_FEATURE_GFX_VF_CURVE,
1498                                                           &min_value,
1499                                                           &max_value);
1500                         size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1501                                               min_value, max_value);
1502                 }
1503                 break;
1504
1505         default:
1506                 break;
1507         }
1508
1509         return size;
1510 }
1511
1512
1513 static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input)
1514 {
1515         struct smu_table_context *table_context = &smu->smu_table;
1516         OverDriveTableExternal_t *boot_overdrive_table =
1517                 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1518         OverDriveTableExternal_t *od_table =
1519                 (OverDriveTableExternal_t *)table_context->overdrive_table;
1520         struct amdgpu_device *adev = smu->adev;
1521         int i;
1522
1523         switch (input) {
1524         case PP_OD_EDIT_FAN_CURVE:
1525                 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1526                         od_table->OverDriveTable.FanLinearTempPoints[i] =
1527                                         boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1528                         od_table->OverDriveTable.FanLinearPwmPoints[i] =
1529                                         boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1530                 }
1531                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1532                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1533                 break;
1534         case PP_OD_EDIT_ACOUSTIC_LIMIT:
1535                 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1536                                         boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1537                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1538                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1539                 break;
1540         case PP_OD_EDIT_ACOUSTIC_TARGET:
1541                 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1542                                         boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1543                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1544                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1545                 break;
1546         case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1547                 od_table->OverDriveTable.FanTargetTemperature =
1548                                         boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1549                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1550                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1551                 break;
1552         case PP_OD_EDIT_FAN_MINIMUM_PWM:
1553                 od_table->OverDriveTable.FanMinimumPwm =
1554                                         boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1555                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1556                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1557                 break;
1558         default:
1559                 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1560                 return -EINVAL;
1561         }
1562
1563         return 0;
1564 }
1565
1566 static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu,
1567                                          enum PP_OD_DPM_TABLE_COMMAND type,
1568                                          long input[],
1569                                          uint32_t size)
1570 {
1571         struct smu_table_context *table_context = &smu->smu_table;
1572         OverDriveTableExternal_t *od_table =
1573                 (OverDriveTableExternal_t *)table_context->overdrive_table;
1574         struct amdgpu_device *adev = smu->adev;
1575         uint32_t offset_of_voltageoffset;
1576         int32_t minimum, maximum;
1577         uint32_t feature_ctrlmask;
1578         int i, ret = 0;
1579
1580         switch (type) {
1581         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1582                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1583                         dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1584                         return -ENOTSUPP;
1585                 }
1586
1587                 for (i = 0; i < size; i += 2) {
1588                         if (i + 2 > size) {
1589                                 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1590                                 return -EINVAL;
1591                         }
1592
1593                         switch (input[i]) {
1594                         case 0:
1595                                 smu_v13_0_0_get_od_setting_limits(smu,
1596                                                                   PP_OD_FEATURE_GFXCLK_FMIN,
1597                                                                   &minimum,
1598                                                                   &maximum);
1599                                 if (input[i + 1] < minimum ||
1600                                     input[i + 1] > maximum) {
1601                                         dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1602                                                 input[i + 1], minimum, maximum);
1603                                         return -EINVAL;
1604                                 }
1605
1606                                 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1607                                 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1608                                 break;
1609
1610                         case 1:
1611                                 smu_v13_0_0_get_od_setting_limits(smu,
1612                                                                   PP_OD_FEATURE_GFXCLK_FMAX,
1613                                                                   &minimum,
1614                                                                   &maximum);
1615                                 if (input[i + 1] < minimum ||
1616                                     input[i + 1] > maximum) {
1617                                         dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1618                                                 input[i + 1], minimum, maximum);
1619                                         return -EINVAL;
1620                                 }
1621
1622                                 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1623                                 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1624                                 break;
1625
1626                         default:
1627                                 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1628                                 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1629                                 return -EINVAL;
1630                         }
1631                 }
1632
1633                 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1634                         dev_err(adev->dev,
1635                                 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1636                                 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1637                                 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1638                         return -EINVAL;
1639                 }
1640                 break;
1641
1642         case PP_OD_EDIT_MCLK_VDDC_TABLE:
1643                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1644                         dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1645                         return -ENOTSUPP;
1646                 }
1647
1648                 for (i = 0; i < size; i += 2) {
1649                         if (i + 2 > size) {
1650                                 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1651                                 return -EINVAL;
1652                         }
1653
1654                         switch (input[i]) {
1655                         case 0:
1656                                 smu_v13_0_0_get_od_setting_limits(smu,
1657                                                                   PP_OD_FEATURE_UCLK_FMIN,
1658                                                                   &minimum,
1659                                                                   &maximum);
1660                                 if (input[i + 1] < minimum ||
1661                                     input[i + 1] > maximum) {
1662                                         dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1663                                                 input[i + 1], minimum, maximum);
1664                                         return -EINVAL;
1665                                 }
1666
1667                                 od_table->OverDriveTable.UclkFmin = input[i + 1];
1668                                 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1669                                 break;
1670
1671                         case 1:
1672                                 smu_v13_0_0_get_od_setting_limits(smu,
1673                                                                   PP_OD_FEATURE_UCLK_FMAX,
1674                                                                   &minimum,
1675                                                                   &maximum);
1676                                 if (input[i + 1] < minimum ||
1677                                     input[i + 1] > maximum) {
1678                                         dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1679                                                 input[i + 1], minimum, maximum);
1680                                         return -EINVAL;
1681                                 }
1682
1683                                 od_table->OverDriveTable.UclkFmax = input[i + 1];
1684                                 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1685                                 break;
1686
1687                         default:
1688                                 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1689                                 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1690                                 return -EINVAL;
1691                         }
1692                 }
1693
1694                 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1695                         dev_err(adev->dev,
1696                                 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1697                                 (uint32_t)od_table->OverDriveTable.UclkFmin,
1698                                 (uint32_t)od_table->OverDriveTable.UclkFmax);
1699                         return -EINVAL;
1700                 }
1701                 break;
1702
1703         case PP_OD_EDIT_VDDGFX_OFFSET:
1704                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1705                         dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1706                         return -ENOTSUPP;
1707                 }
1708
1709                 smu_v13_0_0_get_od_setting_limits(smu,
1710                                                   PP_OD_FEATURE_GFX_VF_CURVE,
1711                                                   &minimum,
1712                                                   &maximum);
1713                 if (input[0] < minimum ||
1714                     input[0] > maximum) {
1715                         dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1716                                  input[0], minimum, maximum);
1717                         return -EINVAL;
1718                 }
1719
1720                 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1721                         od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1722                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1723                 break;
1724
1725         case PP_OD_EDIT_FAN_CURVE:
1726                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1727                         dev_warn(adev->dev, "Fan curve setting not supported!\n");
1728                         return -ENOTSUPP;
1729                 }
1730
1731                 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1732                     input[0] < 0)
1733                         return -EINVAL;
1734
1735                 smu_v13_0_0_get_od_setting_limits(smu,
1736                                                   PP_OD_FEATURE_FAN_CURVE_TEMP,
1737                                                   &minimum,
1738                                                   &maximum);
1739                 if (input[1] < minimum ||
1740                     input[1] > maximum) {
1741                         dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1742                                  input[1], minimum, maximum);
1743                         return -EINVAL;
1744                 }
1745
1746                 smu_v13_0_0_get_od_setting_limits(smu,
1747                                                   PP_OD_FEATURE_FAN_CURVE_PWM,
1748                                                   &minimum,
1749                                                   &maximum);
1750                 if (input[2] < minimum ||
1751                     input[2] > maximum) {
1752                         dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1753                                  input[2], minimum, maximum);
1754                         return -EINVAL;
1755                 }
1756
1757                 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1758                 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1759                 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1760                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1761                 break;
1762
1763         case PP_OD_EDIT_ACOUSTIC_LIMIT:
1764                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1765                         dev_warn(adev->dev, "Fan curve setting not supported!\n");
1766                         return -ENOTSUPP;
1767                 }
1768
1769                 smu_v13_0_0_get_od_setting_limits(smu,
1770                                                   PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1771                                                   &minimum,
1772                                                   &maximum);
1773                 if (input[0] < minimum ||
1774                     input[0] > maximum) {
1775                         dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1776                                  input[0], minimum, maximum);
1777                         return -EINVAL;
1778                 }
1779
1780                 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1781                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1782                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1783                 break;
1784
1785         case PP_OD_EDIT_ACOUSTIC_TARGET:
1786                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1787                         dev_warn(adev->dev, "Fan curve setting not supported!\n");
1788                         return -ENOTSUPP;
1789                 }
1790
1791                 smu_v13_0_0_get_od_setting_limits(smu,
1792                                                   PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1793                                                   &minimum,
1794                                                   &maximum);
1795                 if (input[0] < minimum ||
1796                     input[0] > maximum) {
1797                         dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1798                                  input[0], minimum, maximum);
1799                         return -EINVAL;
1800                 }
1801
1802                 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1803                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1804                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1805                 break;
1806
1807         case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1808                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1809                         dev_warn(adev->dev, "Fan curve setting not supported!\n");
1810                         return -ENOTSUPP;
1811                 }
1812
1813                 smu_v13_0_0_get_od_setting_limits(smu,
1814                                                   PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1815                                                   &minimum,
1816                                                   &maximum);
1817                 if (input[0] < minimum ||
1818                     input[0] > maximum) {
1819                         dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1820                                  input[0], minimum, maximum);
1821                         return -EINVAL;
1822                 }
1823
1824                 od_table->OverDriveTable.FanTargetTemperature = input[0];
1825                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1826                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1827                 break;
1828
1829         case PP_OD_EDIT_FAN_MINIMUM_PWM:
1830                 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1831                         dev_warn(adev->dev, "Fan curve setting not supported!\n");
1832                         return -ENOTSUPP;
1833                 }
1834
1835                 smu_v13_0_0_get_od_setting_limits(smu,
1836                                                   PP_OD_FEATURE_FAN_MINIMUM_PWM,
1837                                                   &minimum,
1838                                                   &maximum);
1839                 if (input[0] < minimum ||
1840                     input[0] > maximum) {
1841                         dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1842                                  input[0], minimum, maximum);
1843                         return -EINVAL;
1844                 }
1845
1846                 od_table->OverDriveTable.FanMinimumPwm = input[0];
1847                 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1848                 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1849                 break;
1850
1851         case PP_OD_RESTORE_DEFAULT_TABLE:
1852                 if (size == 1) {
1853                         ret = smu_v13_0_0_od_restore_table_single(smu, input[0]);
1854                         if (ret)
1855                                 return ret;
1856                 } else {
1857                         feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1858                         memcpy(od_table,
1859                        table_context->boot_overdrive_table,
1860                        sizeof(OverDriveTableExternal_t));
1861                         od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1862                 }
1863                 fallthrough;
1864         case PP_OD_COMMIT_DPM_TABLE:
1865                 /*
1866                  * The member below instructs PMFW the settings focused in
1867                  * this single operation.
1868                  * `uint32_t FeatureCtrlMask;`
1869                  * It does not contain actual informations about user's custom
1870                  * settings. Thus we do not cache it.
1871                  */
1872                 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1873                 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1874                            table_context->user_overdrive_table + offset_of_voltageoffset,
1875                            sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1876                         smu_v13_0_0_dump_od_table(smu, od_table);
1877
1878                         ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
1879                         if (ret) {
1880                                 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1881                                 return ret;
1882                         }
1883
1884                         od_table->OverDriveTable.FeatureCtrlMask = 0;
1885                         memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1886                                (u8 *)od_table + offset_of_voltageoffset,
1887                                sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1888
1889                         if (!memcmp(table_context->user_overdrive_table,
1890                                     table_context->boot_overdrive_table,
1891                                     sizeof(OverDriveTableExternal_t)))
1892                                 smu->user_dpm_profile.user_od = false;
1893                         else
1894                                 smu->user_dpm_profile.user_od = true;
1895                 }
1896                 break;
1897
1898         default:
1899                 return -ENOSYS;
1900         }
1901
1902         return ret;
1903 }
1904
1905 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1906                                         enum smu_clk_type clk_type,
1907                                         uint32_t mask)
1908 {
1909         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1910         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1911         struct smu_13_0_dpm_table *single_dpm_table;
1912         uint32_t soft_min_level, soft_max_level;
1913         uint32_t min_freq, max_freq;
1914         int ret = 0;
1915
1916         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1917         soft_max_level = mask ? (fls(mask) - 1) : 0;
1918
1919         switch (clk_type) {
1920         case SMU_GFXCLK:
1921         case SMU_SCLK:
1922                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1923                 break;
1924         case SMU_MCLK:
1925         case SMU_UCLK:
1926                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1927                 break;
1928         case SMU_SOCCLK:
1929                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1930                 break;
1931         case SMU_FCLK:
1932                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1933                 break;
1934         case SMU_VCLK:
1935         case SMU_VCLK1:
1936                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1937                 break;
1938         case SMU_DCLK:
1939         case SMU_DCLK1:
1940                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1941                 break;
1942         default:
1943                 break;
1944         }
1945
1946         switch (clk_type) {
1947         case SMU_GFXCLK:
1948         case SMU_SCLK:
1949         case SMU_MCLK:
1950         case SMU_UCLK:
1951         case SMU_SOCCLK:
1952         case SMU_FCLK:
1953         case SMU_VCLK:
1954         case SMU_VCLK1:
1955         case SMU_DCLK:
1956         case SMU_DCLK1:
1957                 if (single_dpm_table->is_fine_grained) {
1958                         /* There is only 2 levels for fine grained DPM */
1959                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1960                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1961                 } else {
1962                         if ((soft_max_level >= single_dpm_table->count) ||
1963                             (soft_min_level >= single_dpm_table->count))
1964                                 return -EINVAL;
1965                 }
1966
1967                 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1968                 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1969
1970                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1971                                                             clk_type,
1972                                                             min_freq,
1973                                                             max_freq);
1974                 break;
1975         case SMU_DCEFCLK:
1976         case SMU_PCIE:
1977         default:
1978                 break;
1979         }
1980
1981         return ret;
1982 }
1983
1984 static const struct smu_temperature_range smu13_thermal_policy[] = {
1985         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1986         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1987 };
1988
1989 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
1990                                                      struct smu_temperature_range *range)
1991 {
1992         struct smu_table_context *table_context = &smu->smu_table;
1993         struct smu_13_0_0_powerplay_table *powerplay_table =
1994                 table_context->power_play_table;
1995         PPTable_t *pptable = smu->smu_table.driver_pptable;
1996
1997         if (amdgpu_sriov_vf(smu->adev))
1998                 return 0;
1999
2000         if (!range)
2001                 return -EINVAL;
2002
2003         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2004
2005         range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2006                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2007         range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2008                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2009         range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2010                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2011         range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2012                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2013         range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2014                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2015         range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2016                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2017         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2018         range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2019
2020         return 0;
2021 }
2022
2023 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
2024                                            void **table)
2025 {
2026         struct smu_table_context *smu_table = &smu->smu_table;
2027         struct gpu_metrics_v1_3 *gpu_metrics =
2028                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2029         SmuMetricsExternal_t metrics_ext;
2030         SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2031         int ret = 0;
2032
2033         ret = smu_cmn_get_metrics_table(smu,
2034                                         &metrics_ext,
2035                                         true);
2036         if (ret)
2037                 return ret;
2038
2039         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2040
2041         gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2042         gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2043         gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2044         gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2045         gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2046         gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2047                                              metrics->AvgTemperature[TEMP_VR_MEM1]);
2048
2049         gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2050         gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2051         gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2052                                                metrics->Vcn1ActivityPercentage);
2053
2054         gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2055         gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2056
2057         if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2058                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2059         else
2060                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2061
2062         if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2063                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2064         else
2065                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2066
2067         gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2068         gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2069         gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2070         gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2071
2072         gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2073         gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2074         gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2075         gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2076         gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2077         gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2078         gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2079
2080         gpu_metrics->throttle_status =
2081                         smu_v13_0_get_throttler_status(metrics);
2082         gpu_metrics->indep_throttle_status =
2083                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2084                                                            smu_v13_0_0_throttler_map);
2085
2086         gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2087
2088         gpu_metrics->pcie_link_width = metrics->PcieWidth;
2089         if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2090                 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2091         else
2092                 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2093
2094         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2095
2096         gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2097         gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2098         gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2099
2100         *table = (void *)gpu_metrics;
2101
2102         return sizeof(struct gpu_metrics_v1_3);
2103 }
2104
2105 static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu)
2106 {
2107         struct amdgpu_device *adev = smu->adev;
2108
2109         if (smu_v13_0_0_is_od_feature_supported(smu,
2110                                                 PP_OD_FEATURE_FAN_CURVE_BIT))
2111                 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2112                                             OD_OPS_SUPPORT_FAN_CURVE_SET |
2113                                             OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2114                                             OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2115                                             OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2116                                             OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2117                                             OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2118                                             OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2119                                             OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2120                                             OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET;
2121 }
2122
2123 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu)
2124 {
2125         OverDriveTableExternal_t *od_table =
2126                 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2127         OverDriveTableExternal_t *boot_od_table =
2128                 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2129         OverDriveTableExternal_t *user_od_table =
2130                 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2131         OverDriveTableExternal_t user_od_table_bak;
2132         int ret = 0;
2133         int i;
2134
2135         ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table);
2136         if (ret)
2137                 return ret;
2138
2139         smu_v13_0_0_dump_od_table(smu, boot_od_table);
2140
2141         memcpy(od_table,
2142                boot_od_table,
2143                sizeof(OverDriveTableExternal_t));
2144
2145         /*
2146          * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2147          * but we have to preserve user defined values in "user_od_table".
2148          */
2149         if (!smu->adev->in_suspend) {
2150                 memcpy(user_od_table,
2151                        boot_od_table,
2152                        sizeof(OverDriveTableExternal_t));
2153                 smu->user_dpm_profile.user_od = false;
2154         } else if (smu->user_dpm_profile.user_od) {
2155                 memcpy(&user_od_table_bak,
2156                        user_od_table,
2157                        sizeof(OverDriveTableExternal_t));
2158                 memcpy(user_od_table,
2159                        boot_od_table,
2160                        sizeof(OverDriveTableExternal_t));
2161                 user_od_table->OverDriveTable.GfxclkFmin =
2162                                 user_od_table_bak.OverDriveTable.GfxclkFmin;
2163                 user_od_table->OverDriveTable.GfxclkFmax =
2164                                 user_od_table_bak.OverDriveTable.GfxclkFmax;
2165                 user_od_table->OverDriveTable.UclkFmin =
2166                                 user_od_table_bak.OverDriveTable.UclkFmin;
2167                 user_od_table->OverDriveTable.UclkFmax =
2168                                 user_od_table_bak.OverDriveTable.UclkFmax;
2169                 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2170                         user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2171                                 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2172                 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2173                         user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2174                                 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2175                         user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2176                                 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2177                 }
2178                 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2179                         user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2180                 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2181                         user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2182                 user_od_table->OverDriveTable.FanTargetTemperature =
2183                         user_od_table_bak.OverDriveTable.FanTargetTemperature;
2184                 user_od_table->OverDriveTable.FanMinimumPwm =
2185                         user_od_table_bak.OverDriveTable.FanMinimumPwm;
2186         }
2187
2188         smu_v13_0_0_set_supported_od_feature_mask(smu);
2189
2190         return 0;
2191 }
2192
2193 static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu)
2194 {
2195         struct smu_table_context *table_context = &smu->smu_table;
2196         OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2197         OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2198         int res;
2199
2200         user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2201                                                         BIT(PP_OD_FEATURE_UCLK_BIT) |
2202                                                         BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2203                                                         BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2204         res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table);
2205         user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2206         if (res == 0)
2207                 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2208
2209         return res;
2210 }
2211
2212 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
2213 {
2214         struct smu_13_0_dpm_context *dpm_context =
2215                                 smu->smu_dpm.dpm_context;
2216         struct smu_13_0_dpm_table *gfx_table =
2217                                 &dpm_context->dpm_tables.gfx_table;
2218         struct smu_13_0_dpm_table *mem_table =
2219                                 &dpm_context->dpm_tables.uclk_table;
2220         struct smu_13_0_dpm_table *soc_table =
2221                                 &dpm_context->dpm_tables.soc_table;
2222         struct smu_13_0_dpm_table *vclk_table =
2223                                 &dpm_context->dpm_tables.vclk_table;
2224         struct smu_13_0_dpm_table *dclk_table =
2225                                 &dpm_context->dpm_tables.dclk_table;
2226         struct smu_13_0_dpm_table *fclk_table =
2227                                 &dpm_context->dpm_tables.fclk_table;
2228         struct smu_umd_pstate_table *pstate_table =
2229                                 &smu->pstate_table;
2230         struct smu_table_context *table_context = &smu->smu_table;
2231         PPTable_t *pptable = table_context->driver_pptable;
2232         DriverReportedClocks_t driver_clocks =
2233                         pptable->SkuTable.DriverReportedClocks;
2234
2235         pstate_table->gfxclk_pstate.min = gfx_table->min;
2236         if (driver_clocks.GameClockAc &&
2237             (driver_clocks.GameClockAc < gfx_table->max))
2238                 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2239         else
2240                 pstate_table->gfxclk_pstate.peak = gfx_table->max;
2241
2242         pstate_table->uclk_pstate.min = mem_table->min;
2243         pstate_table->uclk_pstate.peak = mem_table->max;
2244
2245         pstate_table->socclk_pstate.min = soc_table->min;
2246         pstate_table->socclk_pstate.peak = soc_table->max;
2247
2248         pstate_table->vclk_pstate.min = vclk_table->min;
2249         pstate_table->vclk_pstate.peak = vclk_table->max;
2250
2251         pstate_table->dclk_pstate.min = dclk_table->min;
2252         pstate_table->dclk_pstate.peak = dclk_table->max;
2253
2254         pstate_table->fclk_pstate.min = fclk_table->min;
2255         pstate_table->fclk_pstate.peak = fclk_table->max;
2256
2257         if (driver_clocks.BaseClockAc &&
2258             driver_clocks.BaseClockAc < gfx_table->max)
2259                 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2260         else
2261                 pstate_table->gfxclk_pstate.standard = gfx_table->max;
2262         pstate_table->uclk_pstate.standard = mem_table->max;
2263         pstate_table->socclk_pstate.standard = soc_table->min;
2264         pstate_table->vclk_pstate.standard = vclk_table->min;
2265         pstate_table->dclk_pstate.standard = dclk_table->min;
2266         pstate_table->fclk_pstate.standard = fclk_table->min;
2267
2268         return 0;
2269 }
2270
2271 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
2272 {
2273         struct smu_table_context *smu_table = &smu->smu_table;
2274         SmuMetrics_t *metrics =
2275                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
2276         struct amdgpu_device *adev = smu->adev;
2277         uint32_t upper32 = 0, lower32 = 0;
2278         int ret;
2279
2280         ret = smu_cmn_get_metrics_table(smu, NULL, false);
2281         if (ret)
2282                 goto out;
2283
2284         upper32 = metrics->PublicSerialNumberUpper;
2285         lower32 = metrics->PublicSerialNumberLower;
2286
2287 out:
2288         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2289 }
2290
2291 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
2292                                          uint32_t *speed)
2293 {
2294         int ret;
2295
2296         if (!speed)
2297                 return -EINVAL;
2298
2299         ret = smu_v13_0_0_get_smu_metrics_data(smu,
2300                                                METRICS_CURR_FANPWM,
2301                                                speed);
2302         if (ret) {
2303                 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2304                 return ret;
2305         }
2306
2307         /* Convert the PMFW output which is in percent to pwm(255) based */
2308         *speed = min(*speed * 255 / 100, (uint32_t)255);
2309
2310         return 0;
2311 }
2312
2313 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
2314                                          uint32_t *speed)
2315 {
2316         if (!speed)
2317                 return -EINVAL;
2318
2319         return smu_v13_0_0_get_smu_metrics_data(smu,
2320                                                 METRICS_CURR_FANSPEED,
2321                                                 speed);
2322 }
2323
2324 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
2325 {
2326         struct smu_table_context *table_context = &smu->smu_table;
2327         PPTable_t *pptable = table_context->driver_pptable;
2328         SkuTable_t *skutable = &pptable->SkuTable;
2329
2330         /*
2331          * Skip the MGpuFanBoost setting for those ASICs
2332          * which do not support it
2333          */
2334         if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2335                 return 0;
2336
2337         return smu_cmn_send_smc_msg_with_param(smu,
2338                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2339                                                0,
2340                                                NULL);
2341 }
2342
2343 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
2344                                                 uint32_t *current_power_limit,
2345                                                 uint32_t *default_power_limit,
2346                                                 uint32_t *max_power_limit,
2347                                                 uint32_t *min_power_limit)
2348 {
2349         struct smu_table_context *table_context = &smu->smu_table;
2350         struct smu_13_0_0_powerplay_table *powerplay_table =
2351                 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
2352         PPTable_t *pptable = table_context->driver_pptable;
2353         SkuTable_t *skutable = &pptable->SkuTable;
2354         uint32_t power_limit, od_percent_upper, od_percent_lower;
2355
2356         if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2357                 power_limit = smu->adev->pm.ac_power ?
2358                               skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2359                               skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2360
2361         if (current_power_limit)
2362                 *current_power_limit = power_limit;
2363         if (default_power_limit)
2364                 *default_power_limit = power_limit;
2365
2366         if (smu->od_enabled) {
2367                 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2368                 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2369         } else {
2370                 od_percent_upper = 0;
2371                 od_percent_lower = 100;
2372         }
2373
2374         dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2375                                         od_percent_upper, od_percent_lower, power_limit);
2376
2377         if (max_power_limit) {
2378                 *max_power_limit = power_limit * (100 + od_percent_upper);
2379                 *max_power_limit /= 100;
2380         }
2381
2382         if (min_power_limit) {
2383                 *min_power_limit = power_limit * (100 - od_percent_lower);
2384                 *min_power_limit /= 100;
2385         }
2386
2387         return 0;
2388 }
2389
2390 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
2391                                               char *buf)
2392 {
2393         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2394         DpmActivityMonitorCoeffInt_t *activity_monitor =
2395                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2396         static const char *title[] = {
2397                         "PROFILE_INDEX(NAME)",
2398                         "CLOCK_TYPE(NAME)",
2399                         "FPS",
2400                         "MinActiveFreqType",
2401                         "MinActiveFreq",
2402                         "BoosterFreqType",
2403                         "BoosterFreq",
2404                         "PD_Data_limit_c",
2405                         "PD_Data_error_coeff",
2406                         "PD_Data_error_rate_coeff"};
2407         int16_t workload_type = 0;
2408         uint32_t i, size = 0;
2409         int result = 0;
2410
2411         if (!buf)
2412                 return -EINVAL;
2413
2414         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
2415                         title[0], title[1], title[2], title[3], title[4], title[5],
2416                         title[6], title[7], title[8], title[9]);
2417
2418         for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2419                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2420                 workload_type = smu_cmn_to_asic_specific_index(smu,
2421                                                                CMN2ASIC_MAPPING_WORKLOAD,
2422                                                                i);
2423                 if (workload_type == -ENOTSUPP)
2424                         continue;
2425                 else if (workload_type < 0)
2426                         return -EINVAL;
2427
2428                 result = smu_cmn_update_table(smu,
2429                                               SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2430                                               workload_type,
2431                                               (void *)(&activity_monitor_external),
2432                                               false);
2433                 if (result) {
2434                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2435                         return result;
2436                 }
2437
2438                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
2439                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
2440
2441                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2442                         " ",
2443                         0,
2444                         "GFXCLK",
2445                         activity_monitor->Gfx_FPS,
2446                         activity_monitor->Gfx_MinActiveFreqType,
2447                         activity_monitor->Gfx_MinActiveFreq,
2448                         activity_monitor->Gfx_BoosterFreqType,
2449                         activity_monitor->Gfx_BoosterFreq,
2450                         activity_monitor->Gfx_PD_Data_limit_c,
2451                         activity_monitor->Gfx_PD_Data_error_coeff,
2452                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
2453
2454                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2455                         " ",
2456                         1,
2457                         "FCLK",
2458                         activity_monitor->Fclk_FPS,
2459                         activity_monitor->Fclk_MinActiveFreqType,
2460                         activity_monitor->Fclk_MinActiveFreq,
2461                         activity_monitor->Fclk_BoosterFreqType,
2462                         activity_monitor->Fclk_BoosterFreq,
2463                         activity_monitor->Fclk_PD_Data_limit_c,
2464                         activity_monitor->Fclk_PD_Data_error_coeff,
2465                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
2466         }
2467
2468         return size;
2469 }
2470
2471 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
2472                                               long *input,
2473                                               uint32_t size)
2474 {
2475         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2476         DpmActivityMonitorCoeffInt_t *activity_monitor =
2477                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2478         int workload_type, ret = 0;
2479         u32 workload_mask;
2480
2481         smu->power_profile_mode = input[size];
2482
2483         if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
2484                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
2485                 return -EINVAL;
2486         }
2487
2488         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
2489                 ret = smu_cmn_update_table(smu,
2490                                            SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2491                                            WORKLOAD_PPLIB_CUSTOM_BIT,
2492                                            (void *)(&activity_monitor_external),
2493                                            false);
2494                 if (ret) {
2495                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2496                         return ret;
2497                 }
2498
2499                 switch (input[0]) {
2500                 case 0: /* Gfxclk */
2501                         activity_monitor->Gfx_FPS = input[1];
2502                         activity_monitor->Gfx_MinActiveFreqType = input[2];
2503                         activity_monitor->Gfx_MinActiveFreq = input[3];
2504                         activity_monitor->Gfx_BoosterFreqType = input[4];
2505                         activity_monitor->Gfx_BoosterFreq = input[5];
2506                         activity_monitor->Gfx_PD_Data_limit_c = input[6];
2507                         activity_monitor->Gfx_PD_Data_error_coeff = input[7];
2508                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8];
2509                         break;
2510                 case 1: /* Fclk */
2511                         activity_monitor->Fclk_FPS = input[1];
2512                         activity_monitor->Fclk_MinActiveFreqType = input[2];
2513                         activity_monitor->Fclk_MinActiveFreq = input[3];
2514                         activity_monitor->Fclk_BoosterFreqType = input[4];
2515                         activity_monitor->Fclk_BoosterFreq = input[5];
2516                         activity_monitor->Fclk_PD_Data_limit_c = input[6];
2517                         activity_monitor->Fclk_PD_Data_error_coeff = input[7];
2518                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8];
2519                         break;
2520                 }
2521
2522                 ret = smu_cmn_update_table(smu,
2523                                            SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2524                                            WORKLOAD_PPLIB_CUSTOM_BIT,
2525                                            (void *)(&activity_monitor_external),
2526                                            true);
2527                 if (ret) {
2528                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2529                         return ret;
2530                 }
2531         }
2532
2533         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2534         workload_type = smu_cmn_to_asic_specific_index(smu,
2535                                                        CMN2ASIC_MAPPING_WORKLOAD,
2536                                                        smu->power_profile_mode);
2537
2538         if (workload_type < 0)
2539                 return -EINVAL;
2540
2541         workload_mask = 1 << workload_type;
2542
2543         /* Add optimizations for SMU13.0.0.  Reuse the power saving profile */
2544         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &&
2545             (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) &&
2546             ((smu->adev->pm.fw_version == 0x004e6601) ||
2547              (smu->adev->pm.fw_version >= 0x004e7400))) {
2548                 workload_type = smu_cmn_to_asic_specific_index(smu,
2549                                                                CMN2ASIC_MAPPING_WORKLOAD,
2550                                                                PP_SMC_POWER_PROFILE_POWERSAVING);
2551                 if (workload_type >= 0)
2552                         workload_mask |= 1 << workload_type;
2553         }
2554
2555         return smu_cmn_send_smc_msg_with_param(smu,
2556                                                SMU_MSG_SetWorkloadMask,
2557                                                workload_mask,
2558                                                NULL);
2559 }
2560
2561 static int smu_v13_0_0_baco_enter(struct smu_context *smu)
2562 {
2563         struct smu_baco_context *smu_baco = &smu->smu_baco;
2564         struct amdgpu_device *adev = smu->adev;
2565
2566         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2567                 return smu_v13_0_baco_set_armd3_sequence(smu,
2568                                 (smu_baco->maco_support && amdgpu_runtime_pm != 1) ?
2569                                         BACO_SEQ_BAMACO : BACO_SEQ_BACO);
2570         else
2571                 return smu_v13_0_baco_enter(smu);
2572 }
2573
2574 static int smu_v13_0_0_baco_exit(struct smu_context *smu)
2575 {
2576         struct amdgpu_device *adev = smu->adev;
2577         int ret;
2578
2579         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2580                 /* Wait for PMFW handling for the Dstate change */
2581                 usleep_range(10000, 11000);
2582                 ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2583         } else {
2584                 ret = smu_v13_0_baco_exit(smu);
2585         }
2586
2587         if (!ret)
2588                 adev->gfx.is_poweron = false;
2589
2590         return ret;
2591 }
2592
2593 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
2594 {
2595         struct amdgpu_device *adev = smu->adev;
2596         u32 smu_version;
2597         int ret;
2598
2599         /* SRIOV does not support SMU mode1 reset */
2600         if (amdgpu_sriov_vf(adev))
2601                 return false;
2602
2603         /* PMFW support is available since 78.41 */
2604         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2605         if (ret)
2606                 return false;
2607
2608         if (smu_version < 0x004e2900)
2609                 return false;
2610
2611         return true;
2612 }
2613
2614 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
2615                                    struct i2c_msg *msg, int num_msgs)
2616 {
2617         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2618         struct amdgpu_device *adev = smu_i2c->adev;
2619         struct smu_context *smu = adev->powerplay.pp_handle;
2620         struct smu_table_context *smu_table = &smu->smu_table;
2621         struct smu_table *table = &smu_table->driver_table;
2622         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2623         int i, j, r, c;
2624         u16 dir;
2625
2626         if (!adev->pm.dpm_enabled)
2627                 return -EBUSY;
2628
2629         req = kzalloc(sizeof(*req), GFP_KERNEL);
2630         if (!req)
2631                 return -ENOMEM;
2632
2633         req->I2CcontrollerPort = smu_i2c->port;
2634         req->I2CSpeed = I2C_SPEED_FAST_400K;
2635         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2636         dir = msg[0].flags & I2C_M_RD;
2637
2638         for (c = i = 0; i < num_msgs; i++) {
2639                 for (j = 0; j < msg[i].len; j++, c++) {
2640                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2641
2642                         if (!(msg[i].flags & I2C_M_RD)) {
2643                                 /* write */
2644                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2645                                 cmd->ReadWriteData = msg[i].buf[j];
2646                         }
2647
2648                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
2649                                 /* The direction changes.
2650                                  */
2651                                 dir = msg[i].flags & I2C_M_RD;
2652                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2653                         }
2654
2655                         req->NumCmds++;
2656
2657                         /*
2658                          * Insert STOP if we are at the last byte of either last
2659                          * message for the transaction or the client explicitly
2660                          * requires a STOP at this particular message.
2661                          */
2662                         if ((j == msg[i].len - 1) &&
2663                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2664                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2665                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2666                         }
2667                 }
2668         }
2669         mutex_lock(&adev->pm.mutex);
2670         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2671         if (r)
2672                 goto fail;
2673
2674         for (c = i = 0; i < num_msgs; i++) {
2675                 if (!(msg[i].flags & I2C_M_RD)) {
2676                         c += msg[i].len;
2677                         continue;
2678                 }
2679                 for (j = 0; j < msg[i].len; j++, c++) {
2680                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2681
2682                         msg[i].buf[j] = cmd->ReadWriteData;
2683                 }
2684         }
2685         r = num_msgs;
2686 fail:
2687         mutex_unlock(&adev->pm.mutex);
2688         kfree(req);
2689         return r;
2690 }
2691
2692 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
2693 {
2694         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2695 }
2696
2697 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
2698         .master_xfer = smu_v13_0_0_i2c_xfer,
2699         .functionality = smu_v13_0_0_i2c_func,
2700 };
2701
2702 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
2703         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2704         .max_read_len  = MAX_SW_I2C_COMMANDS,
2705         .max_write_len = MAX_SW_I2C_COMMANDS,
2706         .max_comb_1st_msg_len = 2,
2707         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2708 };
2709
2710 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
2711 {
2712         struct amdgpu_device *adev = smu->adev;
2713         int res, i;
2714
2715         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2716                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2717                 struct i2c_adapter *control = &smu_i2c->adapter;
2718
2719                 smu_i2c->adev = adev;
2720                 smu_i2c->port = i;
2721                 mutex_init(&smu_i2c->mutex);
2722                 control->owner = THIS_MODULE;
2723                 control->class = I2C_CLASS_SPD;
2724                 control->dev.parent = &adev->pdev->dev;
2725                 control->algo = &smu_v13_0_0_i2c_algo;
2726                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2727                 control->quirks = &smu_v13_0_0_i2c_control_quirks;
2728                 i2c_set_adapdata(control, smu_i2c);
2729
2730                 res = i2c_add_adapter(control);
2731                 if (res) {
2732                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2733                         goto Out_err;
2734                 }
2735         }
2736
2737         /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2738         /* XXX ideally this would be something in a vbios data table */
2739         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2740         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2741
2742         return 0;
2743 Out_err:
2744         for ( ; i >= 0; i--) {
2745                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2746                 struct i2c_adapter *control = &smu_i2c->adapter;
2747
2748                 i2c_del_adapter(control);
2749         }
2750         return res;
2751 }
2752
2753 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
2754 {
2755         struct amdgpu_device *adev = smu->adev;
2756         int i;
2757
2758         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2759                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2760                 struct i2c_adapter *control = &smu_i2c->adapter;
2761
2762                 i2c_del_adapter(control);
2763         }
2764         adev->pm.ras_eeprom_i2c_bus = NULL;
2765         adev->pm.fru_eeprom_i2c_bus = NULL;
2766 }
2767
2768 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
2769                                      enum pp_mp1_state mp1_state)
2770 {
2771         int ret;
2772
2773         switch (mp1_state) {
2774         case PP_MP1_STATE_UNLOAD:
2775                 ret = smu_cmn_send_smc_msg_with_param(smu,
2776                                                                                           SMU_MSG_PrepareMp1ForUnload,
2777                                                                                           0x55, NULL);
2778
2779                 if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT)
2780                         ret = smu_v13_0_disable_pmfw_state(smu);
2781
2782                 break;
2783         default:
2784                 /* Ignore others */
2785                 ret = 0;
2786         }
2787
2788         return ret;
2789 }
2790
2791 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
2792                                      enum pp_df_cstate state)
2793 {
2794         return smu_cmn_send_smc_msg_with_param(smu,
2795                                                SMU_MSG_DFCstateControl,
2796                                                state,
2797                                                NULL);
2798 }
2799
2800 static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu,
2801                                                 uint32_t supported_version,
2802                                                 uint32_t *param)
2803 {
2804         struct amdgpu_device *adev = smu->adev;
2805         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2806
2807         if ((smu->smc_fw_version >= supported_version) &&
2808                         ras && atomic_read(&ras->in_recovery))
2809                 /* Set RAS fatal error reset flag */
2810                 *param = 1 << 16;
2811         else
2812                 *param = 0;
2813 }
2814
2815 static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
2816 {
2817         int ret;
2818         uint32_t param;
2819         struct amdgpu_device *adev = smu->adev;
2820
2821         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2822         case IP_VERSION(13, 0, 0):
2823                 /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */
2824                 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, &param);
2825
2826                 ret = smu_cmn_send_smc_msg_with_param(smu,
2827                                                 SMU_MSG_Mode1Reset, param, NULL);
2828                 break;
2829
2830         case IP_VERSION(13, 0, 10):
2831                 /* SMU 13_0_10 PMFW supports RAS fatal error reset from 80.28 */
2832                 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, &param);
2833
2834                 ret = smu_cmn_send_debug_smc_msg_with_param(smu,
2835                                                 DEBUGSMC_MSG_Mode1Reset, param);
2836                 break;
2837
2838         default:
2839                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2840                 break;
2841         }
2842
2843         if (!ret)
2844                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2845
2846         return ret;
2847 }
2848
2849 static int smu_v13_0_0_mode2_reset(struct smu_context *smu)
2850 {
2851         int ret;
2852         struct amdgpu_device *adev = smu->adev;
2853
2854         if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2855                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL);
2856         else
2857                 return -EOPNOTSUPP;
2858
2859         return ret;
2860 }
2861
2862 static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu)
2863 {
2864         struct amdgpu_device *adev = smu->adev;
2865
2866         if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2867                 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2868                                                                                    FEATURE_PWR_GFX, NULL);
2869         else
2870                 return -EOPNOTSUPP;
2871 }
2872
2873 static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
2874 {
2875         struct amdgpu_device *adev = smu->adev;
2876
2877         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2878         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2879         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2880
2881         smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2882         smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
2883         smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
2884 }
2885
2886 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
2887                 uint32_t size)
2888 {
2889         int ret = 0;
2890
2891         /* message SMU to update the bad page number on SMUBUS */
2892         ret = smu_cmn_send_smc_msg_with_param(smu,
2893                                           SMU_MSG_SetNumBadMemoryPagesRetired,
2894                                           size, NULL);
2895         if (ret)
2896                 dev_err(smu->adev->dev,
2897                           "[%s] failed to message SMU to update bad memory pages number\n",
2898                           __func__);
2899
2900         return ret;
2901 }
2902
2903 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu,
2904                 uint32_t size)
2905 {
2906         int ret = 0;
2907
2908         /* message SMU to update the bad channel info on SMUBUS */
2909         ret = smu_cmn_send_smc_msg_with_param(smu,
2910                                   SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,
2911                                   size, NULL);
2912         if (ret)
2913                 dev_err(smu->adev->dev,
2914                           "[%s] failed to message SMU to update bad memory pages channel info\n",
2915                           __func__);
2916
2917         return ret;
2918 }
2919
2920 static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu)
2921 {
2922         struct amdgpu_device *adev = smu->adev;
2923         int ret = 0;
2924
2925         if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) &&
2926                 (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION))
2927                 return ret;
2928         else
2929                 return -EOPNOTSUPP;
2930 }
2931
2932 static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu,
2933                                                                         void *table)
2934 {
2935         struct smu_table_context *smu_table = &smu->smu_table;
2936         struct amdgpu_device *adev = smu->adev;
2937         EccInfoTable_t *ecc_table = NULL;
2938         struct ecc_info_per_ch *ecc_info_per_channel = NULL;
2939         int i, ret = 0;
2940         struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
2941
2942         ret = smu_v13_0_0_check_ecc_table_support(smu);
2943         if (ret)
2944                 return ret;
2945
2946         ret = smu_cmn_update_table(smu,
2947                                         SMU_TABLE_ECCINFO,
2948                                         0,
2949                                         smu_table->ecc_table,
2950                                         false);
2951         if (ret) {
2952                 dev_info(adev->dev, "Failed to export SMU ecc table!\n");
2953                 return ret;
2954         }
2955
2956         ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
2957
2958         for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) {
2959                 ecc_info_per_channel = &(eccinfo->ecc[i]);
2960                 ecc_info_per_channel->ce_count_lo_chip =
2961                                 ecc_table->EccInfo[i].ce_count_lo_chip;
2962                 ecc_info_per_channel->ce_count_hi_chip =
2963                                 ecc_table->EccInfo[i].ce_count_hi_chip;
2964                 ecc_info_per_channel->mca_umc_status =
2965                                 ecc_table->EccInfo[i].mca_umc_status;
2966                 ecc_info_per_channel->mca_umc_addr =
2967                                 ecc_table->EccInfo[i].mca_umc_addr;
2968         }
2969
2970         return ret;
2971 }
2972
2973 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
2974         .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
2975         .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
2976         .i2c_init = smu_v13_0_0_i2c_control_init,
2977         .i2c_fini = smu_v13_0_0_i2c_control_fini,
2978         .is_dpm_running = smu_v13_0_0_is_dpm_running,
2979         .dump_pptable = smu_v13_0_0_dump_pptable,
2980         .init_microcode = smu_v13_0_init_microcode,
2981         .load_microcode = smu_v13_0_load_microcode,
2982         .fini_microcode = smu_v13_0_fini_microcode,
2983         .init_smc_tables = smu_v13_0_0_init_smc_tables,
2984         .fini_smc_tables = smu_v13_0_fini_smc_tables,
2985         .init_power = smu_v13_0_init_power,
2986         .fini_power = smu_v13_0_fini_power,
2987         .check_fw_status = smu_v13_0_check_fw_status,
2988         .setup_pptable = smu_v13_0_0_setup_pptable,
2989         .check_fw_version = smu_v13_0_check_fw_version,
2990         .write_pptable = smu_cmn_write_pptable,
2991         .set_driver_table_location = smu_v13_0_set_driver_table_location,
2992         .system_features_control = smu_v13_0_0_system_features_control,
2993         .set_allowed_mask = smu_v13_0_set_allowed_mask,
2994         .get_enabled_mask = smu_cmn_get_enabled_mask,
2995         .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
2996         .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
2997         .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq,
2998         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2999         .read_sensor = smu_v13_0_0_read_sensor,
3000         .feature_is_enabled = smu_cmn_feature_is_enabled,
3001         .print_clk_levels = smu_v13_0_0_print_clk_levels,
3002         .force_clk_levels = smu_v13_0_0_force_clk_levels,
3003         .update_pcie_parameters = smu_v13_0_update_pcie_parameters,
3004         .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
3005         .register_irq_handler = smu_v13_0_register_irq_handler,
3006         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3007         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3008         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3009         .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
3010         .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
3011         .set_default_od_settings = smu_v13_0_0_set_default_od_settings,
3012         .restore_user_od_settings = smu_v13_0_0_restore_user_od_settings,
3013         .od_edit_dpm_table = smu_v13_0_0_od_edit_dpm_table,
3014         .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
3015         .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
3016         .set_performance_level = smu_v13_0_set_performance_level,
3017         .gfx_off_control = smu_v13_0_gfx_off_control,
3018         .get_unique_id = smu_v13_0_0_get_unique_id,
3019         .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
3020         .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
3021         .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
3022         .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
3023         .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
3024         .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
3025         .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
3026         .get_power_limit = smu_v13_0_0_get_power_limit,
3027         .set_power_limit = smu_v13_0_set_power_limit,
3028         .set_power_source = smu_v13_0_set_power_source,
3029         .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
3030         .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
3031         .run_btc = smu_v13_0_run_btc,
3032         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3033         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3034         .set_tool_table_location = smu_v13_0_set_tool_table_location,
3035         .deep_sleep_control = smu_v13_0_deep_sleep_control,
3036         .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
3037         .baco_is_support = smu_v13_0_baco_is_support,
3038         .baco_get_state = smu_v13_0_baco_get_state,
3039         .baco_set_state = smu_v13_0_baco_set_state,
3040         .baco_enter = smu_v13_0_0_baco_enter,
3041         .baco_exit = smu_v13_0_0_baco_exit,
3042         .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
3043         .mode1_reset = smu_v13_0_0_mode1_reset,
3044         .mode2_reset = smu_v13_0_0_mode2_reset,
3045         .enable_gfx_features = smu_v13_0_0_enable_gfx_features,
3046         .set_mp1_state = smu_v13_0_0_set_mp1_state,
3047         .set_df_cstate = smu_v13_0_0_set_df_cstate,
3048         .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num,
3049         .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag,
3050         .gpo_control = smu_v13_0_gpo_control,
3051         .get_ecc_info = smu_v13_0_0_get_ecc_info,
3052         .notify_display_change = smu_v13_0_notify_display_change,
3053 };
3054
3055 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
3056 {
3057         smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
3058         smu->message_map = smu_v13_0_0_message_map;
3059         smu->clock_map = smu_v13_0_0_clk_map;
3060         smu->feature_map = smu_v13_0_0_feature_mask_map;
3061         smu->table_map = smu_v13_0_0_table_map;
3062         smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
3063         smu->workload_map = smu_v13_0_0_workload_map;
3064         smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION;
3065         smu_v13_0_0_set_smu_mailbox_registers(smu);
3066 }