drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_dpm.h"
  31 #include "amdgpu_smu.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "smu_v11_0.h"
  36 #include "smu11_driver_if_sienna_cichlid.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "sienna_cichlid_ppt.h"
  40 #include "smu_v11_0_7_pptable.h"
  41 #include "smu_v11_0_7_ppsmc.h"
  42 #include "nbio/nbio_2_3_offset.h"
  43 #include "nbio/nbio_2_3_sh_mask.h"
  44 #include "thm/thm_11_0_2_offset.h"
  45 #include "thm/thm_11_0_2_sh_mask.h"
  46 #include "mp/mp_11_0_offset.h"
  47 #include "mp/mp_11_0_sh_mask.h"
  48
  49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  50 #include "amdgpu_ras.h"
  51 #include "smu_cmn.h"
  52
  53 /*
  54  * DO NOT use these for err/warn/info/debug messages.
  55  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  56  * They are more MGPU friendly.
  57  */
  58 #undef pr_err
  59 #undef pr_warn
  60 #undef pr_info
  61 #undef pr_debug
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 #define GET_PPTABLE_MEMBER(field, member) do {\
  77         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
  78                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
  79         else\
  80                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
  81 } while(0)
  82
  83 /* STB FIFO depth is in 64bit units */
  84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
  85
  86 /*
  87  * SMU support ECCTABLE since version 58.70.0,
  88  * use this to check whether ECCTABLE feature is supported.
  89  */
  90 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
  91
  92 static int get_table_size(struct smu_context *smu)
  93 {
  94         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
  95                 return sizeof(PPTable_beige_goby_t);
  96         else
  97                 return sizeof(PPTable_t);
  98 }
  99
 100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
 101         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
 102         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
 103         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
 104         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
 105         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
 106         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
 107         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
 108         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 109         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 110         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 111         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 112         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 113         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 114         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 115         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 116         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 117         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 118         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 119         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 120         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 121         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 122         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 123         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 124         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 125         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 126         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 127         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 128         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 129         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 130         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 131         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 132         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 133         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 134         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 135         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 136         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 137         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 138         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 139         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 140         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 141         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 142         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 143         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 144         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 145         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 146         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 147         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 148         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 149         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 150         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 151         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 152         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 153         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 154         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 155         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 156         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 157         MSG_MAP(DriverMode2Reset,               PPSMC_MSG_DriverMode2Reset,            0),
 158 };
 159
 160 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 161         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 162         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 163         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 164         CLK_MAP(FCLK,           PPCLK_FCLK),
 165         CLK_MAP(UCLK,           PPCLK_UCLK),
 166         CLK_MAP(MCLK,           PPCLK_UCLK),
 167         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 168         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 169         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 170         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 171         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 172         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 173         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 174         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 175 };
 176
 177 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 178         FEA_MAP(DPM_PREFETCHER),
 179         FEA_MAP(DPM_GFXCLK),
 180         FEA_MAP(DPM_GFX_GPO),
 181         FEA_MAP(DPM_UCLK),
 182         FEA_MAP(DPM_FCLK),
 183         FEA_MAP(DPM_SOCCLK),
 184         FEA_MAP(DPM_MP0CLK),
 185         FEA_MAP(DPM_LINK),
 186         FEA_MAP(DPM_DCEFCLK),
 187         FEA_MAP(DPM_XGMI),
 188         FEA_MAP(MEM_VDDCI_SCALING),
 189         FEA_MAP(MEM_MVDD_SCALING),
 190         FEA_MAP(DS_GFXCLK),
 191         FEA_MAP(DS_SOCCLK),
 192         FEA_MAP(DS_FCLK),
 193         FEA_MAP(DS_LCLK),
 194         FEA_MAP(DS_DCEFCLK),
 195         FEA_MAP(DS_UCLK),
 196         FEA_MAP(GFX_ULV),
 197         FEA_MAP(FW_DSTATE),
 198         FEA_MAP(GFXOFF),
 199         FEA_MAP(BACO),
 200         FEA_MAP(MM_DPM_PG),
 201         FEA_MAP(RSMU_SMN_CG),
 202         FEA_MAP(PPT),
 203         FEA_MAP(TDC),
 204         FEA_MAP(APCC_PLUS),
 205         FEA_MAP(GTHR),
 206         FEA_MAP(ACDC),
 207         FEA_MAP(VR0HOT),
 208         FEA_MAP(VR1HOT),
 209         FEA_MAP(FW_CTF),
 210         FEA_MAP(FAN_CONTROL),
 211         FEA_MAP(THERMAL),
 212         FEA_MAP(GFX_DCS),
 213         FEA_MAP(RM),
 214         FEA_MAP(LED_DISPLAY),
 215         FEA_MAP(GFX_SS),
 216         FEA_MAP(OUT_OF_BAND_MONITOR),
 217         FEA_MAP(TEMP_DEPENDENT_VMIN),
 218         FEA_MAP(MMHUB_PG),
 219         FEA_MAP(ATHUB_PG),
 220         FEA_MAP(APCC_DFLL),
 221 };
 222
 223 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 224         TAB_MAP(PPTABLE),
 225         TAB_MAP(WATERMARKS),
 226         TAB_MAP(AVFS_PSM_DEBUG),
 227         TAB_MAP(AVFS_FUSE_OVERRIDE),
 228         TAB_MAP(PMSTATUSLOG),
 229         TAB_MAP(SMU_METRICS),
 230         TAB_MAP(DRIVER_SMU_CONFIG),
 231         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 232         TAB_MAP(OVERDRIVE),
 233         TAB_MAP(I2C_COMMANDS),
 234         TAB_MAP(PACE),
 235         TAB_MAP(ECCINFO),
 236 };
 237
 238 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 239         PWR_MAP(AC),
 240         PWR_MAP(DC),
 241 };
 242
 243 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 244         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 245         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 246         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 247         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 248         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 249         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 250         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 251 };
 252
 253 static const uint8_t sienna_cichlid_throttler_map[] = {
 254         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 255         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 256         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 257         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 258         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 259         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 260         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 261         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 262         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 263         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 264         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 265         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 266         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 267         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 268         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 269         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 270         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 271         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 272 };
 273
 274 static int
 275 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 276                                   uint32_t *feature_mask, uint32_t num)
 277 {
 278         struct amdgpu_device *adev = smu->adev;
 279
 280         if (num > 2)
 281                 return -EINVAL;
 282
 283         memset(feature_mask, 0, sizeof(uint32_t) * num);
 284
 285         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 286                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 287                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 288                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 289                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 290                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 291                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 292                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 293                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 294                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 295                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 296                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 297                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 298                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 299                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 300                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 301                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 302                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 303                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 304                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 305
 306         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 307                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 308                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 309         }
 310
 311         if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
 312             (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
 313             !(adev->flags & AMD_IS_APU))
 314                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 315
 316         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 317                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 318                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 319                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 320
 321         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 322                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 323
 324         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 325                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 326
 327         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 328                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 329
 330         if (adev->pm.pp_feature & PP_ULV_MASK)
 331                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 332
 333         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 334                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 335
 336         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 337                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 338
 339         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 340                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 341
 342         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 343                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 344
 345         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 346             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 347                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 348
 349         if (smu->dc_controlled_by_gpio)
 350        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 351
 352         if (amdgpu_device_should_use_aspm(adev))
 353                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 354
 355         return 0;
 356 }
 357
 358 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 359 {
 360         struct smu_table_context *table_context = &smu->smu_table;
 361         struct smu_11_0_7_powerplay_table *powerplay_table =
 362                 table_context->power_play_table;
 363         struct smu_baco_context *smu_baco = &smu->smu_baco;
 364         struct amdgpu_device *adev = smu->adev;
 365         uint32_t val;
 366
 367         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
 368                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 369                 smu_baco->platform_support =
 370                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 371                                                                         false;
 372
 373                 /*
 374                  * Disable BACO entry/exit completely on below SKUs to
 375                  * avoid hardware intermittent failures.
 376                  */
 377                 if (((adev->pdev->device == 0x73A1) &&
 378                     (adev->pdev->revision == 0x00)) ||
 379                     ((adev->pdev->device == 0x73BF) &&
 380                     (adev->pdev->revision == 0xCF)) ||
 381                     ((adev->pdev->device == 0x7422) &&
 382                     (adev->pdev->revision == 0x00)) ||
 383                     ((adev->pdev->device == 0x73A3) &&
 384                     (adev->pdev->revision == 0x00)) ||
 385                     ((adev->pdev->device == 0x73E3) &&
 386                     (adev->pdev->revision == 0x00)))
 387                         smu_baco->platform_support = false;
 388
 389         }
 390 }
 391
 392 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
 393 {
 394         struct smu_table_context *table_context = &smu->smu_table;
 395         PPTable_t *pptable = table_context->driver_pptable;
 396         uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
 397
 398         /* Fan control is not possible if PPTable has it disabled */
 399         smu->adev->pm.no_fan =
 400                 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
 401         if (smu->adev->pm.no_fan)
 402                 dev_info_once(smu->adev->dev,
 403                               "PMFW based fan control disabled");
 404 }
 405
 406 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 407 {
 408         struct smu_table_context *table_context = &smu->smu_table;
 409         struct smu_11_0_7_powerplay_table *powerplay_table =
 410                 table_context->power_play_table;
 411
 412         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 413                 smu->dc_controlled_by_gpio = true;
 414
 415         sienna_cichlid_check_bxco_support(smu);
 416         sienna_cichlid_check_fan_support(smu);
 417
 418         table_context->thermal_controller_type =
 419                 powerplay_table->thermal_controller_type;
 420
 421         /*
 422          * Instead of having its own buffer space and get overdrive_table copied,
 423          * smu->od_settings just points to the actual overdrive_table
 424          */
 425         smu->od_settings = &powerplay_table->overdrive_table;
 426
 427         return 0;
 428 }
 429
 430 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 431 {
 432         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 433         int index, ret;
 434         PPTable_beige_goby_t *ppt_beige_goby;
 435         PPTable_t *ppt;
 436
 437         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
 438                 ppt_beige_goby = smu->smu_table.driver_pptable;
 439         else
 440                 ppt = smu->smu_table.driver_pptable;
 441
 442         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 443                                             smc_dpm_info);
 444
 445         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 446                                       (uint8_t **)&smc_dpm_table);
 447         if (ret)
 448                 return ret;
 449
 450         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
 451                 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
 452                                     smc_dpm_table, I2cControllers);
 453         else
 454                 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
 455                                     smc_dpm_table, I2cControllers);
 456
 457         return 0;
 458 }
 459
 460 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 461 {
 462         struct smu_table_context *table_context = &smu->smu_table;
 463         struct smu_11_0_7_powerplay_table *powerplay_table =
 464                 table_context->power_play_table;
 465         int table_size;
 466
 467         table_size = get_table_size(smu);
 468         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 469                table_size);
 470
 471         return 0;
 472 }
 473
 474 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
 475 {
 476         struct amdgpu_device *adev = smu->adev;
 477         uint32_t *board_reserved;
 478         uint16_t *freq_table_gfx;
 479         uint32_t i;
 480
 481         /* Fix some OEM SKU specific stability issues */
 482         GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
 483         if ((adev->pdev->device == 0x73DF) &&
 484             (adev->pdev->revision == 0XC3) &&
 485             (adev->pdev->subsystem_device == 0x16C2) &&
 486             (adev->pdev->subsystem_vendor == 0x1043))
 487                 board_reserved[0] = 1387;
 488
 489         GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
 490         if ((adev->pdev->device == 0x73DF) &&
 491             (adev->pdev->revision == 0XC3) &&
 492             ((adev->pdev->subsystem_device == 0x16C2) ||
 493             (adev->pdev->subsystem_device == 0x133C)) &&
 494             (adev->pdev->subsystem_vendor == 0x1043)) {
 495                 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
 496                         if (freq_table_gfx[i] > 2500)
 497                                 freq_table_gfx[i] = 2500;
 498                 }
 499         }
 500
 501         return 0;
 502 }
 503
 504 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 505 {
 506         int ret = 0;
 507
 508         ret = smu_v11_0_setup_pptable(smu);
 509         if (ret)
 510                 return ret;
 511
 512         ret = sienna_cichlid_store_powerplay_table(smu);
 513         if (ret)
 514                 return ret;
 515
 516         ret = sienna_cichlid_append_powerplay_table(smu);
 517         if (ret)
 518                 return ret;
 519
 520         ret = sienna_cichlid_check_powerplay_table(smu);
 521         if (ret)
 522                 return ret;
 523
 524         return sienna_cichlid_patch_pptable_quirk(smu);
 525 }
 526
 527 static int sienna_cichlid_tables_init(struct smu_context *smu)
 528 {
 529         struct smu_table_context *smu_table = &smu->smu_table;
 530         struct smu_table *tables = smu_table->tables;
 531         int table_size;
 532
 533         table_size = get_table_size(smu);
 534         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
 535                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 536         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 537                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 538         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 539                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 540         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 541                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 542         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 543                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 544         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 545                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 546         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 547                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 548                        AMDGPU_GEM_DOMAIN_VRAM);
 549         SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
 550                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 551         SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
 552                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 553
 554         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 555         if (!smu_table->metrics_table)
 556                 goto err0_out;
 557         smu_table->metrics_time = 0;
 558
 559         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 560         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 561         if (!smu_table->gpu_metrics_table)
 562                 goto err1_out;
 563
 564         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 565         if (!smu_table->watermarks_table)
 566                 goto err2_out;
 567
 568         smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
 569         if (!smu_table->ecc_table)
 570                 goto err3_out;
 571
 572         smu_table->driver_smu_config_table =
 573                 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
 574         if (!smu_table->driver_smu_config_table)
 575                 goto err4_out;
 576
 577         return 0;
 578
 579 err4_out:
 580         kfree(smu_table->ecc_table);
 581 err3_out:
 582         kfree(smu_table->watermarks_table);
 583 err2_out:
 584         kfree(smu_table->gpu_metrics_table);
 585 err1_out:
 586         kfree(smu_table->metrics_table);
 587 err0_out:
 588         return -ENOMEM;
 589 }
 590
 591 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
 592                                                            bool use_metrics_v3,
 593                                                            bool use_metrics_v2)
 594 {
 595         struct smu_table_context *smu_table= &smu->smu_table;
 596         SmuMetricsExternal_t *metrics_ext =
 597                 (SmuMetricsExternal_t *)(smu_table->metrics_table);
 598         uint32_t throttler_status = 0;
 599         int i;
 600
 601         if (use_metrics_v3) {
 602                 for (i = 0; i < THROTTLER_COUNT; i++)
 603                         throttler_status |=
 604                                 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
 605         } else if (use_metrics_v2) {
 606                 for (i = 0; i < THROTTLER_COUNT; i++)
 607                         throttler_status |=
 608                                 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
 609         } else {
 610                 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
 611         }
 612
 613         return throttler_status;
 614 }
 615
 616 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
 617                                           uint32_t *current_power_limit,
 618                                           uint32_t *default_power_limit,
 619                                           uint32_t *max_power_limit)
 620 {
 621         struct smu_11_0_7_powerplay_table *powerplay_table =
 622                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
 623         uint32_t power_limit, od_percent;
 624         uint16_t *table_member;
 625
 626         GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
 627
 628         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
 629                 power_limit =
 630                         table_member[PPT_THROTTLER_PPT0];
 631         }
 632
 633         if (current_power_limit)
 634                 *current_power_limit = power_limit;
 635         if (default_power_limit)
 636                 *default_power_limit = power_limit;
 637
 638         if (max_power_limit) {
 639                 if (smu->od_enabled) {
 640                         od_percent =
 641                                 le32_to_cpu(powerplay_table->overdrive_table.max[
 642                                                         SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
 643
 644                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
 645                                         od_percent, power_limit);
 646
 647                         power_limit *= (100 + od_percent);
 648                         power_limit /= 100;
 649                 }
 650                 *max_power_limit = power_limit;
 651         }
 652
 653         return 0;
 654 }
 655
 656 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
 657                                         uint32_t *apu_percent,
 658                                         uint32_t *dgpu_percent)
 659 {
 660         struct smu_table_context *smu_table = &smu->smu_table;
 661         SmuMetrics_V4_t *metrics_v4 =
 662                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
 663         uint16_t powerRatio = 0;
 664         uint16_t apu_power_limit = 0;
 665         uint16_t dgpu_power_limit = 0;
 666         uint32_t apu_boost = 0;
 667         uint32_t dgpu_boost = 0;
 668         uint32_t cur_power_limit;
 669
 670         if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
 671                 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
 672                 apu_power_limit = metrics_v4->ApuSTAPMLimit;
 673                 dgpu_power_limit = cur_power_limit;
 674                 powerRatio = (((apu_power_limit +
 675                                                   dgpu_power_limit) * 100) /
 676                                                   metrics_v4->ApuSTAPMSmartShiftLimit);
 677                 if (powerRatio > 100) {
 678                         apu_power_limit = (apu_power_limit * 100) /
 679                                                                          powerRatio;
 680                         dgpu_power_limit = (dgpu_power_limit * 100) /
 681                                                                           powerRatio;
 682                 }
 683                 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
 684                          apu_power_limit != 0) {
 685                         apu_boost = ((metrics_v4->AverageApuSocketPower -
 686                                                         apu_power_limit) * 100) /
 687                                                         apu_power_limit;
 688                         if (apu_boost > 100)
 689                                 apu_boost = 100;
 690                 }
 691
 692                 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
 693                          dgpu_power_limit != 0) {
 694                         dgpu_boost = ((metrics_v4->AverageSocketPower -
 695                                                          dgpu_power_limit) * 100) /
 696                                                          dgpu_power_limit;
 697                         if (dgpu_boost > 100)
 698                                 dgpu_boost = 100;
 699                 }
 700
 701                 if (dgpu_boost >= apu_boost)
 702                         apu_boost = 0;
 703                 else
 704                         dgpu_boost = 0;
 705         }
 706         *apu_percent = apu_boost;
 707         *dgpu_percent = dgpu_boost;
 708 }
 709
 710 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 711                                                MetricsMember_t member,
 712                                                uint32_t *value)
 713 {
 714         struct smu_table_context *smu_table= &smu->smu_table;
 715         SmuMetrics_t *metrics =
 716                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 717         SmuMetrics_V2_t *metrics_v2 =
 718                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
 719         SmuMetrics_V3_t *metrics_v3 =
 720                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
 721         bool use_metrics_v2 = false;
 722         bool use_metrics_v3 = false;
 723         uint16_t average_gfx_activity;
 724         int ret = 0;
 725         uint32_t apu_percent = 0;
 726         uint32_t dgpu_percent = 0;
 727
 728         switch (smu->adev->ip_versions[MP1_HWIP][0]) {
 729         case IP_VERSION(11, 0, 7):
 730                 if (smu->smc_fw_version >= 0x3A4900)
 731                         use_metrics_v3 = true;
 732                 else if (smu->smc_fw_version >= 0x3A4300)
 733                         use_metrics_v2 = true;
 734                 break;
 735         case IP_VERSION(11, 0, 11):
 736                 if (smu->smc_fw_version >= 0x412D00)
 737                         use_metrics_v2 = true;
 738                 break;
 739         case IP_VERSION(11, 0, 12):
 740                 if (smu->smc_fw_version >= 0x3B2300)
 741                         use_metrics_v2 = true;
 742                 break;
 743         case IP_VERSION(11, 0, 13):
 744                 if (smu->smc_fw_version >= 0x491100)
 745                         use_metrics_v2 = true;
 746                 break;
 747         default:
 748                 break;
 749         }
 750
 751         ret = smu_cmn_get_metrics_table(smu,
 752                                         NULL,
 753                                         false);
 754         if (ret)
 755                 return ret;
 756
 757         switch (member) {
 758         case METRICS_CURR_GFXCLK:
 759                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
 760                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
 761                         metrics->CurrClock[PPCLK_GFXCLK];
 762                 break;
 763         case METRICS_CURR_SOCCLK:
 764                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
 765                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
 766                         metrics->CurrClock[PPCLK_SOCCLK];
 767                 break;
 768         case METRICS_CURR_UCLK:
 769                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
 770                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
 771                         metrics->CurrClock[PPCLK_UCLK];
 772                 break;
 773         case METRICS_CURR_VCLK:
 774                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
 775                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
 776                         metrics->CurrClock[PPCLK_VCLK_0];
 777                 break;
 778         case METRICS_CURR_VCLK1:
 779                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
 780                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
 781                         metrics->CurrClock[PPCLK_VCLK_1];
 782                 break;
 783         case METRICS_CURR_DCLK:
 784                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
 785                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
 786                         metrics->CurrClock[PPCLK_DCLK_0];
 787                 break;
 788         case METRICS_CURR_DCLK1:
 789                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
 790                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
 791                         metrics->CurrClock[PPCLK_DCLK_1];
 792                 break;
 793         case METRICS_CURR_DCEFCLK:
 794                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
 795                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
 796                         metrics->CurrClock[PPCLK_DCEFCLK];
 797                 break;
 798         case METRICS_CURR_FCLK:
 799                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
 800                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
 801                         metrics->CurrClock[PPCLK_FCLK];
 802                 break;
 803         case METRICS_AVERAGE_GFXCLK:
 804                 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 805                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 806                         metrics->AverageGfxActivity;
 807                 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 808                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
 809                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
 810                                 metrics->AverageGfxclkFrequencyPostDs;
 811                 else
 812                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
 813                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
 814                                 metrics->AverageGfxclkFrequencyPreDs;
 815                 break;
 816         case METRICS_AVERAGE_FCLK:
 817                 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
 818                         use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
 819                         metrics->AverageFclkFrequencyPostDs;
 820                 break;
 821         case METRICS_AVERAGE_UCLK:
 822                 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
 823                         use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
 824                         metrics->AverageUclkFrequencyPostDs;
 825                 break;
 826         case METRICS_AVERAGE_GFXACTIVITY:
 827                 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 828                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 829                         metrics->AverageGfxActivity;
 830                 break;
 831         case METRICS_AVERAGE_MEMACTIVITY:
 832                 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
 833                         use_metrics_v2 ? metrics_v2->AverageUclkActivity :
 834                         metrics->AverageUclkActivity;
 835                 break;
 836         case METRICS_AVERAGE_SOCKETPOWER:
 837                 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
 838                         use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
 839                         metrics->AverageSocketPower << 8;
 840                 break;
 841         case METRICS_TEMPERATURE_EDGE:
 842                 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
 843                         use_metrics_v2 ? metrics_v2->TemperatureEdge :
 844                         metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 845                 break;
 846         case METRICS_TEMPERATURE_HOTSPOT:
 847                 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
 848                         use_metrics_v2 ? metrics_v2->TemperatureHotspot :
 849                         metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 850                 break;
 851         case METRICS_TEMPERATURE_MEM:
 852                 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
 853                         use_metrics_v2 ? metrics_v2->TemperatureMem :
 854                         metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 855                 break;
 856         case METRICS_TEMPERATURE_VRGFX:
 857                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
 858                         use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
 859                         metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 860                 break;
 861         case METRICS_TEMPERATURE_VRSOC:
 862                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
 863                         use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
 864                         metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 865                 break;
 866         case METRICS_THROTTLER_STATUS:
 867                 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
 868                 break;
 869         case METRICS_CURR_FANSPEED:
 870                 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
 871                         use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
 872                 break;
 873         case METRICS_UNIQUE_ID_UPPER32:
 874                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 875                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
 876                 break;
 877         case METRICS_UNIQUE_ID_LOWER32:
 878                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 879                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
 880                 break;
 881         case METRICS_SS_APU_SHARE:
 882                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 883                 *value = apu_percent;
 884                 break;
 885         case METRICS_SS_DGPU_SHARE:
 886                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 887                 *value = dgpu_percent;
 888                 break;
 889
 890         default:
 891                 *value = UINT_MAX;
 892                 break;
 893         }
 894
 895         return ret;
 896
 897 }
 898
 899 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 900 {
 901         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 902
 903         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 904                                        GFP_KERNEL);
 905         if (!smu_dpm->dpm_context)
 906                 return -ENOMEM;
 907
 908         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 909
 910         return 0;
 911 }
 912
 913 static void sienna_cichlid_stb_init(struct smu_context *smu);
 914
 915 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 916 {
 917         struct amdgpu_device *adev = smu->adev;
 918         int ret = 0;
 919
 920         ret = sienna_cichlid_tables_init(smu);
 921         if (ret)
 922                 return ret;
 923
 924         ret = sienna_cichlid_allocate_dpm_context(smu);
 925         if (ret)
 926                 return ret;
 927
 928         if (!amdgpu_sriov_vf(adev))
 929                 sienna_cichlid_stb_init(smu);
 930
 931         return smu_v11_0_init_smc_tables(smu);
 932 }
 933
 934 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 935 {
 936         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 937         struct smu_11_0_dpm_table *dpm_table;
 938         struct amdgpu_device *adev = smu->adev;
 939         int i, ret = 0;
 940         DpmDescriptor_t *table_member;
 941
 942         /* socclk dpm table setup */
 943         dpm_table = &dpm_context->dpm_tables.soc_table;
 944         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 945         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 946                 ret = smu_v11_0_set_single_dpm_table(smu,
 947                                                      SMU_SOCCLK,
 948                                                      dpm_table);
 949                 if (ret)
 950                         return ret;
 951                 dpm_table->is_fine_grained =
 952                         !table_member[PPCLK_SOCCLK].SnapToDiscrete;
 953         } else {
 954                 dpm_table->count = 1;
 955                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 956                 dpm_table->dpm_levels[0].enabled = true;
 957                 dpm_table->min = dpm_table->dpm_levels[0].value;
 958                 dpm_table->max = dpm_table->dpm_levels[0].value;
 959         }
 960
 961         /* gfxclk dpm table setup */
 962         dpm_table = &dpm_context->dpm_tables.gfx_table;
 963         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 964                 ret = smu_v11_0_set_single_dpm_table(smu,
 965                                                      SMU_GFXCLK,
 966                                                      dpm_table);
 967                 if (ret)
 968                         return ret;
 969                 dpm_table->is_fine_grained =
 970                         !table_member[PPCLK_GFXCLK].SnapToDiscrete;
 971         } else {
 972                 dpm_table->count = 1;
 973                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 974                 dpm_table->dpm_levels[0].enabled = true;
 975                 dpm_table->min = dpm_table->dpm_levels[0].value;
 976                 dpm_table->max = dpm_table->dpm_levels[0].value;
 977         }
 978
 979         /* uclk dpm table setup */
 980         dpm_table = &dpm_context->dpm_tables.uclk_table;
 981         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 982                 ret = smu_v11_0_set_single_dpm_table(smu,
 983                                                      SMU_UCLK,
 984                                                      dpm_table);
 985                 if (ret)
 986                         return ret;
 987                 dpm_table->is_fine_grained =
 988                         !table_member[PPCLK_UCLK].SnapToDiscrete;
 989         } else {
 990                 dpm_table->count = 1;
 991                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 992                 dpm_table->dpm_levels[0].enabled = true;
 993                 dpm_table->min = dpm_table->dpm_levels[0].value;
 994                 dpm_table->max = dpm_table->dpm_levels[0].value;
 995         }
 996
 997         /* fclk dpm table setup */
 998         dpm_table = &dpm_context->dpm_tables.fclk_table;
 999         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1000                 ret = smu_v11_0_set_single_dpm_table(smu,
1001                                                      SMU_FCLK,
1002                                                      dpm_table);
1003                 if (ret)
1004                         return ret;
1005                 dpm_table->is_fine_grained =
1006                         !table_member[PPCLK_FCLK].SnapToDiscrete;
1007         } else {
1008                 dpm_table->count = 1;
1009                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1010                 dpm_table->dpm_levels[0].enabled = true;
1011                 dpm_table->min = dpm_table->dpm_levels[0].value;
1012                 dpm_table->max = dpm_table->dpm_levels[0].value;
1013         }
1014
1015         /* vclk0/1 dpm table setup */
1016         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1017                 if (adev->vcn.harvest_config & (1 << i))
1018                         continue;
1019
1020                 dpm_table = &dpm_context->dpm_tables.vclk_table;
1021                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1022                         ret = smu_v11_0_set_single_dpm_table(smu,
1023                                                              i ? SMU_VCLK1 : SMU_VCLK,
1024                                                              dpm_table);
1025                         if (ret)
1026                                 return ret;
1027                         dpm_table->is_fine_grained =
1028                                 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1029                 } else {
1030                         dpm_table->count = 1;
1031                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1032                         dpm_table->dpm_levels[0].enabled = true;
1033                         dpm_table->min = dpm_table->dpm_levels[0].value;
1034                         dpm_table->max = dpm_table->dpm_levels[0].value;
1035                 }
1036         }
1037
1038         /* dclk0/1 dpm table setup */
1039         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1040                 if (adev->vcn.harvest_config & (1 << i))
1041                         continue;
1042                 dpm_table = &dpm_context->dpm_tables.dclk_table;
1043                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1044                         ret = smu_v11_0_set_single_dpm_table(smu,
1045                                                              i ? SMU_DCLK1 : SMU_DCLK,
1046                                                              dpm_table);
1047                         if (ret)
1048                                 return ret;
1049                         dpm_table->is_fine_grained =
1050                                 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1051                 } else {
1052                         dpm_table->count = 1;
1053                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1054                         dpm_table->dpm_levels[0].enabled = true;
1055                         dpm_table->min = dpm_table->dpm_levels[0].value;
1056                         dpm_table->max = dpm_table->dpm_levels[0].value;
1057                 }
1058         }
1059
1060         /* dcefclk dpm table setup */
1061         dpm_table = &dpm_context->dpm_tables.dcef_table;
1062         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1063                 ret = smu_v11_0_set_single_dpm_table(smu,
1064                                                      SMU_DCEFCLK,
1065                                                      dpm_table);
1066                 if (ret)
1067                         return ret;
1068                 dpm_table->is_fine_grained =
1069                         !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1070         } else {
1071                 dpm_table->count = 1;
1072                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1073                 dpm_table->dpm_levels[0].enabled = true;
1074                 dpm_table->min = dpm_table->dpm_levels[0].value;
1075                 dpm_table->max = dpm_table->dpm_levels[0].value;
1076         }
1077
1078         /* pixelclk dpm table setup */
1079         dpm_table = &dpm_context->dpm_tables.pixel_table;
1080         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1081                 ret = smu_v11_0_set_single_dpm_table(smu,
1082                                                      SMU_PIXCLK,
1083                                                      dpm_table);
1084                 if (ret)
1085                         return ret;
1086                 dpm_table->is_fine_grained =
1087                         !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1088         } else {
1089                 dpm_table->count = 1;
1090                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1091                 dpm_table->dpm_levels[0].enabled = true;
1092                 dpm_table->min = dpm_table->dpm_levels[0].value;
1093                 dpm_table->max = dpm_table->dpm_levels[0].value;
1094         }
1095
1096         /* displayclk dpm table setup */
1097         dpm_table = &dpm_context->dpm_tables.display_table;
1098         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1099                 ret = smu_v11_0_set_single_dpm_table(smu,
1100                                                      SMU_DISPCLK,
1101                                                      dpm_table);
1102                 if (ret)
1103                         return ret;
1104                 dpm_table->is_fine_grained =
1105                         !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1106         } else {
1107                 dpm_table->count = 1;
1108                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1109                 dpm_table->dpm_levels[0].enabled = true;
1110                 dpm_table->min = dpm_table->dpm_levels[0].value;
1111                 dpm_table->max = dpm_table->dpm_levels[0].value;
1112         }
1113
1114         /* phyclk dpm table setup */
1115         dpm_table = &dpm_context->dpm_tables.phy_table;
1116         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1117                 ret = smu_v11_0_set_single_dpm_table(smu,
1118                                                      SMU_PHYCLK,
1119                                                      dpm_table);
1120                 if (ret)
1121                         return ret;
1122                 dpm_table->is_fine_grained =
1123                         !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1124         } else {
1125                 dpm_table->count = 1;
1126                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1127                 dpm_table->dpm_levels[0].enabled = true;
1128                 dpm_table->min = dpm_table->dpm_levels[0].value;
1129                 dpm_table->max = dpm_table->dpm_levels[0].value;
1130         }
1131
1132         return 0;
1133 }
1134
1135 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1136 {
1137         struct amdgpu_device *adev = smu->adev;
1138         int i, ret = 0;
1139
1140         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1141                 if (adev->vcn.harvest_config & (1 << i))
1142                         continue;
1143                 /* vcn dpm on is a prerequisite for vcn power gate messages */
1144                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1145                         ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1146                                                               SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1147                                                               0x10000 * i, NULL);
1148                         if (ret)
1149                                 return ret;
1150                 }
1151         }
1152
1153         return ret;
1154 }
1155
1156 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1157 {
1158         int ret = 0;
1159
1160         if (enable) {
1161                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1162                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1163                         if (ret)
1164                                 return ret;
1165                 }
1166         } else {
1167                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1168                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1169                         if (ret)
1170                                 return ret;
1171                 }
1172         }
1173
1174         return ret;
1175 }
1176
1177 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1178                                        enum smu_clk_type clk_type,
1179                                        uint32_t *value)
1180 {
1181         MetricsMember_t member_type;
1182         int clk_id = 0;
1183
1184         clk_id = smu_cmn_to_asic_specific_index(smu,
1185                                                 CMN2ASIC_MAPPING_CLK,
1186                                                 clk_type);
1187         if (clk_id < 0)
1188                 return clk_id;
1189
1190         switch (clk_id) {
1191         case PPCLK_GFXCLK:
1192                 member_type = METRICS_CURR_GFXCLK;
1193                 break;
1194         case PPCLK_UCLK:
1195                 member_type = METRICS_CURR_UCLK;
1196                 break;
1197         case PPCLK_SOCCLK:
1198                 member_type = METRICS_CURR_SOCCLK;
1199                 break;
1200         case PPCLK_FCLK:
1201                 member_type = METRICS_CURR_FCLK;
1202                 break;
1203         case PPCLK_VCLK_0:
1204                 member_type = METRICS_CURR_VCLK;
1205                 break;
1206         case PPCLK_VCLK_1:
1207                 member_type = METRICS_CURR_VCLK1;
1208                 break;
1209         case PPCLK_DCLK_0:
1210                 member_type = METRICS_CURR_DCLK;
1211                 break;
1212         case PPCLK_DCLK_1:
1213                 member_type = METRICS_CURR_DCLK1;
1214                 break;
1215         case PPCLK_DCEFCLK:
1216                 member_type = METRICS_CURR_DCEFCLK;
1217                 break;
1218         default:
1219                 return -EINVAL;
1220         }
1221
1222         return sienna_cichlid_get_smu_metrics_data(smu,
1223                                                    member_type,
1224                                                    value);
1225
1226 }
1227
1228 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1229 {
1230         DpmDescriptor_t *dpm_desc = NULL;
1231         DpmDescriptor_t *table_member;
1232         uint32_t clk_index = 0;
1233
1234         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1235         clk_index = smu_cmn_to_asic_specific_index(smu,
1236                                                    CMN2ASIC_MAPPING_CLK,
1237                                                    clk_type);
1238         dpm_desc = &table_member[clk_index];
1239
1240         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1241         return dpm_desc->SnapToDiscrete == 0;
1242 }
1243
1244 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1245                                                    enum SMU_11_0_7_ODFEATURE_CAP cap)
1246 {
1247         return od_table->cap[cap];
1248 }
1249
1250 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1251                                                 enum SMU_11_0_7_ODSETTING_ID setting,
1252                                                 uint32_t *min, uint32_t *max)
1253 {
1254         if (min)
1255                 *min = od_table->min[setting];
1256         if (max)
1257                 *max = od_table->max[setting];
1258 }
1259
1260 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1261                         enum smu_clk_type clk_type, char *buf)
1262 {
1263         struct amdgpu_device *adev = smu->adev;
1264         struct smu_table_context *table_context = &smu->smu_table;
1265         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1266         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1267         uint16_t *table_member;
1268
1269         struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1270         OverDriveTable_t *od_table =
1271                 (OverDriveTable_t *)table_context->overdrive_table;
1272         int i, size = 0, ret = 0;
1273         uint32_t cur_value = 0, value = 0, count = 0;
1274         uint32_t freq_values[3] = {0};
1275         uint32_t mark_index = 0;
1276         uint32_t gen_speed, lane_width;
1277         uint32_t min_value, max_value;
1278         uint32_t smu_version;
1279
1280         smu_cmn_get_sysfs_buf(&buf, &size);
1281
1282         switch (clk_type) {
1283         case SMU_GFXCLK:
1284         case SMU_SCLK:
1285         case SMU_SOCCLK:
1286         case SMU_MCLK:
1287         case SMU_UCLK:
1288         case SMU_FCLK:
1289         case SMU_VCLK:
1290         case SMU_VCLK1:
1291         case SMU_DCLK:
1292         case SMU_DCLK1:
1293         case SMU_DCEFCLK:
1294                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1295                 if (ret)
1296                         goto print_clk_out;
1297
1298                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1299                 if (ret)
1300                         goto print_clk_out;
1301
1302                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1303                         for (i = 0; i < count; i++) {
1304                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1305                                 if (ret)
1306                                         goto print_clk_out;
1307
1308                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1309                                                 cur_value == value ? "*" : "");
1310                         }
1311                 } else {
1312                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1313                         if (ret)
1314                                 goto print_clk_out;
1315                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1316                         if (ret)
1317                                 goto print_clk_out;
1318
1319                         freq_values[1] = cur_value;
1320                         mark_index = cur_value == freq_values[0] ? 0 :
1321                                      cur_value == freq_values[2] ? 2 : 1;
1322
1323                         count = 3;
1324                         if (mark_index != 1) {
1325                                 count = 2;
1326                                 freq_values[1] = freq_values[2];
1327                         }
1328
1329                         for (i = 0; i < count; i++) {
1330                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1331                                                 cur_value  == freq_values[i] ? "*" : "");
1332                         }
1333
1334                 }
1335                 break;
1336         case SMU_PCIE:
1337                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1338                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1339                 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1340                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1341                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1342                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1343                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1344                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1345                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1346                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1347                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1348                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1349                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1350                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1351                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1352                                         table_member[i],
1353                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1354                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1355                                         "*" : "");
1356                 break;
1357         case SMU_OD_SCLK:
1358                 if (!smu->od_enabled || !od_table || !od_settings)
1359                         break;
1360
1361                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1362                         break;
1363
1364                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1365                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1366                 break;
1367
1368         case SMU_OD_MCLK:
1369                 if (!smu->od_enabled || !od_table || !od_settings)
1370                         break;
1371
1372                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1373                         break;
1374
1375                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1376                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1377                 break;
1378
1379         case SMU_OD_VDDGFX_OFFSET:
1380                 if (!smu->od_enabled || !od_table || !od_settings)
1381                         break;
1382
1383                 /*
1384                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
1385                  * and onwards SMU firmwares.
1386                  */
1387                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1388                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1389                      (smu_version < 0x003a2900))
1390                         break;
1391
1392                 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1393                 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1394                 break;
1395
1396         case SMU_OD_RANGE:
1397                 if (!smu->od_enabled || !od_table || !od_settings)
1398                         break;
1399
1400                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1401
1402                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1403                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1404                                                             &min_value, NULL);
1405                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1406                                                             NULL, &max_value);
1407                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1408                                         min_value, max_value);
1409                 }
1410
1411                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1412                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1413                                                             &min_value, NULL);
1414                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1415                                                             NULL, &max_value);
1416                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1417                                         min_value, max_value);
1418                 }
1419                 break;
1420
1421         default:
1422                 break;
1423         }
1424
1425 print_clk_out:
1426         return size;
1427 }
1428
1429 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1430                                    enum smu_clk_type clk_type, uint32_t mask)
1431 {
1432         int ret = 0;
1433         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1434
1435         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1436         soft_max_level = mask ? (fls(mask) - 1) : 0;
1437
1438         switch (clk_type) {
1439         case SMU_GFXCLK:
1440         case SMU_SCLK:
1441         case SMU_SOCCLK:
1442         case SMU_MCLK:
1443         case SMU_UCLK:
1444         case SMU_FCLK:
1445                 /* There is only 2 levels for fine grained DPM */
1446                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1447                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1448                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1449                 }
1450
1451                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1452                 if (ret)
1453                         goto forec_level_out;
1454
1455                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1456                 if (ret)
1457                         goto forec_level_out;
1458
1459                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1460                 if (ret)
1461                         goto forec_level_out;
1462                 break;
1463         case SMU_DCEFCLK:
1464                 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1465                 break;
1466         default:
1467                 break;
1468         }
1469
1470 forec_level_out:
1471         return 0;
1472 }
1473
1474 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1475 {
1476         struct smu_11_0_dpm_context *dpm_context =
1477                                 smu->smu_dpm.dpm_context;
1478         struct smu_11_0_dpm_table *gfx_table =
1479                                 &dpm_context->dpm_tables.gfx_table;
1480         struct smu_11_0_dpm_table *mem_table =
1481                                 &dpm_context->dpm_tables.uclk_table;
1482         struct smu_11_0_dpm_table *soc_table =
1483                                 &dpm_context->dpm_tables.soc_table;
1484         struct smu_umd_pstate_table *pstate_table =
1485                                 &smu->pstate_table;
1486         struct amdgpu_device *adev = smu->adev;
1487
1488         pstate_table->gfxclk_pstate.min = gfx_table->min;
1489         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1490
1491         pstate_table->uclk_pstate.min = mem_table->min;
1492         pstate_table->uclk_pstate.peak = mem_table->max;
1493
1494         pstate_table->socclk_pstate.min = soc_table->min;
1495         pstate_table->socclk_pstate.peak = soc_table->max;
1496
1497         switch (adev->ip_versions[MP1_HWIP][0]) {
1498         case IP_VERSION(11, 0, 7):
1499         case IP_VERSION(11, 0, 11):
1500                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1501                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1502                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1503                 break;
1504         case IP_VERSION(11, 0, 12):
1505                 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1506                 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1507                 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1508                 break;
1509         case IP_VERSION(11, 0, 13):
1510                 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1511                 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1512                 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1513                 break;
1514         default:
1515                 break;
1516         }
1517
1518         return 0;
1519 }
1520
1521 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1522 {
1523         int ret = 0;
1524         uint32_t max_freq = 0;
1525
1526         /* Sienna_Cichlid do not support to change display num currently */
1527         return 0;
1528 #if 0
1529         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1530         if (ret)
1531                 return ret;
1532 #endif
1533
1534         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1535                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1536                 if (ret)
1537                         return ret;
1538                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1539                 if (ret)
1540                         return ret;
1541         }
1542
1543         return ret;
1544 }
1545
1546 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1547 {
1548         int ret = 0;
1549
1550         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1551             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1552             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1553 #if 0
1554                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1555                                                   smu->display_config->num_display,
1556                                                   NULL);
1557 #endif
1558                 if (ret)
1559                         return ret;
1560         }
1561
1562         return ret;
1563 }
1564
1565 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1566 {
1567         int ret = 0;
1568         uint64_t feature_enabled;
1569
1570         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1571         if (ret)
1572                 return false;
1573
1574         return !!(feature_enabled & SMC_DPM_FEATURE);
1575 }
1576
1577 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1578                                             uint32_t *speed)
1579 {
1580         if (!speed)
1581                 return -EINVAL;
1582
1583         /*
1584          * For Sienna_Cichlid and later, the fan speed(rpm) reported
1585          * by pmfw is always trustable(even when the fan control feature
1586          * disabled or 0 RPM kicked in).
1587          */
1588         return sienna_cichlid_get_smu_metrics_data(smu,
1589                                                    METRICS_CURR_FANSPEED,
1590                                                    speed);
1591 }
1592
1593 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1594 {
1595         uint16_t *table_member;
1596
1597         GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1598         smu->fan_max_rpm = *table_member;
1599
1600         return 0;
1601 }
1602
1603 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1604 {
1605         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1606         DpmActivityMonitorCoeffInt_t *activity_monitor =
1607                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1608         uint32_t i, size = 0;
1609         int16_t workload_type = 0;
1610         static const char *title[] = {
1611                         "PROFILE_INDEX(NAME)",
1612                         "CLOCK_TYPE(NAME)",
1613                         "FPS",
1614                         "MinFreqType",
1615                         "MinActiveFreqType",
1616                         "MinActiveFreq",
1617                         "BoosterFreqType",
1618                         "BoosterFreq",
1619                         "PD_Data_limit_c",
1620                         "PD_Data_error_coeff",
1621                         "PD_Data_error_rate_coeff"};
1622         int result = 0;
1623
1624         if (!buf)
1625                 return -EINVAL;
1626
1627         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1628                         title[0], title[1], title[2], title[3], title[4], title[5],
1629                         title[6], title[7], title[8], title[9], title[10]);
1630
1631         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1632                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1633                 workload_type = smu_cmn_to_asic_specific_index(smu,
1634                                                                CMN2ASIC_MAPPING_WORKLOAD,
1635                                                                i);
1636                 if (workload_type < 0)
1637                         return -EINVAL;
1638
1639                 result = smu_cmn_update_table(smu,
1640                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1641                                           (void *)(&activity_monitor_external), false);
1642                 if (result) {
1643                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1644                         return result;
1645                 }
1646
1647                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1648                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1649
1650                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1651                         " ",
1652                         0,
1653                         "GFXCLK",
1654                         activity_monitor->Gfx_FPS,
1655                         activity_monitor->Gfx_MinFreqStep,
1656                         activity_monitor->Gfx_MinActiveFreqType,
1657                         activity_monitor->Gfx_MinActiveFreq,
1658                         activity_monitor->Gfx_BoosterFreqType,
1659                         activity_monitor->Gfx_BoosterFreq,
1660                         activity_monitor->Gfx_PD_Data_limit_c,
1661                         activity_monitor->Gfx_PD_Data_error_coeff,
1662                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1663
1664                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1665                         " ",
1666                         1,
1667                         "SOCCLK",
1668                         activity_monitor->Fclk_FPS,
1669                         activity_monitor->Fclk_MinFreqStep,
1670                         activity_monitor->Fclk_MinActiveFreqType,
1671                         activity_monitor->Fclk_MinActiveFreq,
1672                         activity_monitor->Fclk_BoosterFreqType,
1673                         activity_monitor->Fclk_BoosterFreq,
1674                         activity_monitor->Fclk_PD_Data_limit_c,
1675                         activity_monitor->Fclk_PD_Data_error_coeff,
1676                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1677
1678                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1679                         " ",
1680                         2,
1681                         "MEMLK",
1682                         activity_monitor->Mem_FPS,
1683                         activity_monitor->Mem_MinFreqStep,
1684                         activity_monitor->Mem_MinActiveFreqType,
1685                         activity_monitor->Mem_MinActiveFreq,
1686                         activity_monitor->Mem_BoosterFreqType,
1687                         activity_monitor->Mem_BoosterFreq,
1688                         activity_monitor->Mem_PD_Data_limit_c,
1689                         activity_monitor->Mem_PD_Data_error_coeff,
1690                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1691         }
1692
1693         return size;
1694 }
1695
1696 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1697 {
1698
1699         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1700         DpmActivityMonitorCoeffInt_t *activity_monitor =
1701                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1702         int workload_type, ret = 0;
1703
1704         smu->power_profile_mode = input[size];
1705
1706         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1707                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1708                 return -EINVAL;
1709         }
1710
1711         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1712
1713                 ret = smu_cmn_update_table(smu,
1714                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1715                                        (void *)(&activity_monitor_external), false);
1716                 if (ret) {
1717                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1718                         return ret;
1719                 }
1720
1721                 switch (input[0]) {
1722                 case 0: /* Gfxclk */
1723                         activity_monitor->Gfx_FPS = input[1];
1724                         activity_monitor->Gfx_MinFreqStep = input[2];
1725                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1726                         activity_monitor->Gfx_MinActiveFreq = input[4];
1727                         activity_monitor->Gfx_BoosterFreqType = input[5];
1728                         activity_monitor->Gfx_BoosterFreq = input[6];
1729                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1730                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1731                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1732                         break;
1733                 case 1: /* Socclk */
1734                         activity_monitor->Fclk_FPS = input[1];
1735                         activity_monitor->Fclk_MinFreqStep = input[2];
1736                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1737                         activity_monitor->Fclk_MinActiveFreq = input[4];
1738                         activity_monitor->Fclk_BoosterFreqType = input[5];
1739                         activity_monitor->Fclk_BoosterFreq = input[6];
1740                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1741                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1742                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1743                         break;
1744                 case 2: /* Memlk */
1745                         activity_monitor->Mem_FPS = input[1];
1746                         activity_monitor->Mem_MinFreqStep = input[2];
1747                         activity_monitor->Mem_MinActiveFreqType = input[3];
1748                         activity_monitor->Mem_MinActiveFreq = input[4];
1749                         activity_monitor->Mem_BoosterFreqType = input[5];
1750                         activity_monitor->Mem_BoosterFreq = input[6];
1751                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1752                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1753                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1754                         break;
1755                 }
1756
1757                 ret = smu_cmn_update_table(smu,
1758                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1759                                        (void *)(&activity_monitor_external), true);
1760                 if (ret) {
1761                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1762                         return ret;
1763                 }
1764         }
1765
1766         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1767         workload_type = smu_cmn_to_asic_specific_index(smu,
1768                                                        CMN2ASIC_MAPPING_WORKLOAD,
1769                                                        smu->power_profile_mode);
1770         if (workload_type < 0)
1771                 return -EINVAL;
1772         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1773                                     1 << workload_type, NULL);
1774
1775         return ret;
1776 }
1777
1778 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1779 {
1780         struct smu_clocks min_clocks = {0};
1781         struct pp_display_clock_request clock_req;
1782         int ret = 0;
1783
1784         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1785         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1786         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1787
1788         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1789                 clock_req.clock_type = amd_pp_dcef_clock;
1790                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1791
1792                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1793                 if (!ret) {
1794                         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1795                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1796                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1797                                                                   min_clocks.dcef_clock_in_sr/100,
1798                                                                   NULL);
1799                                 if (ret) {
1800                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1801                                         return ret;
1802                                 }
1803                         }
1804                 } else {
1805                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1806                 }
1807         }
1808
1809         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1810                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1811                 if (ret) {
1812                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1813                         return ret;
1814                 }
1815         }
1816
1817         return 0;
1818 }
1819
1820 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1821                                                struct pp_smu_wm_range_sets *clock_ranges)
1822 {
1823         Watermarks_t *table = smu->smu_table.watermarks_table;
1824         int ret = 0;
1825         int i;
1826
1827         if (clock_ranges) {
1828                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1829                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1830                         return -EINVAL;
1831
1832                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1833                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1834                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1835                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1836                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1837                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1838                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1839                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1840                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1841
1842                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1843                                 clock_ranges->reader_wm_sets[i].wm_inst;
1844                 }
1845
1846                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1847                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1848                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1849                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1850                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1851                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1852                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1853                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1854                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1855
1856                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1857                                 clock_ranges->writer_wm_sets[i].wm_inst;
1858                 }
1859
1860                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1861         }
1862
1863         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1864              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1865                 ret = smu_cmn_write_watermarks_table(smu);
1866                 if (ret) {
1867                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1868                         return ret;
1869                 }
1870                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1871         }
1872
1873         return 0;
1874 }
1875
1876 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1877                                  enum amd_pp_sensors sensor,
1878                                  void *data, uint32_t *size)
1879 {
1880         int ret = 0;
1881         uint16_t *temp;
1882         struct amdgpu_device *adev = smu->adev;
1883
1884         if(!data || !size)
1885                 return -EINVAL;
1886
1887         switch (sensor) {
1888         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1889                 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1890                 *(uint16_t *)data = *temp;
1891                 *size = 4;
1892                 break;
1893         case AMDGPU_PP_SENSOR_MEM_LOAD:
1894                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1895                                                           METRICS_AVERAGE_MEMACTIVITY,
1896                                                           (uint32_t *)data);
1897                 *size = 4;
1898                 break;
1899         case AMDGPU_PP_SENSOR_GPU_LOAD:
1900                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1901                                                           METRICS_AVERAGE_GFXACTIVITY,
1902                                                           (uint32_t *)data);
1903                 *size = 4;
1904                 break;
1905         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1906                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1907                                                           METRICS_AVERAGE_SOCKETPOWER,
1908                                                           (uint32_t *)data);
1909                 *size = 4;
1910                 break;
1911         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1912                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1913                                                           METRICS_TEMPERATURE_HOTSPOT,
1914                                                           (uint32_t *)data);
1915                 *size = 4;
1916                 break;
1917         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1918                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1919                                                           METRICS_TEMPERATURE_EDGE,
1920                                                           (uint32_t *)data);
1921                 *size = 4;
1922                 break;
1923         case AMDGPU_PP_SENSOR_MEM_TEMP:
1924                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1925                                                           METRICS_TEMPERATURE_MEM,
1926                                                           (uint32_t *)data);
1927                 *size = 4;
1928                 break;
1929         case AMDGPU_PP_SENSOR_GFX_MCLK:
1930                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1931                                                           METRICS_CURR_UCLK,
1932                                                           (uint32_t *)data);
1933                 *(uint32_t *)data *= 100;
1934                 *size = 4;
1935                 break;
1936         case AMDGPU_PP_SENSOR_GFX_SCLK:
1937                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1938                                                           METRICS_AVERAGE_GFXCLK,
1939                                                           (uint32_t *)data);
1940                 *(uint32_t *)data *= 100;
1941                 *size = 4;
1942                 break;
1943         case AMDGPU_PP_SENSOR_VDDGFX:
1944                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1945                 *size = 4;
1946                 break;
1947         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1948                 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1949                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1950                                                 METRICS_SS_APU_SHARE, (uint32_t *)data);
1951                         *size = 4;
1952                 } else {
1953                         ret = -EOPNOTSUPP;
1954                 }
1955                 break;
1956         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1957                 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1958                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1959                                                 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1960                         *size = 4;
1961                 } else {
1962                         ret = -EOPNOTSUPP;
1963                 }
1964                 break;
1965         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1966         default:
1967                 ret = -EOPNOTSUPP;
1968                 break;
1969         }
1970
1971         return ret;
1972 }
1973
1974 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1975 {
1976         struct amdgpu_device *adev = smu->adev;
1977         uint32_t upper32 = 0, lower32 = 0;
1978
1979         /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1980         if (smu->smc_fw_version < 0x3A5300 ||
1981             smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1982                 return;
1983
1984         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1985                 goto out;
1986         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1987                 goto out;
1988
1989 out:
1990
1991         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1992         if (adev->serial[0] == '\0')
1993                 sprintf(adev->serial, "%016llx", adev->unique_id);
1994 }
1995
1996 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1997 {
1998         uint32_t num_discrete_levels = 0;
1999         uint16_t *dpm_levels = NULL;
2000         uint16_t i = 0;
2001         struct smu_table_context *table_context = &smu->smu_table;
2002         DpmDescriptor_t *table_member1;
2003         uint16_t *table_member2;
2004
2005         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2006                 return -EINVAL;
2007
2008         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2009         num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2010         GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2011         dpm_levels = table_member2;
2012
2013         if (num_discrete_levels == 0 || dpm_levels == NULL)
2014                 return -EINVAL;
2015
2016         *num_states = num_discrete_levels;
2017         for (i = 0; i < num_discrete_levels; i++) {
2018                 /* convert to khz */
2019                 *clocks_in_khz = (*dpm_levels) * 1000;
2020                 clocks_in_khz++;
2021                 dpm_levels++;
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2028                                                 struct smu_temperature_range *range)
2029 {
2030         struct smu_table_context *table_context = &smu->smu_table;
2031         struct smu_11_0_7_powerplay_table *powerplay_table =
2032                                 table_context->power_play_table;
2033         uint16_t *table_member;
2034         uint16_t temp_edge, temp_hotspot, temp_mem;
2035
2036         if (!range)
2037                 return -EINVAL;
2038
2039         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2040
2041         GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2042         temp_edge = table_member[TEMP_EDGE];
2043         temp_hotspot = table_member[TEMP_HOTSPOT];
2044         temp_mem = table_member[TEMP_MEM];
2045
2046         range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2047         range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2048                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2049         range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2050         range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2051                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2052         range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2053         range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2054                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2055
2056         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2057
2058         return 0;
2059 }
2060
2061 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2062                                                 bool disable_memory_clock_switch)
2063 {
2064         int ret = 0;
2065         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2066                 (struct smu_11_0_max_sustainable_clocks *)
2067                         smu->smu_table.max_sustainable_clocks;
2068         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2069         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2070
2071         if(smu->disable_uclk_switch == disable_memory_clock_switch)
2072                 return 0;
2073
2074         if(disable_memory_clock_switch)
2075                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2076         else
2077                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2078
2079         if(!ret)
2080                 smu->disable_uclk_switch = disable_memory_clock_switch;
2081
2082         return ret;
2083 }
2084
2085 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2086                                          uint32_t pcie_gen_cap,
2087                                          uint32_t pcie_width_cap)
2088 {
2089         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2090         struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2091         u32 smu_pcie_arg;
2092         int ret, i;
2093
2094         /* PCIE gen speed and lane width override */
2095         if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2096                 if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap)
2097                         pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1];
2098
2099                 if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap)
2100                         pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1];
2101
2102                 /* Force all levels to use the same settings */
2103                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2104                         pcie_table->pcie_gen[i] = pcie_gen_cap;
2105                         pcie_table->pcie_lane[i] = pcie_width_cap;
2106                 }
2107         } else {
2108                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2109                         if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2110                                 pcie_table->pcie_gen[i] = pcie_gen_cap;
2111                         if (pcie_table->pcie_lane[i] > pcie_width_cap)
2112                                 pcie_table->pcie_lane[i] = pcie_width_cap;
2113                 }
2114         }
2115
2116         for (i = 0; i < NUM_LINK_LEVELS; i++) {
2117                 smu_pcie_arg = (i << 16 |
2118                                 pcie_table->pcie_gen[i] << 8 |
2119                                 pcie_table->pcie_lane[i]);
2120
2121                 ret = smu_cmn_send_smc_msg_with_param(smu,
2122                                 SMU_MSG_OverridePcieParameters,
2123                                 smu_pcie_arg,
2124                                 NULL);
2125                 if (ret)
2126                         return ret;
2127         }
2128
2129         return 0;
2130 }
2131
2132 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2133                                 enum smu_clk_type clk_type,
2134                                 uint32_t *min, uint32_t *max)
2135 {
2136         return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2137 }
2138
2139 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2140                                          OverDriveTable_t *od_table)
2141 {
2142         struct amdgpu_device *adev = smu->adev;
2143         uint32_t smu_version;
2144
2145         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2146                                                           od_table->GfxclkFmax);
2147         dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2148                                                         od_table->UclkFmax);
2149
2150         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2151         if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2152                (smu_version < 0x003a2900)))
2153                 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2154 }
2155
2156 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2157 {
2158         OverDriveTable_t *od_table =
2159                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2160         OverDriveTable_t *boot_od_table =
2161                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2162         OverDriveTable_t *user_od_table =
2163                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2164         OverDriveTable_t user_od_table_bak;
2165         int ret = 0;
2166
2167         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2168                                    0, (void *)boot_od_table, false);
2169         if (ret) {
2170                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2171                 return ret;
2172         }
2173
2174         sienna_cichlid_dump_od_table(smu, boot_od_table);
2175
2176         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2177
2178         /*
2179          * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2180          * but we have to preserve user defined values in "user_od_table".
2181          */
2182         if (!smu->adev->in_suspend) {
2183                 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2184                 smu->user_dpm_profile.user_od = false;
2185         } else if (smu->user_dpm_profile.user_od) {
2186                 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2187                 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2188                 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2189                 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2190                 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2191                 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2192                 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2193         }
2194
2195         return 0;
2196 }
2197
2198 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2199                                                  struct smu_11_0_7_overdrive_table *od_table,
2200                                                  enum SMU_11_0_7_ODSETTING_ID setting,
2201                                                  uint32_t value)
2202 {
2203         if (value < od_table->min[setting]) {
2204                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2205                                           setting, value, od_table->min[setting]);
2206                 return -EINVAL;
2207         }
2208         if (value > od_table->max[setting]) {
2209                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2210                                           setting, value, od_table->max[setting]);
2211                 return -EINVAL;
2212         }
2213
2214         return 0;
2215 }
2216
2217 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2218                                             enum PP_OD_DPM_TABLE_COMMAND type,
2219                                             long input[], uint32_t size)
2220 {
2221         struct smu_table_context *table_context = &smu->smu_table;
2222         OverDriveTable_t *od_table =
2223                 (OverDriveTable_t *)table_context->overdrive_table;
2224         struct smu_11_0_7_overdrive_table *od_settings =
2225                 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2226         struct amdgpu_device *adev = smu->adev;
2227         enum SMU_11_0_7_ODSETTING_ID freq_setting;
2228         uint16_t *freq_ptr;
2229         int i, ret = 0;
2230         uint32_t smu_version;
2231
2232         if (!smu->od_enabled) {
2233                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2234                 return -EINVAL;
2235         }
2236
2237         if (!smu->od_settings) {
2238                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2239                 return -ENOENT;
2240         }
2241
2242         if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2243                 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2244                 return -EINVAL;
2245         }
2246
2247         switch (type) {
2248         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2249                 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2250                                                             SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2251                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2252                         return -ENOTSUPP;
2253                 }
2254
2255                 for (i = 0; i < size; i += 2) {
2256                         if (i + 2 > size) {
2257                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2258                                 return -EINVAL;
2259                         }
2260
2261                         switch (input[i]) {
2262                         case 0:
2263                                 if (input[i + 1] > od_table->GfxclkFmax) {
2264                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2265                                                 input[i + 1], od_table->GfxclkFmax);
2266                                         return -EINVAL;
2267                                 }
2268
2269                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2270                                 freq_ptr = &od_table->GfxclkFmin;
2271                                 break;
2272
2273                         case 1:
2274                                 if (input[i + 1] < od_table->GfxclkFmin) {
2275                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2276                                                 input[i + 1], od_table->GfxclkFmin);
2277                                         return -EINVAL;
2278                                 }
2279
2280                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2281                                 freq_ptr = &od_table->GfxclkFmax;
2282                                 break;
2283
2284                         default:
2285                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2286                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2287                                 return -EINVAL;
2288                         }
2289
2290                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2291                                                                     freq_setting, input[i + 1]);
2292                         if (ret)
2293                                 return ret;
2294
2295                         *freq_ptr = (uint16_t)input[i + 1];
2296                 }
2297                 break;
2298
2299         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2300                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2301                         dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2302                         return -ENOTSUPP;
2303                 }
2304
2305                 for (i = 0; i < size; i += 2) {
2306                         if (i + 2 > size) {
2307                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2308                                 return -EINVAL;
2309                         }
2310
2311                         switch (input[i]) {
2312                         case 0:
2313                                 if (input[i + 1] > od_table->UclkFmax) {
2314                                         dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2315                                                 input[i + 1], od_table->UclkFmax);
2316                                         return -EINVAL;
2317                                 }
2318
2319                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2320                                 freq_ptr = &od_table->UclkFmin;
2321                                 break;
2322
2323                         case 1:
2324                                 if (input[i + 1] < od_table->UclkFmin) {
2325                                         dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2326                                                 input[i + 1], od_table->UclkFmin);
2327                                         return -EINVAL;
2328                                 }
2329
2330                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2331                                 freq_ptr = &od_table->UclkFmax;
2332                                 break;
2333
2334                         default:
2335                                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2336                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2337                                 return -EINVAL;
2338                         }
2339
2340                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2341                                                                     freq_setting, input[i + 1]);
2342                         if (ret)
2343                                 return ret;
2344
2345                         *freq_ptr = (uint16_t)input[i + 1];
2346                 }
2347                 break;
2348
2349         case PP_OD_RESTORE_DEFAULT_TABLE:
2350                 memcpy(table_context->overdrive_table,
2351                                 table_context->boot_overdrive_table,
2352                                 sizeof(OverDriveTable_t));
2353                 fallthrough;
2354
2355         case PP_OD_COMMIT_DPM_TABLE:
2356                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2357                         sienna_cichlid_dump_od_table(smu, od_table);
2358                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2359                         if (ret) {
2360                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2361                                 return ret;
2362                         }
2363                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2364                         smu->user_dpm_profile.user_od = true;
2365
2366                         if (!memcmp(table_context->user_overdrive_table,
2367                                     table_context->boot_overdrive_table,
2368                                     sizeof(OverDriveTable_t)))
2369                                 smu->user_dpm_profile.user_od = false;
2370                 }
2371                 break;
2372
2373         case PP_OD_EDIT_VDDGFX_OFFSET:
2374                 if (size != 1) {
2375                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2376                         return -EINVAL;
2377                 }
2378
2379                 /*
2380                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
2381                  * and onwards SMU firmwares.
2382                  */
2383                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2384                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2385                      (smu_version < 0x003a2900)) {
2386                         dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2387                                                 "only by 58.41.0 and onwards SMU firmwares!\n");
2388                         return -EOPNOTSUPP;
2389                 }
2390
2391                 od_table->VddGfxOffset = (int16_t)input[0];
2392
2393                 sienna_cichlid_dump_od_table(smu, od_table);
2394                 break;
2395
2396         default:
2397                 return -ENOSYS;
2398         }
2399
2400         return ret;
2401 }
2402
2403 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2404 {
2405         struct smu_table_context *table_context = &smu->smu_table;
2406         OverDriveTable_t *od_table = table_context->overdrive_table;
2407         OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2408         int res;
2409
2410         res = smu_v11_0_restore_user_od_settings(smu);
2411         if (res == 0)
2412                 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2413
2414         return res;
2415 }
2416
2417 static int sienna_cichlid_run_btc(struct smu_context *smu)
2418 {
2419         int res;
2420
2421         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2422         if (res)
2423                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2424
2425         return res;
2426 }
2427
2428 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2429 {
2430         struct amdgpu_device *adev = smu->adev;
2431
2432         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2433                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2434         else
2435                 return smu_v11_0_baco_enter(smu);
2436 }
2437
2438 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2439 {
2440         struct amdgpu_device *adev = smu->adev;
2441
2442         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2443                 /* Wait for PMFW handling for the Dstate change */
2444                 msleep(10);
2445                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2446         } else {
2447                 return smu_v11_0_baco_exit(smu);
2448         }
2449 }
2450
2451 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2452 {
2453         struct amdgpu_device *adev = smu->adev;
2454         uint32_t val;
2455         u32 smu_version;
2456
2457         /**
2458          * SRIOV env will not support SMU mode1 reset
2459          * PM FW support mode1 reset from 58.26
2460          */
2461         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2462         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2463                 return false;
2464
2465         /**
2466          * mode1 reset relies on PSP, so we should check if
2467          * PSP is alive.
2468          */
2469         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2470         return val != 0x0;
2471 }
2472
2473 static void beige_goby_dump_pptable(struct smu_context *smu)
2474 {
2475         struct smu_table_context *table_context = &smu->smu_table;
2476         PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2477         int i;
2478
2479         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2480
2481         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2482         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2483         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2484
2485         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2486                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2487                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2488                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2489                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2490         }
2491
2492         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2493                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2494                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2495         }
2496
2497         for (i = 0; i < TEMP_COUNT; i++) {
2498                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2499         }
2500
2501         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2502         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2503         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2504         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2505         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2506
2507         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2508         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2509                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2510                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2511         }
2512         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2513
2514         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2515
2516         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2517         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2518         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2519         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2520
2521         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2522
2523         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2524
2525         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2526         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2527         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2528         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2529
2530         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2531         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2532
2533         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2534         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2535         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2536         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2537         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2538         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2539         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2540         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2541
2542         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2543                         "  .VoltageMode          = 0x%02x\n"
2544                         "  .SnapToDiscrete       = 0x%02x\n"
2545                         "  .NumDiscreteLevels    = 0x%02x\n"
2546                         "  .padding              = 0x%02x\n"
2547                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2548                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2549                         "  .SsFmin               = 0x%04x\n"
2550                         "  .Padding_16           = 0x%04x\n",
2551                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2552                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2553                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2554                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2555                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2556                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2557                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2558                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2559                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2560                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2561                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2562
2563         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2564                         "  .VoltageMode          = 0x%02x\n"
2565                         "  .SnapToDiscrete       = 0x%02x\n"
2566                         "  .NumDiscreteLevels    = 0x%02x\n"
2567                         "  .padding              = 0x%02x\n"
2568                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2569                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2570                         "  .SsFmin               = 0x%04x\n"
2571                         "  .Padding_16           = 0x%04x\n",
2572                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2573                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2574                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2575                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2576                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2577                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2578                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2579                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2580                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2581                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2582                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2583
2584         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2585                         "  .VoltageMode          = 0x%02x\n"
2586                         "  .SnapToDiscrete       = 0x%02x\n"
2587                         "  .NumDiscreteLevels    = 0x%02x\n"
2588                         "  .padding              = 0x%02x\n"
2589                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2590                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2591                         "  .SsFmin               = 0x%04x\n"
2592                         "  .Padding_16           = 0x%04x\n",
2593                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2594                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2595                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2596                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2597                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2598                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2599                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2600                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2601                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2602                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2603                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2604
2605         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2606                         "  .VoltageMode          = 0x%02x\n"
2607                         "  .SnapToDiscrete       = 0x%02x\n"
2608                         "  .NumDiscreteLevels    = 0x%02x\n"
2609                         "  .padding              = 0x%02x\n"
2610                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2611                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2612                         "  .SsFmin               = 0x%04x\n"
2613                         "  .Padding_16           = 0x%04x\n",
2614                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2615                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2616                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2617                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2618                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2619                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2620                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2621                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2622                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2623                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2624                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2625
2626         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2627                         "  .VoltageMode          = 0x%02x\n"
2628                         "  .SnapToDiscrete       = 0x%02x\n"
2629                         "  .NumDiscreteLevels    = 0x%02x\n"
2630                         "  .padding              = 0x%02x\n"
2631                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2632                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2633                         "  .SsFmin               = 0x%04x\n"
2634                         "  .Padding_16           = 0x%04x\n",
2635                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2636                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2637                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2638                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2639                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2640                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2641                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2642                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2643                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2644                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2645                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2646
2647         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2648                         "  .VoltageMode          = 0x%02x\n"
2649                         "  .SnapToDiscrete       = 0x%02x\n"
2650                         "  .NumDiscreteLevels    = 0x%02x\n"
2651                         "  .padding              = 0x%02x\n"
2652                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2653                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2654                         "  .SsFmin               = 0x%04x\n"
2655                         "  .Padding_16           = 0x%04x\n",
2656                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2657                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2658                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2659                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2660                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2661                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2662                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2663                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2664                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2665                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2666                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2667
2668         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2669                         "  .VoltageMode          = 0x%02x\n"
2670                         "  .SnapToDiscrete       = 0x%02x\n"
2671                         "  .NumDiscreteLevels    = 0x%02x\n"
2672                         "  .padding              = 0x%02x\n"
2673                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2674                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2675                         "  .SsFmin               = 0x%04x\n"
2676                         "  .Padding_16           = 0x%04x\n",
2677                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2678                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2679                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2680                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2681                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2682                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2683                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2684                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2685                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2686                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2687                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2688
2689         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2690                         "  .VoltageMode          = 0x%02x\n"
2691                         "  .SnapToDiscrete       = 0x%02x\n"
2692                         "  .NumDiscreteLevels    = 0x%02x\n"
2693                         "  .padding              = 0x%02x\n"
2694                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2695                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2696                         "  .SsFmin               = 0x%04x\n"
2697                         "  .Padding_16           = 0x%04x\n",
2698                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2699                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2700                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2701                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2702                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2703                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2704                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2705                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2706                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2707                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2708                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2709
2710         dev_info(smu->adev->dev, "FreqTableGfx\n");
2711         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2712                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2713
2714         dev_info(smu->adev->dev, "FreqTableVclk\n");
2715         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2716                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2717
2718         dev_info(smu->adev->dev, "FreqTableDclk\n");
2719         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2720                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2721
2722         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2723         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2724                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2725
2726         dev_info(smu->adev->dev, "FreqTableUclk\n");
2727         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2728                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2729
2730         dev_info(smu->adev->dev, "FreqTableFclk\n");
2731         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2732                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2733
2734         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2735         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2736         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2737         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2738         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2739         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2740         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2741         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2742         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2743
2744         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2745         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2746                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2747
2748         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2749         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2750
2751         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2752         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2753                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2754
2755         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2756         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2757                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2758
2759         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2760         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2761                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2762
2763         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2764         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2765                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2766
2767         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2768         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2769         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2770         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2771         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2772
2773         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2774
2775         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2776         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2777         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2778         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2779         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2780         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2781         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2782         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2783         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2784         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2785         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2786
2787         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2788         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2789         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2790         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2791         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2792         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2793
2794         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2795         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2796         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2797         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2798         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2799
2800         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2801         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2802                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2803
2804         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2805         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2806         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2807         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2808
2809         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2810         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2811                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2812
2813         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2814         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2815                 pptable->UclkDpmSrcFreqRange.Fmin);
2816         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2817                 pptable->UclkDpmSrcFreqRange.Fmax);
2818         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2819         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2820                 pptable->UclkDpmTargFreqRange.Fmin);
2821         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2822                 pptable->UclkDpmTargFreqRange.Fmax);
2823         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2824         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2825
2826         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2827         for (i = 0; i < NUM_LINK_LEVELS; i++)
2828                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2829
2830         dev_info(smu->adev->dev, "PcieLaneCount\n");
2831         for (i = 0; i < NUM_LINK_LEVELS; i++)
2832                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2833
2834         dev_info(smu->adev->dev, "LclkFreq\n");
2835         for (i = 0; i < NUM_LINK_LEVELS; i++)
2836                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2837
2838         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2839         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2840
2841         dev_info(smu->adev->dev, "FanGain\n");
2842         for (i = 0; i < TEMP_COUNT; i++)
2843                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2844
2845         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2846         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2847         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2848         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2849         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2850         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2851         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2852         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2853         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2854         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2855         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2856         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2857
2858         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2859         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2860         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2861         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2862
2863         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2864         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2865         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2866         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2867
2868         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2869                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2870                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2871                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2872         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2873                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2874                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2875                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2876         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2877                         pptable->dBtcGbGfxPll.a,
2878                         pptable->dBtcGbGfxPll.b,
2879                         pptable->dBtcGbGfxPll.c);
2880         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2881                         pptable->dBtcGbGfxDfll.a,
2882                         pptable->dBtcGbGfxDfll.b,
2883                         pptable->dBtcGbGfxDfll.c);
2884         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2885                         pptable->dBtcGbSoc.a,
2886                         pptable->dBtcGbSoc.b,
2887                         pptable->dBtcGbSoc.c);
2888         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2889                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2890                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2891         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2892                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2893                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2894
2895         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2896         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2897                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2898                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2899                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2900                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2901         }
2902
2903         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2904                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2905                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2906                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2907         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2908                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2909                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2910                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2911
2912         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2913         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2914
2915         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2916         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2917         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2918         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2919
2920         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2921         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2922         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2923         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2924
2925         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2926         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2927
2928         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2929         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2930                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2931         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2932         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2933
2934         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2935         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2936                         pptable->ReservedEquation0.a,
2937                         pptable->ReservedEquation0.b,
2938                         pptable->ReservedEquation0.c);
2939         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2940                         pptable->ReservedEquation1.a,
2941                         pptable->ReservedEquation1.b,
2942                         pptable->ReservedEquation1.c);
2943         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2944                         pptable->ReservedEquation2.a,
2945                         pptable->ReservedEquation2.b,
2946                         pptable->ReservedEquation2.c);
2947         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2948                         pptable->ReservedEquation3.a,
2949                         pptable->ReservedEquation3.b,
2950                         pptable->ReservedEquation3.c);
2951
2952         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2953         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2954         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2955         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2956         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2957         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2958         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2959         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2960
2961         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2962         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2963         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2964         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2965         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2966         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2967
2968         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2969                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2970                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2971                                 pptable->I2cControllers[i].Enabled);
2972                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2973                                 pptable->I2cControllers[i].Speed);
2974                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2975                                 pptable->I2cControllers[i].SlaveAddress);
2976                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2977                                 pptable->I2cControllers[i].ControllerPort);
2978                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2979                                 pptable->I2cControllers[i].ControllerName);
2980                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2981                                 pptable->I2cControllers[i].ThermalThrotter);
2982                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2983                                 pptable->I2cControllers[i].I2cProtocol);
2984                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2985                                 pptable->I2cControllers[i].PaddingConfig);
2986         }
2987
2988         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2989         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2990         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2991         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2992
2993         dev_info(smu->adev->dev, "Board Parameters:\n");
2994         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2995         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2996         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2997         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2998         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2999         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3000         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3001         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3002
3003         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3004         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3005         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3006
3007         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3008         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3009         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3010
3011         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3012         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3013         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3014
3015         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3016         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3017         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3018
3019         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3020
3021         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3022         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3023         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3024         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3025         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3026         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3027         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3028         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3029         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3030         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3031         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3032         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3033         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3034         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3035         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3036         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3037
3038         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3039         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3040         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3041
3042         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3043         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3044         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3045
3046         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3047         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3048
3049         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3050         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3051         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3052
3053         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3054         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3055         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3056         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3057         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3058
3059         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3060         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3061
3062         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3063         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3064                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3065         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3066         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3067                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3068         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3069         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3070                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3071         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3072         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3073                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3074
3075         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3076         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3077         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3078         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3079
3080         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3081         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3082         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3083         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3084         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3085         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3086         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3087         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3088         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3089         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3090         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3091
3092         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3093         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3094         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3095         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3096         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3097         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3098         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3099         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3100 }
3101
3102 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3103 {
3104         struct smu_table_context *table_context = &smu->smu_table;
3105         PPTable_t *pptable = table_context->driver_pptable;
3106         int i;
3107
3108         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
3109                 beige_goby_dump_pptable(smu);
3110                 return;
3111         }
3112
3113         dev_info(smu->adev->dev, "Dumped PPTable:\n");
3114
3115         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3116         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3117         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3118
3119         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3120                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3121                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3122                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3123                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3124         }
3125
3126         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3127                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3128                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3129         }
3130
3131         for (i = 0; i < TEMP_COUNT; i++) {
3132                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3133         }
3134
3135         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3136         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3137         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3138         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3139         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3140
3141         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3142         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3143                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3144                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3145         }
3146         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3147
3148         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3149
3150         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3151         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3152         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3153         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3154
3155         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3156         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3157
3158         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3159         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3160         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3161         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3162
3163         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3164         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3165         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3166         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3167
3168         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3169         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3170
3171         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3172         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3173         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3174         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3175         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3176         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3177         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3178         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3179
3180         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3181                         "  .VoltageMode          = 0x%02x\n"
3182                         "  .SnapToDiscrete       = 0x%02x\n"
3183                         "  .NumDiscreteLevels    = 0x%02x\n"
3184                         "  .padding              = 0x%02x\n"
3185                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3186                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3187                         "  .SsFmin               = 0x%04x\n"
3188                         "  .Padding_16           = 0x%04x\n",
3189                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3190                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3191                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3192                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3193                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3194                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3195                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3196                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3197                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3198                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3199                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3200
3201         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3202                         "  .VoltageMode          = 0x%02x\n"
3203                         "  .SnapToDiscrete       = 0x%02x\n"
3204                         "  .NumDiscreteLevels    = 0x%02x\n"
3205                         "  .padding              = 0x%02x\n"
3206                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3207                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3208                         "  .SsFmin               = 0x%04x\n"
3209                         "  .Padding_16           = 0x%04x\n",
3210                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3211                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3212                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3213                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3214                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3215                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3216                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3217                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3218                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3219                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3220                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3221
3222         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3223                         "  .VoltageMode          = 0x%02x\n"
3224                         "  .SnapToDiscrete       = 0x%02x\n"
3225                         "  .NumDiscreteLevels    = 0x%02x\n"
3226                         "  .padding              = 0x%02x\n"
3227                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3228                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3229                         "  .SsFmin               = 0x%04x\n"
3230                         "  .Padding_16           = 0x%04x\n",
3231                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3232                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3233                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3234                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3235                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3236                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3237                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3238                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3239                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3240                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3241                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3242
3243         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3244                         "  .VoltageMode          = 0x%02x\n"
3245                         "  .SnapToDiscrete       = 0x%02x\n"
3246                         "  .NumDiscreteLevels    = 0x%02x\n"
3247                         "  .padding              = 0x%02x\n"
3248                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3249                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3250                         "  .SsFmin               = 0x%04x\n"
3251                         "  .Padding_16           = 0x%04x\n",
3252                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3253                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3254                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3255                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3256                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3257                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3258                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3259                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3260                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3261                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3262                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3263
3264         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3265                         "  .VoltageMode          = 0x%02x\n"
3266                         "  .SnapToDiscrete       = 0x%02x\n"
3267                         "  .NumDiscreteLevels    = 0x%02x\n"
3268                         "  .padding              = 0x%02x\n"
3269                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3270                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3271                         "  .SsFmin               = 0x%04x\n"
3272                         "  .Padding_16           = 0x%04x\n",
3273                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3274                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3275                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3276                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3277                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3278                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3279                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3280                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3281                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3282                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3283                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3284
3285         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3286                         "  .VoltageMode          = 0x%02x\n"
3287                         "  .SnapToDiscrete       = 0x%02x\n"
3288                         "  .NumDiscreteLevels    = 0x%02x\n"
3289                         "  .padding              = 0x%02x\n"
3290                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3291                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3292                         "  .SsFmin               = 0x%04x\n"
3293                         "  .Padding_16           = 0x%04x\n",
3294                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3295                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3296                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3297                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3298                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3299                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3300                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3301                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3302                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3303                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3304                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3305
3306         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3307                         "  .VoltageMode          = 0x%02x\n"
3308                         "  .SnapToDiscrete       = 0x%02x\n"
3309                         "  .NumDiscreteLevels    = 0x%02x\n"
3310                         "  .padding              = 0x%02x\n"
3311                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3312                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3313                         "  .SsFmin               = 0x%04x\n"
3314                         "  .Padding_16           = 0x%04x\n",
3315                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3316                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3317                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3318                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3319                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3320                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3321                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3322                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3323                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3324                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3325                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3326
3327         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3328                         "  .VoltageMode          = 0x%02x\n"
3329                         "  .SnapToDiscrete       = 0x%02x\n"
3330                         "  .NumDiscreteLevels    = 0x%02x\n"
3331                         "  .padding              = 0x%02x\n"
3332                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3333                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3334                         "  .SsFmin               = 0x%04x\n"
3335                         "  .Padding_16           = 0x%04x\n",
3336                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3337                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3338                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3339                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3340                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3341                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3342                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3343                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3344                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3345                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3346                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3347
3348         dev_info(smu->adev->dev, "FreqTableGfx\n");
3349         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3350                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3351
3352         dev_info(smu->adev->dev, "FreqTableVclk\n");
3353         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3354                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3355
3356         dev_info(smu->adev->dev, "FreqTableDclk\n");
3357         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3358                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3359
3360         dev_info(smu->adev->dev, "FreqTableSocclk\n");
3361         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3362                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3363
3364         dev_info(smu->adev->dev, "FreqTableUclk\n");
3365         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3366                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3367
3368         dev_info(smu->adev->dev, "FreqTableFclk\n");
3369         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3370                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3371
3372         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3373         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3374         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3375         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3376         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3377         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3378         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3379         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3380         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3381
3382         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3383         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3384                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3385
3386         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3387         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3388
3389         dev_info(smu->adev->dev, "Mp0clkFreq\n");
3390         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3391                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3392
3393         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3394         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3395                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3396
3397         dev_info(smu->adev->dev, "MemVddciVoltage\n");
3398         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3399                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3400
3401         dev_info(smu->adev->dev, "MemMvddVoltage\n");
3402         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3403                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3404
3405         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3406         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3407         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3408         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3409         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3410
3411         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3412
3413         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3414         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3415         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3416         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3417         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3418         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3419         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3420         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3421         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3422         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3423         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3424
3425         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3426         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3427         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3428         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3429         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3430         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3431
3432         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3433         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3434         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3435         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3436         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3437
3438         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3439         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3440                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3441
3442         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3443         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3444         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3445         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3446
3447         dev_info(smu->adev->dev, "UclkDpmPstates\n");
3448         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3449                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3450
3451         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3452         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3453                 pptable->UclkDpmSrcFreqRange.Fmin);
3454         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3455                 pptable->UclkDpmSrcFreqRange.Fmax);
3456         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3457         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3458                 pptable->UclkDpmTargFreqRange.Fmin);
3459         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3460                 pptable->UclkDpmTargFreqRange.Fmax);
3461         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3462         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3463
3464         dev_info(smu->adev->dev, "PcieGenSpeed\n");
3465         for (i = 0; i < NUM_LINK_LEVELS; i++)
3466                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3467
3468         dev_info(smu->adev->dev, "PcieLaneCount\n");
3469         for (i = 0; i < NUM_LINK_LEVELS; i++)
3470                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3471
3472         dev_info(smu->adev->dev, "LclkFreq\n");
3473         for (i = 0; i < NUM_LINK_LEVELS; i++)
3474                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3475
3476         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3477         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3478
3479         dev_info(smu->adev->dev, "FanGain\n");
3480         for (i = 0; i < TEMP_COUNT; i++)
3481                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3482
3483         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3484         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3485         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3486         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3487         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3488         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3489         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3490         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3491         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3492         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3493         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3494         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3495
3496         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3497         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3498         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3499         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3500
3501         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3502         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3503         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3504         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3505
3506         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3507                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3508                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3509                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3510         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3511                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3512                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3513                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3514         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3515                         pptable->dBtcGbGfxPll.a,
3516                         pptable->dBtcGbGfxPll.b,
3517                         pptable->dBtcGbGfxPll.c);
3518         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3519                         pptable->dBtcGbGfxDfll.a,
3520                         pptable->dBtcGbGfxDfll.b,
3521                         pptable->dBtcGbGfxDfll.c);
3522         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3523                         pptable->dBtcGbSoc.a,
3524                         pptable->dBtcGbSoc.b,
3525                         pptable->dBtcGbSoc.c);
3526         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3527                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3528                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3529         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3530                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3531                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3532
3533         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3534         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3535                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
3536                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3537                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
3538                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3539         }
3540
3541         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3542                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3543                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3544                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3545         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3546                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3547                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3548                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3549
3550         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3551         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3552
3553         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3554         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3555         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3556         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3557
3558         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3559         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3560         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3561         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3562
3563         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3564         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3565
3566         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3567         for (i = 0; i < NUM_XGMI_LEVELS; i++)
3568                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3569         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3570         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3571
3572         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3573         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3574                         pptable->ReservedEquation0.a,
3575                         pptable->ReservedEquation0.b,
3576                         pptable->ReservedEquation0.c);
3577         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3578                         pptable->ReservedEquation1.a,
3579                         pptable->ReservedEquation1.b,
3580                         pptable->ReservedEquation1.c);
3581         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3582                         pptable->ReservedEquation2.a,
3583                         pptable->ReservedEquation2.b,
3584                         pptable->ReservedEquation2.c);
3585         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3586                         pptable->ReservedEquation3.a,
3587                         pptable->ReservedEquation3.b,
3588                         pptable->ReservedEquation3.c);
3589
3590         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3591         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3592         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3593         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3594         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3595         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3596         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3597         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3598
3599         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3600         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3601         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3602         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3603         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3604         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3605
3606         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3607                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3608                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
3609                                 pptable->I2cControllers[i].Enabled);
3610                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
3611                                 pptable->I2cControllers[i].Speed);
3612                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
3613                                 pptable->I2cControllers[i].SlaveAddress);
3614                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
3615                                 pptable->I2cControllers[i].ControllerPort);
3616                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
3617                                 pptable->I2cControllers[i].ControllerName);
3618                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
3619                                 pptable->I2cControllers[i].ThermalThrotter);
3620                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
3621                                 pptable->I2cControllers[i].I2cProtocol);
3622                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
3623                                 pptable->I2cControllers[i].PaddingConfig);
3624         }
3625
3626         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3627         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3628         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3629         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3630
3631         dev_info(smu->adev->dev, "Board Parameters:\n");
3632         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3633         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3634         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3635         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3636         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3637         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3638         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3639         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3640
3641         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3642         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3643         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3644
3645         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3646         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3647         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3648
3649         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3650         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3651         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3652
3653         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3654         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3655         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3656
3657         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3658
3659         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3660         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3661         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3662         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3663         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3664         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3665         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3666         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3667         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3668         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3669         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3670         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3671         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3672         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3673         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3674         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3675
3676         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3677         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3678         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3679
3680         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3681         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3682         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3683
3684         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3685         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3686
3687         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3688         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3689         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3690
3691         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3692         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3693         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3694         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3695         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3696
3697         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3698         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3699
3700         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3701         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3702                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3703         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3704         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3705                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3706         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3707         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3708                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3709         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3710         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3711                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3712
3713         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3714         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3715         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3716         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3717
3718         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3719         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3720         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3721         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3722         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3723         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3724         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3725         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3726         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3727         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3728         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3729
3730         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3731         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3732         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3733         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3734         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3735         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3736         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3737         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3738 }
3739
3740 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3741                                    struct i2c_msg *msg, int num_msgs)
3742 {
3743         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3744         struct amdgpu_device *adev = smu_i2c->adev;
3745         struct smu_context *smu = adev->powerplay.pp_handle;
3746         struct smu_table_context *smu_table = &smu->smu_table;
3747         struct smu_table *table = &smu_table->driver_table;
3748         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3749         int i, j, r, c;
3750         u16 dir;
3751
3752         if (!adev->pm.dpm_enabled)
3753                 return -EBUSY;
3754
3755         req = kzalloc(sizeof(*req), GFP_KERNEL);
3756         if (!req)
3757                 return -ENOMEM;
3758
3759         req->I2CcontrollerPort = smu_i2c->port;
3760         req->I2CSpeed = I2C_SPEED_FAST_400K;
3761         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3762         dir = msg[0].flags & I2C_M_RD;
3763
3764         for (c = i = 0; i < num_msgs; i++) {
3765                 for (j = 0; j < msg[i].len; j++, c++) {
3766                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3767
3768                         if (!(msg[i].flags & I2C_M_RD)) {
3769                                 /* write */
3770                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3771                                 cmd->ReadWriteData = msg[i].buf[j];
3772                         }
3773
3774                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3775                                 /* The direction changes.
3776                                  */
3777                                 dir = msg[i].flags & I2C_M_RD;
3778                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3779                         }
3780
3781                         req->NumCmds++;
3782
3783                         /*
3784                          * Insert STOP if we are at the last byte of either last
3785                          * message for the transaction or the client explicitly
3786                          * requires a STOP at this particular message.
3787                          */
3788                         if ((j == msg[i].len - 1) &&
3789                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3790                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3791                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3792                         }
3793                 }
3794         }
3795         mutex_lock(&adev->pm.mutex);
3796         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3797         if (r)
3798                 goto fail;
3799
3800         for (c = i = 0; i < num_msgs; i++) {
3801                 if (!(msg[i].flags & I2C_M_RD)) {
3802                         c += msg[i].len;
3803                         continue;
3804                 }
3805                 for (j = 0; j < msg[i].len; j++, c++) {
3806                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3807
3808                         msg[i].buf[j] = cmd->ReadWriteData;
3809                 }
3810         }
3811         r = num_msgs;
3812 fail:
3813         mutex_unlock(&adev->pm.mutex);
3814         kfree(req);
3815         return r;
3816 }
3817
3818 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3819 {
3820         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3821 }
3822
3823
3824 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3825         .master_xfer = sienna_cichlid_i2c_xfer,
3826         .functionality = sienna_cichlid_i2c_func,
3827 };
3828
3829 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3830         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3831         .max_read_len  = MAX_SW_I2C_COMMANDS,
3832         .max_write_len = MAX_SW_I2C_COMMANDS,
3833         .max_comb_1st_msg_len = 2,
3834         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3835 };
3836
3837 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3838 {
3839         struct amdgpu_device *adev = smu->adev;
3840         int res, i;
3841
3842         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3843                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3844                 struct i2c_adapter *control = &smu_i2c->adapter;
3845
3846                 smu_i2c->adev = adev;
3847                 smu_i2c->port = i;
3848                 mutex_init(&smu_i2c->mutex);
3849                 control->owner = THIS_MODULE;
3850                 control->class = I2C_CLASS_HWMON;
3851                 control->dev.parent = &adev->pdev->dev;
3852                 control->algo = &sienna_cichlid_i2c_algo;
3853                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3854                 control->quirks = &sienna_cichlid_i2c_control_quirks;
3855                 i2c_set_adapdata(control, smu_i2c);
3856
3857                 res = i2c_add_adapter(control);
3858                 if (res) {
3859                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3860                         goto Out_err;
3861                 }
3862         }
3863         /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3864         /* XXX ideally this would be something in a vbios data table */
3865         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3866         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3867
3868         return 0;
3869 Out_err:
3870         for ( ; i >= 0; i--) {
3871                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3872                 struct i2c_adapter *control = &smu_i2c->adapter;
3873
3874                 i2c_del_adapter(control);
3875         }
3876         return res;
3877 }
3878
3879 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3880 {
3881         struct amdgpu_device *adev = smu->adev;
3882         int i;
3883
3884         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3885                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3886                 struct i2c_adapter *control = &smu_i2c->adapter;
3887
3888                 i2c_del_adapter(control);
3889         }
3890         adev->pm.ras_eeprom_i2c_bus = NULL;
3891         adev->pm.fru_eeprom_i2c_bus = NULL;
3892 }
3893
3894 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3895                                               void **table)
3896 {
3897         struct smu_table_context *smu_table = &smu->smu_table;
3898         struct gpu_metrics_v1_3 *gpu_metrics =
3899                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3900         SmuMetricsExternal_t metrics_external;
3901         SmuMetrics_t *metrics =
3902                 &(metrics_external.SmuMetrics);
3903         SmuMetrics_V2_t *metrics_v2 =
3904                 &(metrics_external.SmuMetrics_V2);
3905         SmuMetrics_V3_t *metrics_v3 =
3906                 &(metrics_external.SmuMetrics_V3);
3907         struct amdgpu_device *adev = smu->adev;
3908         bool use_metrics_v2 = false;
3909         bool use_metrics_v3 = false;
3910         uint16_t average_gfx_activity;
3911         int ret = 0;
3912
3913         switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3914         case IP_VERSION(11, 0, 7):
3915                 if (smu->smc_fw_version >= 0x3A4900)
3916                         use_metrics_v3 = true;
3917                 else if (smu->smc_fw_version >= 0x3A4300)
3918                         use_metrics_v2 = true;
3919                 break;
3920         case IP_VERSION(11, 0, 11):
3921                 if (smu->smc_fw_version >= 0x412D00)
3922                         use_metrics_v2 = true;
3923                 break;
3924         case IP_VERSION(11, 0, 12):
3925                 if (smu->smc_fw_version >= 0x3B2300)
3926                         use_metrics_v2 = true;
3927                 break;
3928         case IP_VERSION(11, 0, 13):
3929                 if (smu->smc_fw_version >= 0x491100)
3930                         use_metrics_v2 = true;
3931                 break;
3932         default:
3933                 break;
3934         }
3935
3936         ret = smu_cmn_get_metrics_table(smu,
3937                                         &metrics_external,
3938                                         true);
3939         if (ret)
3940                 return ret;
3941
3942         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3943
3944         gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3945                 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3946         gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3947                 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3948         gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3949                 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3950         gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3951                 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3952         gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3953                 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3954         gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3955                 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3956
3957         gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3958                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3959         gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3960                 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3961         gpu_metrics->average_mm_activity = use_metrics_v3 ?
3962                 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3963                 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3964
3965         gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3966                 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3967         gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3968                 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3969
3970         if (metrics->CurrGfxVoltageOffset)
3971                 gpu_metrics->voltage_gfx =
3972                         (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3973         if (metrics->CurrMemVidOffset)
3974                 gpu_metrics->voltage_mem =
3975                         (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3976         if (metrics->CurrSocVoltageOffset)
3977                 gpu_metrics->voltage_soc =
3978                         (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3979
3980         average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3981                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3982         if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3983                 gpu_metrics->average_gfxclk_frequency =
3984                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3985                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3986                         metrics->AverageGfxclkFrequencyPostDs;
3987         else
3988                 gpu_metrics->average_gfxclk_frequency =
3989                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3990                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3991                         metrics->AverageGfxclkFrequencyPreDs;
3992
3993         gpu_metrics->average_uclk_frequency =
3994                 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3995                 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3996                 metrics->AverageUclkFrequencyPostDs;
3997         gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
3998                 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3999         gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
4000                 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
4001         gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
4002                 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
4003         gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
4004                 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
4005
4006         gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
4007                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
4008         gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
4009                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
4010         gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
4011                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
4012         gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
4013                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
4014         gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
4015                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
4016         gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
4017                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
4018         gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
4019                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4020
4021         gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
4022         gpu_metrics->indep_throttle_status =
4023                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
4024                                                            sienna_cichlid_throttler_map);
4025
4026         gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4027                 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
4028
4029         if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
4030               ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
4031                 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4032                         use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4033                 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4034                         use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
4035         } else {
4036                 gpu_metrics->pcie_link_width =
4037                                 smu_v11_0_get_current_pcie_link_width(smu);
4038                 gpu_metrics->pcie_link_speed =
4039                                 smu_v11_0_get_current_pcie_link_speed(smu);
4040         }
4041
4042         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4043
4044         *table = (void *)gpu_metrics;
4045
4046         return sizeof(struct gpu_metrics_v1_3);
4047 }
4048
4049 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4050 {
4051         uint32_t if_version = 0xff, smu_version = 0xff;
4052         int ret = 0;
4053
4054         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
4055         if (ret)
4056                 return -EOPNOTSUPP;
4057
4058         if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4059                 ret = -EOPNOTSUPP;
4060
4061         return ret;
4062 }
4063
4064 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4065                                         void *table)
4066 {
4067         struct smu_table_context *smu_table = &smu->smu_table;
4068         EccInfoTable_t *ecc_table = NULL;
4069         struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4070         int i, ret = 0;
4071         struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4072
4073         ret = sienna_cichlid_check_ecc_table_support(smu);
4074         if (ret)
4075                 return ret;
4076
4077         ret = smu_cmn_update_table(smu,
4078                                 SMU_TABLE_ECCINFO,
4079                                 0,
4080                                 smu_table->ecc_table,
4081                                 false);
4082         if (ret) {
4083                 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4084                 return ret;
4085         }
4086
4087         ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4088
4089         for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4090                 ecc_info_per_channel = &(eccinfo->ecc[i]);
4091                 ecc_info_per_channel->ce_count_lo_chip =
4092                         ecc_table->EccInfo[i].ce_count_lo_chip;
4093                 ecc_info_per_channel->ce_count_hi_chip =
4094                         ecc_table->EccInfo[i].ce_count_hi_chip;
4095                 ecc_info_per_channel->mca_umc_status =
4096                         ecc_table->EccInfo[i].mca_umc_status;
4097                 ecc_info_per_channel->mca_umc_addr =
4098                         ecc_table->EccInfo[i].mca_umc_addr;
4099         }
4100
4101         return ret;
4102 }
4103 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4104 {
4105         uint16_t *mgpu_fan_boost_limit_rpm;
4106
4107         GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4108         /*
4109          * Skip the MGpuFanBoost setting for those ASICs
4110          * which do not support it
4111          */
4112         if (*mgpu_fan_boost_limit_rpm == 0)
4113                 return 0;
4114
4115         return smu_cmn_send_smc_msg_with_param(smu,
4116                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
4117                                                0,
4118                                                NULL);
4119 }
4120
4121 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4122                                       bool enablement)
4123 {
4124         uint32_t smu_version;
4125         int ret = 0;
4126
4127
4128         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4129                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4130                 if (ret)
4131                         return ret;
4132
4133                 if (enablement) {
4134                         if (smu_version < 0x003a2500) {
4135                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4136                                                                       SMU_MSG_SetGpoFeaturePMask,
4137                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4138                                                                       NULL);
4139                         } else {
4140                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4141                                                                       SMU_MSG_DisallowGpo,
4142                                                                       0,
4143                                                                       NULL);
4144                         }
4145                 } else {
4146                         if (smu_version < 0x003a2500) {
4147                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4148                                                                       SMU_MSG_SetGpoFeaturePMask,
4149                                                                       0,
4150                                                                       NULL);
4151                         } else {
4152                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4153                                                                       SMU_MSG_DisallowGpo,
4154                                                                       1,
4155                                                                       NULL);
4156                         }
4157                 }
4158         }
4159
4160         return ret;
4161 }
4162
4163 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4164 {
4165         uint32_t smu_version;
4166         int ret = 0;
4167
4168         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4169         if (ret)
4170                 return ret;
4171
4172         /*
4173          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4174          * onwards PMFWs.
4175          */
4176         if (smu_version < 0x003A2D00)
4177                 return 0;
4178
4179         return smu_cmn_send_smc_msg_with_param(smu,
4180                                                SMU_MSG_Enable2ndUSB20Port,
4181                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4182                                                1 : 0,
4183                                                NULL);
4184 }
4185
4186 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4187                                                   bool en)
4188 {
4189         int ret = 0;
4190
4191         if (en) {
4192                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4193                 if (ret)
4194                         return ret;
4195         }
4196
4197         return smu_v11_0_system_features_control(smu, en);
4198 }
4199
4200 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4201                                         enum pp_mp1_state mp1_state)
4202 {
4203         int ret;
4204
4205         switch (mp1_state) {
4206         case PP_MP1_STATE_UNLOAD:
4207                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4208                 break;
4209         default:
4210                 /* Ignore others */
4211                 ret = 0;
4212         }
4213
4214         return ret;
4215 }
4216
4217 static void sienna_cichlid_stb_init(struct smu_context *smu)
4218 {
4219         struct amdgpu_device *adev = smu->adev;
4220         uint32_t reg;
4221
4222         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4223         smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4224
4225         /* STB is disabled */
4226         if (!smu->stb_context.enabled)
4227                 return;
4228
4229         spin_lock_init(&smu->stb_context.lock);
4230
4231         /* STB buffer size in bytes as function of FIFO depth */
4232         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4233         smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4234         smu->stb_context.stb_buf_size *=  SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4235
4236         dev_info(smu->adev->dev, "STB initialized to %d entries",
4237                  smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4238
4239 }
4240
4241 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4242                                                             struct config_table_setting *table)
4243 {
4244         struct amdgpu_device *adev = smu->adev;
4245
4246         if (!table)
4247                 return -EINVAL;
4248
4249         table->gfxclk_average_tau = 10;
4250         table->socclk_average_tau = 10;
4251         table->fclk_average_tau = 10;
4252         table->uclk_average_tau = 10;
4253         table->gfx_activity_average_tau = 10;
4254         table->mem_activity_average_tau = 10;
4255         table->socket_power_average_tau = 100;
4256         if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
4257                 table->apu_socket_power_average_tau = 100;
4258
4259         return 0;
4260 }
4261
4262 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4263                                            struct config_table_setting *table)
4264 {
4265         DriverSmuConfigExternal_t driver_smu_config_table;
4266
4267         if (!table)
4268                 return -EINVAL;
4269
4270         memset(&driver_smu_config_table,
4271                0,
4272                sizeof(driver_smu_config_table));
4273         driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4274                                 table->gfxclk_average_tau;
4275         driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4276                                 table->fclk_average_tau;
4277         driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4278                                 table->uclk_average_tau;
4279         driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4280                                 table->gfx_activity_average_tau;
4281         driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4282                                 table->mem_activity_average_tau;
4283         driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4284                                 table->socket_power_average_tau;
4285
4286         return smu_cmn_update_table(smu,
4287                                     SMU_TABLE_DRIVER_SMU_CONFIG,
4288                                     0,
4289                                     (void *)&driver_smu_config_table,
4290                                     true);
4291 }
4292
4293 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4294                                               void *buf,
4295                                               uint32_t size)
4296 {
4297         uint32_t *p = buf;
4298         struct amdgpu_device *adev = smu->adev;
4299
4300         /* No need to disable interrupts for now as we don't lock it yet from ISR */
4301         spin_lock(&smu->stb_context.lock);
4302
4303         /*
4304          * Read the STB FIFO in units of 32bit since this is the accessor window
4305          * (register width) we have.
4306          */
4307         buf = ((char *) buf) + size;
4308         while ((void *)p < buf)
4309                 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4310
4311         spin_unlock(&smu->stb_context.lock);
4312
4313         return 0;
4314 }
4315
4316 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4317 {
4318         return true;
4319 }
4320
4321 static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4322 {
4323         u32 smu_version;
4324         int ret = 0, index;
4325         struct amdgpu_device *adev = smu->adev;
4326         int timeout = 100;
4327
4328         smu_cmn_get_smc_version(smu, NULL, &smu_version);
4329
4330         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4331                                                 SMU_MSG_DriverMode2Reset);
4332
4333         mutex_lock(&smu->message_lock);
4334
4335         ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4336                                                SMU_RESET_MODE_2);
4337
4338         ret = smu_cmn_wait_for_response(smu);
4339         while (ret != 0 && timeout) {
4340                 ret = smu_cmn_wait_for_response(smu);
4341                 /* Wait a bit more time for getting ACK */
4342                 if (ret != 0) {
4343                         --timeout;
4344                         usleep_range(500, 1000);
4345                         continue;
4346                 } else {
4347                         break;
4348                 }
4349         }
4350
4351         if (!timeout) {
4352                 dev_err(adev->dev,
4353                         "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4354                         SMU_RESET_MODE_2, ret);
4355                 goto out;
4356         }
4357
4358         dev_info(smu->adev->dev, "restore config space...\n");
4359         /* Restore the config space saved during init */
4360         amdgpu_device_load_pci_state(adev->pdev);
4361 out:
4362         mutex_unlock(&smu->message_lock);
4363
4364         return ret;
4365 }
4366
4367 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4368         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4369         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4370         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4371         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4372         .i2c_init = sienna_cichlid_i2c_control_init,
4373         .i2c_fini = sienna_cichlid_i2c_control_fini,
4374         .print_clk_levels = sienna_cichlid_print_clk_levels,
4375         .force_clk_levels = sienna_cichlid_force_clk_levels,
4376         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4377         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4378         .display_config_changed = sienna_cichlid_display_config_changed,
4379         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4380         .is_dpm_running = sienna_cichlid_is_dpm_running,
4381         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4382         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4383         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4384         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4385         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4386         .read_sensor = sienna_cichlid_read_sensor,
4387         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4388         .set_performance_level = smu_v11_0_set_performance_level,
4389         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4390         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4391         .get_power_limit = sienna_cichlid_get_power_limit,
4392         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4393         .dump_pptable = sienna_cichlid_dump_pptable,
4394         .init_microcode = smu_v11_0_init_microcode,
4395         .load_microcode = smu_v11_0_load_microcode,
4396         .fini_microcode = smu_v11_0_fini_microcode,
4397         .init_smc_tables = sienna_cichlid_init_smc_tables,
4398         .fini_smc_tables = smu_v11_0_fini_smc_tables,
4399         .init_power = smu_v11_0_init_power,
4400         .fini_power = smu_v11_0_fini_power,
4401         .check_fw_status = smu_v11_0_check_fw_status,
4402         .setup_pptable = sienna_cichlid_setup_pptable,
4403         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4404         .check_fw_version = smu_v11_0_check_fw_version,
4405         .write_pptable = smu_cmn_write_pptable,
4406         .set_driver_table_location = smu_v11_0_set_driver_table_location,
4407         .set_tool_table_location = smu_v11_0_set_tool_table_location,
4408         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4409         .system_features_control = sienna_cichlid_system_features_control,
4410         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4411         .send_smc_msg = smu_cmn_send_smc_msg,
4412         .init_display_count = NULL,
4413         .set_allowed_mask = smu_v11_0_set_allowed_mask,
4414         .get_enabled_mask = smu_cmn_get_enabled_mask,
4415         .feature_is_enabled = smu_cmn_feature_is_enabled,
4416         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4417         .notify_display_change = NULL,
4418         .set_power_limit = smu_v11_0_set_power_limit,
4419         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4420         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4421         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4422         .set_min_dcef_deep_sleep = NULL,
4423         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4424         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4425         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4426         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4427         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4428         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4429         .gfx_off_control = smu_v11_0_gfx_off_control,
4430         .register_irq_handler = smu_v11_0_register_irq_handler,
4431         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4432         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4433         .baco_is_support = smu_v11_0_baco_is_support,
4434         .baco_get_state = smu_v11_0_baco_get_state,
4435         .baco_set_state = smu_v11_0_baco_set_state,
4436         .baco_enter = sienna_cichlid_baco_enter,
4437         .baco_exit = sienna_cichlid_baco_exit,
4438         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4439         .mode1_reset = smu_v11_0_mode1_reset,
4440         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4441         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4442         .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4443         .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4444         .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
4445         .run_btc = sienna_cichlid_run_btc,
4446         .set_power_source = smu_v11_0_set_power_source,
4447         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4448         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4449         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4450         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4451         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4452         .deep_sleep_control = smu_v11_0_deep_sleep_control,
4453         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4454         .interrupt_work = smu_v11_0_interrupt_work,
4455         .gpo_control = sienna_cichlid_gpo_control,
4456         .set_mp1_state = sienna_cichlid_set_mp1_state,
4457         .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4458         .get_ecc_info = sienna_cichlid_get_ecc_info,
4459         .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4460         .set_config_table = sienna_cichlid_set_config_table,
4461         .get_unique_id = sienna_cichlid_get_unique_id,
4462         .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4463         .mode2_reset = sienna_cichlid_mode2_reset,
4464 };
4465
4466 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4467 {
4468         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4469         smu->message_map = sienna_cichlid_message_map;
4470         smu->clock_map = sienna_cichlid_clk_map;
4471         smu->feature_map = sienna_cichlid_feature_mask_map;
4472         smu->table_map = sienna_cichlid_table_map;
4473         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4474         smu->workload_map = sienna_cichlid_workload_map;
4475         smu_v11_0_set_smu_mailbox_registers(smu);
4476 }