drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_dpm.h"
  31 #include "amdgpu_smu.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "soc15_common.h"
  36 #include "smu_v11_0.h"
  37 #include "smu11_driver_if_navi10.h"
  38 #include "atom.h"
  39 #include "navi10_ppt.h"
  40 #include "smu_v11_0_pptable.h"
  41 #include "smu_v11_0_ppsmc.h"
  42 #include "nbio/nbio_2_3_offset.h"
  43 #include "nbio/nbio_2_3_sh_mask.h"
  44 #include "thm/thm_11_0_2_offset.h"
  45 #include "thm/thm_11_0_2_sh_mask.h"
  46
  47 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  48 #include "smu_cmn.h"
  49 #include "smu_11_0_cdr_table.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define FEATURE_MASK(feature) (1ULL << feature)
  62 #define SMC_DPM_FEATURE ( \
  63         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  64         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  65         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  66         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  67         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  68         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  69         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  70         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  71
  72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
  73
  74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  75         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  76         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  77         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  78         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,    0),
  79         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,   0),
  80         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,         0),
  81         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,        0),
  82         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,         0),
  83         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,        0),
  84         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,        0),
  85         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,       0),
  86         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow,     1),
  87         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh,    1),
  88         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,              0),
  89         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                  0),
  90         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
  91         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         1),
  92         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,         0),
  93         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,          0),
  94         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        1),
  95         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  96         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,            0),
  97         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable,             0),
  98         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc,                       0),
  99         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                    0),
 100         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,             1),
 101         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,             1),
 102         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,             0),
 103         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,             0),
 104         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,                1),
 105         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,                1),
 106         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,            1),
 107         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig,       0),
 108         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,                0),
 109         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,        0),
 110         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,         0),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,       0),
 112         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk,       0),
 113         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,        0),
 114         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,            0),
 115         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,            0),
 116         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  0),
 117         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
 118         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,       0),
 119         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,        0),
 120         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,           0),
 121         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt,             0),
 122         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays,                0),
 123         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
 124         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow,  0),
 125         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                  0),
 126         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
 127         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                  0),
 128         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,          1),
 129         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData,                 0),
 130         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                     0),
 131         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset,           0),
 132         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown,        0),
 133         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
 134         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
 135         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  0),
 136         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                0),
 137         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,               0),
 138         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                        0),
 139         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0),
 140         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange,   0),
 141         MSG_MAP(GetVoltageByDpm,                PPSMC_MSG_GetVoltageByDpm,              0),
 142         MSG_MAP(GetVoltageByDpmOverdrive,       PPSMC_MSG_GetVoltageByDpmOverdrive,     0),
 143         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,      0),
 144         MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
 145         MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
 146         MSG_MAP(GET_UMC_FW_WA,                  PPSMC_MSG_GetUMCFWWA,                   0),
 147 };
 148
 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 150         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 151         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 152         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 153         CLK_MAP(FCLK, PPCLK_SOCCLK),
 154         CLK_MAP(UCLK, PPCLK_UCLK),
 155         CLK_MAP(MCLK, PPCLK_UCLK),
 156         CLK_MAP(DCLK, PPCLK_DCLK),
 157         CLK_MAP(VCLK, PPCLK_VCLK),
 158         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 159         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 160         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 161         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 162 };
 163
 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 165         FEA_MAP(DPM_PREFETCHER),
 166         FEA_MAP(DPM_GFXCLK),
 167         FEA_MAP(DPM_GFX_PACE),
 168         FEA_MAP(DPM_UCLK),
 169         FEA_MAP(DPM_SOCCLK),
 170         FEA_MAP(DPM_MP0CLK),
 171         FEA_MAP(DPM_LINK),
 172         FEA_MAP(DPM_DCEFCLK),
 173         FEA_MAP(MEM_VDDCI_SCALING),
 174         FEA_MAP(MEM_MVDD_SCALING),
 175         FEA_MAP(DS_GFXCLK),
 176         FEA_MAP(DS_SOCCLK),
 177         FEA_MAP(DS_LCLK),
 178         FEA_MAP(DS_DCEFCLK),
 179         FEA_MAP(DS_UCLK),
 180         FEA_MAP(GFX_ULV),
 181         FEA_MAP(FW_DSTATE),
 182         FEA_MAP(GFXOFF),
 183         FEA_MAP(BACO),
 184         FEA_MAP(VCN_PG),
 185         FEA_MAP(JPEG_PG),
 186         FEA_MAP(USB_PG),
 187         FEA_MAP(RSMU_SMN_CG),
 188         FEA_MAP(PPT),
 189         FEA_MAP(TDC),
 190         FEA_MAP(GFX_EDC),
 191         FEA_MAP(APCC_PLUS),
 192         FEA_MAP(GTHR),
 193         FEA_MAP(ACDC),
 194         FEA_MAP(VR0HOT),
 195         FEA_MAP(VR1HOT),
 196         FEA_MAP(FW_CTF),
 197         FEA_MAP(FAN_CONTROL),
 198         FEA_MAP(THERMAL),
 199         FEA_MAP(GFX_DCS),
 200         FEA_MAP(RM),
 201         FEA_MAP(LED_DISPLAY),
 202         FEA_MAP(GFX_SS),
 203         FEA_MAP(OUT_OF_BAND_MONITOR),
 204         FEA_MAP(TEMP_DEPENDENT_VMIN),
 205         FEA_MAP(MMHUB_PG),
 206         FEA_MAP(ATHUB_PG),
 207         FEA_MAP(APCC_DFLL),
 208 };
 209
 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 211         TAB_MAP(PPTABLE),
 212         TAB_MAP(WATERMARKS),
 213         TAB_MAP(AVFS),
 214         TAB_MAP(AVFS_PSM_DEBUG),
 215         TAB_MAP(AVFS_FUSE_OVERRIDE),
 216         TAB_MAP(PMSTATUSLOG),
 217         TAB_MAP(SMU_METRICS),
 218         TAB_MAP(DRIVER_SMU_CONFIG),
 219         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 220         TAB_MAP(OVERDRIVE),
 221         TAB_MAP(I2C_COMMANDS),
 222         TAB_MAP(PACE),
 223 };
 224
 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 226         PWR_MAP(AC),
 227         PWR_MAP(DC),
 228 };
 229
 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 231         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 232         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 233         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 234         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 235         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 236         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 237         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 238 };
 239
 240 static const uint8_t navi1x_throttler_map[] = {
 241         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 242         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 243         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 244         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 245         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 246         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 247         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 248         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 249         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 250         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 251         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 252         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 253         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 254         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 255         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 256         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 257         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 258         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 259 };
 260
 261
 262 static bool is_asic_secure(struct smu_context *smu)
 263 {
 264         struct amdgpu_device *adev = smu->adev;
 265         bool is_secure = true;
 266         uint32_t mp0_fw_intf;
 267
 268         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 269                                    (smnMP0_FW_INTF & 0xffffffff));
 270
 271         if (!(mp0_fw_intf & (1 << 19)))
 272                 is_secure = false;
 273
 274         return is_secure;
 275 }
 276
 277 static int
 278 navi10_get_allowed_feature_mask(struct smu_context *smu,
 279                                   uint32_t *feature_mask, uint32_t num)
 280 {
 281         struct amdgpu_device *adev = smu->adev;
 282
 283         if (num > 2)
 284                 return -EINVAL;
 285
 286         memset(feature_mask, 0, sizeof(uint32_t) * num);
 287
 288         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 289                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 290                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 291                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 292                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 293                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 294                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 295                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 296                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 297                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 298                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 299                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 300                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 301                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 302                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 303                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 304                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 305                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 306                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 307                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
 308                                 | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
 309
 310         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 311                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 312
 313         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 314                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 315
 316         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 317                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 318
 319         if (adev->pm.pp_feature & PP_ULV_MASK)
 320                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 321
 322         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 323                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 324
 325         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 326                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 327
 328         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 329                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 330
 331         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 332                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 333
 334         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 335                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 336
 337         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 338                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 339
 340         if (smu->dc_controlled_by_gpio)
 341                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 342
 343         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 344                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 345
 346         /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
 347         if (!(is_asic_secure(smu) &&
 348               (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
 349               (adev->rev_id == 0)) &&
 350             (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
 351                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 352                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 353                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 354
 355         /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
 356         if (is_asic_secure(smu) &&
 357             (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
 358             (adev->rev_id == 0))
 359                 *(uint64_t *)feature_mask &=
 360                                 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 361
 362         return 0;
 363 }
 364
 365 static void navi10_check_bxco_support(struct smu_context *smu)
 366 {
 367         struct smu_table_context *table_context = &smu->smu_table;
 368         struct smu_11_0_powerplay_table *powerplay_table =
 369                 table_context->power_play_table;
 370         struct smu_baco_context *smu_baco = &smu->smu_baco;
 371         struct amdgpu_device *adev = smu->adev;
 372         uint32_t val;
 373
 374         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 375             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 376                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 377                 smu_baco->platform_support =
 378                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 379                                                                         false;
 380         }
 381 }
 382
 383 static int navi10_check_powerplay_table(struct smu_context *smu)
 384 {
 385         struct smu_table_context *table_context = &smu->smu_table;
 386         struct smu_11_0_powerplay_table *powerplay_table =
 387                 table_context->power_play_table;
 388
 389         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 390                 smu->dc_controlled_by_gpio = true;
 391
 392         navi10_check_bxco_support(smu);
 393
 394         table_context->thermal_controller_type =
 395                 powerplay_table->thermal_controller_type;
 396
 397         /*
 398          * Instead of having its own buffer space and get overdrive_table copied,
 399          * smu->od_settings just points to the actual overdrive_table
 400          */
 401         smu->od_settings = &powerplay_table->overdrive_table;
 402
 403         return 0;
 404 }
 405
 406 static int navi10_append_powerplay_table(struct smu_context *smu)
 407 {
 408         struct amdgpu_device *adev = smu->adev;
 409         struct smu_table_context *table_context = &smu->smu_table;
 410         PPTable_t *smc_pptable = table_context->driver_pptable;
 411         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 412         struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
 413         int index, ret;
 414
 415         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 416                                            smc_dpm_info);
 417
 418         ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 419                                       (uint8_t **)&smc_dpm_table);
 420         if (ret)
 421                 return ret;
 422
 423         dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 424                         smc_dpm_table->table_header.format_revision,
 425                         smc_dpm_table->table_header.content_revision);
 426
 427         if (smc_dpm_table->table_header.format_revision != 4) {
 428                 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
 429                 return -EINVAL;
 430         }
 431
 432         switch (smc_dpm_table->table_header.content_revision) {
 433         case 5: /* nv10 and nv14 */
 434                 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
 435                                     smc_dpm_table, I2cControllers);
 436                 break;
 437         case 7: /* nv12 */
 438                 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 439                                               (uint8_t **)&smc_dpm_table_v4_7);
 440                 if (ret)
 441                         return ret;
 442                 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
 443                                     smc_dpm_table_v4_7, I2cControllers);
 444                 break;
 445         default:
 446                 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
 447                                 smc_dpm_table->table_header.content_revision);
 448                 return -EINVAL;
 449         }
 450
 451         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 452                 /* TODO: remove it once SMU fw fix it */
 453                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int navi10_store_powerplay_table(struct smu_context *smu)
 460 {
 461         struct smu_table_context *table_context = &smu->smu_table;
 462         struct smu_11_0_powerplay_table *powerplay_table =
 463                 table_context->power_play_table;
 464
 465         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 466                sizeof(PPTable_t));
 467
 468         return 0;
 469 }
 470
 471 static int navi10_setup_pptable(struct smu_context *smu)
 472 {
 473         int ret = 0;
 474
 475         ret = smu_v11_0_setup_pptable(smu);
 476         if (ret)
 477                 return ret;
 478
 479         ret = navi10_store_powerplay_table(smu);
 480         if (ret)
 481                 return ret;
 482
 483         ret = navi10_append_powerplay_table(smu);
 484         if (ret)
 485                 return ret;
 486
 487         ret = navi10_check_powerplay_table(smu);
 488         if (ret)
 489                 return ret;
 490
 491         return ret;
 492 }
 493
 494 static int navi10_tables_init(struct smu_context *smu)
 495 {
 496         struct smu_table_context *smu_table = &smu->smu_table;
 497         struct smu_table *tables = smu_table->tables;
 498         struct smu_table *dummy_read_1_table =
 499                         &smu_table->dummy_read_1_table;
 500
 501         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 502                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 503         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 504                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 505         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
 506                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 507         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 508                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 509         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 510                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 511         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 512                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 513         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 514                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 515                        AMDGPU_GEM_DOMAIN_VRAM);
 516         SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t),
 517                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 518
 519         dummy_read_1_table->size = 0x40000;
 520         dummy_read_1_table->align = PAGE_SIZE;
 521         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 522
 523         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
 524                                            GFP_KERNEL);
 525         if (!smu_table->metrics_table)
 526                 goto err0_out;
 527         smu_table->metrics_time = 0;
 528
 529         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 530         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 531         if (!smu_table->gpu_metrics_table)
 532                 goto err1_out;
 533
 534         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 535         if (!smu_table->watermarks_table)
 536                 goto err2_out;
 537
 538         smu_table->driver_smu_config_table =
 539                 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
 540         if (!smu_table->driver_smu_config_table)
 541                 goto err3_out;
 542
 543         return 0;
 544
 545 err3_out:
 546         kfree(smu_table->watermarks_table);
 547 err2_out:
 548         kfree(smu_table->gpu_metrics_table);
 549 err1_out:
 550         kfree(smu_table->metrics_table);
 551 err0_out:
 552         return -ENOMEM;
 553 }
 554
 555 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
 556                                               MetricsMember_t member,
 557                                               uint32_t *value)
 558 {
 559         struct smu_table_context *smu_table = &smu->smu_table;
 560         SmuMetrics_legacy_t *metrics =
 561                 (SmuMetrics_legacy_t *)smu_table->metrics_table;
 562         int ret = 0;
 563
 564         ret = smu_cmn_get_metrics_table(smu,
 565                                         NULL,
 566                                         false);
 567         if (ret)
 568                 return ret;
 569
 570         switch (member) {
 571         case METRICS_CURR_GFXCLK:
 572                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 573                 break;
 574         case METRICS_CURR_SOCCLK:
 575                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 576                 break;
 577         case METRICS_CURR_UCLK:
 578                 *value = metrics->CurrClock[PPCLK_UCLK];
 579                 break;
 580         case METRICS_CURR_VCLK:
 581                 *value = metrics->CurrClock[PPCLK_VCLK];
 582                 break;
 583         case METRICS_CURR_DCLK:
 584                 *value = metrics->CurrClock[PPCLK_DCLK];
 585                 break;
 586         case METRICS_CURR_DCEFCLK:
 587                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 588                 break;
 589         case METRICS_AVERAGE_GFXCLK:
 590                 *value = metrics->AverageGfxclkFrequency;
 591                 break;
 592         case METRICS_AVERAGE_SOCCLK:
 593                 *value = metrics->AverageSocclkFrequency;
 594                 break;
 595         case METRICS_AVERAGE_UCLK:
 596                 *value = metrics->AverageUclkFrequency;
 597                 break;
 598         case METRICS_AVERAGE_GFXACTIVITY:
 599                 *value = metrics->AverageGfxActivity;
 600                 break;
 601         case METRICS_AVERAGE_MEMACTIVITY:
 602                 *value = metrics->AverageUclkActivity;
 603                 break;
 604         case METRICS_AVERAGE_SOCKETPOWER:
 605                 *value = metrics->AverageSocketPower << 8;
 606                 break;
 607         case METRICS_TEMPERATURE_EDGE:
 608                 *value = metrics->TemperatureEdge *
 609                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 610                 break;
 611         case METRICS_TEMPERATURE_HOTSPOT:
 612                 *value = metrics->TemperatureHotspot *
 613                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 614                 break;
 615         case METRICS_TEMPERATURE_MEM:
 616                 *value = metrics->TemperatureMem *
 617                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 618                 break;
 619         case METRICS_TEMPERATURE_VRGFX:
 620                 *value = metrics->TemperatureVrGfx *
 621                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 622                 break;
 623         case METRICS_TEMPERATURE_VRSOC:
 624                 *value = metrics->TemperatureVrSoc *
 625                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 626                 break;
 627         case METRICS_THROTTLER_STATUS:
 628                 *value = metrics->ThrottlerStatus;
 629                 break;
 630         case METRICS_CURR_FANSPEED:
 631                 *value = metrics->CurrFanSpeed;
 632                 break;
 633         default:
 634                 *value = UINT_MAX;
 635                 break;
 636         }
 637
 638         return ret;
 639 }
 640
 641 static int navi10_get_smu_metrics_data(struct smu_context *smu,
 642                                        MetricsMember_t member,
 643                                        uint32_t *value)
 644 {
 645         struct smu_table_context *smu_table = &smu->smu_table;
 646         SmuMetrics_t *metrics =
 647                 (SmuMetrics_t *)smu_table->metrics_table;
 648         int ret = 0;
 649
 650         ret = smu_cmn_get_metrics_table(smu,
 651                                         NULL,
 652                                         false);
 653         if (ret)
 654                 return ret;
 655
 656         switch (member) {
 657         case METRICS_CURR_GFXCLK:
 658                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 659                 break;
 660         case METRICS_CURR_SOCCLK:
 661                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 662                 break;
 663         case METRICS_CURR_UCLK:
 664                 *value = metrics->CurrClock[PPCLK_UCLK];
 665                 break;
 666         case METRICS_CURR_VCLK:
 667                 *value = metrics->CurrClock[PPCLK_VCLK];
 668                 break;
 669         case METRICS_CURR_DCLK:
 670                 *value = metrics->CurrClock[PPCLK_DCLK];
 671                 break;
 672         case METRICS_CURR_DCEFCLK:
 673                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 674                 break;
 675         case METRICS_AVERAGE_GFXCLK:
 676                 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
 677                         *value = metrics->AverageGfxclkFrequencyPreDs;
 678                 else
 679                         *value = metrics->AverageGfxclkFrequencyPostDs;
 680                 break;
 681         case METRICS_AVERAGE_SOCCLK:
 682                 *value = metrics->AverageSocclkFrequency;
 683                 break;
 684         case METRICS_AVERAGE_UCLK:
 685                 *value = metrics->AverageUclkFrequencyPostDs;
 686                 break;
 687         case METRICS_AVERAGE_GFXACTIVITY:
 688                 *value = metrics->AverageGfxActivity;
 689                 break;
 690         case METRICS_AVERAGE_MEMACTIVITY:
 691                 *value = metrics->AverageUclkActivity;
 692                 break;
 693         case METRICS_AVERAGE_SOCKETPOWER:
 694                 *value = metrics->AverageSocketPower << 8;
 695                 break;
 696         case METRICS_TEMPERATURE_EDGE:
 697                 *value = metrics->TemperatureEdge *
 698                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 699                 break;
 700         case METRICS_TEMPERATURE_HOTSPOT:
 701                 *value = metrics->TemperatureHotspot *
 702                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 703                 break;
 704         case METRICS_TEMPERATURE_MEM:
 705                 *value = metrics->TemperatureMem *
 706                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 707                 break;
 708         case METRICS_TEMPERATURE_VRGFX:
 709                 *value = metrics->TemperatureVrGfx *
 710                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 711                 break;
 712         case METRICS_TEMPERATURE_VRSOC:
 713                 *value = metrics->TemperatureVrSoc *
 714                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 715                 break;
 716         case METRICS_THROTTLER_STATUS:
 717                 *value = metrics->ThrottlerStatus;
 718                 break;
 719         case METRICS_CURR_FANSPEED:
 720                 *value = metrics->CurrFanSpeed;
 721                 break;
 722         default:
 723                 *value = UINT_MAX;
 724                 break;
 725         }
 726
 727         return ret;
 728 }
 729
 730 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
 731                                               MetricsMember_t member,
 732                                               uint32_t *value)
 733 {
 734         struct smu_table_context *smu_table = &smu->smu_table;
 735         SmuMetrics_NV12_legacy_t *metrics =
 736                 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
 737         int ret = 0;
 738
 739         ret = smu_cmn_get_metrics_table(smu,
 740                                         NULL,
 741                                         false);
 742         if (ret)
 743                 return ret;
 744
 745         switch (member) {
 746         case METRICS_CURR_GFXCLK:
 747                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 748                 break;
 749         case METRICS_CURR_SOCCLK:
 750                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 751                 break;
 752         case METRICS_CURR_UCLK:
 753                 *value = metrics->CurrClock[PPCLK_UCLK];
 754                 break;
 755         case METRICS_CURR_VCLK:
 756                 *value = metrics->CurrClock[PPCLK_VCLK];
 757                 break;
 758         case METRICS_CURR_DCLK:
 759                 *value = metrics->CurrClock[PPCLK_DCLK];
 760                 break;
 761         case METRICS_CURR_DCEFCLK:
 762                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 763                 break;
 764         case METRICS_AVERAGE_GFXCLK:
 765                 *value = metrics->AverageGfxclkFrequency;
 766                 break;
 767         case METRICS_AVERAGE_SOCCLK:
 768                 *value = metrics->AverageSocclkFrequency;
 769                 break;
 770         case METRICS_AVERAGE_UCLK:
 771                 *value = metrics->AverageUclkFrequency;
 772                 break;
 773         case METRICS_AVERAGE_GFXACTIVITY:
 774                 *value = metrics->AverageGfxActivity;
 775                 break;
 776         case METRICS_AVERAGE_MEMACTIVITY:
 777                 *value = metrics->AverageUclkActivity;
 778                 break;
 779         case METRICS_AVERAGE_SOCKETPOWER:
 780                 *value = metrics->AverageSocketPower << 8;
 781                 break;
 782         case METRICS_TEMPERATURE_EDGE:
 783                 *value = metrics->TemperatureEdge *
 784                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 785                 break;
 786         case METRICS_TEMPERATURE_HOTSPOT:
 787                 *value = metrics->TemperatureHotspot *
 788                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 789                 break;
 790         case METRICS_TEMPERATURE_MEM:
 791                 *value = metrics->TemperatureMem *
 792                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 793                 break;
 794         case METRICS_TEMPERATURE_VRGFX:
 795                 *value = metrics->TemperatureVrGfx *
 796                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 797                 break;
 798         case METRICS_TEMPERATURE_VRSOC:
 799                 *value = metrics->TemperatureVrSoc *
 800                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 801                 break;
 802         case METRICS_THROTTLER_STATUS:
 803                 *value = metrics->ThrottlerStatus;
 804                 break;
 805         case METRICS_CURR_FANSPEED:
 806                 *value = metrics->CurrFanSpeed;
 807                 break;
 808         default:
 809                 *value = UINT_MAX;
 810                 break;
 811         }
 812
 813         return ret;
 814 }
 815
 816 static int navi12_get_smu_metrics_data(struct smu_context *smu,
 817                                        MetricsMember_t member,
 818                                        uint32_t *value)
 819 {
 820         struct smu_table_context *smu_table = &smu->smu_table;
 821         SmuMetrics_NV12_t *metrics =
 822                 (SmuMetrics_NV12_t *)smu_table->metrics_table;
 823         int ret = 0;
 824
 825         ret = smu_cmn_get_metrics_table(smu,
 826                                         NULL,
 827                                         false);
 828         if (ret)
 829                 return ret;
 830
 831         switch (member) {
 832         case METRICS_CURR_GFXCLK:
 833                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 834                 break;
 835         case METRICS_CURR_SOCCLK:
 836                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 837                 break;
 838         case METRICS_CURR_UCLK:
 839                 *value = metrics->CurrClock[PPCLK_UCLK];
 840                 break;
 841         case METRICS_CURR_VCLK:
 842                 *value = metrics->CurrClock[PPCLK_VCLK];
 843                 break;
 844         case METRICS_CURR_DCLK:
 845                 *value = metrics->CurrClock[PPCLK_DCLK];
 846                 break;
 847         case METRICS_CURR_DCEFCLK:
 848                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 849                 break;
 850         case METRICS_AVERAGE_GFXCLK:
 851                 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
 852                         *value = metrics->AverageGfxclkFrequencyPreDs;
 853                 else
 854                         *value = metrics->AverageGfxclkFrequencyPostDs;
 855                 break;
 856         case METRICS_AVERAGE_SOCCLK:
 857                 *value = metrics->AverageSocclkFrequency;
 858                 break;
 859         case METRICS_AVERAGE_UCLK:
 860                 *value = metrics->AverageUclkFrequencyPostDs;
 861                 break;
 862         case METRICS_AVERAGE_GFXACTIVITY:
 863                 *value = metrics->AverageGfxActivity;
 864                 break;
 865         case METRICS_AVERAGE_MEMACTIVITY:
 866                 *value = metrics->AverageUclkActivity;
 867                 break;
 868         case METRICS_AVERAGE_SOCKETPOWER:
 869                 *value = metrics->AverageSocketPower << 8;
 870                 break;
 871         case METRICS_TEMPERATURE_EDGE:
 872                 *value = metrics->TemperatureEdge *
 873                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 874                 break;
 875         case METRICS_TEMPERATURE_HOTSPOT:
 876                 *value = metrics->TemperatureHotspot *
 877                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 878                 break;
 879         case METRICS_TEMPERATURE_MEM:
 880                 *value = metrics->TemperatureMem *
 881                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 882                 break;
 883         case METRICS_TEMPERATURE_VRGFX:
 884                 *value = metrics->TemperatureVrGfx *
 885                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 886                 break;
 887         case METRICS_TEMPERATURE_VRSOC:
 888                 *value = metrics->TemperatureVrSoc *
 889                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 890                 break;
 891         case METRICS_THROTTLER_STATUS:
 892                 *value = metrics->ThrottlerStatus;
 893                 break;
 894         case METRICS_CURR_FANSPEED:
 895                 *value = metrics->CurrFanSpeed;
 896                 break;
 897         default:
 898                 *value = UINT_MAX;
 899                 break;
 900         }
 901
 902         return ret;
 903 }
 904
 905 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
 906                                        MetricsMember_t member,
 907                                        uint32_t *value)
 908 {
 909         struct amdgpu_device *adev = smu->adev;
 910         uint32_t smu_version;
 911         int ret = 0;
 912
 913         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 914         if (ret) {
 915                 dev_err(adev->dev, "Failed to get smu version!\n");
 916                 return ret;
 917         }
 918
 919         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
 920         case IP_VERSION(11, 0, 9):
 921                 if (smu_version > 0x00341C00)
 922                         ret = navi12_get_smu_metrics_data(smu, member, value);
 923                 else
 924                         ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
 925                 break;
 926         case IP_VERSION(11, 0, 0):
 927         case IP_VERSION(11, 0, 5):
 928         default:
 929                 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
 930                       IP_VERSION(11, 0, 5)) &&
 931                      smu_version > 0x00351F00) ||
 932                     ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
 933                       IP_VERSION(11, 0, 0)) &&
 934                      smu_version > 0x002A3B00))
 935                         ret = navi10_get_smu_metrics_data(smu, member, value);
 936                 else
 937                         ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
 938                 break;
 939         }
 940
 941         return ret;
 942 }
 943
 944 static int navi10_allocate_dpm_context(struct smu_context *smu)
 945 {
 946         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 947
 948         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 949                                        GFP_KERNEL);
 950         if (!smu_dpm->dpm_context)
 951                 return -ENOMEM;
 952
 953         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 954
 955         return 0;
 956 }
 957
 958 static int navi10_init_smc_tables(struct smu_context *smu)
 959 {
 960         int ret = 0;
 961
 962         ret = navi10_tables_init(smu);
 963         if (ret)
 964                 return ret;
 965
 966         ret = navi10_allocate_dpm_context(smu);
 967         if (ret)
 968                 return ret;
 969
 970         return smu_v11_0_init_smc_tables(smu);
 971 }
 972
 973 static int navi10_set_default_dpm_table(struct smu_context *smu)
 974 {
 975         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 976         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 977         struct smu_11_0_dpm_table *dpm_table;
 978         int ret = 0;
 979
 980         /* socclk dpm table setup */
 981         dpm_table = &dpm_context->dpm_tables.soc_table;
 982         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 983                 ret = smu_v11_0_set_single_dpm_table(smu,
 984                                                      SMU_SOCCLK,
 985                                                      dpm_table);
 986                 if (ret)
 987                         return ret;
 988                 dpm_table->is_fine_grained =
 989                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 990         } else {
 991                 dpm_table->count = 1;
 992                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 993                 dpm_table->dpm_levels[0].enabled = true;
 994                 dpm_table->min = dpm_table->dpm_levels[0].value;
 995                 dpm_table->max = dpm_table->dpm_levels[0].value;
 996         }
 997
 998         /* gfxclk dpm table setup */
 999         dpm_table = &dpm_context->dpm_tables.gfx_table;
1000         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1001                 ret = smu_v11_0_set_single_dpm_table(smu,
1002                                                      SMU_GFXCLK,
1003                                                      dpm_table);
1004                 if (ret)
1005                         return ret;
1006                 dpm_table->is_fine_grained =
1007                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1008         } else {
1009                 dpm_table->count = 1;
1010                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1011                 dpm_table->dpm_levels[0].enabled = true;
1012                 dpm_table->min = dpm_table->dpm_levels[0].value;
1013                 dpm_table->max = dpm_table->dpm_levels[0].value;
1014         }
1015
1016         /* uclk dpm table setup */
1017         dpm_table = &dpm_context->dpm_tables.uclk_table;
1018         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1019                 ret = smu_v11_0_set_single_dpm_table(smu,
1020                                                      SMU_UCLK,
1021                                                      dpm_table);
1022                 if (ret)
1023                         return ret;
1024                 dpm_table->is_fine_grained =
1025                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1026         } else {
1027                 dpm_table->count = 1;
1028                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1029                 dpm_table->dpm_levels[0].enabled = true;
1030                 dpm_table->min = dpm_table->dpm_levels[0].value;
1031                 dpm_table->max = dpm_table->dpm_levels[0].value;
1032         }
1033
1034         /* vclk dpm table setup */
1035         dpm_table = &dpm_context->dpm_tables.vclk_table;
1036         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1037                 ret = smu_v11_0_set_single_dpm_table(smu,
1038                                                      SMU_VCLK,
1039                                                      dpm_table);
1040                 if (ret)
1041                         return ret;
1042                 dpm_table->is_fine_grained =
1043                         !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1044         } else {
1045                 dpm_table->count = 1;
1046                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1047                 dpm_table->dpm_levels[0].enabled = true;
1048                 dpm_table->min = dpm_table->dpm_levels[0].value;
1049                 dpm_table->max = dpm_table->dpm_levels[0].value;
1050         }
1051
1052         /* dclk dpm table setup */
1053         dpm_table = &dpm_context->dpm_tables.dclk_table;
1054         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1055                 ret = smu_v11_0_set_single_dpm_table(smu,
1056                                                      SMU_DCLK,
1057                                                      dpm_table);
1058                 if (ret)
1059                         return ret;
1060                 dpm_table->is_fine_grained =
1061                         !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1062         } else {
1063                 dpm_table->count = 1;
1064                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1065                 dpm_table->dpm_levels[0].enabled = true;
1066                 dpm_table->min = dpm_table->dpm_levels[0].value;
1067                 dpm_table->max = dpm_table->dpm_levels[0].value;
1068         }
1069
1070         /* dcefclk dpm table setup */
1071         dpm_table = &dpm_context->dpm_tables.dcef_table;
1072         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1073                 ret = smu_v11_0_set_single_dpm_table(smu,
1074                                                      SMU_DCEFCLK,
1075                                                      dpm_table);
1076                 if (ret)
1077                         return ret;
1078                 dpm_table->is_fine_grained =
1079                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1080         } else {
1081                 dpm_table->count = 1;
1082                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1083                 dpm_table->dpm_levels[0].enabled = true;
1084                 dpm_table->min = dpm_table->dpm_levels[0].value;
1085                 dpm_table->max = dpm_table->dpm_levels[0].value;
1086         }
1087
1088         /* pixelclk dpm table setup */
1089         dpm_table = &dpm_context->dpm_tables.pixel_table;
1090         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1091                 ret = smu_v11_0_set_single_dpm_table(smu,
1092                                                      SMU_PIXCLK,
1093                                                      dpm_table);
1094                 if (ret)
1095                         return ret;
1096                 dpm_table->is_fine_grained =
1097                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1098         } else {
1099                 dpm_table->count = 1;
1100                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1101                 dpm_table->dpm_levels[0].enabled = true;
1102                 dpm_table->min = dpm_table->dpm_levels[0].value;
1103                 dpm_table->max = dpm_table->dpm_levels[0].value;
1104         }
1105
1106         /* displayclk dpm table setup */
1107         dpm_table = &dpm_context->dpm_tables.display_table;
1108         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1109                 ret = smu_v11_0_set_single_dpm_table(smu,
1110                                                      SMU_DISPCLK,
1111                                                      dpm_table);
1112                 if (ret)
1113                         return ret;
1114                 dpm_table->is_fine_grained =
1115                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1116         } else {
1117                 dpm_table->count = 1;
1118                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1119                 dpm_table->dpm_levels[0].enabled = true;
1120                 dpm_table->min = dpm_table->dpm_levels[0].value;
1121                 dpm_table->max = dpm_table->dpm_levels[0].value;
1122         }
1123
1124         /* phyclk dpm table setup */
1125         dpm_table = &dpm_context->dpm_tables.phy_table;
1126         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1127                 ret = smu_v11_0_set_single_dpm_table(smu,
1128                                                      SMU_PHYCLK,
1129                                                      dpm_table);
1130                 if (ret)
1131                         return ret;
1132                 dpm_table->is_fine_grained =
1133                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1134         } else {
1135                 dpm_table->count = 1;
1136                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1137                 dpm_table->dpm_levels[0].enabled = true;
1138                 dpm_table->min = dpm_table->dpm_levels[0].value;
1139                 dpm_table->max = dpm_table->dpm_levels[0].value;
1140         }
1141
1142         return 0;
1143 }
1144
1145 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1146 {
1147         int ret = 0;
1148
1149         if (enable) {
1150                 /* vcn dpm on is a prerequisite for vcn power gate messages */
1151                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1152                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1153                         if (ret)
1154                                 return ret;
1155                 }
1156         } else {
1157                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1158                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1159                         if (ret)
1160                                 return ret;
1161                 }
1162         }
1163
1164         return ret;
1165 }
1166
1167 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1168 {
1169         int ret = 0;
1170
1171         if (enable) {
1172                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1173                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1174                         if (ret)
1175                                 return ret;
1176                 }
1177         } else {
1178                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1179                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1180                         if (ret)
1181                                 return ret;
1182                 }
1183         }
1184
1185         return ret;
1186 }
1187
1188 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1189                                        enum smu_clk_type clk_type,
1190                                        uint32_t *value)
1191 {
1192         MetricsMember_t member_type;
1193         int clk_id = 0;
1194
1195         clk_id = smu_cmn_to_asic_specific_index(smu,
1196                                                 CMN2ASIC_MAPPING_CLK,
1197                                                 clk_type);
1198         if (clk_id < 0)
1199                 return clk_id;
1200
1201         switch (clk_id) {
1202         case PPCLK_GFXCLK:
1203                 member_type = METRICS_CURR_GFXCLK;
1204                 break;
1205         case PPCLK_UCLK:
1206                 member_type = METRICS_CURR_UCLK;
1207                 break;
1208         case PPCLK_SOCCLK:
1209                 member_type = METRICS_CURR_SOCCLK;
1210                 break;
1211         case PPCLK_VCLK:
1212                 member_type = METRICS_CURR_VCLK;
1213                 break;
1214         case PPCLK_DCLK:
1215                 member_type = METRICS_CURR_DCLK;
1216                 break;
1217         case PPCLK_DCEFCLK:
1218                 member_type = METRICS_CURR_DCEFCLK;
1219                 break;
1220         default:
1221                 return -EINVAL;
1222         }
1223
1224         return navi1x_get_smu_metrics_data(smu,
1225                                            member_type,
1226                                            value);
1227 }
1228
1229 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1230 {
1231         PPTable_t *pptable = smu->smu_table.driver_pptable;
1232         DpmDescriptor_t *dpm_desc = NULL;
1233         uint32_t clk_index = 0;
1234
1235         clk_index = smu_cmn_to_asic_specific_index(smu,
1236                                                    CMN2ASIC_MAPPING_CLK,
1237                                                    clk_type);
1238         dpm_desc = &pptable->DpmDescriptor[clk_index];
1239
1240         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1241         return dpm_desc->SnapToDiscrete == 0;
1242 }
1243
1244 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1245 {
1246         return od_table->cap[cap];
1247 }
1248
1249 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1250                                         enum SMU_11_0_ODSETTING_ID setting,
1251                                         uint32_t *min, uint32_t *max)
1252 {
1253         if (min)
1254                 *min = od_table->min[setting];
1255         if (max)
1256                 *max = od_table->max[setting];
1257 }
1258
1259 static int navi10_emit_clk_levels(struct smu_context *smu,
1260                                   enum smu_clk_type clk_type,
1261                                   char *buf,
1262                                   int *offset)
1263 {
1264         uint16_t *curve_settings;
1265         int ret = 0;
1266         uint32_t cur_value = 0, value = 0;
1267         uint32_t freq_values[3] = {0};
1268         uint32_t i, levels, mark_index = 0, count = 0;
1269         struct smu_table_context *table_context = &smu->smu_table;
1270         uint32_t gen_speed, lane_width;
1271         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1272         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1273         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1274         OverDriveTable_t *od_table =
1275                 (OverDriveTable_t *)table_context->overdrive_table;
1276         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1277         uint32_t min_value, max_value;
1278
1279         switch (clk_type) {
1280         case SMU_GFXCLK:
1281         case SMU_SCLK:
1282         case SMU_SOCCLK:
1283         case SMU_MCLK:
1284         case SMU_UCLK:
1285         case SMU_FCLK:
1286         case SMU_VCLK:
1287         case SMU_DCLK:
1288         case SMU_DCEFCLK:
1289                 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1290                 if (ret)
1291                         return ret;
1292
1293                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1294                 if (ret)
1295                         return ret;
1296
1297                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1298                         for (i = 0; i < count; i++) {
1299                                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1300                                                                       clk_type, i, &value);
1301                                 if (ret)
1302                                         return ret;
1303
1304                                 *offset += sysfs_emit_at(buf, *offset,
1305                                                 "%d: %uMhz %s\n",
1306                                                 i, value,
1307                                                 cur_value == value ? "*" : "");
1308                         }
1309                 } else {
1310                         ret = smu_v11_0_get_dpm_freq_by_index(smu,
1311                                                               clk_type, 0, &freq_values[0]);
1312                         if (ret)
1313                                 return ret;
1314                         ret = smu_v11_0_get_dpm_freq_by_index(smu,
1315                                                               clk_type,
1316                                                               count - 1,
1317                                                               &freq_values[2]);
1318                         if (ret)
1319                                 return ret;
1320
1321                         freq_values[1] = cur_value;
1322                         mark_index = cur_value == freq_values[0] ? 0 :
1323                                      cur_value == freq_values[2] ? 2 : 1;
1324
1325                         levels = 3;
1326                         if (mark_index != 1) {
1327                                 levels = 2;
1328                                 freq_values[1] = freq_values[2];
1329                         }
1330
1331                         for (i = 0; i < levels; i++) {
1332                                 *offset += sysfs_emit_at(buf, *offset,
1333                                                 "%d: %uMhz %s\n",
1334                                                 i, freq_values[i],
1335                                                 i == mark_index ? "*" : "");
1336                         }
1337                 }
1338                 break;
1339         case SMU_PCIE:
1340                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1341                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1342                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1343                         *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i,
1344                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1345                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1346                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1347                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1348                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1349                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1350                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1351                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1352                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1353                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1354                                         pptable->LclkFreq[i],
1355                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1356                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1357                                         "*" : "");
1358                 }
1359                 break;
1360         case SMU_OD_SCLK:
1361                 if (!smu->od_enabled || !od_table || !od_settings)
1362                         return -EOPNOTSUPP;
1363                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1364                         break;
1365                 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n",
1366                                           od_table->GfxclkFmin, od_table->GfxclkFmax);
1367                 break;
1368         case SMU_OD_MCLK:
1369                 if (!smu->od_enabled || !od_table || !od_settings)
1370                         return -EOPNOTSUPP;
1371                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1372                         break;
1373                 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax);
1374                 break;
1375         case SMU_OD_VDDC_CURVE:
1376                 if (!smu->od_enabled || !od_table || !od_settings)
1377                         return -EOPNOTSUPP;
1378                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1379                         break;
1380                 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n");
1381                 for (i = 0; i < 3; i++) {
1382                         switch (i) {
1383                         case 0:
1384                                 curve_settings = &od_table->GfxclkFreq1;
1385                                 break;
1386                         case 1:
1387                                 curve_settings = &od_table->GfxclkFreq2;
1388                                 break;
1389                         case 2:
1390                                 curve_settings = &od_table->GfxclkFreq3;
1391                                 break;
1392                         default:
1393                                 break;
1394                         }
1395                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n",
1396                                                   i, curve_settings[0],
1397                                         curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1398                 }
1399                 break;
1400         case SMU_OD_RANGE:
1401                 if (!smu->od_enabled || !od_table || !od_settings)
1402                         return -EOPNOTSUPP;
1403                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
1404
1405                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1406                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1407                                                     &min_value, NULL);
1408                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1409                                                     NULL, &max_value);
1410                         *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n",
1411                                         min_value, max_value);
1412                 }
1413
1414                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1415                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1416                                                     &min_value, &max_value);
1417                         *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n",
1418                                         min_value, max_value);
1419                 }
1420
1421                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1422                         navi10_od_setting_get_range(od_settings,
1423                                                     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1424                                                     &min_value, &max_value);
1425                         *offset += sysfs_emit_at(buf, *offset,
1426                                                  "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1427                                                  min_value, max_value);
1428                         navi10_od_setting_get_range(od_settings,
1429                                                     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1430                                                     &min_value, &max_value);
1431                         *offset += sysfs_emit_at(buf, *offset,
1432                                                  "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1433                                                  min_value, max_value);
1434                         navi10_od_setting_get_range(od_settings,
1435                                                     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1436                                                     &min_value, &max_value);
1437                         *offset += sysfs_emit_at(buf, *offset,
1438                                                  "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1439                                                  min_value, max_value);
1440                         navi10_od_setting_get_range(od_settings,
1441                                                     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1442                                                     &min_value, &max_value);
1443                         *offset += sysfs_emit_at(buf, *offset,
1444                                                  "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1445                                                  min_value, max_value);
1446                         navi10_od_setting_get_range(od_settings,
1447                                                     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1448                                                     &min_value, &max_value);
1449                         *offset += sysfs_emit_at(buf, *offset,
1450                                                  "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1451                                                  min_value, max_value);
1452                         navi10_od_setting_get_range(od_settings,
1453                                                     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1454                                                     &min_value, &max_value);
1455                         *offset += sysfs_emit_at(buf, *offset,
1456                                                  "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1457                                                  min_value, max_value);
1458                 }
1459
1460                 break;
1461         default:
1462                 break;
1463         }
1464
1465         return 0;
1466 }
1467
1468 static int navi10_print_clk_levels(struct smu_context *smu,
1469                         enum smu_clk_type clk_type, char *buf)
1470 {
1471         uint16_t *curve_settings;
1472         int i, levels, size = 0, ret = 0;
1473         uint32_t cur_value = 0, value = 0, count = 0;
1474         uint32_t freq_values[3] = {0};
1475         uint32_t mark_index = 0;
1476         struct smu_table_context *table_context = &smu->smu_table;
1477         uint32_t gen_speed, lane_width;
1478         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1479         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1480         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1481         OverDriveTable_t *od_table =
1482                 (OverDriveTable_t *)table_context->overdrive_table;
1483         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1484         uint32_t min_value, max_value;
1485
1486         smu_cmn_get_sysfs_buf(&buf, &size);
1487
1488         switch (clk_type) {
1489         case SMU_GFXCLK:
1490         case SMU_SCLK:
1491         case SMU_SOCCLK:
1492         case SMU_MCLK:
1493         case SMU_UCLK:
1494         case SMU_FCLK:
1495         case SMU_VCLK:
1496         case SMU_DCLK:
1497         case SMU_DCEFCLK:
1498                 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1499                 if (ret)
1500                         return size;
1501
1502                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1503                 if (ret)
1504                         return size;
1505
1506                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1507                         for (i = 0; i < count; i++) {
1508                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1509                                 if (ret)
1510                                         return size;
1511
1512                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1513                                                 cur_value == value ? "*" : "");
1514                         }
1515                 } else {
1516                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1517                         if (ret)
1518                                 return size;
1519                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1520                         if (ret)
1521                                 return size;
1522
1523                         freq_values[1] = cur_value;
1524                         mark_index = cur_value == freq_values[0] ? 0 :
1525                                      cur_value == freq_values[2] ? 2 : 1;
1526
1527                         levels = 3;
1528                         if (mark_index != 1) {
1529                                 levels = 2;
1530                                 freq_values[1] = freq_values[2];
1531                         }
1532
1533                         for (i = 0; i < levels; i++) {
1534                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1535                                                 i == mark_index ? "*" : "");
1536                         }
1537                 }
1538                 break;
1539         case SMU_PCIE:
1540                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1541                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1542                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1543                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1544                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1545                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1546                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1547                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1548                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1549                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1550                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1551                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1552                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1553                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1554                                         pptable->LclkFreq[i],
1555                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1556                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1557                                         "*" : "");
1558                 break;
1559         case SMU_OD_SCLK:
1560                 if (!smu->od_enabled || !od_table || !od_settings)
1561                         break;
1562                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1563                         break;
1564                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1565                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1566                                       od_table->GfxclkFmin, od_table->GfxclkFmax);
1567                 break;
1568         case SMU_OD_MCLK:
1569                 if (!smu->od_enabled || !od_table || !od_settings)
1570                         break;
1571                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1572                         break;
1573                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1574                 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax);
1575                 break;
1576         case SMU_OD_VDDC_CURVE:
1577                 if (!smu->od_enabled || !od_table || !od_settings)
1578                         break;
1579                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1580                         break;
1581                 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
1582                 for (i = 0; i < 3; i++) {
1583                         switch (i) {
1584                         case 0:
1585                                 curve_settings = &od_table->GfxclkFreq1;
1586                                 break;
1587                         case 1:
1588                                 curve_settings = &od_table->GfxclkFreq2;
1589                                 break;
1590                         case 2:
1591                                 curve_settings = &od_table->GfxclkFreq3;
1592                                 break;
1593                         default:
1594                                 break;
1595                         }
1596                         size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n",
1597                                               i, curve_settings[0],
1598                                         curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1599                 }
1600                 break;
1601         case SMU_OD_RANGE:
1602                 if (!smu->od_enabled || !od_table || !od_settings)
1603                         break;
1604                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1605
1606                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1607                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1608                                                     &min_value, NULL);
1609                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1610                                                     NULL, &max_value);
1611                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1612                                         min_value, max_value);
1613                 }
1614
1615                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1616                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1617                                                     &min_value, &max_value);
1618                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1619                                         min_value, max_value);
1620                 }
1621
1622                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1623                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1624                                                     &min_value, &max_value);
1625                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1626                                               min_value, max_value);
1627                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1628                                                     &min_value, &max_value);
1629                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1630                                               min_value, max_value);
1631                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1632                                                     &min_value, &max_value);
1633                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1634                                               min_value, max_value);
1635                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1636                                                     &min_value, &max_value);
1637                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1638                                               min_value, max_value);
1639                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1640                                                     &min_value, &max_value);
1641                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1642                                               min_value, max_value);
1643                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1644                                                     &min_value, &max_value);
1645                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1646                                               min_value, max_value);
1647                 }
1648
1649                 break;
1650         default:
1651                 break;
1652         }
1653
1654         return size;
1655 }
1656
1657 static int navi10_force_clk_levels(struct smu_context *smu,
1658                                    enum smu_clk_type clk_type, uint32_t mask)
1659 {
1660
1661         int ret = 0;
1662         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1663
1664         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1665         soft_max_level = mask ? (fls(mask) - 1) : 0;
1666
1667         switch (clk_type) {
1668         case SMU_GFXCLK:
1669         case SMU_SCLK:
1670         case SMU_SOCCLK:
1671         case SMU_MCLK:
1672         case SMU_UCLK:
1673         case SMU_FCLK:
1674                 /* There is only 2 levels for fine grained DPM */
1675                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1676                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1677                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1678                 }
1679
1680                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1681                 if (ret)
1682                         return 0;
1683
1684                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1685                 if (ret)
1686                         return 0;
1687
1688                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1689                 if (ret)
1690                         return 0;
1691                 break;
1692         case SMU_DCEFCLK:
1693                 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n");
1694                 break;
1695
1696         default:
1697                 break;
1698         }
1699
1700         return 0;
1701 }
1702
1703 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1704 {
1705         struct smu_11_0_dpm_context *dpm_context =
1706                                 smu->smu_dpm.dpm_context;
1707         struct smu_11_0_dpm_table *gfx_table =
1708                                 &dpm_context->dpm_tables.gfx_table;
1709         struct smu_11_0_dpm_table *mem_table =
1710                                 &dpm_context->dpm_tables.uclk_table;
1711         struct smu_11_0_dpm_table *soc_table =
1712                                 &dpm_context->dpm_tables.soc_table;
1713         struct smu_umd_pstate_table *pstate_table =
1714                                 &smu->pstate_table;
1715         struct amdgpu_device *adev = smu->adev;
1716         uint32_t sclk_freq;
1717
1718         pstate_table->gfxclk_pstate.min = gfx_table->min;
1719         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1720         case IP_VERSION(11, 0, 0):
1721                 switch (adev->pdev->revision) {
1722                 case 0xf0: /* XTX */
1723                 case 0xc0:
1724                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1725                         break;
1726                 case 0xf1: /* XT */
1727                 case 0xc1:
1728                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1729                         break;
1730                 default: /* XL */
1731                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1732                         break;
1733                 }
1734                 break;
1735         case IP_VERSION(11, 0, 5):
1736                 switch (adev->pdev->revision) {
1737                 case 0xc7: /* XT */
1738                 case 0xf4:
1739                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1740                         break;
1741                 case 0xc1: /* XTM */
1742                 case 0xf2:
1743                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1744                         break;
1745                 case 0xc3: /* XLM */
1746                 case 0xf3:
1747                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1748                         break;
1749                 case 0xc5: /* XTX */
1750                 case 0xf6:
1751                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1752                         break;
1753                 default: /* XL */
1754                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1755                         break;
1756                 }
1757                 break;
1758         case IP_VERSION(11, 0, 9):
1759                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1760                 break;
1761         default:
1762                 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1763                 break;
1764         }
1765         pstate_table->gfxclk_pstate.peak = sclk_freq;
1766
1767         pstate_table->uclk_pstate.min = mem_table->min;
1768         pstate_table->uclk_pstate.peak = mem_table->max;
1769
1770         pstate_table->socclk_pstate.min = soc_table->min;
1771         pstate_table->socclk_pstate.peak = soc_table->max;
1772
1773         if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1774             mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1775             soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1776                 pstate_table->gfxclk_pstate.standard =
1777                         NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1778                 pstate_table->uclk_pstate.standard =
1779                         NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1780                 pstate_table->socclk_pstate.standard =
1781                         NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1782         } else {
1783                 pstate_table->gfxclk_pstate.standard =
1784                         pstate_table->gfxclk_pstate.min;
1785                 pstate_table->uclk_pstate.standard =
1786                         pstate_table->uclk_pstate.min;
1787                 pstate_table->socclk_pstate.standard =
1788                         pstate_table->socclk_pstate.min;
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1795                                                  enum smu_clk_type clk_type,
1796                                                  struct pp_clock_levels_with_latency *clocks)
1797 {
1798         int ret = 0, i = 0;
1799         uint32_t level_count = 0, freq = 0;
1800
1801         switch (clk_type) {
1802         case SMU_GFXCLK:
1803         case SMU_DCEFCLK:
1804         case SMU_SOCCLK:
1805         case SMU_MCLK:
1806         case SMU_UCLK:
1807                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1808                 if (ret)
1809                         return ret;
1810
1811                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1812                 clocks->num_levels = level_count;
1813
1814                 for (i = 0; i < level_count; i++) {
1815                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1816                         if (ret)
1817                                 return ret;
1818
1819                         clocks->data[i].clocks_in_khz = freq * 1000;
1820                         clocks->data[i].latency_in_us = 0;
1821                 }
1822                 break;
1823         default:
1824                 break;
1825         }
1826
1827         return ret;
1828 }
1829
1830 static int navi10_pre_display_config_changed(struct smu_context *smu)
1831 {
1832         int ret = 0;
1833         uint32_t max_freq = 0;
1834
1835         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1836         if (ret)
1837                 return ret;
1838
1839         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1840                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1841                 if (ret)
1842                         return ret;
1843                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1844                 if (ret)
1845                         return ret;
1846         }
1847
1848         return ret;
1849 }
1850
1851 static int navi10_display_config_changed(struct smu_context *smu)
1852 {
1853         int ret = 0;
1854
1855         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1856             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1857             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1858                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1859                                                   smu->display_config->num_display,
1860                                                   NULL);
1861                 if (ret)
1862                         return ret;
1863         }
1864
1865         return ret;
1866 }
1867
1868 static bool navi10_is_dpm_running(struct smu_context *smu)
1869 {
1870         int ret = 0;
1871         uint64_t feature_enabled;
1872
1873         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1874         if (ret)
1875                 return false;
1876
1877         return !!(feature_enabled & SMC_DPM_FEATURE);
1878 }
1879
1880 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1881                                     uint32_t *speed)
1882 {
1883         int ret = 0;
1884
1885         if (!speed)
1886                 return -EINVAL;
1887
1888         switch (smu_v11_0_get_fan_control_mode(smu)) {
1889         case AMD_FAN_CTRL_AUTO:
1890                 ret = navi10_get_smu_metrics_data(smu,
1891                                                   METRICS_CURR_FANSPEED,
1892                                                   speed);
1893                 break;
1894         default:
1895                 ret = smu_v11_0_get_fan_speed_rpm(smu,
1896                                                   speed);
1897                 break;
1898         }
1899
1900         return ret;
1901 }
1902
1903 static int navi10_get_fan_parameters(struct smu_context *smu)
1904 {
1905         PPTable_t *pptable = smu->smu_table.driver_pptable;
1906
1907         smu->fan_max_rpm = pptable->FanMaximumRpm;
1908
1909         return 0;
1910 }
1911
1912 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1913 {
1914         DpmActivityMonitorCoeffInt_t activity_monitor;
1915         uint32_t i, size = 0;
1916         int16_t workload_type = 0;
1917         static const char *title[] = {
1918                         "PROFILE_INDEX(NAME)",
1919                         "CLOCK_TYPE(NAME)",
1920                         "FPS",
1921                         "MinFreqType",
1922                         "MinActiveFreqType",
1923                         "MinActiveFreq",
1924                         "BoosterFreqType",
1925                         "BoosterFreq",
1926                         "PD_Data_limit_c",
1927                         "PD_Data_error_coeff",
1928                         "PD_Data_error_rate_coeff"};
1929         int result = 0;
1930
1931         if (!buf)
1932                 return -EINVAL;
1933
1934         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1935                         title[0], title[1], title[2], title[3], title[4], title[5],
1936                         title[6], title[7], title[8], title[9], title[10]);
1937
1938         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1939                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1940                 workload_type = smu_cmn_to_asic_specific_index(smu,
1941                                                                CMN2ASIC_MAPPING_WORKLOAD,
1942                                                                i);
1943                 if (workload_type < 0)
1944                         return -EINVAL;
1945
1946                 result = smu_cmn_update_table(smu,
1947                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1948                                           (void *)(&activity_monitor), false);
1949                 if (result) {
1950                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1951                         return result;
1952                 }
1953
1954                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1955                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1956
1957                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1958                         " ",
1959                         0,
1960                         "GFXCLK",
1961                         activity_monitor.Gfx_FPS,
1962                         activity_monitor.Gfx_MinFreqStep,
1963                         activity_monitor.Gfx_MinActiveFreqType,
1964                         activity_monitor.Gfx_MinActiveFreq,
1965                         activity_monitor.Gfx_BoosterFreqType,
1966                         activity_monitor.Gfx_BoosterFreq,
1967                         activity_monitor.Gfx_PD_Data_limit_c,
1968                         activity_monitor.Gfx_PD_Data_error_coeff,
1969                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1970
1971                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1972                         " ",
1973                         1,
1974                         "SOCCLK",
1975                         activity_monitor.Soc_FPS,
1976                         activity_monitor.Soc_MinFreqStep,
1977                         activity_monitor.Soc_MinActiveFreqType,
1978                         activity_monitor.Soc_MinActiveFreq,
1979                         activity_monitor.Soc_BoosterFreqType,
1980                         activity_monitor.Soc_BoosterFreq,
1981                         activity_monitor.Soc_PD_Data_limit_c,
1982                         activity_monitor.Soc_PD_Data_error_coeff,
1983                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1984
1985                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1986                         " ",
1987                         2,
1988                         "MEMLK",
1989                         activity_monitor.Mem_FPS,
1990                         activity_monitor.Mem_MinFreqStep,
1991                         activity_monitor.Mem_MinActiveFreqType,
1992                         activity_monitor.Mem_MinActiveFreq,
1993                         activity_monitor.Mem_BoosterFreqType,
1994                         activity_monitor.Mem_BoosterFreq,
1995                         activity_monitor.Mem_PD_Data_limit_c,
1996                         activity_monitor.Mem_PD_Data_error_coeff,
1997                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1998         }
1999
2000         return size;
2001 }
2002
2003 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
2004 {
2005         DpmActivityMonitorCoeffInt_t activity_monitor;
2006         int workload_type, ret = 0;
2007
2008         smu->power_profile_mode = input[size];
2009
2010         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
2011                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
2012                 return -EINVAL;
2013         }
2014
2015         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
2016
2017                 ret = smu_cmn_update_table(smu,
2018                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2019                                        (void *)(&activity_monitor), false);
2020                 if (ret) {
2021                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2022                         return ret;
2023                 }
2024
2025                 switch (input[0]) {
2026                 case 0: /* Gfxclk */
2027                         activity_monitor.Gfx_FPS = input[1];
2028                         activity_monitor.Gfx_MinFreqStep = input[2];
2029                         activity_monitor.Gfx_MinActiveFreqType = input[3];
2030                         activity_monitor.Gfx_MinActiveFreq = input[4];
2031                         activity_monitor.Gfx_BoosterFreqType = input[5];
2032                         activity_monitor.Gfx_BoosterFreq = input[6];
2033                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
2034                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
2035                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
2036                         break;
2037                 case 1: /* Socclk */
2038                         activity_monitor.Soc_FPS = input[1];
2039                         activity_monitor.Soc_MinFreqStep = input[2];
2040                         activity_monitor.Soc_MinActiveFreqType = input[3];
2041                         activity_monitor.Soc_MinActiveFreq = input[4];
2042                         activity_monitor.Soc_BoosterFreqType = input[5];
2043                         activity_monitor.Soc_BoosterFreq = input[6];
2044                         activity_monitor.Soc_PD_Data_limit_c = input[7];
2045                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
2046                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
2047                         break;
2048                 case 2: /* Memlk */
2049                         activity_monitor.Mem_FPS = input[1];
2050                         activity_monitor.Mem_MinFreqStep = input[2];
2051                         activity_monitor.Mem_MinActiveFreqType = input[3];
2052                         activity_monitor.Mem_MinActiveFreq = input[4];
2053                         activity_monitor.Mem_BoosterFreqType = input[5];
2054                         activity_monitor.Mem_BoosterFreq = input[6];
2055                         activity_monitor.Mem_PD_Data_limit_c = input[7];
2056                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
2057                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
2058                         break;
2059                 }
2060
2061                 ret = smu_cmn_update_table(smu,
2062                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2063                                        (void *)(&activity_monitor), true);
2064                 if (ret) {
2065                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2066                         return ret;
2067                 }
2068         }
2069
2070         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2071         workload_type = smu_cmn_to_asic_specific_index(smu,
2072                                                        CMN2ASIC_MAPPING_WORKLOAD,
2073                                                        smu->power_profile_mode);
2074         if (workload_type < 0)
2075                 return -EINVAL;
2076         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2077                                     1 << workload_type, NULL);
2078
2079         return ret;
2080 }
2081
2082 static int navi10_notify_smc_display_config(struct smu_context *smu)
2083 {
2084         struct smu_clocks min_clocks = {0};
2085         struct pp_display_clock_request clock_req;
2086         int ret = 0;
2087
2088         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2089         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2090         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2091
2092         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2093                 clock_req.clock_type = amd_pp_dcef_clock;
2094                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2095
2096                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
2097                 if (!ret) {
2098                         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2099                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2100                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
2101                                                                   min_clocks.dcef_clock_in_sr/100,
2102                                                                   NULL);
2103                                 if (ret) {
2104                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
2105                                         return ret;
2106                                 }
2107                         }
2108                 } else {
2109                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
2110                 }
2111         }
2112
2113         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2114                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
2115                 if (ret) {
2116                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
2117                         return ret;
2118                 }
2119         }
2120
2121         return 0;
2122 }
2123
2124 static int navi10_set_watermarks_table(struct smu_context *smu,
2125                                        struct pp_smu_wm_range_sets *clock_ranges)
2126 {
2127         Watermarks_t *table = smu->smu_table.watermarks_table;
2128         int ret = 0;
2129         int i;
2130
2131         if (clock_ranges) {
2132                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
2133                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
2134                         return -EINVAL;
2135
2136                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
2137                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
2138                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
2139                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
2140                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
2141                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
2142                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
2143                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
2144                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
2145
2146                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
2147                                 clock_ranges->reader_wm_sets[i].wm_inst;
2148                 }
2149
2150                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
2151                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
2152                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
2153                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
2154                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
2155                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
2156                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
2157                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
2158                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
2159
2160                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
2161                                 clock_ranges->writer_wm_sets[i].wm_inst;
2162                 }
2163
2164                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
2165         }
2166
2167         /* pass data to smu controller */
2168         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2169              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2170                 ret = smu_cmn_write_watermarks_table(smu);
2171                 if (ret) {
2172                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
2173                         return ret;
2174                 }
2175                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2176         }
2177
2178         return 0;
2179 }
2180
2181 static int navi10_read_sensor(struct smu_context *smu,
2182                                  enum amd_pp_sensors sensor,
2183                                  void *data, uint32_t *size)
2184 {
2185         int ret = 0;
2186         struct smu_table_context *table_context = &smu->smu_table;
2187         PPTable_t *pptable = table_context->driver_pptable;
2188
2189         if (!data || !size)
2190                 return -EINVAL;
2191
2192         switch (sensor) {
2193         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
2194                 *(uint32_t *)data = pptable->FanMaximumRpm;
2195                 *size = 4;
2196                 break;
2197         case AMDGPU_PP_SENSOR_MEM_LOAD:
2198                 ret = navi1x_get_smu_metrics_data(smu,
2199                                                   METRICS_AVERAGE_MEMACTIVITY,
2200                                                   (uint32_t *)data);
2201                 *size = 4;
2202                 break;
2203         case AMDGPU_PP_SENSOR_GPU_LOAD:
2204                 ret = navi1x_get_smu_metrics_data(smu,
2205                                                   METRICS_AVERAGE_GFXACTIVITY,
2206                                                   (uint32_t *)data);
2207                 *size = 4;
2208                 break;
2209         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
2210                 ret = navi1x_get_smu_metrics_data(smu,
2211                                                   METRICS_AVERAGE_SOCKETPOWER,
2212                                                   (uint32_t *)data);
2213                 *size = 4;
2214                 break;
2215         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2216                 ret = navi1x_get_smu_metrics_data(smu,
2217                                                   METRICS_TEMPERATURE_HOTSPOT,
2218                                                   (uint32_t *)data);
2219                 *size = 4;
2220                 break;
2221         case AMDGPU_PP_SENSOR_EDGE_TEMP:
2222                 ret = navi1x_get_smu_metrics_data(smu,
2223                                                   METRICS_TEMPERATURE_EDGE,
2224                                                   (uint32_t *)data);
2225                 *size = 4;
2226                 break;
2227         case AMDGPU_PP_SENSOR_MEM_TEMP:
2228                 ret = navi1x_get_smu_metrics_data(smu,
2229                                                   METRICS_TEMPERATURE_MEM,
2230                                                   (uint32_t *)data);
2231                 *size = 4;
2232                 break;
2233         case AMDGPU_PP_SENSOR_GFX_MCLK:
2234                 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2235                 *(uint32_t *)data *= 100;
2236                 *size = 4;
2237                 break;
2238         case AMDGPU_PP_SENSOR_GFX_SCLK:
2239                 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2240                 *(uint32_t *)data *= 100;
2241                 *size = 4;
2242                 break;
2243         case AMDGPU_PP_SENSOR_VDDGFX:
2244                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2245                 *size = 4;
2246                 break;
2247         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2248         default:
2249                 ret = -EOPNOTSUPP;
2250                 break;
2251         }
2252
2253         return ret;
2254 }
2255
2256 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2257 {
2258         uint32_t num_discrete_levels = 0;
2259         uint16_t *dpm_levels = NULL;
2260         uint16_t i = 0;
2261         struct smu_table_context *table_context = &smu->smu_table;
2262         PPTable_t *driver_ppt = NULL;
2263
2264         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2265                 return -EINVAL;
2266
2267         driver_ppt = table_context->driver_pptable;
2268         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2269         dpm_levels = driver_ppt->FreqTableUclk;
2270
2271         if (num_discrete_levels == 0 || dpm_levels == NULL)
2272                 return -EINVAL;
2273
2274         *num_states = num_discrete_levels;
2275         for (i = 0; i < num_discrete_levels; i++) {
2276                 /* convert to khz */
2277                 *clocks_in_khz = (*dpm_levels) * 1000;
2278                 clocks_in_khz++;
2279                 dpm_levels++;
2280         }
2281
2282         return 0;
2283 }
2284
2285 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2286                                                 struct smu_temperature_range *range)
2287 {
2288         struct smu_table_context *table_context = &smu->smu_table;
2289         struct smu_11_0_powerplay_table *powerplay_table =
2290                                 table_context->power_play_table;
2291         PPTable_t *pptable = smu->smu_table.driver_pptable;
2292
2293         if (!range)
2294                 return -EINVAL;
2295
2296         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2297
2298         range->max = pptable->TedgeLimit *
2299                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2300         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2301                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2302         range->hotspot_crit_max = pptable->ThotspotLimit *
2303                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2304         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2305                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2306         range->mem_crit_max = pptable->TmemLimit *
2307                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2308         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2309                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2310         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2311
2312         return 0;
2313 }
2314
2315 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2316                                                 bool disable_memory_clock_switch)
2317 {
2318         int ret = 0;
2319         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2320                 (struct smu_11_0_max_sustainable_clocks *)
2321                         smu->smu_table.max_sustainable_clocks;
2322         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2323         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2324
2325         if (smu->disable_uclk_switch == disable_memory_clock_switch)
2326                 return 0;
2327
2328         if (disable_memory_clock_switch)
2329                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2330         else
2331                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2332
2333         if (!ret)
2334                 smu->disable_uclk_switch = disable_memory_clock_switch;
2335
2336         return ret;
2337 }
2338
2339 static int navi10_get_power_limit(struct smu_context *smu,
2340                                   uint32_t *current_power_limit,
2341                                   uint32_t *default_power_limit,
2342                                   uint32_t *max_power_limit)
2343 {
2344         struct smu_11_0_powerplay_table *powerplay_table =
2345                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2346         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2347         PPTable_t *pptable = smu->smu_table.driver_pptable;
2348         uint32_t power_limit, od_percent;
2349
2350         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2351                 /* the last hope to figure out the ppt limit */
2352                 if (!pptable) {
2353                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2354                         return -EINVAL;
2355                 }
2356                 power_limit =
2357                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2358         }
2359
2360         if (current_power_limit)
2361                 *current_power_limit = power_limit;
2362         if (default_power_limit)
2363                 *default_power_limit = power_limit;
2364
2365         if (max_power_limit) {
2366                 if (smu->od_enabled &&
2367                     navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2368                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2369
2370                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2371
2372                         power_limit *= (100 + od_percent);
2373                         power_limit /= 100;
2374                 }
2375
2376                 *max_power_limit = power_limit;
2377         }
2378
2379         return 0;
2380 }
2381
2382 static int navi10_update_pcie_parameters(struct smu_context *smu,
2383                                      uint32_t pcie_gen_cap,
2384                                      uint32_t pcie_width_cap)
2385 {
2386         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2387         PPTable_t *pptable = smu->smu_table.driver_pptable;
2388         uint32_t smu_pcie_arg;
2389         int ret, i;
2390
2391         /* lclk dpm table setup */
2392         for (i = 0; i < MAX_PCIE_CONF; i++) {
2393                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2394                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2395         }
2396
2397         for (i = 0; i < NUM_LINK_LEVELS; i++) {
2398                 smu_pcie_arg = (i << 16) |
2399                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2400                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2401                                         pptable->PcieLaneCount[i] : pcie_width_cap);
2402                 ret = smu_cmn_send_smc_msg_with_param(smu,
2403                                           SMU_MSG_OverridePcieParameters,
2404                                           smu_pcie_arg,
2405                                           NULL);
2406
2407                 if (ret)
2408                         return ret;
2409
2410                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2411                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2412                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2413                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2414         }
2415
2416         return 0;
2417 }
2418
2419 static inline void navi10_dump_od_table(struct smu_context *smu,
2420                                         OverDriveTable_t *od_table)
2421 {
2422         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2423         dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2424         dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2425         dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2426         dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2427         dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2428 }
2429
2430 static int navi10_od_setting_check_range(struct smu_context *smu,
2431                                          struct smu_11_0_overdrive_table *od_table,
2432                                          enum SMU_11_0_ODSETTING_ID setting,
2433                                          uint32_t value)
2434 {
2435         if (value < od_table->min[setting]) {
2436                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2437                 return -EINVAL;
2438         }
2439         if (value > od_table->max[setting]) {
2440                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2441                 return -EINVAL;
2442         }
2443         return 0;
2444 }
2445
2446 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2447                                                      uint16_t *voltage,
2448                                                      uint32_t freq)
2449 {
2450         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2451         uint32_t value = 0;
2452         int ret;
2453
2454         ret = smu_cmn_send_smc_msg_with_param(smu,
2455                                           SMU_MSG_GetVoltageByDpm,
2456                                           param,
2457                                           &value);
2458         if (ret) {
2459                 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2460                 return ret;
2461         }
2462
2463         *voltage = (uint16_t)value;
2464
2465         return 0;
2466 }
2467
2468 static int navi10_baco_enter(struct smu_context *smu)
2469 {
2470         struct amdgpu_device *adev = smu->adev;
2471
2472         /*
2473          * This aims the case below:
2474          *   amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded
2475          *
2476          * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To
2477          * make that possible, PMFW needs to acknowledge the dstate transition
2478          * process for both gfx(function 0) and audio(function 1) function of
2479          * the ASIC.
2480          *
2481          * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the
2482          * device representing the audio function of the ASIC. And that means
2483          * even if the sound driver(snd_hda_intel) was not loaded yet, it's still
2484          * possible runpm suspend kicked on the ASIC. However without the dstate
2485          * transition notification from audio function, pmfw cannot handle the
2486          * BACO in/exit correctly. And that will cause driver hang on runpm
2487          * resuming.
2488          *
2489          * To address this, we revert to legacy message way(driver masters the
2490          * timing for BACO in/exit) on sound driver missing.
2491          */
2492         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2493                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2494         else
2495                 return smu_v11_0_baco_enter(smu);
2496 }
2497
2498 static int navi10_baco_exit(struct smu_context *smu)
2499 {
2500         struct amdgpu_device *adev = smu->adev;
2501
2502         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2503                 /* Wait for PMFW handling for the Dstate change */
2504                 msleep(10);
2505                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2506         } else {
2507                 return smu_v11_0_baco_exit(smu);
2508         }
2509 }
2510
2511 static int navi10_set_default_od_settings(struct smu_context *smu)
2512 {
2513         OverDriveTable_t *od_table =
2514                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2515         OverDriveTable_t *boot_od_table =
2516                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2517         OverDriveTable_t *user_od_table =
2518                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2519         int ret = 0;
2520
2521         /*
2522          * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2523          *   - either they already have the default OD settings got during cold bootup
2524          *   - or they have some user customized OD settings which cannot be overwritten
2525          */
2526         if (smu->adev->in_suspend)
2527                 return 0;
2528
2529         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
2530         if (ret) {
2531                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2532                 return ret;
2533         }
2534
2535         if (!boot_od_table->GfxclkVolt1) {
2536                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2537                                                                 &boot_od_table->GfxclkVolt1,
2538                                                                 boot_od_table->GfxclkFreq1);
2539                 if (ret)
2540                         return ret;
2541         }
2542
2543         if (!boot_od_table->GfxclkVolt2) {
2544                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2545                                                                 &boot_od_table->GfxclkVolt2,
2546                                                                 boot_od_table->GfxclkFreq2);
2547                 if (ret)
2548                         return ret;
2549         }
2550
2551         if (!boot_od_table->GfxclkVolt3) {
2552                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2553                                                                 &boot_od_table->GfxclkVolt3,
2554                                                                 boot_od_table->GfxclkFreq3);
2555                 if (ret)
2556                         return ret;
2557         }
2558
2559         navi10_dump_od_table(smu, boot_od_table);
2560
2561         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2562         memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2563
2564         return 0;
2565 }
2566
2567 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size)
2568 {
2569         int i;
2570         int ret = 0;
2571         struct smu_table_context *table_context = &smu->smu_table;
2572         OverDriveTable_t *od_table;
2573         struct smu_11_0_overdrive_table *od_settings;
2574         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2575         uint16_t *freq_ptr, *voltage_ptr;
2576         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2577
2578         if (!smu->od_enabled) {
2579                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2580                 return -EINVAL;
2581         }
2582
2583         if (!smu->od_settings) {
2584                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2585                 return -ENOENT;
2586         }
2587
2588         od_settings = smu->od_settings;
2589
2590         switch (type) {
2591         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2592                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2593                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2594                         return -ENOTSUPP;
2595                 }
2596                 if (!table_context->overdrive_table) {
2597                         dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2598                         return -EINVAL;
2599                 }
2600                 for (i = 0; i < size; i += 2) {
2601                         if (i + 2 > size) {
2602                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2603                                 return -EINVAL;
2604                         }
2605                         switch (input[i]) {
2606                         case 0:
2607                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2608                                 freq_ptr = &od_table->GfxclkFmin;
2609                                 if (input[i + 1] > od_table->GfxclkFmax) {
2610                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2611                                                 input[i + 1],
2612                                                 od_table->GfxclkFmin);
2613                                         return -EINVAL;
2614                                 }
2615                                 break;
2616                         case 1:
2617                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2618                                 freq_ptr = &od_table->GfxclkFmax;
2619                                 if (input[i + 1] < od_table->GfxclkFmin) {
2620                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2621                                                 input[i + 1],
2622                                                 od_table->GfxclkFmax);
2623                                         return -EINVAL;
2624                                 }
2625                                 break;
2626                         default:
2627                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2628                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2629                                 return -EINVAL;
2630                         }
2631                         ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2632                         if (ret)
2633                                 return ret;
2634                         *freq_ptr = input[i + 1];
2635                 }
2636                 break;
2637         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2638                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2639                         dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2640                         return -ENOTSUPP;
2641                 }
2642                 if (size < 2) {
2643                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2644                         return -EINVAL;
2645                 }
2646                 if (input[0] != 1) {
2647                         dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2648                         dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2649                         return -EINVAL;
2650                 }
2651                 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2652                 if (ret)
2653                         return ret;
2654                 od_table->UclkFmax = input[1];
2655                 break;
2656         case PP_OD_RESTORE_DEFAULT_TABLE:
2657                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2658                         dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2659                         return -EINVAL;
2660                 }
2661                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2662                 break;
2663         case PP_OD_COMMIT_DPM_TABLE:
2664                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2665                         navi10_dump_od_table(smu, od_table);
2666                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2667                         if (ret) {
2668                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2669                                 return ret;
2670                         }
2671                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2672                         smu->user_dpm_profile.user_od = true;
2673
2674                         if (!memcmp(table_context->user_overdrive_table,
2675                                     table_context->boot_overdrive_table,
2676                                     sizeof(OverDriveTable_t)))
2677                                 smu->user_dpm_profile.user_od = false;
2678                 }
2679                 break;
2680         case PP_OD_EDIT_VDDC_CURVE:
2681                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2682                         dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2683                         return -ENOTSUPP;
2684                 }
2685                 if (size < 3) {
2686                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2687                         return -EINVAL;
2688                 }
2689                 if (!od_table) {
2690                         dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2691                         return -EINVAL;
2692                 }
2693
2694                 switch (input[0]) {
2695                 case 0:
2696                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2697                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2698                         freq_ptr = &od_table->GfxclkFreq1;
2699                         voltage_ptr = &od_table->GfxclkVolt1;
2700                         break;
2701                 case 1:
2702                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2703                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2704                         freq_ptr = &od_table->GfxclkFreq2;
2705                         voltage_ptr = &od_table->GfxclkVolt2;
2706                         break;
2707                 case 2:
2708                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2709                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2710                         freq_ptr = &od_table->GfxclkFreq3;
2711                         voltage_ptr = &od_table->GfxclkVolt3;
2712                         break;
2713                 default:
2714                         dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2715                         dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2716                         return -EINVAL;
2717                 }
2718                 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2719                 if (ret)
2720                         return ret;
2721                 // Allow setting zero to disable the OverDrive VDDC curve
2722                 if (input[2] != 0) {
2723                         ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2724                         if (ret)
2725                                 return ret;
2726                         *freq_ptr = input[1];
2727                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2728                         dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2729                 } else {
2730                         // If setting 0, disable all voltage curve settings
2731                         od_table->GfxclkVolt1 = 0;
2732                         od_table->GfxclkVolt2 = 0;
2733                         od_table->GfxclkVolt3 = 0;
2734                 }
2735                 navi10_dump_od_table(smu, od_table);
2736                 break;
2737         default:
2738                 return -ENOSYS;
2739         }
2740         return ret;
2741 }
2742
2743 static int navi10_run_btc(struct smu_context *smu)
2744 {
2745         int ret = 0;
2746
2747         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2748         if (ret)
2749                 dev_err(smu->adev->dev, "RunBtc failed!\n");
2750
2751         return ret;
2752 }
2753
2754 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2755 {
2756         struct amdgpu_device *adev = smu->adev;
2757
2758         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2759                 return false;
2760
2761         if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0) ||
2762             amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5))
2763                 return true;
2764
2765         return false;
2766 }
2767
2768 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2769 {
2770         uint32_t uclk_count, uclk_min, uclk_max;
2771         int ret = 0;
2772
2773         /* This workaround can be applied only with uclk dpm enabled */
2774         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2775                 return 0;
2776
2777         ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2778         if (ret)
2779                 return ret;
2780
2781         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2782         if (ret)
2783                 return ret;
2784
2785         /*
2786          * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2787          * This workaround is needed only when the max uclk frequency
2788          * not greater than that.
2789          */
2790         if (uclk_max > 0x2EE)
2791                 return 0;
2792
2793         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2794         if (ret)
2795                 return ret;
2796
2797         /* Force UCLK out of the highest DPM */
2798         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2799         if (ret)
2800                 return ret;
2801
2802         /* Revert the UCLK Hardmax */
2803         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2804         if (ret)
2805                 return ret;
2806
2807         /*
2808          * In this case, SMU already disabled dummy pstate during enablement
2809          * of UCLK DPM, we have to re-enabled it.
2810          */
2811         return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2812 }
2813
2814 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2815 {
2816         struct smu_table_context *smu_table = &smu->smu_table;
2817         struct smu_table *dummy_read_table =
2818                                 &smu_table->dummy_read_1_table;
2819         char *dummy_table = dummy_read_table->cpu_addr;
2820         int ret = 0;
2821         uint32_t i;
2822
2823         for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2824                 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2825                 dummy_table += 0x1000;
2826                 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2827                 dummy_table += 0x1000;
2828         }
2829
2830         amdgpu_asic_flush_hdp(smu->adev, NULL);
2831
2832         ret = smu_cmn_send_smc_msg_with_param(smu,
2833                                               SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2834                                               upper_32_bits(dummy_read_table->mc_address),
2835                                               NULL);
2836         if (ret)
2837                 return ret;
2838
2839         return smu_cmn_send_smc_msg_with_param(smu,
2840                                                SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2841                                                lower_32_bits(dummy_read_table->mc_address),
2842                                                NULL);
2843 }
2844
2845 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2846 {
2847         struct amdgpu_device *adev = smu->adev;
2848         uint8_t umc_fw_greater_than_v136 = false;
2849         uint8_t umc_fw_disable_cdr = false;
2850         uint32_t pmfw_version;
2851         uint32_t param;
2852         int ret = 0;
2853
2854         if (!navi10_need_umc_cdr_workaround(smu))
2855                 return 0;
2856
2857         ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
2858         if (ret) {
2859                 dev_err(adev->dev, "Failed to get smu version!\n");
2860                 return ret;
2861         }
2862
2863         /*
2864          * The messages below are only supported by Navi10 42.53.0 and later
2865          * PMFWs and Navi14 53.29.0 and later PMFWs.
2866          * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2867          * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2868          * - PPSMC_MSG_GetUMCFWWA
2869          */
2870         if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
2871              (pmfw_version >= 0x2a3500)) ||
2872             ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) &&
2873              (pmfw_version >= 0x351D00))) {
2874                 ret = smu_cmn_send_smc_msg_with_param(smu,
2875                                                       SMU_MSG_GET_UMC_FW_WA,
2876                                                       0,
2877                                                       &param);
2878                 if (ret)
2879                         return ret;
2880
2881                 /* First bit indicates if the UMC f/w is above v137 */
2882                 umc_fw_greater_than_v136 = param & 0x1;
2883
2884                 /* Second bit indicates if hybrid-cdr is disabled */
2885                 umc_fw_disable_cdr = param & 0x2;
2886
2887                 /* w/a only allowed if UMC f/w is <= 136 */
2888                 if (umc_fw_greater_than_v136)
2889                         return 0;
2890
2891                 if (umc_fw_disable_cdr) {
2892                         if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2893                             IP_VERSION(11, 0, 0))
2894                                 return navi10_umc_hybrid_cdr_workaround(smu);
2895                 } else {
2896                         return navi10_set_dummy_pstates_table_location(smu);
2897                 }
2898         } else {
2899                 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2900                     IP_VERSION(11, 0, 0))
2901                         return navi10_umc_hybrid_cdr_workaround(smu);
2902         }
2903
2904         return 0;
2905 }
2906
2907 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2908                                              void **table)
2909 {
2910         struct smu_table_context *smu_table = &smu->smu_table;
2911         struct gpu_metrics_v1_3 *gpu_metrics =
2912                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2913         SmuMetrics_legacy_t metrics;
2914         int ret = 0;
2915
2916         ret = smu_cmn_get_metrics_table(smu,
2917                                         NULL,
2918                                         true);
2919         if (ret)
2920                 return ret;
2921
2922         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2923
2924         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2925
2926         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2927         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2928         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2929         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2930         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2931         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2932
2933         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2934         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2935
2936         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2937
2938         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2939         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2940         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2941
2942         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2943         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2944         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2945         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2946         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2947
2948         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2949         gpu_metrics->indep_throttle_status =
2950                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2951                                                            navi1x_throttler_map);
2952
2953         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2954
2955         gpu_metrics->pcie_link_width =
2956                         smu_v11_0_get_current_pcie_link_width(smu);
2957         gpu_metrics->pcie_link_speed =
2958                         smu_v11_0_get_current_pcie_link_speed(smu);
2959
2960         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2961
2962         if (metrics.CurrGfxVoltageOffset)
2963                 gpu_metrics->voltage_gfx =
2964                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2965         if (metrics.CurrMemVidOffset)
2966                 gpu_metrics->voltage_mem =
2967                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2968         if (metrics.CurrSocVoltageOffset)
2969                 gpu_metrics->voltage_soc =
2970                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2971
2972         *table = (void *)gpu_metrics;
2973
2974         return sizeof(struct gpu_metrics_v1_3);
2975 }
2976
2977 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2978                            struct i2c_msg *msg, int num_msgs)
2979 {
2980         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2981         struct amdgpu_device *adev = smu_i2c->adev;
2982         struct smu_context *smu = adev->powerplay.pp_handle;
2983         struct smu_table_context *smu_table = &smu->smu_table;
2984         struct smu_table *table = &smu_table->driver_table;
2985         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2986         int i, j, r, c;
2987         u16 dir;
2988
2989         if (!adev->pm.dpm_enabled)
2990                 return -EBUSY;
2991
2992         req = kzalloc(sizeof(*req), GFP_KERNEL);
2993         if (!req)
2994                 return -ENOMEM;
2995
2996         req->I2CcontrollerPort = smu_i2c->port;
2997         req->I2CSpeed = I2C_SPEED_FAST_400K;
2998         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2999         dir = msg[0].flags & I2C_M_RD;
3000
3001         for (c = i = 0; i < num_msgs; i++) {
3002                 for (j = 0; j < msg[i].len; j++, c++) {
3003                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3004
3005                         if (!(msg[i].flags & I2C_M_RD)) {
3006                                 /* write */
3007                                 cmd->Cmd = I2C_CMD_WRITE;
3008                                 cmd->RegisterAddr = msg[i].buf[j];
3009                         }
3010
3011                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3012                                 /* The direction changes.
3013                                  */
3014                                 dir = msg[i].flags & I2C_M_RD;
3015                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3016                         }
3017
3018                         req->NumCmds++;
3019
3020                         /*
3021                          * Insert STOP if we are at the last byte of either last
3022                          * message for the transaction or the client explicitly
3023                          * requires a STOP at this particular message.
3024                          */
3025                         if ((j == msg[i].len - 1) &&
3026                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3027                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3028                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3029                         }
3030                 }
3031         }
3032         mutex_lock(&adev->pm.mutex);
3033         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3034         if (r)
3035                 goto fail;
3036
3037         for (c = i = 0; i < num_msgs; i++) {
3038                 if (!(msg[i].flags & I2C_M_RD)) {
3039                         c += msg[i].len;
3040                         continue;
3041                 }
3042                 for (j = 0; j < msg[i].len; j++, c++) {
3043                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3044
3045                         msg[i].buf[j] = cmd->Data;
3046                 }
3047         }
3048         r = num_msgs;
3049 fail:
3050         mutex_unlock(&adev->pm.mutex);
3051         kfree(req);
3052         return r;
3053 }
3054
3055 static u32 navi10_i2c_func(struct i2c_adapter *adap)
3056 {
3057         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3058 }
3059
3060
3061 static const struct i2c_algorithm navi10_i2c_algo = {
3062         .master_xfer = navi10_i2c_xfer,
3063         .functionality = navi10_i2c_func,
3064 };
3065
3066 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
3067         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3068         .max_read_len  = MAX_SW_I2C_COMMANDS,
3069         .max_write_len = MAX_SW_I2C_COMMANDS,
3070         .max_comb_1st_msg_len = 2,
3071         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3072 };
3073
3074 static int navi10_i2c_control_init(struct smu_context *smu)
3075 {
3076         struct amdgpu_device *adev = smu->adev;
3077         int res, i;
3078
3079         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3080                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3081                 struct i2c_adapter *control = &smu_i2c->adapter;
3082
3083                 smu_i2c->adev = adev;
3084                 smu_i2c->port = i;
3085                 mutex_init(&smu_i2c->mutex);
3086                 control->owner = THIS_MODULE;
3087                 control->class = I2C_CLASS_HWMON;
3088                 control->dev.parent = &adev->pdev->dev;
3089                 control->algo = &navi10_i2c_algo;
3090                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3091                 control->quirks = &navi10_i2c_control_quirks;
3092                 i2c_set_adapdata(control, smu_i2c);
3093
3094                 res = i2c_add_adapter(control);
3095                 if (res) {
3096                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3097                         goto Out_err;
3098                 }
3099         }
3100
3101         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3102         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3103
3104         return 0;
3105 Out_err:
3106         for ( ; i >= 0; i--) {
3107                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3108                 struct i2c_adapter *control = &smu_i2c->adapter;
3109
3110                 i2c_del_adapter(control);
3111         }
3112         return res;
3113 }
3114
3115 static void navi10_i2c_control_fini(struct smu_context *smu)
3116 {
3117         struct amdgpu_device *adev = smu->adev;
3118         int i;
3119
3120         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3121                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3122                 struct i2c_adapter *control = &smu_i2c->adapter;
3123
3124                 i2c_del_adapter(control);
3125         }
3126         adev->pm.ras_eeprom_i2c_bus = NULL;
3127         adev->pm.fru_eeprom_i2c_bus = NULL;
3128 }
3129
3130 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
3131                                       void **table)
3132 {
3133         struct smu_table_context *smu_table = &smu->smu_table;
3134         struct gpu_metrics_v1_3 *gpu_metrics =
3135                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3136         SmuMetrics_t metrics;
3137         int ret = 0;
3138
3139         ret = smu_cmn_get_metrics_table(smu,
3140                                         NULL,
3141                                         true);
3142         if (ret)
3143                 return ret;
3144
3145         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
3146
3147         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3148
3149         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3150         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3151         gpu_metrics->temperature_mem = metrics.TemperatureMem;
3152         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3153         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3154         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3155
3156         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3157         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3158
3159         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3160
3161         if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3162                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3163         else
3164                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3165
3166         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3167         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3168
3169         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3170         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3171         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3172         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3173         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3174
3175         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3176         gpu_metrics->indep_throttle_status =
3177                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3178                                                            navi1x_throttler_map);
3179
3180         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3181
3182         gpu_metrics->pcie_link_width = metrics.PcieWidth;
3183         gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3184
3185         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3186
3187         if (metrics.CurrGfxVoltageOffset)
3188                 gpu_metrics->voltage_gfx =
3189                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3190         if (metrics.CurrMemVidOffset)
3191                 gpu_metrics->voltage_mem =
3192                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3193         if (metrics.CurrSocVoltageOffset)
3194                 gpu_metrics->voltage_soc =
3195                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3196
3197         *table = (void *)gpu_metrics;
3198
3199         return sizeof(struct gpu_metrics_v1_3);
3200 }
3201
3202 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
3203                                              void **table)
3204 {
3205         struct smu_table_context *smu_table = &smu->smu_table;
3206         struct gpu_metrics_v1_3 *gpu_metrics =
3207                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3208         SmuMetrics_NV12_legacy_t metrics;
3209         int ret = 0;
3210
3211         ret = smu_cmn_get_metrics_table(smu,
3212                                         NULL,
3213                                         true);
3214         if (ret)
3215                 return ret;
3216
3217         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
3218
3219         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3220
3221         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3222         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3223         gpu_metrics->temperature_mem = metrics.TemperatureMem;
3224         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3225         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3226         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3227
3228         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3229         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3230
3231         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3232
3233         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
3234         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3235         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
3236
3237         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3238         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3239         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3240         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3241
3242         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3243         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3244         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3245         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3246         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3247
3248         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3249         gpu_metrics->indep_throttle_status =
3250                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3251                                                            navi1x_throttler_map);
3252
3253         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3254
3255         gpu_metrics->pcie_link_width =
3256                         smu_v11_0_get_current_pcie_link_width(smu);
3257         gpu_metrics->pcie_link_speed =
3258                         smu_v11_0_get_current_pcie_link_speed(smu);
3259
3260         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3261
3262         if (metrics.CurrGfxVoltageOffset)
3263                 gpu_metrics->voltage_gfx =
3264                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3265         if (metrics.CurrMemVidOffset)
3266                 gpu_metrics->voltage_mem =
3267                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3268         if (metrics.CurrSocVoltageOffset)
3269                 gpu_metrics->voltage_soc =
3270                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3271
3272         *table = (void *)gpu_metrics;
3273
3274         return sizeof(struct gpu_metrics_v1_3);
3275 }
3276
3277 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
3278                                       void **table)
3279 {
3280         struct smu_table_context *smu_table = &smu->smu_table;
3281         struct gpu_metrics_v1_3 *gpu_metrics =
3282                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3283         SmuMetrics_NV12_t metrics;
3284         int ret = 0;
3285
3286         ret = smu_cmn_get_metrics_table(smu,
3287                                         NULL,
3288                                         true);
3289         if (ret)
3290                 return ret;
3291
3292         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
3293
3294         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3295
3296         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3297         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3298         gpu_metrics->temperature_mem = metrics.TemperatureMem;
3299         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3300         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3301         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3302
3303         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3304         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3305
3306         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3307
3308         if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3309                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3310         else
3311                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3312
3313         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3314         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3315
3316         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3317         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3318         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3319         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3320
3321         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3322         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3323         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3324         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3325         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3326
3327         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3328         gpu_metrics->indep_throttle_status =
3329                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3330                                                            navi1x_throttler_map);
3331
3332         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3333
3334         gpu_metrics->pcie_link_width = metrics.PcieWidth;
3335         gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3336
3337         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3338
3339         if (metrics.CurrGfxVoltageOffset)
3340                 gpu_metrics->voltage_gfx =
3341                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3342         if (metrics.CurrMemVidOffset)
3343                 gpu_metrics->voltage_mem =
3344                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3345         if (metrics.CurrSocVoltageOffset)
3346                 gpu_metrics->voltage_soc =
3347                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3348
3349         *table = (void *)gpu_metrics;
3350
3351         return sizeof(struct gpu_metrics_v1_3);
3352 }
3353
3354 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
3355                                       void **table)
3356 {
3357         struct amdgpu_device *adev = smu->adev;
3358         uint32_t smu_version;
3359         int ret = 0;
3360
3361         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3362         if (ret) {
3363                 dev_err(adev->dev, "Failed to get smu version!\n");
3364                 return ret;
3365         }
3366
3367         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
3368         case IP_VERSION(11, 0, 9):
3369                 if (smu_version > 0x00341C00)
3370                         ret = navi12_get_gpu_metrics(smu, table);
3371                 else
3372                         ret = navi12_get_legacy_gpu_metrics(smu, table);
3373                 break;
3374         case IP_VERSION(11, 0, 0):
3375         case IP_VERSION(11, 0, 5):
3376         default:
3377                 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
3378                       IP_VERSION(11, 0, 5)) &&
3379                      smu_version > 0x00351F00) ||
3380                     ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
3381                       IP_VERSION(11, 0, 0)) &&
3382                      smu_version > 0x002A3B00))
3383                         ret = navi10_get_gpu_metrics(smu, table);
3384                 else
3385                         ret = navi10_get_legacy_gpu_metrics(smu, table);
3386                 break;
3387         }
3388
3389         return ret;
3390 }
3391
3392 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3393 {
3394         struct smu_table_context *table_context = &smu->smu_table;
3395         PPTable_t *smc_pptable = table_context->driver_pptable;
3396         struct amdgpu_device *adev = smu->adev;
3397         uint32_t param = 0;
3398
3399         /* Navi12 does not support this */
3400         if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9))
3401                 return 0;
3402
3403         /*
3404          * Skip the MGpuFanBoost setting for those ASICs
3405          * which do not support it
3406          */
3407         if (!smc_pptable->MGpuFanBoostLimitRpm)
3408                 return 0;
3409
3410         /* Workaround for WS SKU */
3411         if (adev->pdev->device == 0x7312 &&
3412             adev->pdev->revision == 0)
3413                 param = 0xD188;
3414
3415         return smu_cmn_send_smc_msg_with_param(smu,
3416                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
3417                                                param,
3418                                                NULL);
3419 }
3420
3421 static int navi10_post_smu_init(struct smu_context *smu)
3422 {
3423         struct amdgpu_device *adev = smu->adev;
3424         int ret = 0;
3425
3426         if (amdgpu_sriov_vf(adev))
3427                 return 0;
3428
3429         ret = navi10_run_umc_cdr_workaround(smu);
3430         if (ret)
3431                 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3432
3433         return ret;
3434 }
3435
3436 static int navi10_get_default_config_table_settings(struct smu_context *smu,
3437                                                     struct config_table_setting *table)
3438 {
3439         if (!table)
3440                 return -EINVAL;
3441
3442         table->gfxclk_average_tau = 10;
3443         table->socclk_average_tau = 10;
3444         table->uclk_average_tau = 10;
3445         table->gfx_activity_average_tau = 10;
3446         table->mem_activity_average_tau = 10;
3447         table->socket_power_average_tau = 10;
3448
3449         return 0;
3450 }
3451
3452 static int navi10_set_config_table(struct smu_context *smu,
3453                                    struct config_table_setting *table)
3454 {
3455         DriverSmuConfig_t driver_smu_config_table;
3456
3457         if (!table)
3458                 return -EINVAL;
3459
3460         memset(&driver_smu_config_table,
3461                0,
3462                sizeof(driver_smu_config_table));
3463
3464         driver_smu_config_table.GfxclkAverageLpfTau =
3465                                 table->gfxclk_average_tau;
3466         driver_smu_config_table.SocclkAverageLpfTau =
3467                                 table->socclk_average_tau;
3468         driver_smu_config_table.UclkAverageLpfTau =
3469                                 table->uclk_average_tau;
3470         driver_smu_config_table.GfxActivityLpfTau =
3471                                 table->gfx_activity_average_tau;
3472         driver_smu_config_table.UclkActivityLpfTau =
3473                                 table->mem_activity_average_tau;
3474         driver_smu_config_table.SocketPowerLpfTau =
3475                                 table->socket_power_average_tau;
3476
3477         return smu_cmn_update_table(smu,
3478                                     SMU_TABLE_DRIVER_SMU_CONFIG,
3479                                     0,
3480                                     (void *)&driver_smu_config_table,
3481                                     true);
3482 }
3483
3484 static const struct pptable_funcs navi10_ppt_funcs = {
3485         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3486         .set_default_dpm_table = navi10_set_default_dpm_table,
3487         .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3488         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3489         .i2c_init = navi10_i2c_control_init,
3490         .i2c_fini = navi10_i2c_control_fini,
3491         .print_clk_levels = navi10_print_clk_levels,
3492         .emit_clk_levels = navi10_emit_clk_levels,
3493         .force_clk_levels = navi10_force_clk_levels,
3494         .populate_umd_state_clk = navi10_populate_umd_state_clk,
3495         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3496         .pre_display_config_changed = navi10_pre_display_config_changed,
3497         .display_config_changed = navi10_display_config_changed,
3498         .notify_smc_display_config = navi10_notify_smc_display_config,
3499         .is_dpm_running = navi10_is_dpm_running,
3500         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3501         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
3502         .get_power_profile_mode = navi10_get_power_profile_mode,
3503         .set_power_profile_mode = navi10_set_power_profile_mode,
3504         .set_watermarks_table = navi10_set_watermarks_table,
3505         .read_sensor = navi10_read_sensor,
3506         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3507         .set_performance_level = smu_v11_0_set_performance_level,
3508         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3509         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3510         .get_power_limit = navi10_get_power_limit,
3511         .update_pcie_parameters = navi10_update_pcie_parameters,
3512         .init_microcode = smu_v11_0_init_microcode,
3513         .load_microcode = smu_v11_0_load_microcode,
3514         .fini_microcode = smu_v11_0_fini_microcode,
3515         .init_smc_tables = navi10_init_smc_tables,
3516         .fini_smc_tables = smu_v11_0_fini_smc_tables,
3517         .init_power = smu_v11_0_init_power,
3518         .fini_power = smu_v11_0_fini_power,
3519         .check_fw_status = smu_v11_0_check_fw_status,
3520         .setup_pptable = navi10_setup_pptable,
3521         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3522         .check_fw_version = smu_v11_0_check_fw_version,
3523         .write_pptable = smu_cmn_write_pptable,
3524         .set_driver_table_location = smu_v11_0_set_driver_table_location,
3525         .set_tool_table_location = smu_v11_0_set_tool_table_location,
3526         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3527         .system_features_control = smu_v11_0_system_features_control,
3528         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3529         .send_smc_msg = smu_cmn_send_smc_msg,
3530         .init_display_count = smu_v11_0_init_display_count,
3531         .set_allowed_mask = smu_v11_0_set_allowed_mask,
3532         .get_enabled_mask = smu_cmn_get_enabled_mask,
3533         .feature_is_enabled = smu_cmn_feature_is_enabled,
3534         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3535         .notify_display_change = smu_v11_0_notify_display_change,
3536         .set_power_limit = smu_v11_0_set_power_limit,
3537         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3538         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3539         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3540         .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3541         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3542         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3543         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3544         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3545         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3546         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3547         .gfx_off_control = smu_v11_0_gfx_off_control,
3548         .register_irq_handler = smu_v11_0_register_irq_handler,
3549         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3550         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3551         .baco_is_support = smu_v11_0_baco_is_support,
3552         .baco_get_state = smu_v11_0_baco_get_state,
3553         .baco_set_state = smu_v11_0_baco_set_state,
3554         .baco_enter = navi10_baco_enter,
3555         .baco_exit = navi10_baco_exit,
3556         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3557         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3558         .set_default_od_settings = navi10_set_default_od_settings,
3559         .od_edit_dpm_table = navi10_od_edit_dpm_table,
3560         .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3561         .run_btc = navi10_run_btc,
3562         .set_power_source = smu_v11_0_set_power_source,
3563         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3564         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3565         .get_gpu_metrics = navi1x_get_gpu_metrics,
3566         .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3567         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3568         .deep_sleep_control = smu_v11_0_deep_sleep_control,
3569         .get_fan_parameters = navi10_get_fan_parameters,
3570         .post_init = navi10_post_smu_init,
3571         .interrupt_work = smu_v11_0_interrupt_work,
3572         .set_mp1_state = smu_cmn_set_mp1_state,
3573         .get_default_config_table_settings = navi10_get_default_config_table_settings,
3574         .set_config_table = navi10_set_config_table,
3575 };
3576
3577 void navi10_set_ppt_funcs(struct smu_context *smu)
3578 {
3579         smu->ppt_funcs = &navi10_ppt_funcs;
3580         smu->message_map = navi10_message_map;
3581         smu->clock_map = navi10_clk_map;
3582         smu->feature_map = navi10_feature_mask_map;
3583         smu->table_map = navi10_table_map;
3584         smu->pwr_src_map = navi10_pwr_src_map;
3585         smu->workload_map = navi10_workload_map;
3586         smu_v11_0_set_smu_mailbox_registers(smu);
3587 }