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24 #ifndef __SMU_V14_0_0_PPSMC_H__
25 #define __SMU_V14_0_0_PPSMC_H__
27 /*! @mainpage PMFW-PPS (PPLib) Message Interface
28 This documentation contains the subsections:\n\n
34 /** @def PPS_PMFW_IF_VER
35 * PPS (PPLib) to PMFW IF version 1.0
37 #define PPS_PMFW_IF_VER "1.0" ///< Major.Minor
39 /** @defgroup ResponseCodes PMFW Response Codes
42 // SMU Response Codes:
43 #define PPSMC_Result_OK 0x1 ///< Message Response OK
44 #define PPSMC_Result_Failed 0xFF ///< Message Response Failed
45 #define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
46 #define PPSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
47 #define PPSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
50 /** @defgroup definitions Message definitions
53 // Message Definitions:
54 #define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
55 #define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
56 #define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version
57 #define PPSMC_MSG_PowerDownVcn1 0x04 ///< Power down VCN1
58 #define PPSMC_MSG_PowerUpVcn1 0x05 ///< Power up VCN1; VCN1 is power gated by default
59 #define PPSMC_MSG_PowerDownVcn0 0x06 ///< Power down VCN0
60 #define PPSMC_MSG_PowerUpVcn0 0x07 ///< Power up VCN0; VCN0 is power gated by default
61 #define PPSMC_MSG_SetHardMinVcn0 0x08 ///< For wireless display
62 #define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
63 #define PPSMC_MSG_SetHardMinVcn1 0x0A ///< For wireless display
64 #define PPSMC_MSG_SetSoftMinVcn1 0x0B ///< Set soft min for VCN1 clocks (VCLK1 and DCLK1)
65 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
66 #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
67 #define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
68 #define PPSMC_MSG_TransferTableSmu2Dram 0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM
69 #define PPSMC_MSG_TransferTableDram2Smu 0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM
70 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
71 #define PPSMC_MSG_GetEnabledSmuFeatures 0x12 ///< Get enabled features in PMFW
72 #define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK
73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
74 #define PPSMC_MSG_SetSoftMinVcn0 0x15 ///< Set soft min for VCN0 clocks (VCLK0 and DCLK0)
75 #define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
76 #define PPSMC_MSG_spare_0x17 0x17 ///< Get GFX clock frequency
77 #define PPSMC_MSG_spare_0x18 0x18 ///< Get FCLK frequency
78 #define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of allowing GFXOFF entry
79 #define PPSMC_MSG_DisallowGfxOff 0x1A ///< Inform PMFW of disallowing GFXOFF entry
80 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
81 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
82 #define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK
83 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
84 #define PPSMC_MSG_SetSoftMaxVcn0 0x1F ///< Set soft max for VCN0 clocks (VCLK0 and DCLK0)
85 #define PPSMC_MSG_spare_0x20 0x20 ///< Set power limit percentage
86 #define PPSMC_MSG_PowerDownJpeg0 0x21 ///< Power down Jpeg of VCN0
87 #define PPSMC_MSG_PowerUpJpeg0 0x22 ///< Power up Jpeg of VCN0; VCN0 is power gated by default
88 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
89 #define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK
90 #define PPSMC_MSG_AllowZstates 0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
91 #define PPSMC_MSG_PowerDownJpeg1 0x26 ///< Power down Jpeg of VCN1
92 #define PPSMC_MSG_PowerUpJpeg1 0x27 ///< Power up Jpeg of VCN1; VCN1 is power gated by default
93 #define PPSMC_MSG_SetSoftMaxVcn1 0x28 ///< Set soft max for VCN1 clocks (VCLK1 and DCLK1)
94 #define PPSMC_MSG_PowerDownIspByTile 0x29 ///< ISP is power gated by default
95 #define PPSMC_MSG_PowerUpIspByTile 0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM
96 #define PPSMC_MSG_SetHardMinIspiclkByFreq 0x2B ///< Set HardMin by frequency for ISPICLK
97 #define PPSMC_MSG_SetHardMinIspxclkByFreq 0x2C ///< Set HardMin by frequency for ISPXCLK
98 #define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN0.UMSCH (aka VSCH) scheduler
99 #define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN0.UMSCH (aka VSCH) scheduler
100 #define PPSMC_Message_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
101 #define PPSMC_Message_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
102 #define PPSMC_MSG_PowerUpVpe 0x31 ///< Power up VPE
103 #define PPSMC_MSG_PowerDownVpe 0x32 ///< Power down VPE
104 #define PPSMC_MSG_GetVpeDpmTable 0x33 ///< Get VPE DPM table
105 #define PPSMC_MSG_EnableLSdma 0x34 ///< Enable LSDMA
106 #define PPSMC_MSG_DisableLSdma 0x35 ///< Disable LSDMA
107 #define PPSMC_MSG_SetSoftMaxVpe 0x36 ///<
108 #define PPSMC_MSG_SetSoftMinVpe 0x37 ///<
109 #define PPSMC_MSG_AllocMALLCache 0x38 ///< Allocating MALL Cache
110 #define PPSMC_MSG_ReleaseMALLCache 0x39 ///< Releasing MALL Cache
111 #define PPSMC_Message_Count 0x3A ///< Total number of PPSMC messages
115 * @defgroup enums Enum Definitions
119 /** @enum Mode_Reset_e
120 * Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
122 //argument for PPSMC_MSG_GfxDeviceDriverReset
124 MODE1_RESET = 1, ///< Mode reset type 1
125 MODE2_RESET = 2 ///< Mode reset type 2
131 * Zstate types, argument for PPSMC_MSG_AllowZstates
133 //Argument for PPSMC_MSG_AllowZstates
135 DISALLOW_ZSTATES = 0, ///< Disallow Zstates
136 ALLOW_ZSTATES_Z8 = 8, ///< Allows Z8 only
137 ALLOW_ZSTATES_Z9 = 9, ///< Allows Z9 and Z8