2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
25 #include <linux/acpi_amd_wbrf.h>
26 #include <linux/units.h>
29 #include "kgd_pp_interface.h"
30 #include "dm_pp_interface.h"
31 #include "dm_pp_smu.h"
32 #include "smu_types.h"
33 #include "linux/firmware.h"
35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
38 #define SMU_FW_NAME_LEN 0x24
40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1)
42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2)
45 #define SMU_THROTTLER_PPT0_BIT 0
46 #define SMU_THROTTLER_PPT1_BIT 1
47 #define SMU_THROTTLER_PPT2_BIT 2
48 #define SMU_THROTTLER_PPT3_BIT 3
49 #define SMU_THROTTLER_SPL_BIT 4
50 #define SMU_THROTTLER_FPPT_BIT 5
51 #define SMU_THROTTLER_SPPT_BIT 6
52 #define SMU_THROTTLER_SPPT_APU_BIT 7
55 #define SMU_THROTTLER_TDC_GFX_BIT 16
56 #define SMU_THROTTLER_TDC_SOC_BIT 17
57 #define SMU_THROTTLER_TDC_MEM_BIT 18
58 #define SMU_THROTTLER_TDC_VDD_BIT 19
59 #define SMU_THROTTLER_TDC_CVIP_BIT 20
60 #define SMU_THROTTLER_EDC_CPU_BIT 21
61 #define SMU_THROTTLER_EDC_GFX_BIT 22
62 #define SMU_THROTTLER_APCC_BIT 23
65 #define SMU_THROTTLER_TEMP_GPU_BIT 32
66 #define SMU_THROTTLER_TEMP_CORE_BIT 33
67 #define SMU_THROTTLER_TEMP_MEM_BIT 34
68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35
69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
70 #define SMU_THROTTLER_TEMP_SOC_BIT 37
71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38
72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39
73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40
74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41
75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42
76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43
77 #define SMU_THROTTLER_VRHOT0_BIT 44
78 #define SMU_THROTTLER_VRHOT1_BIT 45
79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46
80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47
83 #define SMU_THROTTLER_PPM_BIT 56
84 #define SMU_THROTTLER_FIT_BIT 57
86 struct smu_hw_power_state {
90 struct smu_power_state;
92 enum smu_state_ui_label {
93 SMU_STATE_UI_LABEL_NONE,
94 SMU_STATE_UI_LABEL_BATTERY,
95 SMU_STATE_UI_TABEL_MIDDLE_LOW,
96 SMU_STATE_UI_LABEL_BALLANCED,
97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
98 SMU_STATE_UI_LABEL_PERFORMANCE,
99 SMU_STATE_UI_LABEL_BACO,
102 enum smu_state_classification_flag {
103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
126 struct smu_state_classification_block {
127 enum smu_state_ui_label ui_label;
128 enum smu_state_classification_flag flags;
130 bool temporary_state;
134 struct smu_state_pcie_block {
138 enum smu_refreshrate_source {
139 SMU_REFRESHRATE_SOURCE_EDID,
140 SMU_REFRESHRATE_SOURCE_EXPLICIT
143 struct smu_state_display_block {
144 bool disable_frame_modulation;
145 bool limit_refreshrate;
146 enum smu_refreshrate_source refreshrate_source;
147 int explicit_refreshrate;
148 int edid_refreshrate_index;
149 bool enable_vari_bright;
152 struct smu_state_memory_block {
158 struct smu_state_software_algorithm_block {
159 bool disable_load_balancing;
160 bool enable_sleep_for_timestamps;
163 struct smu_temperature_range {
166 int edge_emergency_max;
168 int hotspot_crit_max;
169 int hotspot_emergency_max;
172 int mem_emergency_max;
173 int software_shutdown_temp;
174 int software_shutdown_temp_offset;
177 struct smu_state_validation_block {
178 bool single_display_only;
180 uint8_t supported_power_levels;
183 struct smu_uvd_clocks {
189 * Structure to hold a SMU Power State.
191 struct smu_power_state {
193 struct list_head ordered_list;
194 struct list_head all_states_list;
196 struct smu_state_classification_block classification;
197 struct smu_state_validation_block validation;
198 struct smu_state_pcie_block pcie;
199 struct smu_state_display_block display;
200 struct smu_state_memory_block memory;
201 struct smu_state_software_algorithm_block software;
202 struct smu_uvd_clocks uvd_clocks;
203 struct smu_hw_power_state hardware;
206 enum smu_power_src_type {
209 SMU_POWER_SOURCE_COUNT,
212 enum smu_ppt_limit_type {
213 SMU_DEFAULT_PPT_LIMIT = 0,
217 enum smu_ppt_limit_level {
218 SMU_PPT_LIMIT_MIN = -1,
219 SMU_PPT_LIMIT_CURRENT,
220 SMU_PPT_LIMIT_DEFAULT,
224 enum smu_memory_pool_size {
225 SMU_MEMORY_POOL_SIZE_ZERO = 0,
226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
232 struct smu_user_dpm_profile {
234 uint32_t power_limit;
235 uint32_t fan_speed_pwm;
236 uint32_t fan_speed_rpm;
240 /* user clock state information */
241 uint32_t clk_mask[SMU_CLK_COUNT];
242 uint32_t clk_dependency;
245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
247 tables[table_id].size = s; \
248 tables[table_id].align = a; \
249 tables[table_id].domain = d; \
258 struct amdgpu_bo *bo;
262 enum smu_perf_level_designation {
264 PERF_LEVEL_POWER_CONTAINMENT,
267 struct smu_performance_level {
269 uint32_t memory_clock;
272 uint32_t non_local_mem_freq;
273 uint32_t non_local_mem_width;
276 struct smu_clock_info {
277 uint32_t min_mem_clk;
278 uint32_t max_mem_clk;
279 uint32_t min_eng_clk;
280 uint32_t max_eng_clk;
281 uint32_t min_bus_bandwidth;
282 uint32_t max_bus_bandwidth;
285 struct smu_bios_boot_up_values {
299 uint32_t pp_table_id;
300 uint32_t format_revision;
301 uint32_t content_revision;
304 uint32_t firmware_caps;
308 SMU_TABLE_PPTABLE = 0,
309 SMU_TABLE_WATERMARKS,
310 SMU_TABLE_CUSTOM_DPM,
313 SMU_TABLE_AVFS_PSM_DEBUG,
314 SMU_TABLE_AVFS_FUSE_OVERRIDE,
315 SMU_TABLE_PMSTATUSLOG,
316 SMU_TABLE_SMU_METRICS,
317 SMU_TABLE_DRIVER_SMU_CONFIG,
318 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
320 SMU_TABLE_I2C_COMMANDS,
323 SMU_TABLE_COMBO_PPTABLE,
328 struct smu_table_context {
329 void *power_play_table;
330 uint32_t power_play_table_size;
331 void *hardcode_pptable;
332 unsigned long metrics_time;
335 void *watermarks_table;
337 void *max_sustainable_clocks;
338 struct smu_bios_boot_up_values boot_values;
339 void *driver_pptable;
342 void *driver_smu_config_table;
343 struct smu_table tables[SMU_TABLE_COUNT];
345 * The driver table is just a staging buffer for
346 * uploading/downloading content from the SMU.
348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
349 * SMU_MSG_TransferTableDram2Smu instructs SMU
350 * which content driver is interested.
352 struct smu_table driver_table;
353 struct smu_table memory_pool;
354 struct smu_table dummy_read_1_table;
355 uint8_t thermal_controller_type;
357 void *overdrive_table;
358 void *boot_overdrive_table;
359 void *user_overdrive_table;
361 uint32_t gpu_metrics_table_size;
362 void *gpu_metrics_table;
365 struct smu_dpm_context {
366 uint32_t dpm_context_size;
368 void *golden_dpm_context;
369 enum amd_dpm_forced_level dpm_level;
370 enum amd_dpm_forced_level saved_dpm_level;
371 enum amd_dpm_forced_level requested_dpm_level;
372 struct smu_power_state *dpm_request_power_state;
373 struct smu_power_state *dpm_current_power_state;
374 struct mclock_latency_table *mclk_latency_table;
377 struct smu_power_gate {
383 atomic_t umsch_mm_gated;
386 struct smu_power_context {
388 uint32_t power_context_size;
389 struct smu_power_gate power_gate;
392 #define SMU_FEATURE_MAX (64)
394 uint32_t feature_num;
395 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
396 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
400 uint32_t engine_clock;
401 uint32_t memory_clock;
402 uint32_t bus_bandwidth;
403 uint32_t engine_clock_in_sr;
405 uint32_t dcef_clock_in_sr;
408 #define MAX_REGULAR_DPM_NUM 16
409 struct mclk_latency_entries {
413 struct mclock_latency_table {
415 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
418 enum smu_reset_mode {
424 enum smu_baco_state {
425 SMU_BACO_STATE_ENTER = 0,
430 struct smu_baco_context {
432 bool platform_support;
436 struct smu_freq_info {
442 struct pstates_clk_freq {
446 struct smu_freq_info custom;
447 struct smu_freq_info curr;
450 struct smu_umd_pstate_table {
451 struct pstates_clk_freq gfxclk_pstate;
452 struct pstates_clk_freq socclk_pstate;
453 struct pstates_clk_freq uclk_pstate;
454 struct pstates_clk_freq vclk_pstate;
455 struct pstates_clk_freq dclk_pstate;
456 struct pstates_clk_freq fclk_pstate;
459 struct cmn2asic_msg_mapping {
465 struct cmn2asic_mapping {
471 uint32_t stb_buf_size;
476 #define WORKLOAD_POLICY_MAX 7
479 * Configure wbrf event handling pace as there can be only one
480 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms.
482 #define SMU_WBRF_EVENT_HANDLING_PACE 10
485 struct amdgpu_device *adev;
486 struct amdgpu_irq_src irq_source;
488 const struct pptable_funcs *ppt_funcs;
489 const struct cmn2asic_msg_mapping *message_map;
490 const struct cmn2asic_mapping *clock_map;
491 const struct cmn2asic_mapping *feature_map;
492 const struct cmn2asic_mapping *table_map;
493 const struct cmn2asic_mapping *pwr_src_map;
494 const struct cmn2asic_mapping *workload_map;
495 struct mutex message_lock;
498 struct smu_table_context smu_table;
499 struct smu_dpm_context smu_dpm;
500 struct smu_power_context smu_power;
501 struct smu_feature smu_feature;
502 struct amd_pp_display_configuration *display_config;
503 struct smu_baco_context smu_baco;
504 struct smu_temperature_range thermal_range;
507 struct smu_umd_pstate_table pstate_table;
508 uint32_t pstate_sclk;
509 uint32_t pstate_mclk;
512 uint32_t current_power_limit;
513 uint32_t default_power_limit;
514 uint32_t max_power_limit;
515 uint32_t min_power_limit;
518 uint32_t ppt_offset_bytes;
519 uint32_t ppt_size_bytes;
520 uint8_t *ppt_start_addr;
522 bool support_power_containment;
523 bool disable_watermark;
525 #define WATERMARKS_EXIST (1 << 0)
526 #define WATERMARKS_LOADED (1 << 1)
527 uint32_t watermarks_bitmap;
528 uint32_t hard_min_uclk_req_from_dal;
529 bool disable_uclk_switch;
531 uint32_t workload_mask;
532 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
533 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
534 uint32_t power_profile_mode;
535 uint32_t default_power_profile_mode;
539 uint32_t smc_driver_if_version;
540 uint32_t smc_fw_if_version;
541 uint32_t smc_fw_version;
543 bool uploading_custom_pp_table;
544 bool dc_controlled_by_gpio;
546 struct work_struct throttling_logging_work;
547 atomic64_t throttle_int_counter;
548 struct work_struct interrupt_work;
550 unsigned fan_max_rpm;
551 unsigned manual_fan_speed_pwm;
553 uint32_t gfx_default_hard_min_freq;
554 uint32_t gfx_default_soft_max_freq;
555 uint32_t gfx_actual_hard_min_freq;
556 uint32_t gfx_actual_soft_max_freq;
559 uint32_t cpu_default_soft_min_freq;
560 uint32_t cpu_default_soft_max_freq;
561 uint32_t cpu_actual_soft_min_freq;
562 uint32_t cpu_actual_soft_max_freq;
563 uint32_t cpu_core_id_select;
564 uint16_t cpu_core_num;
566 struct smu_user_dpm_profile user_dpm_profile;
568 struct stb_context stb_context;
570 struct firmware pptable_firmware;
580 struct delayed_work swctf_delayed_work;
582 enum pp_xgmi_plpd_mode plpd_mode;
584 /* data structures for wbrf feature support */
586 struct notifier_block wbrf_notifier;
587 struct delayed_work wbrf_delayed_work;
593 * struct pptable_funcs - Callbacks used to interact with the SMU.
595 struct pptable_funcs {
597 * @run_btc: Calibrate voltage/frequency curve to fit the system's
598 * power delivery and voltage margins. Required for adaptive
599 * voltage frequency scaling (AVFS).
601 int (*run_btc)(struct smu_context *smu);
604 * @get_allowed_feature_mask: Get allowed feature mask.
605 * &feature_mask: Array to store feature mask.
606 * &num: Elements in &feature_mask.
608 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
611 * @get_current_power_state: Get the current power state.
613 * Return: Current power state on success, negative errno on failure.
615 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
618 * @set_default_dpm_table: Retrieve the default overdrive settings from
621 int (*set_default_dpm_table)(struct smu_context *smu);
623 int (*set_power_state)(struct smu_context *smu);
626 * @populate_umd_state_clk: Populate the UMD power state table with
629 int (*populate_umd_state_clk)(struct smu_context *smu);
632 * @print_clk_levels: Print DPM clock levels for a clock domain
633 * to buffer. Star current level.
635 * Used for sysfs interfaces.
636 * Return: Number of characters written to the buffer
638 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
641 * @emit_clk_levels: Print DPM clock levels for a clock domain
642 * to buffer using sysfs_emit_at. Star current level.
644 * Used for sysfs interfaces.
646 * &offset: offset within buffer to start printing, which is updated by the
649 * Return: 0 on Success or Negative to indicate an error occurred.
651 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);
654 * @force_clk_levels: Set a range of allowed DPM levels for a clock
656 * &clk_type: Clock domain.
657 * &mask: Range of allowed DPM levels.
659 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
662 * @od_edit_dpm_table: Edit the custom overdrive DPM table.
663 * &type: Type of edit.
664 * &input: Edit parameters.
665 * &size: Size of &input.
667 int (*od_edit_dpm_table)(struct smu_context *smu,
668 enum PP_OD_DPM_TABLE_COMMAND type,
669 long *input, uint32_t size);
672 * @restore_user_od_settings: Restore the user customized
673 * OD settings on S3/S4/Runpm resume.
675 int (*restore_user_od_settings)(struct smu_context *smu);
678 * @get_clock_by_type_with_latency: Get the speed and latency of a clock
681 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
682 enum smu_clk_type clk_type,
684 pp_clock_levels_with_latency
687 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
690 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
691 enum amd_pp_clock_type type,
693 pp_clock_levels_with_voltage
697 * @get_power_profile_mode: Print all power profile modes to
698 * buffer. Star current mode.
700 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
703 * @set_power_profile_mode: Set a power profile mode. Also used to
704 * create/set custom power profile modes.
705 * &input: Power profile mode parameters.
706 * &size: Size of &input.
708 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
711 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
714 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
717 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
720 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
723 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU
725 int (*set_gfx_power_up_by_imu)(struct smu_context *smu);
728 * @read_sensor: Read data from a sensor.
729 * &sensor: Sensor to read data from.
730 * &data: Sensor reading.
731 * &size: Size of &data.
733 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
734 void *data, uint32_t *size);
737 * @get_apu_thermal_limit: get apu core limit from smu
738 * &limit: current limit temperature in millidegrees Celsius
740 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit);
743 * @set_apu_thermal_limit: update all controllers with new limit
744 * &limit: limit temperature to be setted, in millidegrees Celsius
746 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit);
749 * @pre_display_config_changed: Prepare GPU for a display configuration
752 * Disable display tracking and pin memory clock speed to maximum. Used
753 * in display component synchronization.
755 int (*pre_display_config_changed)(struct smu_context *smu);
758 * @display_config_changed: Notify the SMU of the current display
761 * Allows SMU to properly track blanking periods for memory clock
762 * adjustment. Used in display component synchronization.
764 int (*display_config_changed)(struct smu_context *smu);
766 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
769 * @notify_smc_display_config: Applies display requirements to the
770 * current power state.
772 * Optimize deep sleep DCEFclk and mclk for the current display
773 * configuration. Used in display component synchronization.
775 int (*notify_smc_display_config)(struct smu_context *smu);
778 * @is_dpm_running: Check if DPM is running.
780 * Return: True if DPM is running, false otherwise.
782 bool (*is_dpm_running)(struct smu_context *smu);
785 * @get_fan_speed_pwm: Get the current fan speed in PWM.
787 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed);
790 * @get_fan_speed_rpm: Get the current fan speed in rpm.
792 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
795 * @set_watermarks_table: Configure and upload the watermarks tables to
798 int (*set_watermarks_table)(struct smu_context *smu,
799 struct pp_smu_wm_range_sets *clock_ranges);
802 * @get_thermal_temperature_range: Get safe thermal limits in Celcius.
804 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
807 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
808 * &clocks_in_khz: Array of DPM levels.
809 * &num_states: Elements in &clocks_in_khz.
811 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
814 * @set_default_od_settings: Set the overdrive tables to defaults.
816 int (*set_default_od_settings)(struct smu_context *smu);
819 * @set_performance_level: Set a performance level.
821 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
824 * @display_disable_memory_clock_switch: Enable/disable dynamic memory
827 * Disabling this feature forces memory clock speed to maximum.
828 * Enabling sets the minimum memory clock capable of driving the
829 * current display configuration.
831 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
834 * @dump_pptable: Print the power play table to the system log.
836 void (*dump_pptable)(struct smu_context *smu);
839 * @get_power_limit: Get the device's power limits.
841 int (*get_power_limit)(struct smu_context *smu,
842 uint32_t *current_power_limit,
843 uint32_t *default_power_limit,
844 uint32_t *max_power_limit,
845 uint32_t *min_power_limit);
848 * @get_ppt_limit: Get the device's ppt limits.
850 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
851 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
854 * @set_df_cstate: Set data fabric cstate.
856 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
859 * @select_xgmi_plpd_policy: Select xgmi per-link power down policy.
861 int (*select_xgmi_plpd_policy)(struct smu_context *smu,
862 enum pp_xgmi_plpd_mode mode);
865 * @update_pcie_parameters: Update and upload the system's PCIe
866 * capabilites to the SMU.
867 * &pcie_gen_cap: Maximum allowed PCIe generation.
868 * &pcie_width_cap: Maximum allowed PCIe width.
870 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap);
873 * @i2c_init: Initialize i2c.
875 * The i2c bus is used internally by the SMU voltage regulators and
876 * other devices. The i2c's EEPROM also stores bad page tables on boards
879 int (*i2c_init)(struct smu_context *smu);
882 * @i2c_fini: Tear down i2c.
884 void (*i2c_fini)(struct smu_context *smu);
887 * @get_unique_id: Get the GPU's unique id. Used for asset tracking.
889 void (*get_unique_id)(struct smu_context *smu);
892 * @get_dpm_clock_table: Get a copy of the DPM clock table.
894 * Used by display component in bandwidth and watermark calculations.
896 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
899 * @init_microcode: Request the SMU's firmware from the kernel.
901 int (*init_microcode)(struct smu_context *smu);
904 * @load_microcode: Load firmware onto the SMU.
906 int (*load_microcode)(struct smu_context *smu);
909 * @fini_microcode: Release the SMU's firmware.
911 void (*fini_microcode)(struct smu_context *smu);
914 * @init_smc_tables: Initialize the SMU tables.
916 int (*init_smc_tables)(struct smu_context *smu);
919 * @fini_smc_tables: Release the SMU tables.
921 int (*fini_smc_tables)(struct smu_context *smu);
924 * @init_power: Initialize the power gate table context.
926 int (*init_power)(struct smu_context *smu);
929 * @fini_power: Release the power gate table context.
931 int (*fini_power)(struct smu_context *smu);
934 * @check_fw_status: Check the SMU's firmware status.
936 * Return: Zero if check passes, negative errno on failure.
938 int (*check_fw_status)(struct smu_context *smu);
941 * @set_mp1_state: put SMU into a correct state for comming
942 * resume from runpm or gpu reset.
944 int (*set_mp1_state)(struct smu_context *smu,
945 enum pp_mp1_state mp1_state);
948 * @setup_pptable: Initialize the power play table and populate it with
951 int (*setup_pptable)(struct smu_context *smu);
954 * @get_vbios_bootup_values: Get default boot values from the VBIOS.
956 int (*get_vbios_bootup_values)(struct smu_context *smu);
959 * @check_fw_version: Print driver and SMU interface versions to the
962 * Interface mismatch is not a critical failure.
964 int (*check_fw_version)(struct smu_context *smu);
967 * @powergate_sdma: Power up/down system direct memory access.
969 int (*powergate_sdma)(struct smu_context *smu, bool gate);
972 * @set_gfx_cgpg: Enable/disable graphics engine course grain power
975 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
978 * @write_pptable: Write the power play table to the SMU.
980 int (*write_pptable)(struct smu_context *smu);
983 * @set_driver_table_location: Send the location of the driver table to
986 int (*set_driver_table_location)(struct smu_context *smu);
989 * @set_tool_table_location: Send the location of the tool table to the
992 int (*set_tool_table_location)(struct smu_context *smu);
995 * @notify_memory_pool_location: Send the location of the memory pool to
998 int (*notify_memory_pool_location)(struct smu_context *smu);
1001 * @system_features_control: Enable/disable all SMU features.
1003 int (*system_features_control)(struct smu_context *smu, bool en);
1006 * @send_smc_msg_with_param: Send a message with a parameter to the SMU.
1007 * &msg: Type of message.
1008 * ¶m: Message parameter.
1009 * &read_arg: SMU response (optional).
1011 int (*send_smc_msg_with_param)(struct smu_context *smu,
1012 enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
1015 * @send_smc_msg: Send a message to the SMU.
1016 * &msg: Type of message.
1017 * &read_arg: SMU response (optional).
1019 int (*send_smc_msg)(struct smu_context *smu,
1020 enum smu_message_type msg,
1021 uint32_t *read_arg);
1024 * @init_display_count: Notify the SMU of the number of display
1025 * components in current display configuration.
1027 int (*init_display_count)(struct smu_context *smu, uint32_t count);
1030 * @set_allowed_mask: Notify the SMU of the features currently allowed
1033 int (*set_allowed_mask)(struct smu_context *smu);
1036 * @get_enabled_mask: Get a mask of features that are currently enabled
1038 * &feature_mask: Enabled feature mask.
1040 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
1043 * @feature_is_enabled: Test if a feature is enabled.
1045 * Return: One if enabled, zero if disabled.
1047 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
1050 * @disable_all_features_with_exception: Disable all features with
1051 * exception to those in &mask.
1053 int (*disable_all_features_with_exception)(struct smu_context *smu,
1054 enum smu_feature_mask mask);
1057 * @notify_display_change: General interface call to let SMU know about DC change
1059 int (*notify_display_change)(struct smu_context *smu);
1062 * @set_power_limit: Set power limit in watts.
1064 int (*set_power_limit)(struct smu_context *smu,
1065 enum smu_ppt_limit_type limit_type,
1069 * @init_max_sustainable_clocks: Populate max sustainable clock speed
1070 * table with values from the SMU.
1072 int (*init_max_sustainable_clocks)(struct smu_context *smu);
1075 * @enable_thermal_alert: Enable thermal alert interrupts.
1077 int (*enable_thermal_alert)(struct smu_context *smu);
1080 * @disable_thermal_alert: Disable thermal alert interrupts.
1082 int (*disable_thermal_alert)(struct smu_context *smu);
1085 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
1086 * clock speed in MHz.
1088 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
1091 * @display_clock_voltage_request: Set a hard minimum frequency
1092 * for a clock domain.
1094 int (*display_clock_voltage_request)(struct smu_context *smu, struct
1095 pp_display_clock_request
1099 * @get_fan_control_mode: Get the current fan control mode.
1101 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
1104 * @set_fan_control_mode: Set the fan control mode.
1106 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
1109 * @set_fan_speed_pwm: Set a static fan speed in PWM.
1111 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed);
1114 * @set_fan_speed_rpm: Set a static fan speed in rpm.
1116 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
1119 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
1120 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
1122 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
1125 * @gfx_off_control: Enable/disable graphics engine poweroff.
1127 int (*gfx_off_control)(struct smu_context *smu, bool enable);
1131 * @get_gfx_off_status: Get graphics engine poweroff status.
1134 * 0 - GFXOFF(default).
1135 * 1 - Transition out of GFX State.
1136 * 2 - Not in GFXOFF.
1137 * 3 - Transition into GFXOFF.
1139 uint32_t (*get_gfx_off_status)(struct smu_context *smu);
1142 * @gfx_off_entrycount: total GFXOFF entry count at the time of
1143 * query since system power-up
1145 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount);
1148 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging
1150 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start);
1153 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval
1155 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency);
1158 * @register_irq_handler: Register interupt request handlers.
1160 int (*register_irq_handler)(struct smu_context *smu);
1163 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
1165 int (*set_azalia_d3_pme)(struct smu_context *smu);
1168 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
1169 * clock speeds table.
1171 * Provides a way for the display component (DC) to get the max
1172 * sustainable clocks from the SMU.
1174 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
1177 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off).
1179 bool (*baco_is_support)(struct smu_context *smu);
1182 * @baco_get_state: Get the current BACO state.
1184 * Return: Current BACO state.
1186 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
1189 * @baco_set_state: Enter/exit BACO.
1191 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
1194 * @baco_enter: Enter BACO.
1196 int (*baco_enter)(struct smu_context *smu);
1199 * @baco_exit: Exit Baco.
1201 int (*baco_exit)(struct smu_context *smu);
1204 * @mode1_reset_is_support: Check if GPU supports mode1 reset.
1206 bool (*mode1_reset_is_support)(struct smu_context *smu);
1208 * @mode2_reset_is_support: Check if GPU supports mode2 reset.
1210 bool (*mode2_reset_is_support)(struct smu_context *smu);
1213 * @mode1_reset: Perform mode1 reset.
1215 * Complete GPU reset.
1217 int (*mode1_reset)(struct smu_context *smu);
1220 * @mode2_reset: Perform mode2 reset.
1222 * Mode2 reset generally does not reset as many IPs as mode1 reset. The
1223 * IPs reset varies by asic.
1225 int (*mode2_reset)(struct smu_context *smu);
1226 /* for gfx feature enablement after mode2 reset */
1227 int (*enable_gfx_features)(struct smu_context *smu);
1230 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock
1233 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
1236 * @set_soft_freq_limited_range: Set the soft frequency range of a clock
1239 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
1242 * @set_power_source: Notify the SMU of the current power source.
1244 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
1247 * @log_thermal_throttling_event: Print a thermal throttling warning to
1250 void (*log_thermal_throttling_event)(struct smu_context *smu);
1253 * @get_pp_feature_mask: Print a human readable table of enabled
1254 * features to buffer.
1256 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
1259 * @set_pp_feature_mask: Request the SMU enable/disable features to
1260 * match those enabled in &new_mask.
1262 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
1265 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
1267 * Return: Size of &table
1269 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
1272 * @get_pm_metrics: Get one snapshot of power management metrics from
1275 * Return: Size of the metrics sample
1277 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics,
1281 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
1283 int (*enable_mgpu_fan_boost)(struct smu_context *smu);
1286 * @gfx_ulv_control: Enable/disable ultra low voltage.
1288 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
1291 * @deep_sleep_control: Enable/disable deep sleep.
1293 int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
1296 * @get_fan_parameters: Get fan parameters.
1298 * Get maximum fan speed from the power play table.
1300 int (*get_fan_parameters)(struct smu_context *smu);
1303 * @post_init: Helper function for asic specific workarounds.
1305 int (*post_init)(struct smu_context *smu);
1308 * @interrupt_work: Work task scheduled from SMU interrupt handler.
1310 void (*interrupt_work)(struct smu_context *smu);
1313 * @gpo_control: Enable/disable graphics power optimization if supported.
1315 int (*gpo_control)(struct smu_context *smu, bool enablement);
1318 * @gfx_state_change_set: Send the current graphics state to the SMU.
1320 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
1323 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
1324 * parameters to defaults.
1326 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
1329 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
1331 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
1334 * @wait_for_event: Wait for events from SMU.
1336 int (*wait_for_event)(struct smu_context *smu,
1337 enum smu_event_type event, uint64_t event_arg);
1340 * @sned_hbm_bad_pages_num: message SMU to update bad page number
1343 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
1346 * @get_ecc_table: message SMU to get ECC INFO table.
1348 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
1352 * @stb_collect_info: Collects Smart Trace Buffers data.
1354 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size);
1357 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings.
1359 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table);
1362 * @set_config_table: Apply the input DriverSmuConfig table settings.
1364 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table);
1367 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info
1370 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size);
1373 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP
1375 int (*init_pptable_microcode)(struct smu_context *smu);
1378 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power
1381 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable);
1384 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power
1387 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);
1390 * @notify_rlc_state: Notify RLC power state to SMU.
1392 int (*notify_rlc_state)(struct smu_context *smu, bool en);
1395 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature
1397 bool (*is_asic_wbrf_supported)(struct smu_context *smu);
1400 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported
1402 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable);
1405 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied
1407 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu,
1408 struct freq_band_range *exclusion_ranges);
1412 METRICS_CURR_GFXCLK,
1413 METRICS_CURR_SOCCLK,
1420 METRICS_CURR_DCEFCLK,
1421 METRICS_AVERAGE_CPUCLK,
1422 METRICS_AVERAGE_GFXCLK,
1423 METRICS_AVERAGE_SOCCLK,
1424 METRICS_AVERAGE_FCLK,
1425 METRICS_AVERAGE_UCLK,
1426 METRICS_AVERAGE_VCLK,
1427 METRICS_AVERAGE_DCLK,
1428 METRICS_AVERAGE_VCLK1,
1429 METRICS_AVERAGE_DCLK1,
1430 METRICS_AVERAGE_GFXACTIVITY,
1431 METRICS_AVERAGE_MEMACTIVITY,
1432 METRICS_AVERAGE_VCNACTIVITY,
1433 METRICS_AVERAGE_SOCKETPOWER,
1434 METRICS_TEMPERATURE_EDGE,
1435 METRICS_TEMPERATURE_HOTSPOT,
1436 METRICS_TEMPERATURE_MEM,
1437 METRICS_TEMPERATURE_VRGFX,
1438 METRICS_TEMPERATURE_VRSOC,
1439 METRICS_TEMPERATURE_VRMEM,
1440 METRICS_THROTTLER_STATUS,
1441 METRICS_CURR_FANSPEED,
1442 METRICS_VOLTAGE_VDDSOC,
1443 METRICS_VOLTAGE_VDDGFX,
1444 METRICS_SS_APU_SHARE,
1445 METRICS_SS_DGPU_SHARE,
1446 METRICS_UNIQUE_ID_UPPER32,
1447 METRICS_UNIQUE_ID_LOWER32,
1450 METRICS_CURR_FANPWM,
1451 METRICS_CURR_SOCKETPOWER,
1452 METRICS_AVERAGE_VPECLK,
1453 METRICS_AVERAGE_IPUCLK,
1454 METRICS_AVERAGE_MPIPUCLK,
1455 METRICS_THROTTLER_RESIDENCY_PROCHOT,
1456 METRICS_THROTTLER_RESIDENCY_SPL,
1457 METRICS_THROTTLER_RESIDENCY_FPPT,
1458 METRICS_THROTTLER_RESIDENCY_SPPT,
1459 METRICS_THROTTLER_RESIDENCY_THM_CORE,
1460 METRICS_THROTTLER_RESIDENCY_THM_GFX,
1461 METRICS_THROTTLER_RESIDENCY_THM_SOC,
1464 enum smu_cmn2asic_mapping_type {
1465 CMN2ASIC_MAPPING_MSG,
1466 CMN2ASIC_MAPPING_CLK,
1467 CMN2ASIC_MAPPING_FEATURE,
1468 CMN2ASIC_MAPPING_TABLE,
1469 CMN2ASIC_MAPPING_PWR,
1470 CMN2ASIC_MAPPING_WORKLOAD,
1481 #define MSG_MAP(msg, index, valid_in_vf) \
1482 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
1484 #define CLK_MAP(clk, index) \
1485 [SMU_##clk] = {1, (index)}
1487 #define FEA_MAP(fea) \
1488 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
1490 #define FEA_MAP_REVERSE(fea) \
1491 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1493 #define FEA_MAP_HALF_REVERSE(fea) \
1494 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1496 #define TAB_MAP(tab) \
1497 [SMU_TABLE_##tab] = {1, TABLE_##tab}
1499 #define TAB_MAP_VALID(tab) \
1500 [SMU_TABLE_##tab] = {1, TABLE_##tab}
1502 #define TAB_MAP_INVALID(tab) \
1503 [SMU_TABLE_##tab] = {0, TABLE_##tab}
1505 #define PWR_MAP(tab) \
1506 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
1508 #define WORKLOAD_MAP(profile, workload) \
1509 [profile] = {1, (workload)}
1512 * smu_memcpy_trailing - Copy the end of one structure into the middle of another
1514 * @dst: Pointer to destination struct
1515 * @first_dst_member: The member name in @dst where the overwrite begins
1516 * @last_dst_member: The member name in @dst where the overwrite ends after
1517 * @src: Pointer to the source struct
1518 * @first_src_member: The member name in @src where the copy begins
1521 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \
1522 src, first_src_member) \
1524 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \
1525 size_t __src_size = sizeof(*(src)) - __src_offset; \
1526 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \
1527 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \
1529 BUILD_BUG_ON(__src_size != __dst_size); \
1530 __builtin_memcpy((u8 *)(dst) + __dst_offset, \
1531 (u8 *)(src) + __src_offset, \
1541 uint32_t WifiBandEntryNum;
1542 WifiOneBand_t WifiBandEntry[11];
1543 uint32_t MmHubPadding[8];
1544 } WifiBandEntryTable_t;
1546 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
1547 int smu_get_power_limit(void *handle,
1549 enum pp_power_limit_level pp_limit_level,
1550 enum pp_power_type pp_power_type);
1552 bool smu_mode1_reset_is_support(struct smu_context *smu);
1553 bool smu_mode2_reset_is_support(struct smu_context *smu);
1554 int smu_mode1_reset(struct smu_context *smu);
1556 extern const struct amd_ip_funcs smu_ip_funcs;
1558 bool is_support_sw_smu(struct amdgpu_device *adev);
1559 bool is_support_cclk_dpm(struct amdgpu_device *adev);
1560 int smu_write_watermarks_table(struct smu_context *smu);
1562 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1563 uint32_t *min, uint32_t *max);
1565 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1566 uint32_t min, uint32_t max);
1568 int smu_set_gfx_power_up_by_imu(struct smu_context *smu);
1570 int smu_set_ac_dc(struct smu_context *smu);
1572 int smu_set_xgmi_plpd_mode(struct smu_context *smu,
1573 enum pp_xgmi_plpd_mode mode);
1575 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value);
1577 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value);
1579 int smu_set_residency_gfxoff(struct smu_context *smu, bool value);
1581 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);
1583 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
1585 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1586 uint64_t event_arg);
1587 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc);
1588 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size);
1589 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
1590 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
1591 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);