2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define SWSMU_CODE_LAYER_L1
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
29 #include "amdgpu_smu.h"
30 #include "smu_internal.h"
32 #include "arcturus_ppt.h"
33 #include "navi10_ppt.h"
34 #include "sienna_cichlid_ppt.h"
35 #include "renoir_ppt.h"
36 #include "vangogh_ppt.h"
37 #include "aldebaran_ppt.h"
38 #include "yellow_carp_ppt.h"
39 #include "cyan_skillfish_ppt.h"
40 #include "smu_v13_0_0_ppt.h"
41 #include "smu_v13_0_4_ppt.h"
42 #include "smu_v13_0_5_ppt.h"
43 #include "smu_v13_0_7_ppt.h"
47 * DO NOT use these for err/warn/info/debug messages.
48 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
49 * They are more MGPU friendly.
56 static const struct amd_pm_funcs swsmu_pm_funcs;
57 static int smu_force_smuclk_levels(struct smu_context *smu,
58 enum smu_clk_type clk_type,
60 static int smu_handle_task(struct smu_context *smu,
61 enum amd_dpm_forced_level level,
62 enum amd_pp_task task_id);
63 static int smu_reset(struct smu_context *smu);
64 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
65 static int smu_set_fan_control_mode(void *handle, u32 value);
66 static int smu_set_power_limit(void *handle, uint32_t limit);
67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
71 static int smu_sys_get_pp_feature_mask(void *handle,
74 struct smu_context *smu = handle;
76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
79 return smu_get_pp_feature_mask(smu, buf);
82 static int smu_sys_set_pp_feature_mask(void *handle,
85 struct smu_context *smu = handle;
87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
90 return smu_set_pp_feature_mask(smu, new_mask);
93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
95 if (!smu->ppt_funcs->set_gfx_off_residency)
98 return smu_set_gfx_off_residency(smu, value);
101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
103 if (!smu->ppt_funcs->get_gfx_off_residency)
106 return smu_get_gfx_off_residency(smu, value);
109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
111 if (!smu->ppt_funcs->get_gfx_off_entrycount)
114 return smu_get_gfx_off_entrycount(smu, value);
117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
119 if (!smu->ppt_funcs->get_gfx_off_status)
122 *value = smu_get_gfx_off_status(smu);
127 int smu_set_soft_freq_range(struct smu_context *smu,
128 enum smu_clk_type clk_type,
134 if (smu->ppt_funcs->set_soft_freq_limited_range)
135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
143 int smu_get_dpm_freq_range(struct smu_context *smu,
144 enum smu_clk_type clk_type,
153 if (smu->ppt_funcs->get_dpm_ultimate_freq)
154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
164 if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu)
167 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
170 static u32 smu_get_mclk(void *handle, bool low)
172 struct smu_context *smu = handle;
176 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
177 low ? &clk_freq : NULL,
178 !low ? &clk_freq : NULL);
181 return clk_freq * 100;
184 static u32 smu_get_sclk(void *handle, bool low)
186 struct smu_context *smu = handle;
190 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
191 low ? &clk_freq : NULL,
192 !low ? &clk_freq : NULL);
195 return clk_freq * 100;
198 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
201 struct smu_power_context *smu_power = &smu->smu_power;
202 struct smu_power_gate *power_gate = &smu_power->power_gate;
205 if (!smu->ppt_funcs->dpm_set_vcn_enable)
208 if (atomic_read(&power_gate->vcn_gated) ^ enable)
211 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
213 atomic_set(&power_gate->vcn_gated, !enable);
218 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
221 struct smu_power_context *smu_power = &smu->smu_power;
222 struct smu_power_gate *power_gate = &smu_power->power_gate;
225 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
228 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
231 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
233 atomic_set(&power_gate->jpeg_gated, !enable);
239 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
241 * @handle: smu_context pointer
242 * @block_type: the IP block to power gate/ungate
243 * @gate: to power gate if true, ungate otherwise
245 * This API uses no smu->mutex lock protection due to:
246 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
247 * This is guarded to be race condition free by the caller.
248 * 2. Or get called on user setting request of power_dpm_force_performance_level.
249 * Under this case, the smu->mutex lock protection is already enforced on
250 * the parent API smu_force_performance_level of the call path.
252 static int smu_dpm_set_power_gate(void *handle,
256 struct smu_context *smu = handle;
259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
260 dev_WARN(smu->adev->dev,
261 "SMU uninitialized but power %s requested for %u!\n",
262 gate ? "gate" : "ungate", block_type);
266 switch (block_type) {
268 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
269 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
271 case AMD_IP_BLOCK_TYPE_UVD:
272 case AMD_IP_BLOCK_TYPE_VCN:
273 ret = smu_dpm_set_vcn_enable(smu, !gate);
275 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
276 gate ? "gate" : "ungate");
278 case AMD_IP_BLOCK_TYPE_GFX:
279 ret = smu_gfx_off_control(smu, gate);
281 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
282 gate ? "enable" : "disable");
284 case AMD_IP_BLOCK_TYPE_SDMA:
285 ret = smu_powergate_sdma(smu, gate);
287 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
288 gate ? "gate" : "ungate");
290 case AMD_IP_BLOCK_TYPE_JPEG:
291 ret = smu_dpm_set_jpeg_enable(smu, !gate);
293 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
294 gate ? "gate" : "ungate");
297 dev_err(smu->adev->dev, "Unsupported block type!\n");
305 * smu_set_user_clk_dependencies - set user profile clock dependencies
307 * @smu: smu_context pointer
308 * @clk: enum smu_clk_type type
310 * Enable/Disable the clock dependency for the @clk type.
312 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
314 if (smu->adev->in_suspend)
317 if (clk == SMU_MCLK) {
318 smu->user_dpm_profile.clk_dependency = 0;
319 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
320 } else if (clk == SMU_FCLK) {
321 /* MCLK takes precedence over FCLK */
322 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
325 smu->user_dpm_profile.clk_dependency = 0;
326 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
327 } else if (clk == SMU_SOCCLK) {
328 /* MCLK takes precedence over SOCCLK */
329 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
332 smu->user_dpm_profile.clk_dependency = 0;
333 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
335 /* Add clk dependencies here, if any */
340 * smu_restore_dpm_user_profile - reinstate user dpm profile
342 * @smu: smu_context pointer
344 * Restore the saved user power configurations include power limit,
345 * clock frequencies, fan control mode and fan speed.
347 static void smu_restore_dpm_user_profile(struct smu_context *smu)
349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
352 if (!smu->adev->in_suspend)
355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
358 /* Enable restore flag */
359 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
361 /* set the user dpm power limit */
362 if (smu->user_dpm_profile.power_limit) {
363 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
365 dev_err(smu->adev->dev, "Failed to set power limit value\n");
368 /* set the user dpm clock configurations */
369 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
370 enum smu_clk_type clk_type;
372 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
374 * Iterate over smu clk type and force the saved user clk
375 * configs, skip if clock dependency is enabled
377 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
378 smu->user_dpm_profile.clk_mask[clk_type]) {
379 ret = smu_force_smuclk_levels(smu, clk_type,
380 smu->user_dpm_profile.clk_mask[clk_type]);
382 dev_err(smu->adev->dev,
383 "Failed to set clock type = %d\n", clk_type);
388 /* set the user dpm fan configurations */
389 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
390 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
392 if (ret != -EOPNOTSUPP) {
393 smu->user_dpm_profile.fan_speed_pwm = 0;
394 smu->user_dpm_profile.fan_speed_rpm = 0;
395 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
396 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
399 if (smu->user_dpm_profile.fan_speed_pwm) {
400 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
401 if (ret != -EOPNOTSUPP)
402 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
405 if (smu->user_dpm_profile.fan_speed_rpm) {
406 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
407 if (ret != -EOPNOTSUPP)
408 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
412 /* Restore user customized OD settings */
413 if (smu->user_dpm_profile.user_od) {
414 if (smu->ppt_funcs->restore_user_od_settings) {
415 ret = smu->ppt_funcs->restore_user_od_settings(smu);
417 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
421 /* Disable restore flag */
422 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
425 static int smu_get_power_num_states(void *handle,
426 struct pp_states_info *state_info)
431 /* not support power state */
432 memset(state_info, 0, sizeof(struct pp_states_info));
433 state_info->nums = 1;
434 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
439 bool is_support_sw_smu(struct amdgpu_device *adev)
441 /* vega20 is 11.0.2, but it's supported via the powerplay code */
442 if (adev->asic_type == CHIP_VEGA20)
445 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
451 bool is_support_cclk_dpm(struct amdgpu_device *adev)
453 struct smu_context *smu = adev->powerplay.pp_handle;
455 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
462 static int smu_sys_get_pp_table(void *handle,
465 struct smu_context *smu = handle;
466 struct smu_table_context *smu_table = &smu->smu_table;
468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
471 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
474 if (smu_table->hardcode_pptable)
475 *table = smu_table->hardcode_pptable;
477 *table = smu_table->power_play_table;
479 return smu_table->power_play_table_size;
482 static int smu_sys_set_pp_table(void *handle,
486 struct smu_context *smu = handle;
487 struct smu_table_context *smu_table = &smu->smu_table;
488 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
494 if (header->usStructureSize != size) {
495 dev_err(smu->adev->dev, "pp table size not matched !\n");
499 if (!smu_table->hardcode_pptable) {
500 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
501 if (!smu_table->hardcode_pptable)
505 memcpy(smu_table->hardcode_pptable, buf, size);
506 smu_table->power_play_table = smu_table->hardcode_pptable;
507 smu_table->power_play_table_size = size;
510 * Special hw_fini action(for Navi1x, the DPMs disablement will be
511 * skipped) may be needed for custom pptable uploading.
513 smu->uploading_custom_pp_table = true;
515 ret = smu_reset(smu);
517 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
519 smu->uploading_custom_pp_table = false;
524 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
526 struct smu_feature *feature = &smu->smu_feature;
527 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
531 * With SCPM enabled, the allowed featuremasks setting(via
532 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
533 * That means there is no way to let PMFW knows the settings below.
534 * Thus, we just assume all the features are allowed under
537 if (smu->adev->scpm_enabled) {
538 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
542 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
544 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
549 bitmap_or(feature->allowed, feature->allowed,
550 (unsigned long *)allowed_feature_mask,
551 feature->feature_num);
556 static int smu_set_funcs(struct amdgpu_device *adev)
558 struct smu_context *smu = adev->powerplay.pp_handle;
560 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
561 smu->od_enabled = true;
563 switch (adev->ip_versions[MP1_HWIP][0]) {
564 case IP_VERSION(11, 0, 0):
565 case IP_VERSION(11, 0, 5):
566 case IP_VERSION(11, 0, 9):
567 navi10_set_ppt_funcs(smu);
569 case IP_VERSION(11, 0, 7):
570 case IP_VERSION(11, 0, 11):
571 case IP_VERSION(11, 0, 12):
572 case IP_VERSION(11, 0, 13):
573 sienna_cichlid_set_ppt_funcs(smu);
575 case IP_VERSION(12, 0, 0):
576 case IP_VERSION(12, 0, 1):
577 renoir_set_ppt_funcs(smu);
579 case IP_VERSION(11, 5, 0):
580 vangogh_set_ppt_funcs(smu);
582 case IP_VERSION(13, 0, 1):
583 case IP_VERSION(13, 0, 3):
584 case IP_VERSION(13, 0, 8):
585 yellow_carp_set_ppt_funcs(smu);
587 case IP_VERSION(13, 0, 4):
588 smu_v13_0_4_set_ppt_funcs(smu);
590 case IP_VERSION(13, 0, 5):
591 smu_v13_0_5_set_ppt_funcs(smu);
593 case IP_VERSION(11, 0, 8):
594 cyan_skillfish_set_ppt_funcs(smu);
596 case IP_VERSION(11, 0, 2):
597 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
598 arcturus_set_ppt_funcs(smu);
599 /* OD is not supported on Arcturus */
600 smu->od_enabled =false;
602 case IP_VERSION(13, 0, 2):
603 aldebaran_set_ppt_funcs(smu);
604 /* Enable pp_od_clk_voltage node */
605 smu->od_enabled = true;
607 case IP_VERSION(13, 0, 0):
608 case IP_VERSION(13, 0, 10):
609 smu_v13_0_0_set_ppt_funcs(smu);
611 case IP_VERSION(13, 0, 7):
612 smu_v13_0_7_set_ppt_funcs(smu);
621 static int smu_early_init(void *handle)
623 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
624 struct smu_context *smu;
626 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
631 smu->pm_enabled = !!amdgpu_dpm;
633 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
634 smu->smu_baco.platform_support = false;
635 smu->user_dpm_profile.fan_mode = -1;
637 mutex_init(&smu->message_lock);
639 adev->powerplay.pp_handle = smu;
640 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
642 return smu_set_funcs(adev);
645 static int smu_set_default_dpm_table(struct smu_context *smu)
647 struct smu_power_context *smu_power = &smu->smu_power;
648 struct smu_power_gate *power_gate = &smu_power->power_gate;
649 int vcn_gate, jpeg_gate;
652 if (!smu->ppt_funcs->set_default_dpm_table)
655 vcn_gate = atomic_read(&power_gate->vcn_gated);
656 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
658 ret = smu_dpm_set_vcn_enable(smu, true);
662 ret = smu_dpm_set_jpeg_enable(smu, true);
666 ret = smu->ppt_funcs->set_default_dpm_table(smu);
668 dev_err(smu->adev->dev,
669 "Failed to setup default dpm clock tables!\n");
671 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
673 smu_dpm_set_vcn_enable(smu, !vcn_gate);
677 static int smu_apply_default_config_table_settings(struct smu_context *smu)
679 struct amdgpu_device *adev = smu->adev;
682 ret = smu_get_default_config_table_settings(smu,
683 &adev->pm.config_table);
687 return smu_set_config_table(smu, &adev->pm.config_table);
690 static int smu_late_init(void *handle)
692 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
693 struct smu_context *smu = adev->powerplay.pp_handle;
696 smu_set_fine_grain_gfx_freq_parameters(smu);
698 if (!smu->pm_enabled)
701 ret = smu_post_init(smu);
703 dev_err(adev->dev, "Failed to post smu init!\n");
707 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
708 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
711 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
712 ret = smu_set_default_od_settings(smu);
714 dev_err(adev->dev, "Failed to setup default OD settings!\n");
719 ret = smu_populate_umd_state_clk(smu);
721 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
725 ret = smu_get_asic_power_limits(smu,
726 &smu->current_power_limit,
727 &smu->default_power_limit,
728 &smu->max_power_limit);
730 dev_err(adev->dev, "Failed to get asic power limits!\n");
734 if (!amdgpu_sriov_vf(adev))
735 smu_get_unique_id(smu);
737 smu_get_fan_parameters(smu);
740 smu->smu_dpm.dpm_level,
741 AMD_PP_TASK_COMPLETE_INIT);
743 ret = smu_apply_default_config_table_settings(smu);
744 if (ret && (ret != -EOPNOTSUPP)) {
745 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
749 smu_restore_dpm_user_profile(smu);
754 static int smu_init_fb_allocations(struct smu_context *smu)
756 struct amdgpu_device *adev = smu->adev;
757 struct smu_table_context *smu_table = &smu->smu_table;
758 struct smu_table *tables = smu_table->tables;
759 struct smu_table *driver_table = &(smu_table->driver_table);
760 uint32_t max_table_size = 0;
763 /* VRAM allocation for tool table */
764 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
765 ret = amdgpu_bo_create_kernel(adev,
766 tables[SMU_TABLE_PMSTATUSLOG].size,
767 tables[SMU_TABLE_PMSTATUSLOG].align,
768 tables[SMU_TABLE_PMSTATUSLOG].domain,
769 &tables[SMU_TABLE_PMSTATUSLOG].bo,
770 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
771 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
773 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
778 /* VRAM allocation for driver table */
779 for (i = 0; i < SMU_TABLE_COUNT; i++) {
780 if (tables[i].size == 0)
783 if (i == SMU_TABLE_PMSTATUSLOG)
786 if (max_table_size < tables[i].size)
787 max_table_size = tables[i].size;
790 driver_table->size = max_table_size;
791 driver_table->align = PAGE_SIZE;
792 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
794 ret = amdgpu_bo_create_kernel(adev,
797 driver_table->domain,
799 &driver_table->mc_address,
800 &driver_table->cpu_addr);
802 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
803 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
804 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
805 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
806 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
812 static int smu_fini_fb_allocations(struct smu_context *smu)
814 struct smu_table_context *smu_table = &smu->smu_table;
815 struct smu_table *tables = smu_table->tables;
816 struct smu_table *driver_table = &(smu_table->driver_table);
818 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
819 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
820 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
821 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
823 amdgpu_bo_free_kernel(&driver_table->bo,
824 &driver_table->mc_address,
825 &driver_table->cpu_addr);
831 * smu_alloc_memory_pool - allocate memory pool in the system memory
833 * @smu: amdgpu_device pointer
835 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
836 * and DramLogSetDramAddr can notify it changed.
838 * Returns 0 on success, error on failure.
840 static int smu_alloc_memory_pool(struct smu_context *smu)
842 struct amdgpu_device *adev = smu->adev;
843 struct smu_table_context *smu_table = &smu->smu_table;
844 struct smu_table *memory_pool = &smu_table->memory_pool;
845 uint64_t pool_size = smu->pool_size;
848 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
851 memory_pool->size = pool_size;
852 memory_pool->align = PAGE_SIZE;
853 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
856 case SMU_MEMORY_POOL_SIZE_256_MB:
857 case SMU_MEMORY_POOL_SIZE_512_MB:
858 case SMU_MEMORY_POOL_SIZE_1_GB:
859 case SMU_MEMORY_POOL_SIZE_2_GB:
860 ret = amdgpu_bo_create_kernel(adev,
865 &memory_pool->mc_address,
866 &memory_pool->cpu_addr);
868 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
877 static int smu_free_memory_pool(struct smu_context *smu)
879 struct smu_table_context *smu_table = &smu->smu_table;
880 struct smu_table *memory_pool = &smu_table->memory_pool;
882 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
885 amdgpu_bo_free_kernel(&memory_pool->bo,
886 &memory_pool->mc_address,
887 &memory_pool->cpu_addr);
889 memset(memory_pool, 0, sizeof(struct smu_table));
894 static int smu_alloc_dummy_read_table(struct smu_context *smu)
896 struct smu_table_context *smu_table = &smu->smu_table;
897 struct smu_table *dummy_read_1_table =
898 &smu_table->dummy_read_1_table;
899 struct amdgpu_device *adev = smu->adev;
902 dummy_read_1_table->size = 0x40000;
903 dummy_read_1_table->align = PAGE_SIZE;
904 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
906 ret = amdgpu_bo_create_kernel(adev,
907 dummy_read_1_table->size,
908 dummy_read_1_table->align,
909 dummy_read_1_table->domain,
910 &dummy_read_1_table->bo,
911 &dummy_read_1_table->mc_address,
912 &dummy_read_1_table->cpu_addr);
914 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
919 static void smu_free_dummy_read_table(struct smu_context *smu)
921 struct smu_table_context *smu_table = &smu->smu_table;
922 struct smu_table *dummy_read_1_table =
923 &smu_table->dummy_read_1_table;
926 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
927 &dummy_read_1_table->mc_address,
928 &dummy_read_1_table->cpu_addr);
930 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
933 static int smu_smc_table_sw_init(struct smu_context *smu)
938 * Create smu_table structure, and init smc tables such as
939 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
941 ret = smu_init_smc_tables(smu);
943 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
948 * Create smu_power_context structure, and allocate smu_dpm_context and
949 * context size to fill the smu_power_context data.
951 ret = smu_init_power(smu);
953 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
958 * allocate vram bos to store smc table contents.
960 ret = smu_init_fb_allocations(smu);
964 ret = smu_alloc_memory_pool(smu);
968 ret = smu_alloc_dummy_read_table(smu);
972 ret = smu_i2c_init(smu);
979 static int smu_smc_table_sw_fini(struct smu_context *smu)
985 smu_free_dummy_read_table(smu);
987 ret = smu_free_memory_pool(smu);
991 ret = smu_fini_fb_allocations(smu);
995 ret = smu_fini_power(smu);
997 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1001 ret = smu_fini_smc_tables(smu);
1003 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1010 static void smu_throttling_logging_work_fn(struct work_struct *work)
1012 struct smu_context *smu = container_of(work, struct smu_context,
1013 throttling_logging_work);
1015 smu_log_thermal_throttling(smu);
1018 static void smu_interrupt_work_fn(struct work_struct *work)
1020 struct smu_context *smu = container_of(work, struct smu_context,
1023 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1024 smu->ppt_funcs->interrupt_work(smu);
1027 static int smu_sw_init(void *handle)
1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1030 struct smu_context *smu = adev->powerplay.pp_handle;
1033 smu->pool_size = adev->pm.smu_prv_buffer_size;
1034 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1035 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1036 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1038 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1039 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1040 atomic64_set(&smu->throttle_int_counter, 0);
1041 smu->watermarks_bitmap = 0;
1042 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1043 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1045 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1046 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1048 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1049 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1050 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1051 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1052 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1053 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1054 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1055 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1057 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1058 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1059 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1060 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1061 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1062 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1063 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1064 smu->display_config = &adev->pm.pm_display_cfg;
1066 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1067 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1069 ret = smu_init_microcode(smu);
1071 dev_err(adev->dev, "Failed to load smu firmware!\n");
1075 ret = smu_smc_table_sw_init(smu);
1077 dev_err(adev->dev, "Failed to sw init smc table!\n");
1081 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1082 ret = smu_get_vbios_bootup_values(smu);
1084 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1088 ret = smu_init_pptable_microcode(smu);
1090 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1094 ret = smu_register_irq_handler(smu);
1096 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1100 /* If there is no way to query fan control mode, fan control is not supported */
1101 if (!smu->ppt_funcs->get_fan_control_mode)
1102 smu->adev->pm.no_fan = true;
1107 static int smu_sw_fini(void *handle)
1109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1110 struct smu_context *smu = adev->powerplay.pp_handle;
1113 ret = smu_smc_table_sw_fini(smu);
1115 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1119 smu_fini_microcode(smu);
1124 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1126 struct amdgpu_device *adev = smu->adev;
1127 struct smu_temperature_range *range =
1128 &smu->thermal_range;
1131 if (!smu->ppt_funcs->get_thermal_temperature_range)
1134 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1138 adev->pm.dpm.thermal.min_temp = range->min;
1139 adev->pm.dpm.thermal.max_temp = range->max;
1140 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1141 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1142 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1143 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1144 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1145 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1146 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1151 static int smu_smc_hw_setup(struct smu_context *smu)
1153 struct smu_feature *feature = &smu->smu_feature;
1154 struct amdgpu_device *adev = smu->adev;
1155 uint32_t pcie_gen = 0, pcie_width = 0;
1156 uint64_t features_supported;
1159 switch (adev->ip_versions[MP1_HWIP][0]) {
1160 case IP_VERSION(11, 0, 7):
1161 case IP_VERSION(11, 0, 11):
1162 case IP_VERSION(11, 5, 0):
1163 case IP_VERSION(11, 0, 12):
1164 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1165 dev_info(adev->dev, "dpm has been enabled\n");
1166 ret = smu_system_features_control(smu, true);
1168 dev_err(adev->dev, "Failed system features control!\n");
1176 ret = smu_init_display_count(smu, 0);
1178 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1182 ret = smu_set_driver_table_location(smu);
1184 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1189 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1191 ret = smu_set_tool_table_location(smu);
1193 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1198 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1201 ret = smu_notify_memory_pool_location(smu);
1203 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1207 ret = smu_setup_pptable(smu);
1209 dev_err(adev->dev, "Failed to setup pptable!\n");
1213 /* smu_dump_pptable(smu); */
1216 * With SCPM enabled, PSP is responsible for the PPTable transferring
1217 * (to SMU). Driver involvement is not needed and permitted.
1219 if (!adev->scpm_enabled) {
1221 * Copy pptable bo in the vram to smc with SMU MSGs such as
1222 * SetDriverDramAddr and TransferTableDram2Smu.
1224 ret = smu_write_pptable(smu);
1226 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1231 /* issue Run*Btc msg */
1232 ret = smu_run_btc(smu);
1237 * With SCPM enabled, these actions(and relevant messages) are
1238 * not needed and permitted.
1240 if (!adev->scpm_enabled) {
1241 ret = smu_feature_set_allowed_mask(smu);
1243 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1248 ret = smu_system_features_control(smu, true);
1250 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1254 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1256 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1259 bitmap_copy(feature->supported,
1260 (unsigned long *)&features_supported,
1261 feature->feature_num);
1263 if (!smu_is_dpm_running(smu))
1264 dev_info(adev->dev, "dpm has been disabled\n");
1267 * Set initialized values (get from vbios) to dpm tables context such as
1268 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1271 ret = smu_set_default_dpm_table(smu);
1273 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1277 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1279 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1281 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1283 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1286 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1287 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1288 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1290 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1292 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1294 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1296 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1298 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1300 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1302 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1304 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1308 ret = smu_get_thermal_temperature_range(smu);
1310 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1314 ret = smu_enable_thermal_alert(smu);
1316 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1320 ret = smu_notify_display_change(smu);
1322 dev_err(adev->dev, "Failed to notify display change!\n");
1327 * Set min deep sleep dce fclk with bootup value from vbios via
1328 * SetMinDeepSleepDcefclk MSG.
1330 ret = smu_set_min_dcef_deep_sleep(smu,
1331 smu->smu_table.boot_values.dcefclk / 100);
1336 static int smu_start_smc_engine(struct smu_context *smu)
1338 struct amdgpu_device *adev = smu->adev;
1341 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1342 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1343 if (smu->ppt_funcs->load_microcode) {
1344 ret = smu->ppt_funcs->load_microcode(smu);
1351 if (smu->ppt_funcs->check_fw_status) {
1352 ret = smu->ppt_funcs->check_fw_status(smu);
1354 dev_err(adev->dev, "SMC is not ready\n");
1360 * Send msg GetDriverIfVersion to check if the return value is equal
1361 * with DRIVER_IF_VERSION of smc header.
1363 ret = smu_check_fw_version(smu);
1370 static int smu_hw_init(void *handle)
1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374 struct smu_context *smu = adev->powerplay.pp_handle;
1376 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1377 smu->pm_enabled = false;
1381 ret = smu_start_smc_engine(smu);
1383 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1388 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
1389 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1390 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
1392 dev_err(adev->dev, "Failed to Enable gfx imu!\n");
1397 smu_dpm_set_vcn_enable(smu, true);
1398 smu_dpm_set_jpeg_enable(smu, true);
1399 smu_set_gfx_cgpg(smu, true);
1402 if (!smu->pm_enabled)
1405 ret = smu_get_driver_allowed_feature_mask(smu);
1409 ret = smu_smc_hw_setup(smu);
1411 dev_err(adev->dev, "Failed to setup smc hw!\n");
1416 * Move maximum sustainable clock retrieving here considering
1417 * 1. It is not needed on resume(from S3).
1418 * 2. DAL settings come between .hw_init and .late_init of SMU.
1419 * And DAL needs to know the maximum sustainable clocks. Thus
1420 * it cannot be put in .late_init().
1422 ret = smu_init_max_sustainable_clocks(smu);
1424 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1428 adev->pm.dpm_enabled = true;
1430 dev_info(adev->dev, "SMU is initialized successfully!\n");
1435 static int smu_disable_dpms(struct smu_context *smu)
1437 struct amdgpu_device *adev = smu->adev;
1439 bool use_baco = !smu->is_apu &&
1440 ((amdgpu_in_reset(adev) &&
1441 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1442 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1445 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1446 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1448 switch (adev->ip_versions[MP1_HWIP][0]) {
1449 case IP_VERSION(13, 0, 0):
1450 case IP_VERSION(13, 0, 7):
1457 * For custom pptable uploading, skip the DPM features
1458 * disable process on Navi1x ASICs.
1459 * - As the gfx related features are under control of
1460 * RLC on those ASICs. RLC reinitialization will be
1461 * needed to reenable them. That will cost much more
1464 * - SMU firmware can handle the DPM reenablement
1467 if (smu->uploading_custom_pp_table) {
1468 switch (adev->ip_versions[MP1_HWIP][0]) {
1469 case IP_VERSION(11, 0, 0):
1470 case IP_VERSION(11, 0, 5):
1471 case IP_VERSION(11, 0, 9):
1472 case IP_VERSION(11, 0, 7):
1473 case IP_VERSION(11, 0, 11):
1474 case IP_VERSION(11, 5, 0):
1475 case IP_VERSION(11, 0, 12):
1476 case IP_VERSION(11, 0, 13):
1484 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1485 * on BACO in. Driver involvement is unnecessary.
1488 switch (adev->ip_versions[MP1_HWIP][0]) {
1489 case IP_VERSION(11, 0, 7):
1490 case IP_VERSION(11, 0, 0):
1491 case IP_VERSION(11, 0, 5):
1492 case IP_VERSION(11, 0, 9):
1493 case IP_VERSION(13, 0, 7):
1501 * For gpu reset, runpm and hibernation through BACO,
1502 * BACO feature has to be kept enabled.
1504 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1505 ret = smu_disable_all_features_with_exception(smu,
1506 SMU_FEATURE_BACO_BIT);
1508 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1510 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1511 if (!adev->scpm_enabled) {
1512 ret = smu_system_features_control(smu, false);
1514 dev_err(adev->dev, "Failed to disable smu features.\n");
1518 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1519 adev->gfx.rlc.funcs->stop)
1520 adev->gfx.rlc.funcs->stop(adev);
1525 static int smu_smc_hw_cleanup(struct smu_context *smu)
1527 struct amdgpu_device *adev = smu->adev;
1530 cancel_work_sync(&smu->throttling_logging_work);
1531 cancel_work_sync(&smu->interrupt_work);
1533 ret = smu_disable_thermal_alert(smu);
1535 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1539 ret = smu_disable_dpms(smu);
1541 dev_err(adev->dev, "Fail to disable dpm features!\n");
1548 static int smu_hw_fini(void *handle)
1550 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1551 struct smu_context *smu = adev->powerplay.pp_handle;
1553 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1556 smu_dpm_set_vcn_enable(smu, false);
1557 smu_dpm_set_jpeg_enable(smu, false);
1559 adev->vcn.cur_state = AMD_PG_STATE_GATE;
1560 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1562 if (!smu->pm_enabled)
1565 adev->pm.dpm_enabled = false;
1567 return smu_smc_hw_cleanup(smu);
1570 static void smu_late_fini(void *handle)
1572 struct amdgpu_device *adev = handle;
1573 struct smu_context *smu = adev->powerplay.pp_handle;
1578 static int smu_reset(struct smu_context *smu)
1580 struct amdgpu_device *adev = smu->adev;
1583 ret = smu_hw_fini(adev);
1587 ret = smu_hw_init(adev);
1591 ret = smu_late_init(adev);
1598 static int smu_suspend(void *handle)
1600 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1601 struct smu_context *smu = adev->powerplay.pp_handle;
1605 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1608 if (!smu->pm_enabled)
1611 adev->pm.dpm_enabled = false;
1613 ret = smu_smc_hw_cleanup(smu);
1617 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1619 smu_set_gfx_cgpg(smu, false);
1622 * pwfw resets entrycount when device is suspended, so we save the
1623 * last value to be used when we resume to keep it consistent
1625 ret = smu_get_entrycount_gfxoff(smu, &count);
1627 adev->gfx.gfx_off_entrycount = count;
1632 static int smu_resume(void *handle)
1635 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1636 struct smu_context *smu = adev->powerplay.pp_handle;
1638 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1641 if (!smu->pm_enabled)
1644 dev_info(adev->dev, "SMU is resuming...\n");
1646 ret = smu_start_smc_engine(smu);
1648 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1652 ret = smu_smc_hw_setup(smu);
1654 dev_err(adev->dev, "Failed to setup smc hw!\n");
1658 smu_set_gfx_cgpg(smu, true);
1660 smu->disable_uclk_switch = 0;
1662 adev->pm.dpm_enabled = true;
1664 dev_info(adev->dev, "SMU is resumed successfully!\n");
1669 static int smu_display_configuration_change(void *handle,
1670 const struct amd_pp_display_configuration *display_config)
1672 struct smu_context *smu = handle;
1674 int num_of_active_display = 0;
1676 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1679 if (!display_config)
1682 smu_set_min_dcef_deep_sleep(smu,
1683 display_config->min_dcef_deep_sleep_set_clk / 100);
1685 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1686 if (display_config->displays[index].controller_id != 0)
1687 num_of_active_display++;
1693 static int smu_set_clockgating_state(void *handle,
1694 enum amd_clockgating_state state)
1699 static int smu_set_powergating_state(void *handle,
1700 enum amd_powergating_state state)
1705 static int smu_enable_umd_pstate(void *handle,
1706 enum amd_dpm_forced_level *level)
1708 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1709 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1710 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1711 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1713 struct smu_context *smu = (struct smu_context*)(handle);
1714 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1716 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1719 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1720 /* enter umd pstate, save current level, disable gfx cg*/
1721 if (*level & profile_mode_mask) {
1722 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1723 smu_gpo_control(smu, false);
1724 smu_gfx_ulv_control(smu, false);
1725 smu_deep_sleep_control(smu, false);
1726 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1729 /* exit umd pstate, restore level, enable gfx cg*/
1730 if (!(*level & profile_mode_mask)) {
1731 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1732 *level = smu_dpm_ctx->saved_dpm_level;
1733 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1734 smu_deep_sleep_control(smu, true);
1735 smu_gfx_ulv_control(smu, true);
1736 smu_gpo_control(smu, true);
1743 static int smu_bump_power_profile_mode(struct smu_context *smu,
1745 uint32_t param_size)
1749 if (smu->ppt_funcs->set_power_profile_mode)
1750 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1755 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1756 enum amd_dpm_forced_level level,
1757 bool skip_display_settings)
1762 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1764 if (!skip_display_settings) {
1765 ret = smu_display_config_changed(smu);
1767 dev_err(smu->adev->dev, "Failed to change display config!");
1772 ret = smu_apply_clocks_adjust_rules(smu);
1774 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1778 if (!skip_display_settings) {
1779 ret = smu_notify_smc_display_config(smu);
1781 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1786 if (smu_dpm_ctx->dpm_level != level) {
1787 ret = smu_asic_set_performance_level(smu, level);
1789 dev_err(smu->adev->dev, "Failed to set performance level!");
1793 /* update the saved copy */
1794 smu_dpm_ctx->dpm_level = level;
1797 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1798 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1799 index = fls(smu->workload_mask);
1800 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1801 workload = smu->workload_setting[index];
1803 if (smu->power_profile_mode != workload)
1804 smu_bump_power_profile_mode(smu, &workload, 0);
1810 static int smu_handle_task(struct smu_context *smu,
1811 enum amd_dpm_forced_level level,
1812 enum amd_pp_task task_id)
1816 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1820 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1821 ret = smu_pre_display_config_changed(smu);
1824 ret = smu_adjust_power_state_dynamic(smu, level, false);
1826 case AMD_PP_TASK_COMPLETE_INIT:
1827 case AMD_PP_TASK_READJUST_POWER_STATE:
1828 ret = smu_adjust_power_state_dynamic(smu, level, true);
1837 static int smu_handle_dpm_task(void *handle,
1838 enum amd_pp_task task_id,
1839 enum amd_pm_state_type *user_state)
1841 struct smu_context *smu = handle;
1842 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1844 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
1848 static int smu_switch_power_profile(void *handle,
1849 enum PP_SMC_POWER_PROFILE type,
1852 struct smu_context *smu = handle;
1853 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1857 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1860 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1864 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1865 index = fls(smu->workload_mask);
1866 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1867 workload = smu->workload_setting[index];
1869 smu->workload_mask |= (1 << smu->workload_prority[type]);
1870 index = fls(smu->workload_mask);
1871 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1872 workload = smu->workload_setting[index];
1875 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1876 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1877 smu_bump_power_profile_mode(smu, &workload, 0);
1882 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1884 struct smu_context *smu = handle;
1885 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1887 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1890 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1893 return smu_dpm_ctx->dpm_level;
1896 static int smu_force_performance_level(void *handle,
1897 enum amd_dpm_forced_level level)
1899 struct smu_context *smu = handle;
1900 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1903 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1906 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1909 ret = smu_enable_umd_pstate(smu, &level);
1913 ret = smu_handle_task(smu, level,
1914 AMD_PP_TASK_READJUST_POWER_STATE);
1916 /* reset user dpm clock state */
1917 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1918 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1919 smu->user_dpm_profile.clk_dependency = 0;
1925 static int smu_set_display_count(void *handle, uint32_t count)
1927 struct smu_context *smu = handle;
1929 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1932 return smu_init_display_count(smu, count);
1935 static int smu_force_smuclk_levels(struct smu_context *smu,
1936 enum smu_clk_type clk_type,
1939 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1942 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1945 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1946 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1950 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1951 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1952 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1953 smu->user_dpm_profile.clk_mask[clk_type] = mask;
1954 smu_set_user_clk_dependencies(smu, clk_type);
1961 static int smu_force_ppclk_levels(void *handle,
1962 enum pp_clock_type type,
1965 struct smu_context *smu = handle;
1966 enum smu_clk_type clk_type;
1970 clk_type = SMU_SCLK; break;
1972 clk_type = SMU_MCLK; break;
1974 clk_type = SMU_PCIE; break;
1976 clk_type = SMU_SOCCLK; break;
1978 clk_type = SMU_FCLK; break;
1980 clk_type = SMU_DCEFCLK; break;
1982 clk_type = SMU_VCLK; break;
1984 clk_type = SMU_DCLK; break;
1986 clk_type = SMU_OD_SCLK; break;
1988 clk_type = SMU_OD_MCLK; break;
1990 clk_type = SMU_OD_VDDC_CURVE; break;
1992 clk_type = SMU_OD_RANGE; break;
1997 return smu_force_smuclk_levels(smu, clk_type, mask);
2001 * On system suspending or resetting, the dpm_enabled
2002 * flag will be cleared. So that those SMU services which
2003 * are not supported will be gated.
2004 * However, the mp1 state setting should still be granted
2005 * even if the dpm_enabled cleared.
2007 static int smu_set_mp1_state(void *handle,
2008 enum pp_mp1_state mp1_state)
2010 struct smu_context *smu = handle;
2013 if (!smu->pm_enabled)
2016 if (smu->ppt_funcs &&
2017 smu->ppt_funcs->set_mp1_state)
2018 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2023 static int smu_set_df_cstate(void *handle,
2024 enum pp_df_cstate state)
2026 struct smu_context *smu = handle;
2029 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2032 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2035 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2037 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2042 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2046 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2049 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2052 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2054 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2059 int smu_write_watermarks_table(struct smu_context *smu)
2061 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2064 return smu_set_watermarks_table(smu, NULL);
2067 static int smu_set_watermarks_for_clock_ranges(void *handle,
2068 struct pp_smu_wm_range_sets *clock_ranges)
2070 struct smu_context *smu = handle;
2072 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2075 if (smu->disable_watermark)
2078 return smu_set_watermarks_table(smu, clock_ranges);
2081 int smu_set_ac_dc(struct smu_context *smu)
2085 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2088 /* controlled by firmware */
2089 if (smu->dc_controlled_by_gpio)
2092 ret = smu_set_power_source(smu,
2093 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2094 SMU_POWER_SOURCE_DC);
2096 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2097 smu->adev->pm.ac_power ? "AC" : "DC");
2102 const struct amd_ip_funcs smu_ip_funcs = {
2104 .early_init = smu_early_init,
2105 .late_init = smu_late_init,
2106 .sw_init = smu_sw_init,
2107 .sw_fini = smu_sw_fini,
2108 .hw_init = smu_hw_init,
2109 .hw_fini = smu_hw_fini,
2110 .late_fini = smu_late_fini,
2111 .suspend = smu_suspend,
2112 .resume = smu_resume,
2114 .check_soft_reset = NULL,
2115 .wait_for_idle = NULL,
2117 .set_clockgating_state = smu_set_clockgating_state,
2118 .set_powergating_state = smu_set_powergating_state,
2121 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2123 .type = AMD_IP_BLOCK_TYPE_SMC,
2127 .funcs = &smu_ip_funcs,
2130 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2132 .type = AMD_IP_BLOCK_TYPE_SMC,
2136 .funcs = &smu_ip_funcs,
2139 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2141 .type = AMD_IP_BLOCK_TYPE_SMC,
2145 .funcs = &smu_ip_funcs,
2148 static int smu_load_microcode(void *handle)
2150 struct smu_context *smu = handle;
2151 struct amdgpu_device *adev = smu->adev;
2154 if (!smu->pm_enabled)
2157 /* This should be used for non PSP loading */
2158 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2161 if (smu->ppt_funcs->load_microcode) {
2162 ret = smu->ppt_funcs->load_microcode(smu);
2164 dev_err(adev->dev, "Load microcode failed\n");
2169 if (smu->ppt_funcs->check_fw_status) {
2170 ret = smu->ppt_funcs->check_fw_status(smu);
2172 dev_err(adev->dev, "SMC is not ready\n");
2180 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2184 if (smu->ppt_funcs->set_gfx_cgpg)
2185 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2190 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2192 struct smu_context *smu = handle;
2195 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2198 if (!smu->ppt_funcs->set_fan_speed_rpm)
2201 if (speed == U32_MAX)
2204 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2205 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2206 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2207 smu->user_dpm_profile.fan_speed_rpm = speed;
2209 /* Override custom PWM setting as they cannot co-exist */
2210 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2211 smu->user_dpm_profile.fan_speed_pwm = 0;
2218 * smu_get_power_limit - Request one of the SMU Power Limits
2220 * @handle: pointer to smu context
2221 * @limit: requested limit is written back to this variable
2222 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2223 * @pp_power_type: &pp_power_type type of power
2224 * Return: 0 on success, <0 on error
2227 int smu_get_power_limit(void *handle,
2229 enum pp_power_limit_level pp_limit_level,
2230 enum pp_power_type pp_power_type)
2232 struct smu_context *smu = handle;
2233 struct amdgpu_device *adev = smu->adev;
2234 enum smu_ppt_limit_level limit_level;
2235 uint32_t limit_type;
2238 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2241 switch(pp_power_type) {
2242 case PP_PWR_TYPE_SUSTAINED:
2243 limit_type = SMU_DEFAULT_PPT_LIMIT;
2245 case PP_PWR_TYPE_FAST:
2246 limit_type = SMU_FAST_PPT_LIMIT;
2253 switch(pp_limit_level){
2254 case PP_PWR_LIMIT_CURRENT:
2255 limit_level = SMU_PPT_LIMIT_CURRENT;
2257 case PP_PWR_LIMIT_DEFAULT:
2258 limit_level = SMU_PPT_LIMIT_DEFAULT;
2260 case PP_PWR_LIMIT_MAX:
2261 limit_level = SMU_PPT_LIMIT_MAX;
2263 case PP_PWR_LIMIT_MIN:
2269 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2270 if (smu->ppt_funcs->get_ppt_limit)
2271 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2273 switch (limit_level) {
2274 case SMU_PPT_LIMIT_CURRENT:
2275 switch (adev->ip_versions[MP1_HWIP][0]) {
2276 case IP_VERSION(13, 0, 2):
2277 case IP_VERSION(11, 0, 7):
2278 case IP_VERSION(11, 0, 11):
2279 case IP_VERSION(11, 0, 12):
2280 case IP_VERSION(11, 0, 13):
2281 ret = smu_get_asic_power_limits(smu,
2282 &smu->current_power_limit,
2289 *limit = smu->current_power_limit;
2291 case SMU_PPT_LIMIT_DEFAULT:
2292 *limit = smu->default_power_limit;
2294 case SMU_PPT_LIMIT_MAX:
2295 *limit = smu->max_power_limit;
2305 static int smu_set_power_limit(void *handle, uint32_t limit)
2307 struct smu_context *smu = handle;
2308 uint32_t limit_type = limit >> 24;
2311 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2315 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2316 if (smu->ppt_funcs->set_power_limit)
2317 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2319 if (limit > smu->max_power_limit) {
2320 dev_err(smu->adev->dev,
2321 "New power limit (%d) is over the max allowed %d\n",
2322 limit, smu->max_power_limit);
2327 limit = smu->current_power_limit;
2329 if (smu->ppt_funcs->set_power_limit) {
2330 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2331 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2332 smu->user_dpm_profile.power_limit = limit;
2338 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2342 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2345 if (smu->ppt_funcs->print_clk_levels)
2346 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2351 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2353 enum smu_clk_type clk_type;
2357 clk_type = SMU_SCLK; break;
2359 clk_type = SMU_MCLK; break;
2361 clk_type = SMU_PCIE; break;
2363 clk_type = SMU_SOCCLK; break;
2365 clk_type = SMU_FCLK; break;
2367 clk_type = SMU_DCEFCLK; break;
2369 clk_type = SMU_VCLK; break;
2371 clk_type = SMU_DCLK; break;
2373 clk_type = SMU_OD_SCLK; break;
2375 clk_type = SMU_OD_MCLK; break;
2377 clk_type = SMU_OD_VDDC_CURVE; break;
2379 clk_type = SMU_OD_RANGE; break;
2380 case OD_VDDGFX_OFFSET:
2381 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2383 clk_type = SMU_OD_CCLK; break;
2385 clk_type = SMU_CLK_COUNT; break;
2391 static int smu_print_ppclk_levels(void *handle,
2392 enum pp_clock_type type,
2395 struct smu_context *smu = handle;
2396 enum smu_clk_type clk_type;
2398 clk_type = smu_convert_to_smuclk(type);
2399 if (clk_type == SMU_CLK_COUNT)
2402 return smu_print_smuclk_levels(smu, clk_type, buf);
2405 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2407 struct smu_context *smu = handle;
2408 enum smu_clk_type clk_type;
2410 clk_type = smu_convert_to_smuclk(type);
2411 if (clk_type == SMU_CLK_COUNT)
2414 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2417 if (!smu->ppt_funcs->emit_clk_levels)
2420 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2424 static int smu_od_edit_dpm_table(void *handle,
2425 enum PP_OD_DPM_TABLE_COMMAND type,
2426 long *input, uint32_t size)
2428 struct smu_context *smu = handle;
2431 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2434 if (smu->ppt_funcs->od_edit_dpm_table) {
2435 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2441 static int smu_read_sensor(void *handle,
2446 struct smu_context *smu = handle;
2447 struct smu_umd_pstate_table *pstate_table =
2450 uint32_t *size, size_val;
2452 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2455 if (!data || !size_arg)
2458 size_val = *size_arg;
2461 if (smu->ppt_funcs->read_sensor)
2462 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2466 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2467 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2470 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2471 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2474 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2475 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2478 case AMDGPU_PP_SENSOR_UVD_POWER:
2479 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2482 case AMDGPU_PP_SENSOR_VCE_POWER:
2483 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2486 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2487 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2490 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2491 *(uint32_t *)data = 0;
2501 // assign uint32_t to int
2502 *size_arg = size_val;
2507 static int smu_get_power_profile_mode(void *handle, char *buf)
2509 struct smu_context *smu = handle;
2511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2512 !smu->ppt_funcs->get_power_profile_mode)
2517 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
2520 static int smu_set_power_profile_mode(void *handle,
2522 uint32_t param_size)
2524 struct smu_context *smu = handle;
2526 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2527 !smu->ppt_funcs->set_power_profile_mode)
2530 return smu_bump_power_profile_mode(smu, param, param_size);
2533 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
2535 struct smu_context *smu = handle;
2537 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2540 if (!smu->ppt_funcs->get_fan_control_mode)
2546 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
2551 static int smu_set_fan_control_mode(void *handle, u32 value)
2553 struct smu_context *smu = handle;
2556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2559 if (!smu->ppt_funcs->set_fan_control_mode)
2562 if (value == U32_MAX)
2565 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2569 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2570 smu->user_dpm_profile.fan_mode = value;
2572 /* reset user dpm fan speed */
2573 if (value != AMD_FAN_CTRL_MANUAL) {
2574 smu->user_dpm_profile.fan_speed_pwm = 0;
2575 smu->user_dpm_profile.fan_speed_rpm = 0;
2576 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2584 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2586 struct smu_context *smu = handle;
2589 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2592 if (!smu->ppt_funcs->get_fan_speed_pwm)
2598 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2603 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2605 struct smu_context *smu = handle;
2608 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2611 if (!smu->ppt_funcs->set_fan_speed_pwm)
2614 if (speed == U32_MAX)
2617 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2618 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2619 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2620 smu->user_dpm_profile.fan_speed_pwm = speed;
2622 /* Override custom RPM setting as they cannot co-exist */
2623 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2624 smu->user_dpm_profile.fan_speed_rpm = 0;
2630 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2632 struct smu_context *smu = handle;
2635 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2638 if (!smu->ppt_funcs->get_fan_speed_rpm)
2644 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2649 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2651 struct smu_context *smu = handle;
2653 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2656 return smu_set_min_dcef_deep_sleep(smu, clk);
2659 static int smu_get_clock_by_type_with_latency(void *handle,
2660 enum amd_pp_clock_type type,
2661 struct pp_clock_levels_with_latency *clocks)
2663 struct smu_context *smu = handle;
2664 enum smu_clk_type clk_type;
2667 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2670 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2672 case amd_pp_sys_clock:
2673 clk_type = SMU_GFXCLK;
2675 case amd_pp_mem_clock:
2676 clk_type = SMU_MCLK;
2678 case amd_pp_dcef_clock:
2679 clk_type = SMU_DCEFCLK;
2681 case amd_pp_disp_clock:
2682 clk_type = SMU_DISPCLK;
2685 dev_err(smu->adev->dev, "Invalid clock type!\n");
2689 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2695 static int smu_display_clock_voltage_request(void *handle,
2696 struct pp_display_clock_request *clock_req)
2698 struct smu_context *smu = handle;
2701 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2704 if (smu->ppt_funcs->display_clock_voltage_request)
2705 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2711 static int smu_display_disable_memory_clock_switch(void *handle,
2712 bool disable_memory_clock_switch)
2714 struct smu_context *smu = handle;
2717 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2720 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2721 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2726 static int smu_set_xgmi_pstate(void *handle,
2729 struct smu_context *smu = handle;
2732 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2735 if (smu->ppt_funcs->set_xgmi_pstate)
2736 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2739 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2744 static int smu_get_baco_capability(void *handle, bool *cap)
2746 struct smu_context *smu = handle;
2750 if (!smu->pm_enabled)
2753 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2754 *cap = smu->ppt_funcs->baco_is_support(smu);
2759 static int smu_baco_set_state(void *handle, int state)
2761 struct smu_context *smu = handle;
2764 if (!smu->pm_enabled)
2768 if (smu->ppt_funcs->baco_exit)
2769 ret = smu->ppt_funcs->baco_exit(smu);
2770 } else if (state == 1) {
2771 if (smu->ppt_funcs->baco_enter)
2772 ret = smu->ppt_funcs->baco_enter(smu);
2778 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2779 (state)?"enter":"exit");
2784 bool smu_mode1_reset_is_support(struct smu_context *smu)
2788 if (!smu->pm_enabled)
2791 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2792 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2797 bool smu_mode2_reset_is_support(struct smu_context *smu)
2801 if (!smu->pm_enabled)
2804 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2805 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2810 int smu_mode1_reset(struct smu_context *smu)
2814 if (!smu->pm_enabled)
2817 if (smu->ppt_funcs->mode1_reset)
2818 ret = smu->ppt_funcs->mode1_reset(smu);
2823 static int smu_mode2_reset(void *handle)
2825 struct smu_context *smu = handle;
2828 if (!smu->pm_enabled)
2831 if (smu->ppt_funcs->mode2_reset)
2832 ret = smu->ppt_funcs->mode2_reset(smu);
2835 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2840 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2841 struct pp_smu_nv_clock_table *max_clocks)
2843 struct smu_context *smu = handle;
2846 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2849 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2850 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2855 static int smu_get_uclk_dpm_states(void *handle,
2856 unsigned int *clock_values_in_khz,
2857 unsigned int *num_states)
2859 struct smu_context *smu = handle;
2862 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2865 if (smu->ppt_funcs->get_uclk_dpm_states)
2866 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2871 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2873 struct smu_context *smu = handle;
2874 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2876 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2879 if (smu->ppt_funcs->get_current_power_state)
2880 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2885 static int smu_get_dpm_clock_table(void *handle,
2886 struct dpm_clocks *clock_table)
2888 struct smu_context *smu = handle;
2891 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2894 if (smu->ppt_funcs->get_dpm_clock_table)
2895 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2900 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2902 struct smu_context *smu = handle;
2904 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2907 if (!smu->ppt_funcs->get_gpu_metrics)
2910 return smu->ppt_funcs->get_gpu_metrics(smu, table);
2913 static int smu_enable_mgpu_fan_boost(void *handle)
2915 struct smu_context *smu = handle;
2918 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2921 if (smu->ppt_funcs->enable_mgpu_fan_boost)
2922 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2927 static int smu_gfx_state_change_set(void *handle,
2930 struct smu_context *smu = handle;
2933 if (smu->ppt_funcs->gfx_state_change_set)
2934 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
2939 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
2943 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
2944 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
2949 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
2951 int ret = -EOPNOTSUPP;
2953 if (smu->ppt_funcs &&
2954 smu->ppt_funcs->get_ecc_info)
2955 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
2961 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
2963 struct smu_context *smu = handle;
2964 struct smu_table_context *smu_table = &smu->smu_table;
2965 struct smu_table *memory_pool = &smu_table->memory_pool;
2972 if (memory_pool->bo) {
2973 *addr = memory_pool->cpu_addr;
2974 *size = memory_pool->size;
2980 static const struct amd_pm_funcs swsmu_pm_funcs = {
2981 /* export for sysfs */
2982 .set_fan_control_mode = smu_set_fan_control_mode,
2983 .get_fan_control_mode = smu_get_fan_control_mode,
2984 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
2985 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
2986 .force_clock_level = smu_force_ppclk_levels,
2987 .print_clock_levels = smu_print_ppclk_levels,
2988 .emit_clock_levels = smu_emit_ppclk_levels,
2989 .force_performance_level = smu_force_performance_level,
2990 .read_sensor = smu_read_sensor,
2991 .get_performance_level = smu_get_performance_level,
2992 .get_current_power_state = smu_get_current_power_state,
2993 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
2994 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
2995 .get_pp_num_states = smu_get_power_num_states,
2996 .get_pp_table = smu_sys_get_pp_table,
2997 .set_pp_table = smu_sys_set_pp_table,
2998 .switch_power_profile = smu_switch_power_profile,
2999 /* export to amdgpu */
3000 .dispatch_tasks = smu_handle_dpm_task,
3001 .load_firmware = smu_load_microcode,
3002 .set_powergating_by_smu = smu_dpm_set_power_gate,
3003 .set_power_limit = smu_set_power_limit,
3004 .get_power_limit = smu_get_power_limit,
3005 .get_power_profile_mode = smu_get_power_profile_mode,
3006 .set_power_profile_mode = smu_set_power_profile_mode,
3007 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3008 .set_mp1_state = smu_set_mp1_state,
3009 .gfx_state_change_set = smu_gfx_state_change_set,
3011 .get_sclk = smu_get_sclk,
3012 .get_mclk = smu_get_mclk,
3013 .display_configuration_change = smu_display_configuration_change,
3014 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3015 .display_clock_voltage_request = smu_display_clock_voltage_request,
3016 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3017 .set_active_display_count = smu_set_display_count,
3018 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3019 .get_asic_baco_capability = smu_get_baco_capability,
3020 .set_asic_baco_state = smu_baco_set_state,
3021 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3022 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3023 .asic_reset_mode_2 = smu_mode2_reset,
3024 .set_df_cstate = smu_set_df_cstate,
3025 .set_xgmi_pstate = smu_set_xgmi_pstate,
3026 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3027 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3028 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3029 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3030 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3031 .get_dpm_clock_table = smu_get_dpm_clock_table,
3032 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3035 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3040 if (smu->ppt_funcs->wait_for_event)
3041 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3046 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3049 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3052 /* Confirm the buffer allocated is of correct size */
3053 if (size != smu->stb_context.stb_buf_size)
3057 * No need to lock smu mutex as we access STB directly through MMIO
3058 * and not going through SMU messaging route (for now at least).
3059 * For registers access rely on implementation internal locking.
3061 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3064 #if defined(CONFIG_DEBUG_FS)
3066 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3068 struct amdgpu_device *adev = filp->f_inode->i_private;
3069 struct smu_context *smu = adev->powerplay.pp_handle;
3073 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3077 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3081 filp->private_data = buf;
3090 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3093 struct amdgpu_device *adev = filp->f_inode->i_private;
3094 struct smu_context *smu = adev->powerplay.pp_handle;
3097 if (!filp->private_data)
3100 return simple_read_from_buffer(buf,
3102 pos, filp->private_data,
3103 smu->stb_context.stb_buf_size);
3106 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3108 kvfree(filp->private_data);
3109 filp->private_data = NULL;
3115 * We have to define not only read method but also
3116 * open and release because .read takes up to PAGE_SIZE
3117 * data each time so and so is invoked multiple times.
3118 * We allocate the STB buffer in .open and release it
3121 static const struct file_operations smu_stb_debugfs_fops = {
3122 .owner = THIS_MODULE,
3123 .open = smu_stb_debugfs_open,
3124 .read = smu_stb_debugfs_read,
3125 .release = smu_stb_debugfs_release,
3126 .llseek = default_llseek,
3131 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3133 #if defined(CONFIG_DEBUG_FS)
3135 struct smu_context *smu = adev->powerplay.pp_handle;
3137 if (!smu || (!smu->stb_context.stb_buf_size))
3140 debugfs_create_file_size("amdgpu_smu_stb_dump",
3142 adev_to_drm(adev)->primary->debugfs_root,
3144 &smu_stb_debugfs_fops,
3145 smu->stb_context.stb_buf_size);
3149 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3153 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3154 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3159 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3163 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3164 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);