2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define SWSMU_CODE_LAYER_L1
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
29 #include "amdgpu_smu.h"
30 #include "smu_internal.h"
32 #include "arcturus_ppt.h"
33 #include "navi10_ppt.h"
34 #include "sienna_cichlid_ppt.h"
35 #include "renoir_ppt.h"
36 #include "vangogh_ppt.h"
37 #include "aldebaran_ppt.h"
38 #include "yellow_carp_ppt.h"
39 #include "cyan_skillfish_ppt.h"
40 #include "smu_v13_0_0_ppt.h"
41 #include "smu_v13_0_4_ppt.h"
42 #include "smu_v13_0_5_ppt.h"
43 #include "smu_v13_0_7_ppt.h"
47 * DO NOT use these for err/warn/info/debug messages.
48 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
49 * They are more MGPU friendly.
56 static const struct amd_pm_funcs swsmu_pm_funcs;
57 static int smu_force_smuclk_levels(struct smu_context *smu,
58 enum smu_clk_type clk_type,
60 static int smu_handle_task(struct smu_context *smu,
61 enum amd_dpm_forced_level level,
62 enum amd_pp_task task_id);
63 static int smu_reset(struct smu_context *smu);
64 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
65 static int smu_set_fan_control_mode(void *handle, u32 value);
66 static int smu_set_power_limit(void *handle, uint32_t limit);
67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
71 static int smu_sys_get_pp_feature_mask(void *handle,
74 struct smu_context *smu = handle;
76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
79 return smu_get_pp_feature_mask(smu, buf);
82 static int smu_sys_set_pp_feature_mask(void *handle,
85 struct smu_context *smu = handle;
87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
90 return smu_set_pp_feature_mask(smu, new_mask);
93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
95 if (!smu->ppt_funcs->set_gfx_off_residency)
98 return smu_set_gfx_off_residency(smu, value);
101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
103 if (!smu->ppt_funcs->get_gfx_off_residency)
106 return smu_get_gfx_off_residency(smu, value);
109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
111 if (!smu->ppt_funcs->get_gfx_off_entrycount)
114 return smu_get_gfx_off_entrycount(smu, value);
117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
119 if (!smu->ppt_funcs->get_gfx_off_status)
122 *value = smu_get_gfx_off_status(smu);
127 int smu_set_soft_freq_range(struct smu_context *smu,
128 enum smu_clk_type clk_type,
134 if (smu->ppt_funcs->set_soft_freq_limited_range)
135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
143 int smu_get_dpm_freq_range(struct smu_context *smu,
144 enum smu_clk_type clk_type,
153 if (smu->ppt_funcs->get_dpm_ultimate_freq)
154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
164 if (!smu->ppt_funcs || !smu->ppt_funcs->set_gfx_power_up_by_imu)
167 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
170 static u32 smu_get_mclk(void *handle, bool low)
172 struct smu_context *smu = handle;
176 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
177 low ? &clk_freq : NULL,
178 !low ? &clk_freq : NULL);
181 return clk_freq * 100;
184 static u32 smu_get_sclk(void *handle, bool low)
186 struct smu_context *smu = handle;
190 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
191 low ? &clk_freq : NULL,
192 !low ? &clk_freq : NULL);
195 return clk_freq * 100;
198 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
201 struct smu_power_context *smu_power = &smu->smu_power;
202 struct smu_power_gate *power_gate = &smu_power->power_gate;
205 if (!smu->ppt_funcs->dpm_set_vcn_enable)
208 if (atomic_read(&power_gate->vcn_gated) ^ enable)
211 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
213 atomic_set(&power_gate->vcn_gated, !enable);
218 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
221 struct smu_power_context *smu_power = &smu->smu_power;
222 struct smu_power_gate *power_gate = &smu_power->power_gate;
225 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
228 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
231 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
233 atomic_set(&power_gate->jpeg_gated, !enable);
239 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
241 * @handle: smu_context pointer
242 * @block_type: the IP block to power gate/ungate
243 * @gate: to power gate if true, ungate otherwise
245 * This API uses no smu->mutex lock protection due to:
246 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
247 * This is guarded to be race condition free by the caller.
248 * 2. Or get called on user setting request of power_dpm_force_performance_level.
249 * Under this case, the smu->mutex lock protection is already enforced on
250 * the parent API smu_force_performance_level of the call path.
252 static int smu_dpm_set_power_gate(void *handle,
256 struct smu_context *smu = handle;
259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
260 dev_WARN(smu->adev->dev,
261 "SMU uninitialized but power %s requested for %u!\n",
262 gate ? "gate" : "ungate", block_type);
266 switch (block_type) {
268 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
269 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
271 case AMD_IP_BLOCK_TYPE_UVD:
272 case AMD_IP_BLOCK_TYPE_VCN:
273 ret = smu_dpm_set_vcn_enable(smu, !gate);
275 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
276 gate ? "gate" : "ungate");
278 case AMD_IP_BLOCK_TYPE_GFX:
279 ret = smu_gfx_off_control(smu, gate);
281 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
282 gate ? "enable" : "disable");
284 case AMD_IP_BLOCK_TYPE_SDMA:
285 ret = smu_powergate_sdma(smu, gate);
287 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
288 gate ? "gate" : "ungate");
290 case AMD_IP_BLOCK_TYPE_JPEG:
291 ret = smu_dpm_set_jpeg_enable(smu, !gate);
293 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
294 gate ? "gate" : "ungate");
297 dev_err(smu->adev->dev, "Unsupported block type!\n");
305 * smu_set_user_clk_dependencies - set user profile clock dependencies
307 * @smu: smu_context pointer
308 * @clk: enum smu_clk_type type
310 * Enable/Disable the clock dependency for the @clk type.
312 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
314 if (smu->adev->in_suspend)
317 if (clk == SMU_MCLK) {
318 smu->user_dpm_profile.clk_dependency = 0;
319 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
320 } else if (clk == SMU_FCLK) {
321 /* MCLK takes precedence over FCLK */
322 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
325 smu->user_dpm_profile.clk_dependency = 0;
326 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
327 } else if (clk == SMU_SOCCLK) {
328 /* MCLK takes precedence over SOCCLK */
329 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
332 smu->user_dpm_profile.clk_dependency = 0;
333 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
335 /* Add clk dependencies here, if any */
340 * smu_restore_dpm_user_profile - reinstate user dpm profile
342 * @smu: smu_context pointer
344 * Restore the saved user power configurations include power limit,
345 * clock frequencies, fan control mode and fan speed.
347 static void smu_restore_dpm_user_profile(struct smu_context *smu)
349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
352 if (!smu->adev->in_suspend)
355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
358 /* Enable restore flag */
359 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
361 /* set the user dpm power limit */
362 if (smu->user_dpm_profile.power_limit) {
363 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
365 dev_err(smu->adev->dev, "Failed to set power limit value\n");
368 /* set the user dpm clock configurations */
369 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
370 enum smu_clk_type clk_type;
372 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
374 * Iterate over smu clk type and force the saved user clk
375 * configs, skip if clock dependency is enabled
377 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
378 smu->user_dpm_profile.clk_mask[clk_type]) {
379 ret = smu_force_smuclk_levels(smu, clk_type,
380 smu->user_dpm_profile.clk_mask[clk_type]);
382 dev_err(smu->adev->dev,
383 "Failed to set clock type = %d\n", clk_type);
388 /* set the user dpm fan configurations */
389 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
390 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
392 if (ret != -EOPNOTSUPP) {
393 smu->user_dpm_profile.fan_speed_pwm = 0;
394 smu->user_dpm_profile.fan_speed_rpm = 0;
395 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
396 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
399 if (smu->user_dpm_profile.fan_speed_pwm) {
400 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
401 if (ret != -EOPNOTSUPP)
402 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
405 if (smu->user_dpm_profile.fan_speed_rpm) {
406 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
407 if (ret != -EOPNOTSUPP)
408 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
412 /* Restore user customized OD settings */
413 if (smu->user_dpm_profile.user_od) {
414 if (smu->ppt_funcs->restore_user_od_settings) {
415 ret = smu->ppt_funcs->restore_user_od_settings(smu);
417 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
421 /* Disable restore flag */
422 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
425 static int smu_get_power_num_states(void *handle,
426 struct pp_states_info *state_info)
431 /* not support power state */
432 memset(state_info, 0, sizeof(struct pp_states_info));
433 state_info->nums = 1;
434 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
439 bool is_support_sw_smu(struct amdgpu_device *adev)
441 /* vega20 is 11.0.2, but it's supported via the powerplay code */
442 if (adev->asic_type == CHIP_VEGA20)
445 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
451 bool is_support_cclk_dpm(struct amdgpu_device *adev)
453 struct smu_context *smu = adev->powerplay.pp_handle;
455 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
462 static int smu_sys_get_pp_table(void *handle,
465 struct smu_context *smu = handle;
466 struct smu_table_context *smu_table = &smu->smu_table;
468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
471 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
474 if (smu_table->hardcode_pptable)
475 *table = smu_table->hardcode_pptable;
477 *table = smu_table->power_play_table;
479 return smu_table->power_play_table_size;
482 static int smu_sys_set_pp_table(void *handle,
486 struct smu_context *smu = handle;
487 struct smu_table_context *smu_table = &smu->smu_table;
488 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
494 if (header->usStructureSize != size) {
495 dev_err(smu->adev->dev, "pp table size not matched !\n");
499 if (!smu_table->hardcode_pptable) {
500 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
501 if (!smu_table->hardcode_pptable)
505 memcpy(smu_table->hardcode_pptable, buf, size);
506 smu_table->power_play_table = smu_table->hardcode_pptable;
507 smu_table->power_play_table_size = size;
510 * Special hw_fini action(for Navi1x, the DPMs disablement will be
511 * skipped) may be needed for custom pptable uploading.
513 smu->uploading_custom_pp_table = true;
515 ret = smu_reset(smu);
517 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
519 smu->uploading_custom_pp_table = false;
524 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
526 struct smu_feature *feature = &smu->smu_feature;
527 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
531 * With SCPM enabled, the allowed featuremasks setting(via
532 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
533 * That means there is no way to let PMFW knows the settings below.
534 * Thus, we just assume all the features are allowed under
537 if (smu->adev->scpm_enabled) {
538 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
542 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
544 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
549 bitmap_or(feature->allowed, feature->allowed,
550 (unsigned long *)allowed_feature_mask,
551 feature->feature_num);
556 static int smu_set_funcs(struct amdgpu_device *adev)
558 struct smu_context *smu = adev->powerplay.pp_handle;
560 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
561 smu->od_enabled = true;
563 switch (adev->ip_versions[MP1_HWIP][0]) {
564 case IP_VERSION(11, 0, 0):
565 case IP_VERSION(11, 0, 5):
566 case IP_VERSION(11, 0, 9):
567 navi10_set_ppt_funcs(smu);
569 case IP_VERSION(11, 0, 7):
570 case IP_VERSION(11, 0, 11):
571 case IP_VERSION(11, 0, 12):
572 case IP_VERSION(11, 0, 13):
573 sienna_cichlid_set_ppt_funcs(smu);
575 case IP_VERSION(12, 0, 0):
576 case IP_VERSION(12, 0, 1):
577 renoir_set_ppt_funcs(smu);
579 case IP_VERSION(11, 5, 0):
580 vangogh_set_ppt_funcs(smu);
582 case IP_VERSION(13, 0, 1):
583 case IP_VERSION(13, 0, 3):
584 case IP_VERSION(13, 0, 8):
585 yellow_carp_set_ppt_funcs(smu);
587 case IP_VERSION(13, 0, 4):
588 case IP_VERSION(13, 0, 11):
589 smu_v13_0_4_set_ppt_funcs(smu);
591 case IP_VERSION(13, 0, 5):
592 smu_v13_0_5_set_ppt_funcs(smu);
594 case IP_VERSION(11, 0, 8):
595 cyan_skillfish_set_ppt_funcs(smu);
597 case IP_VERSION(11, 0, 2):
598 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
599 arcturus_set_ppt_funcs(smu);
600 /* OD is not supported on Arcturus */
601 smu->od_enabled =false;
603 case IP_VERSION(13, 0, 2):
604 aldebaran_set_ppt_funcs(smu);
605 /* Enable pp_od_clk_voltage node */
606 smu->od_enabled = true;
608 case IP_VERSION(13, 0, 0):
609 case IP_VERSION(13, 0, 10):
610 smu_v13_0_0_set_ppt_funcs(smu);
612 case IP_VERSION(13, 0, 7):
613 smu_v13_0_7_set_ppt_funcs(smu);
622 static int smu_early_init(void *handle)
624 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
625 struct smu_context *smu;
627 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
632 smu->pm_enabled = !!amdgpu_dpm;
634 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
635 smu->smu_baco.platform_support = false;
636 smu->user_dpm_profile.fan_mode = -1;
638 mutex_init(&smu->message_lock);
640 adev->powerplay.pp_handle = smu;
641 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
643 return smu_set_funcs(adev);
646 static int smu_set_default_dpm_table(struct smu_context *smu)
648 struct smu_power_context *smu_power = &smu->smu_power;
649 struct smu_power_gate *power_gate = &smu_power->power_gate;
650 int vcn_gate, jpeg_gate;
653 if (!smu->ppt_funcs->set_default_dpm_table)
656 vcn_gate = atomic_read(&power_gate->vcn_gated);
657 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
659 ret = smu_dpm_set_vcn_enable(smu, true);
663 ret = smu_dpm_set_jpeg_enable(smu, true);
667 ret = smu->ppt_funcs->set_default_dpm_table(smu);
669 dev_err(smu->adev->dev,
670 "Failed to setup default dpm clock tables!\n");
672 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
674 smu_dpm_set_vcn_enable(smu, !vcn_gate);
678 static int smu_apply_default_config_table_settings(struct smu_context *smu)
680 struct amdgpu_device *adev = smu->adev;
683 ret = smu_get_default_config_table_settings(smu,
684 &adev->pm.config_table);
688 return smu_set_config_table(smu, &adev->pm.config_table);
691 static int smu_late_init(void *handle)
693 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
694 struct smu_context *smu = adev->powerplay.pp_handle;
697 smu_set_fine_grain_gfx_freq_parameters(smu);
699 if (!smu->pm_enabled)
702 ret = smu_post_init(smu);
704 dev_err(adev->dev, "Failed to post smu init!\n");
708 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
709 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
712 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
713 ret = smu_set_default_od_settings(smu);
715 dev_err(adev->dev, "Failed to setup default OD settings!\n");
720 ret = smu_populate_umd_state_clk(smu);
722 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
726 ret = smu_get_asic_power_limits(smu,
727 &smu->current_power_limit,
728 &smu->default_power_limit,
729 &smu->max_power_limit);
731 dev_err(adev->dev, "Failed to get asic power limits!\n");
735 if (!amdgpu_sriov_vf(adev))
736 smu_get_unique_id(smu);
738 smu_get_fan_parameters(smu);
741 smu->smu_dpm.dpm_level,
742 AMD_PP_TASK_COMPLETE_INIT);
744 ret = smu_apply_default_config_table_settings(smu);
745 if (ret && (ret != -EOPNOTSUPP)) {
746 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
750 smu_restore_dpm_user_profile(smu);
755 static int smu_init_fb_allocations(struct smu_context *smu)
757 struct amdgpu_device *adev = smu->adev;
758 struct smu_table_context *smu_table = &smu->smu_table;
759 struct smu_table *tables = smu_table->tables;
760 struct smu_table *driver_table = &(smu_table->driver_table);
761 uint32_t max_table_size = 0;
764 /* VRAM allocation for tool table */
765 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
766 ret = amdgpu_bo_create_kernel(adev,
767 tables[SMU_TABLE_PMSTATUSLOG].size,
768 tables[SMU_TABLE_PMSTATUSLOG].align,
769 tables[SMU_TABLE_PMSTATUSLOG].domain,
770 &tables[SMU_TABLE_PMSTATUSLOG].bo,
771 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
772 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
774 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
779 /* VRAM allocation for driver table */
780 for (i = 0; i < SMU_TABLE_COUNT; i++) {
781 if (tables[i].size == 0)
784 if (i == SMU_TABLE_PMSTATUSLOG)
787 if (max_table_size < tables[i].size)
788 max_table_size = tables[i].size;
791 driver_table->size = max_table_size;
792 driver_table->align = PAGE_SIZE;
793 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
795 ret = amdgpu_bo_create_kernel(adev,
798 driver_table->domain,
800 &driver_table->mc_address,
801 &driver_table->cpu_addr);
803 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
804 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
805 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
806 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
807 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
813 static int smu_fini_fb_allocations(struct smu_context *smu)
815 struct smu_table_context *smu_table = &smu->smu_table;
816 struct smu_table *tables = smu_table->tables;
817 struct smu_table *driver_table = &(smu_table->driver_table);
819 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
820 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
821 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
822 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
824 amdgpu_bo_free_kernel(&driver_table->bo,
825 &driver_table->mc_address,
826 &driver_table->cpu_addr);
832 * smu_alloc_memory_pool - allocate memory pool in the system memory
834 * @smu: amdgpu_device pointer
836 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
837 * and DramLogSetDramAddr can notify it changed.
839 * Returns 0 on success, error on failure.
841 static int smu_alloc_memory_pool(struct smu_context *smu)
843 struct amdgpu_device *adev = smu->adev;
844 struct smu_table_context *smu_table = &smu->smu_table;
845 struct smu_table *memory_pool = &smu_table->memory_pool;
846 uint64_t pool_size = smu->pool_size;
849 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
852 memory_pool->size = pool_size;
853 memory_pool->align = PAGE_SIZE;
854 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
857 case SMU_MEMORY_POOL_SIZE_256_MB:
858 case SMU_MEMORY_POOL_SIZE_512_MB:
859 case SMU_MEMORY_POOL_SIZE_1_GB:
860 case SMU_MEMORY_POOL_SIZE_2_GB:
861 ret = amdgpu_bo_create_kernel(adev,
866 &memory_pool->mc_address,
867 &memory_pool->cpu_addr);
869 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
878 static int smu_free_memory_pool(struct smu_context *smu)
880 struct smu_table_context *smu_table = &smu->smu_table;
881 struct smu_table *memory_pool = &smu_table->memory_pool;
883 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
886 amdgpu_bo_free_kernel(&memory_pool->bo,
887 &memory_pool->mc_address,
888 &memory_pool->cpu_addr);
890 memset(memory_pool, 0, sizeof(struct smu_table));
895 static int smu_alloc_dummy_read_table(struct smu_context *smu)
897 struct smu_table_context *smu_table = &smu->smu_table;
898 struct smu_table *dummy_read_1_table =
899 &smu_table->dummy_read_1_table;
900 struct amdgpu_device *adev = smu->adev;
903 dummy_read_1_table->size = 0x40000;
904 dummy_read_1_table->align = PAGE_SIZE;
905 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
907 ret = amdgpu_bo_create_kernel(adev,
908 dummy_read_1_table->size,
909 dummy_read_1_table->align,
910 dummy_read_1_table->domain,
911 &dummy_read_1_table->bo,
912 &dummy_read_1_table->mc_address,
913 &dummy_read_1_table->cpu_addr);
915 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
920 static void smu_free_dummy_read_table(struct smu_context *smu)
922 struct smu_table_context *smu_table = &smu->smu_table;
923 struct smu_table *dummy_read_1_table =
924 &smu_table->dummy_read_1_table;
927 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
928 &dummy_read_1_table->mc_address,
929 &dummy_read_1_table->cpu_addr);
931 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
934 static int smu_smc_table_sw_init(struct smu_context *smu)
939 * Create smu_table structure, and init smc tables such as
940 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
942 ret = smu_init_smc_tables(smu);
944 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
949 * Create smu_power_context structure, and allocate smu_dpm_context and
950 * context size to fill the smu_power_context data.
952 ret = smu_init_power(smu);
954 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
959 * allocate vram bos to store smc table contents.
961 ret = smu_init_fb_allocations(smu);
965 ret = smu_alloc_memory_pool(smu);
969 ret = smu_alloc_dummy_read_table(smu);
973 ret = smu_i2c_init(smu);
980 static int smu_smc_table_sw_fini(struct smu_context *smu)
986 smu_free_dummy_read_table(smu);
988 ret = smu_free_memory_pool(smu);
992 ret = smu_fini_fb_allocations(smu);
996 ret = smu_fini_power(smu);
998 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1002 ret = smu_fini_smc_tables(smu);
1004 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1011 static void smu_throttling_logging_work_fn(struct work_struct *work)
1013 struct smu_context *smu = container_of(work, struct smu_context,
1014 throttling_logging_work);
1016 smu_log_thermal_throttling(smu);
1019 static void smu_interrupt_work_fn(struct work_struct *work)
1021 struct smu_context *smu = container_of(work, struct smu_context,
1024 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1025 smu->ppt_funcs->interrupt_work(smu);
1028 static int smu_sw_init(void *handle)
1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031 struct smu_context *smu = adev->powerplay.pp_handle;
1034 smu->pool_size = adev->pm.smu_prv_buffer_size;
1035 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1036 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1037 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1039 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1040 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1041 atomic64_set(&smu->throttle_int_counter, 0);
1042 smu->watermarks_bitmap = 0;
1043 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1044 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1046 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1047 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1049 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1050 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1051 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1052 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1053 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1054 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1055 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1056 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1058 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1059 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1060 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1061 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1062 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1063 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1064 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1065 smu->display_config = &adev->pm.pm_display_cfg;
1067 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1068 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1070 ret = smu_init_microcode(smu);
1072 dev_err(adev->dev, "Failed to load smu firmware!\n");
1076 ret = smu_smc_table_sw_init(smu);
1078 dev_err(adev->dev, "Failed to sw init smc table!\n");
1082 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1083 ret = smu_get_vbios_bootup_values(smu);
1085 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1089 ret = smu_init_pptable_microcode(smu);
1091 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1095 ret = smu_register_irq_handler(smu);
1097 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1101 /* If there is no way to query fan control mode, fan control is not supported */
1102 if (!smu->ppt_funcs->get_fan_control_mode)
1103 smu->adev->pm.no_fan = true;
1108 static int smu_sw_fini(void *handle)
1110 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111 struct smu_context *smu = adev->powerplay.pp_handle;
1114 ret = smu_smc_table_sw_fini(smu);
1116 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1120 smu_fini_microcode(smu);
1125 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1127 struct amdgpu_device *adev = smu->adev;
1128 struct smu_temperature_range *range =
1129 &smu->thermal_range;
1132 if (!smu->ppt_funcs->get_thermal_temperature_range)
1135 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1139 adev->pm.dpm.thermal.min_temp = range->min;
1140 adev->pm.dpm.thermal.max_temp = range->max;
1141 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1142 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1143 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1144 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1145 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1146 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1147 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1152 static int smu_smc_hw_setup(struct smu_context *smu)
1154 struct smu_feature *feature = &smu->smu_feature;
1155 struct amdgpu_device *adev = smu->adev;
1156 uint32_t pcie_gen = 0, pcie_width = 0;
1157 uint64_t features_supported;
1160 switch (adev->ip_versions[MP1_HWIP][0]) {
1161 case IP_VERSION(11, 0, 7):
1162 case IP_VERSION(11, 0, 11):
1163 case IP_VERSION(11, 5, 0):
1164 case IP_VERSION(11, 0, 12):
1165 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1166 dev_info(adev->dev, "dpm has been enabled\n");
1167 ret = smu_system_features_control(smu, true);
1169 dev_err(adev->dev, "Failed system features control!\n");
1177 ret = smu_init_display_count(smu, 0);
1179 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1183 ret = smu_set_driver_table_location(smu);
1185 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1190 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1192 ret = smu_set_tool_table_location(smu);
1194 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1199 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1202 ret = smu_notify_memory_pool_location(smu);
1204 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1208 ret = smu_setup_pptable(smu);
1210 dev_err(adev->dev, "Failed to setup pptable!\n");
1214 /* smu_dump_pptable(smu); */
1217 * With SCPM enabled, PSP is responsible for the PPTable transferring
1218 * (to SMU). Driver involvement is not needed and permitted.
1220 if (!adev->scpm_enabled) {
1222 * Copy pptable bo in the vram to smc with SMU MSGs such as
1223 * SetDriverDramAddr and TransferTableDram2Smu.
1225 ret = smu_write_pptable(smu);
1227 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1232 /* issue Run*Btc msg */
1233 ret = smu_run_btc(smu);
1238 * With SCPM enabled, these actions(and relevant messages) are
1239 * not needed and permitted.
1241 if (!adev->scpm_enabled) {
1242 ret = smu_feature_set_allowed_mask(smu);
1244 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1249 ret = smu_system_features_control(smu, true);
1251 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1255 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1257 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1260 bitmap_copy(feature->supported,
1261 (unsigned long *)&features_supported,
1262 feature->feature_num);
1264 if (!smu_is_dpm_running(smu))
1265 dev_info(adev->dev, "dpm has been disabled\n");
1268 * Set initialized values (get from vbios) to dpm tables context such as
1269 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1272 ret = smu_set_default_dpm_table(smu);
1274 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1278 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1280 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1282 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1284 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1287 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1288 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1289 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1291 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1293 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1295 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1297 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1299 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1301 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1303 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1305 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1309 ret = smu_get_thermal_temperature_range(smu);
1311 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1315 ret = smu_enable_thermal_alert(smu);
1317 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1321 ret = smu_notify_display_change(smu);
1323 dev_err(adev->dev, "Failed to notify display change!\n");
1328 * Set min deep sleep dce fclk with bootup value from vbios via
1329 * SetMinDeepSleepDcefclk MSG.
1331 ret = smu_set_min_dcef_deep_sleep(smu,
1332 smu->smu_table.boot_values.dcefclk / 100);
1337 static int smu_start_smc_engine(struct smu_context *smu)
1339 struct amdgpu_device *adev = smu->adev;
1342 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1343 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1344 if (smu->ppt_funcs->load_microcode) {
1345 ret = smu->ppt_funcs->load_microcode(smu);
1352 if (smu->ppt_funcs->check_fw_status) {
1353 ret = smu->ppt_funcs->check_fw_status(smu);
1355 dev_err(adev->dev, "SMC is not ready\n");
1361 * Send msg GetDriverIfVersion to check if the return value is equal
1362 * with DRIVER_IF_VERSION of smc header.
1364 ret = smu_check_fw_version(smu);
1371 static int smu_hw_init(void *handle)
1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375 struct smu_context *smu = adev->powerplay.pp_handle;
1377 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1378 smu->pm_enabled = false;
1382 ret = smu_start_smc_engine(smu);
1384 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1389 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
1390 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1391 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
1393 dev_err(adev->dev, "Failed to Enable gfx imu!\n");
1398 smu_dpm_set_vcn_enable(smu, true);
1399 smu_dpm_set_jpeg_enable(smu, true);
1400 smu_set_gfx_cgpg(smu, true);
1403 if (!smu->pm_enabled)
1406 ret = smu_get_driver_allowed_feature_mask(smu);
1410 ret = smu_smc_hw_setup(smu);
1412 dev_err(adev->dev, "Failed to setup smc hw!\n");
1417 * Move maximum sustainable clock retrieving here considering
1418 * 1. It is not needed on resume(from S3).
1419 * 2. DAL settings come between .hw_init and .late_init of SMU.
1420 * And DAL needs to know the maximum sustainable clocks. Thus
1421 * it cannot be put in .late_init().
1423 ret = smu_init_max_sustainable_clocks(smu);
1425 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1429 adev->pm.dpm_enabled = true;
1431 dev_info(adev->dev, "SMU is initialized successfully!\n");
1436 static int smu_disable_dpms(struct smu_context *smu)
1438 struct amdgpu_device *adev = smu->adev;
1440 bool use_baco = !smu->is_apu &&
1441 ((amdgpu_in_reset(adev) &&
1442 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1443 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1446 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1447 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1449 switch (adev->ip_versions[MP1_HWIP][0]) {
1450 case IP_VERSION(13, 0, 0):
1451 case IP_VERSION(13, 0, 7):
1452 case IP_VERSION(13, 0, 10):
1459 * For custom pptable uploading, skip the DPM features
1460 * disable process on Navi1x ASICs.
1461 * - As the gfx related features are under control of
1462 * RLC on those ASICs. RLC reinitialization will be
1463 * needed to reenable them. That will cost much more
1466 * - SMU firmware can handle the DPM reenablement
1469 if (smu->uploading_custom_pp_table) {
1470 switch (adev->ip_versions[MP1_HWIP][0]) {
1471 case IP_VERSION(11, 0, 0):
1472 case IP_VERSION(11, 0, 5):
1473 case IP_VERSION(11, 0, 9):
1474 case IP_VERSION(11, 0, 7):
1475 case IP_VERSION(11, 0, 11):
1476 case IP_VERSION(11, 5, 0):
1477 case IP_VERSION(11, 0, 12):
1478 case IP_VERSION(11, 0, 13):
1486 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1487 * on BACO in. Driver involvement is unnecessary.
1490 switch (adev->ip_versions[MP1_HWIP][0]) {
1491 case IP_VERSION(11, 0, 7):
1492 case IP_VERSION(11, 0, 0):
1493 case IP_VERSION(11, 0, 5):
1494 case IP_VERSION(11, 0, 9):
1495 case IP_VERSION(13, 0, 7):
1503 * For gpu reset, runpm and hibernation through BACO,
1504 * BACO feature has to be kept enabled.
1506 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1507 ret = smu_disable_all_features_with_exception(smu,
1508 SMU_FEATURE_BACO_BIT);
1510 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1512 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1513 if (!adev->scpm_enabled) {
1514 ret = smu_system_features_control(smu, false);
1516 dev_err(adev->dev, "Failed to disable smu features.\n");
1520 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1521 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
1522 adev->gfx.rlc.funcs->stop(adev);
1527 static int smu_smc_hw_cleanup(struct smu_context *smu)
1529 struct amdgpu_device *adev = smu->adev;
1532 cancel_work_sync(&smu->throttling_logging_work);
1533 cancel_work_sync(&smu->interrupt_work);
1535 ret = smu_disable_thermal_alert(smu);
1537 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1541 ret = smu_disable_dpms(smu);
1543 dev_err(adev->dev, "Fail to disable dpm features!\n");
1550 static int smu_hw_fini(void *handle)
1552 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1553 struct smu_context *smu = adev->powerplay.pp_handle;
1555 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1558 smu_dpm_set_vcn_enable(smu, false);
1559 smu_dpm_set_jpeg_enable(smu, false);
1561 adev->vcn.cur_state = AMD_PG_STATE_GATE;
1562 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1564 if (!smu->pm_enabled)
1567 adev->pm.dpm_enabled = false;
1569 return smu_smc_hw_cleanup(smu);
1572 static void smu_late_fini(void *handle)
1574 struct amdgpu_device *adev = handle;
1575 struct smu_context *smu = adev->powerplay.pp_handle;
1580 static int smu_reset(struct smu_context *smu)
1582 struct amdgpu_device *adev = smu->adev;
1585 ret = smu_hw_fini(adev);
1589 ret = smu_hw_init(adev);
1593 ret = smu_late_init(adev);
1600 static int smu_suspend(void *handle)
1602 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1603 struct smu_context *smu = adev->powerplay.pp_handle;
1607 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1610 if (!smu->pm_enabled)
1613 adev->pm.dpm_enabled = false;
1615 ret = smu_smc_hw_cleanup(smu);
1619 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1621 smu_set_gfx_cgpg(smu, false);
1624 * pwfw resets entrycount when device is suspended, so we save the
1625 * last value to be used when we resume to keep it consistent
1627 ret = smu_get_entrycount_gfxoff(smu, &count);
1629 adev->gfx.gfx_off_entrycount = count;
1634 static int smu_resume(void *handle)
1637 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1638 struct smu_context *smu = adev->powerplay.pp_handle;
1640 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1643 if (!smu->pm_enabled)
1646 dev_info(adev->dev, "SMU is resuming...\n");
1648 ret = smu_start_smc_engine(smu);
1650 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1654 ret = smu_smc_hw_setup(smu);
1656 dev_err(adev->dev, "Failed to setup smc hw!\n");
1660 smu_set_gfx_cgpg(smu, true);
1662 smu->disable_uclk_switch = 0;
1664 adev->pm.dpm_enabled = true;
1666 dev_info(adev->dev, "SMU is resumed successfully!\n");
1671 static int smu_display_configuration_change(void *handle,
1672 const struct amd_pp_display_configuration *display_config)
1674 struct smu_context *smu = handle;
1676 int num_of_active_display = 0;
1678 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1681 if (!display_config)
1684 smu_set_min_dcef_deep_sleep(smu,
1685 display_config->min_dcef_deep_sleep_set_clk / 100);
1687 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1688 if (display_config->displays[index].controller_id != 0)
1689 num_of_active_display++;
1695 static int smu_set_clockgating_state(void *handle,
1696 enum amd_clockgating_state state)
1701 static int smu_set_powergating_state(void *handle,
1702 enum amd_powergating_state state)
1707 static int smu_enable_umd_pstate(void *handle,
1708 enum amd_dpm_forced_level *level)
1710 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1711 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1712 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1713 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1715 struct smu_context *smu = (struct smu_context*)(handle);
1716 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1718 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1721 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1722 /* enter umd pstate, save current level, disable gfx cg*/
1723 if (*level & profile_mode_mask) {
1724 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1725 smu_gpo_control(smu, false);
1726 smu_gfx_ulv_control(smu, false);
1727 smu_deep_sleep_control(smu, false);
1728 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1731 /* exit umd pstate, restore level, enable gfx cg*/
1732 if (!(*level & profile_mode_mask)) {
1733 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1734 *level = smu_dpm_ctx->saved_dpm_level;
1735 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1736 smu_deep_sleep_control(smu, true);
1737 smu_gfx_ulv_control(smu, true);
1738 smu_gpo_control(smu, true);
1745 static int smu_bump_power_profile_mode(struct smu_context *smu,
1747 uint32_t param_size)
1751 if (smu->ppt_funcs->set_power_profile_mode)
1752 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1757 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1758 enum amd_dpm_forced_level level,
1759 bool skip_display_settings)
1764 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1766 if (!skip_display_settings) {
1767 ret = smu_display_config_changed(smu);
1769 dev_err(smu->adev->dev, "Failed to change display config!");
1774 ret = smu_apply_clocks_adjust_rules(smu);
1776 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1780 if (!skip_display_settings) {
1781 ret = smu_notify_smc_display_config(smu);
1783 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1788 if (smu_dpm_ctx->dpm_level != level) {
1789 ret = smu_asic_set_performance_level(smu, level);
1791 dev_err(smu->adev->dev, "Failed to set performance level!");
1795 /* update the saved copy */
1796 smu_dpm_ctx->dpm_level = level;
1799 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1800 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1801 index = fls(smu->workload_mask);
1802 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1803 workload = smu->workload_setting[index];
1805 if (smu->power_profile_mode != workload)
1806 smu_bump_power_profile_mode(smu, &workload, 0);
1812 static int smu_handle_task(struct smu_context *smu,
1813 enum amd_dpm_forced_level level,
1814 enum amd_pp_task task_id)
1818 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1822 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1823 ret = smu_pre_display_config_changed(smu);
1826 ret = smu_adjust_power_state_dynamic(smu, level, false);
1828 case AMD_PP_TASK_COMPLETE_INIT:
1829 case AMD_PP_TASK_READJUST_POWER_STATE:
1830 ret = smu_adjust_power_state_dynamic(smu, level, true);
1839 static int smu_handle_dpm_task(void *handle,
1840 enum amd_pp_task task_id,
1841 enum amd_pm_state_type *user_state)
1843 struct smu_context *smu = handle;
1844 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1846 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
1850 static int smu_switch_power_profile(void *handle,
1851 enum PP_SMC_POWER_PROFILE type,
1854 struct smu_context *smu = handle;
1855 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1859 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1862 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1866 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1867 index = fls(smu->workload_mask);
1868 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1869 workload = smu->workload_setting[index];
1871 smu->workload_mask |= (1 << smu->workload_prority[type]);
1872 index = fls(smu->workload_mask);
1873 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1874 workload = smu->workload_setting[index];
1877 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1878 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1879 smu_bump_power_profile_mode(smu, &workload, 0);
1884 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1886 struct smu_context *smu = handle;
1887 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1889 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1892 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1895 return smu_dpm_ctx->dpm_level;
1898 static int smu_force_performance_level(void *handle,
1899 enum amd_dpm_forced_level level)
1901 struct smu_context *smu = handle;
1902 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1905 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1908 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1911 ret = smu_enable_umd_pstate(smu, &level);
1915 ret = smu_handle_task(smu, level,
1916 AMD_PP_TASK_READJUST_POWER_STATE);
1918 /* reset user dpm clock state */
1919 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1920 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1921 smu->user_dpm_profile.clk_dependency = 0;
1927 static int smu_set_display_count(void *handle, uint32_t count)
1929 struct smu_context *smu = handle;
1931 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1934 return smu_init_display_count(smu, count);
1937 static int smu_force_smuclk_levels(struct smu_context *smu,
1938 enum smu_clk_type clk_type,
1941 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1944 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1947 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1948 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1952 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1953 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1954 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1955 smu->user_dpm_profile.clk_mask[clk_type] = mask;
1956 smu_set_user_clk_dependencies(smu, clk_type);
1963 static int smu_force_ppclk_levels(void *handle,
1964 enum pp_clock_type type,
1967 struct smu_context *smu = handle;
1968 enum smu_clk_type clk_type;
1972 clk_type = SMU_SCLK; break;
1974 clk_type = SMU_MCLK; break;
1976 clk_type = SMU_PCIE; break;
1978 clk_type = SMU_SOCCLK; break;
1980 clk_type = SMU_FCLK; break;
1982 clk_type = SMU_DCEFCLK; break;
1984 clk_type = SMU_VCLK; break;
1986 clk_type = SMU_DCLK; break;
1988 clk_type = SMU_OD_SCLK; break;
1990 clk_type = SMU_OD_MCLK; break;
1992 clk_type = SMU_OD_VDDC_CURVE; break;
1994 clk_type = SMU_OD_RANGE; break;
1999 return smu_force_smuclk_levels(smu, clk_type, mask);
2003 * On system suspending or resetting, the dpm_enabled
2004 * flag will be cleared. So that those SMU services which
2005 * are not supported will be gated.
2006 * However, the mp1 state setting should still be granted
2007 * even if the dpm_enabled cleared.
2009 static int smu_set_mp1_state(void *handle,
2010 enum pp_mp1_state mp1_state)
2012 struct smu_context *smu = handle;
2015 if (!smu->pm_enabled)
2018 if (smu->ppt_funcs &&
2019 smu->ppt_funcs->set_mp1_state)
2020 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2025 static int smu_set_df_cstate(void *handle,
2026 enum pp_df_cstate state)
2028 struct smu_context *smu = handle;
2031 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2034 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2037 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2039 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2044 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2048 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2051 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2054 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2056 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2061 int smu_write_watermarks_table(struct smu_context *smu)
2063 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2066 return smu_set_watermarks_table(smu, NULL);
2069 static int smu_set_watermarks_for_clock_ranges(void *handle,
2070 struct pp_smu_wm_range_sets *clock_ranges)
2072 struct smu_context *smu = handle;
2074 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2077 if (smu->disable_watermark)
2080 return smu_set_watermarks_table(smu, clock_ranges);
2083 int smu_set_ac_dc(struct smu_context *smu)
2087 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2090 /* controlled by firmware */
2091 if (smu->dc_controlled_by_gpio)
2094 ret = smu_set_power_source(smu,
2095 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2096 SMU_POWER_SOURCE_DC);
2098 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2099 smu->adev->pm.ac_power ? "AC" : "DC");
2104 const struct amd_ip_funcs smu_ip_funcs = {
2106 .early_init = smu_early_init,
2107 .late_init = smu_late_init,
2108 .sw_init = smu_sw_init,
2109 .sw_fini = smu_sw_fini,
2110 .hw_init = smu_hw_init,
2111 .hw_fini = smu_hw_fini,
2112 .late_fini = smu_late_fini,
2113 .suspend = smu_suspend,
2114 .resume = smu_resume,
2116 .check_soft_reset = NULL,
2117 .wait_for_idle = NULL,
2119 .set_clockgating_state = smu_set_clockgating_state,
2120 .set_powergating_state = smu_set_powergating_state,
2123 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2125 .type = AMD_IP_BLOCK_TYPE_SMC,
2129 .funcs = &smu_ip_funcs,
2132 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2134 .type = AMD_IP_BLOCK_TYPE_SMC,
2138 .funcs = &smu_ip_funcs,
2141 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2143 .type = AMD_IP_BLOCK_TYPE_SMC,
2147 .funcs = &smu_ip_funcs,
2150 static int smu_load_microcode(void *handle)
2152 struct smu_context *smu = handle;
2153 struct amdgpu_device *adev = smu->adev;
2156 if (!smu->pm_enabled)
2159 /* This should be used for non PSP loading */
2160 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2163 if (smu->ppt_funcs->load_microcode) {
2164 ret = smu->ppt_funcs->load_microcode(smu);
2166 dev_err(adev->dev, "Load microcode failed\n");
2171 if (smu->ppt_funcs->check_fw_status) {
2172 ret = smu->ppt_funcs->check_fw_status(smu);
2174 dev_err(adev->dev, "SMC is not ready\n");
2182 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2186 if (smu->ppt_funcs->set_gfx_cgpg)
2187 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2192 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2194 struct smu_context *smu = handle;
2197 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2200 if (!smu->ppt_funcs->set_fan_speed_rpm)
2203 if (speed == U32_MAX)
2206 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2207 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2208 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2209 smu->user_dpm_profile.fan_speed_rpm = speed;
2211 /* Override custom PWM setting as they cannot co-exist */
2212 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2213 smu->user_dpm_profile.fan_speed_pwm = 0;
2220 * smu_get_power_limit - Request one of the SMU Power Limits
2222 * @handle: pointer to smu context
2223 * @limit: requested limit is written back to this variable
2224 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2225 * @pp_power_type: &pp_power_type type of power
2226 * Return: 0 on success, <0 on error
2229 int smu_get_power_limit(void *handle,
2231 enum pp_power_limit_level pp_limit_level,
2232 enum pp_power_type pp_power_type)
2234 struct smu_context *smu = handle;
2235 struct amdgpu_device *adev = smu->adev;
2236 enum smu_ppt_limit_level limit_level;
2237 uint32_t limit_type;
2240 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2243 switch(pp_power_type) {
2244 case PP_PWR_TYPE_SUSTAINED:
2245 limit_type = SMU_DEFAULT_PPT_LIMIT;
2247 case PP_PWR_TYPE_FAST:
2248 limit_type = SMU_FAST_PPT_LIMIT;
2255 switch(pp_limit_level){
2256 case PP_PWR_LIMIT_CURRENT:
2257 limit_level = SMU_PPT_LIMIT_CURRENT;
2259 case PP_PWR_LIMIT_DEFAULT:
2260 limit_level = SMU_PPT_LIMIT_DEFAULT;
2262 case PP_PWR_LIMIT_MAX:
2263 limit_level = SMU_PPT_LIMIT_MAX;
2265 case PP_PWR_LIMIT_MIN:
2271 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2272 if (smu->ppt_funcs->get_ppt_limit)
2273 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2275 switch (limit_level) {
2276 case SMU_PPT_LIMIT_CURRENT:
2277 switch (adev->ip_versions[MP1_HWIP][0]) {
2278 case IP_VERSION(13, 0, 2):
2279 case IP_VERSION(11, 0, 7):
2280 case IP_VERSION(11, 0, 11):
2281 case IP_VERSION(11, 0, 12):
2282 case IP_VERSION(11, 0, 13):
2283 ret = smu_get_asic_power_limits(smu,
2284 &smu->current_power_limit,
2291 *limit = smu->current_power_limit;
2293 case SMU_PPT_LIMIT_DEFAULT:
2294 *limit = smu->default_power_limit;
2296 case SMU_PPT_LIMIT_MAX:
2297 *limit = smu->max_power_limit;
2307 static int smu_set_power_limit(void *handle, uint32_t limit)
2309 struct smu_context *smu = handle;
2310 uint32_t limit_type = limit >> 24;
2313 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2317 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2318 if (smu->ppt_funcs->set_power_limit)
2319 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2321 if (limit > smu->max_power_limit) {
2322 dev_err(smu->adev->dev,
2323 "New power limit (%d) is over the max allowed %d\n",
2324 limit, smu->max_power_limit);
2329 limit = smu->current_power_limit;
2331 if (smu->ppt_funcs->set_power_limit) {
2332 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2333 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2334 smu->user_dpm_profile.power_limit = limit;
2340 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2344 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2347 if (smu->ppt_funcs->print_clk_levels)
2348 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2353 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2355 enum smu_clk_type clk_type;
2359 clk_type = SMU_SCLK; break;
2361 clk_type = SMU_MCLK; break;
2363 clk_type = SMU_PCIE; break;
2365 clk_type = SMU_SOCCLK; break;
2367 clk_type = SMU_FCLK; break;
2369 clk_type = SMU_DCEFCLK; break;
2371 clk_type = SMU_VCLK; break;
2373 clk_type = SMU_DCLK; break;
2375 clk_type = SMU_OD_SCLK; break;
2377 clk_type = SMU_OD_MCLK; break;
2379 clk_type = SMU_OD_VDDC_CURVE; break;
2381 clk_type = SMU_OD_RANGE; break;
2382 case OD_VDDGFX_OFFSET:
2383 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2385 clk_type = SMU_OD_CCLK; break;
2387 clk_type = SMU_CLK_COUNT; break;
2393 static int smu_print_ppclk_levels(void *handle,
2394 enum pp_clock_type type,
2397 struct smu_context *smu = handle;
2398 enum smu_clk_type clk_type;
2400 clk_type = smu_convert_to_smuclk(type);
2401 if (clk_type == SMU_CLK_COUNT)
2404 return smu_print_smuclk_levels(smu, clk_type, buf);
2407 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2409 struct smu_context *smu = handle;
2410 enum smu_clk_type clk_type;
2412 clk_type = smu_convert_to_smuclk(type);
2413 if (clk_type == SMU_CLK_COUNT)
2416 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2419 if (!smu->ppt_funcs->emit_clk_levels)
2422 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2426 static int smu_od_edit_dpm_table(void *handle,
2427 enum PP_OD_DPM_TABLE_COMMAND type,
2428 long *input, uint32_t size)
2430 struct smu_context *smu = handle;
2433 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2436 if (smu->ppt_funcs->od_edit_dpm_table) {
2437 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2443 static int smu_read_sensor(void *handle,
2448 struct smu_context *smu = handle;
2449 struct smu_umd_pstate_table *pstate_table =
2452 uint32_t *size, size_val;
2454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2457 if (!data || !size_arg)
2460 size_val = *size_arg;
2463 if (smu->ppt_funcs->read_sensor)
2464 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2468 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2469 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2472 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2473 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2476 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2477 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2480 case AMDGPU_PP_SENSOR_UVD_POWER:
2481 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2484 case AMDGPU_PP_SENSOR_VCE_POWER:
2485 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2488 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2489 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2492 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2493 *(uint32_t *)data = 0;
2503 // assign uint32_t to int
2504 *size_arg = size_val;
2509 static int smu_get_power_profile_mode(void *handle, char *buf)
2511 struct smu_context *smu = handle;
2513 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2514 !smu->ppt_funcs->get_power_profile_mode)
2519 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
2522 static int smu_set_power_profile_mode(void *handle,
2524 uint32_t param_size)
2526 struct smu_context *smu = handle;
2528 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2529 !smu->ppt_funcs->set_power_profile_mode)
2532 return smu_bump_power_profile_mode(smu, param, param_size);
2535 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
2537 struct smu_context *smu = handle;
2539 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2542 if (!smu->ppt_funcs->get_fan_control_mode)
2548 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
2553 static int smu_set_fan_control_mode(void *handle, u32 value)
2555 struct smu_context *smu = handle;
2558 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2561 if (!smu->ppt_funcs->set_fan_control_mode)
2564 if (value == U32_MAX)
2567 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2571 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2572 smu->user_dpm_profile.fan_mode = value;
2574 /* reset user dpm fan speed */
2575 if (value != AMD_FAN_CTRL_MANUAL) {
2576 smu->user_dpm_profile.fan_speed_pwm = 0;
2577 smu->user_dpm_profile.fan_speed_rpm = 0;
2578 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2586 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2588 struct smu_context *smu = handle;
2591 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2594 if (!smu->ppt_funcs->get_fan_speed_pwm)
2600 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2605 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2607 struct smu_context *smu = handle;
2610 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2613 if (!smu->ppt_funcs->set_fan_speed_pwm)
2616 if (speed == U32_MAX)
2619 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2620 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2621 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2622 smu->user_dpm_profile.fan_speed_pwm = speed;
2624 /* Override custom RPM setting as they cannot co-exist */
2625 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2626 smu->user_dpm_profile.fan_speed_rpm = 0;
2632 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2634 struct smu_context *smu = handle;
2637 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2640 if (!smu->ppt_funcs->get_fan_speed_rpm)
2646 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2651 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2653 struct smu_context *smu = handle;
2655 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2658 return smu_set_min_dcef_deep_sleep(smu, clk);
2661 static int smu_get_clock_by_type_with_latency(void *handle,
2662 enum amd_pp_clock_type type,
2663 struct pp_clock_levels_with_latency *clocks)
2665 struct smu_context *smu = handle;
2666 enum smu_clk_type clk_type;
2669 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2672 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2674 case amd_pp_sys_clock:
2675 clk_type = SMU_GFXCLK;
2677 case amd_pp_mem_clock:
2678 clk_type = SMU_MCLK;
2680 case amd_pp_dcef_clock:
2681 clk_type = SMU_DCEFCLK;
2683 case amd_pp_disp_clock:
2684 clk_type = SMU_DISPCLK;
2687 dev_err(smu->adev->dev, "Invalid clock type!\n");
2691 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2697 static int smu_display_clock_voltage_request(void *handle,
2698 struct pp_display_clock_request *clock_req)
2700 struct smu_context *smu = handle;
2703 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2706 if (smu->ppt_funcs->display_clock_voltage_request)
2707 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2713 static int smu_display_disable_memory_clock_switch(void *handle,
2714 bool disable_memory_clock_switch)
2716 struct smu_context *smu = handle;
2719 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2722 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2723 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2728 static int smu_set_xgmi_pstate(void *handle,
2731 struct smu_context *smu = handle;
2734 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2737 if (smu->ppt_funcs->set_xgmi_pstate)
2738 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2741 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2746 static int smu_get_baco_capability(void *handle, bool *cap)
2748 struct smu_context *smu = handle;
2752 if (!smu->pm_enabled)
2755 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2756 *cap = smu->ppt_funcs->baco_is_support(smu);
2761 static int smu_baco_set_state(void *handle, int state)
2763 struct smu_context *smu = handle;
2766 if (!smu->pm_enabled)
2770 if (smu->ppt_funcs->baco_exit)
2771 ret = smu->ppt_funcs->baco_exit(smu);
2772 } else if (state == 1) {
2773 if (smu->ppt_funcs->baco_enter)
2774 ret = smu->ppt_funcs->baco_enter(smu);
2780 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2781 (state)?"enter":"exit");
2786 bool smu_mode1_reset_is_support(struct smu_context *smu)
2790 if (!smu->pm_enabled)
2793 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2794 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2799 bool smu_mode2_reset_is_support(struct smu_context *smu)
2803 if (!smu->pm_enabled)
2806 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2807 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2812 int smu_mode1_reset(struct smu_context *smu)
2816 if (!smu->pm_enabled)
2819 if (smu->ppt_funcs->mode1_reset)
2820 ret = smu->ppt_funcs->mode1_reset(smu);
2825 static int smu_mode2_reset(void *handle)
2827 struct smu_context *smu = handle;
2830 if (!smu->pm_enabled)
2833 if (smu->ppt_funcs->mode2_reset)
2834 ret = smu->ppt_funcs->mode2_reset(smu);
2837 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2842 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2843 struct pp_smu_nv_clock_table *max_clocks)
2845 struct smu_context *smu = handle;
2848 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2851 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2852 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2857 static int smu_get_uclk_dpm_states(void *handle,
2858 unsigned int *clock_values_in_khz,
2859 unsigned int *num_states)
2861 struct smu_context *smu = handle;
2864 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2867 if (smu->ppt_funcs->get_uclk_dpm_states)
2868 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2873 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2875 struct smu_context *smu = handle;
2876 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2878 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2881 if (smu->ppt_funcs->get_current_power_state)
2882 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2887 static int smu_get_dpm_clock_table(void *handle,
2888 struct dpm_clocks *clock_table)
2890 struct smu_context *smu = handle;
2893 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2896 if (smu->ppt_funcs->get_dpm_clock_table)
2897 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2902 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2904 struct smu_context *smu = handle;
2906 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2909 if (!smu->ppt_funcs->get_gpu_metrics)
2912 return smu->ppt_funcs->get_gpu_metrics(smu, table);
2915 static int smu_enable_mgpu_fan_boost(void *handle)
2917 struct smu_context *smu = handle;
2920 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2923 if (smu->ppt_funcs->enable_mgpu_fan_boost)
2924 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2929 static int smu_gfx_state_change_set(void *handle,
2932 struct smu_context *smu = handle;
2935 if (smu->ppt_funcs->gfx_state_change_set)
2936 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
2941 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
2945 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
2946 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
2951 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
2953 int ret = -EOPNOTSUPP;
2955 if (smu->ppt_funcs &&
2956 smu->ppt_funcs->get_ecc_info)
2957 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
2963 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
2965 struct smu_context *smu = handle;
2966 struct smu_table_context *smu_table = &smu->smu_table;
2967 struct smu_table *memory_pool = &smu_table->memory_pool;
2974 if (memory_pool->bo) {
2975 *addr = memory_pool->cpu_addr;
2976 *size = memory_pool->size;
2982 static const struct amd_pm_funcs swsmu_pm_funcs = {
2983 /* export for sysfs */
2984 .set_fan_control_mode = smu_set_fan_control_mode,
2985 .get_fan_control_mode = smu_get_fan_control_mode,
2986 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
2987 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
2988 .force_clock_level = smu_force_ppclk_levels,
2989 .print_clock_levels = smu_print_ppclk_levels,
2990 .emit_clock_levels = smu_emit_ppclk_levels,
2991 .force_performance_level = smu_force_performance_level,
2992 .read_sensor = smu_read_sensor,
2993 .get_performance_level = smu_get_performance_level,
2994 .get_current_power_state = smu_get_current_power_state,
2995 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
2996 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
2997 .get_pp_num_states = smu_get_power_num_states,
2998 .get_pp_table = smu_sys_get_pp_table,
2999 .set_pp_table = smu_sys_set_pp_table,
3000 .switch_power_profile = smu_switch_power_profile,
3001 /* export to amdgpu */
3002 .dispatch_tasks = smu_handle_dpm_task,
3003 .load_firmware = smu_load_microcode,
3004 .set_powergating_by_smu = smu_dpm_set_power_gate,
3005 .set_power_limit = smu_set_power_limit,
3006 .get_power_limit = smu_get_power_limit,
3007 .get_power_profile_mode = smu_get_power_profile_mode,
3008 .set_power_profile_mode = smu_set_power_profile_mode,
3009 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3010 .set_mp1_state = smu_set_mp1_state,
3011 .gfx_state_change_set = smu_gfx_state_change_set,
3013 .get_sclk = smu_get_sclk,
3014 .get_mclk = smu_get_mclk,
3015 .display_configuration_change = smu_display_configuration_change,
3016 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3017 .display_clock_voltage_request = smu_display_clock_voltage_request,
3018 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3019 .set_active_display_count = smu_set_display_count,
3020 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3021 .get_asic_baco_capability = smu_get_baco_capability,
3022 .set_asic_baco_state = smu_baco_set_state,
3023 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3024 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3025 .asic_reset_mode_2 = smu_mode2_reset,
3026 .set_df_cstate = smu_set_df_cstate,
3027 .set_xgmi_pstate = smu_set_xgmi_pstate,
3028 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3029 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3030 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3031 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3032 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3033 .get_dpm_clock_table = smu_get_dpm_clock_table,
3034 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3037 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3042 if (smu->ppt_funcs->wait_for_event)
3043 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3048 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3051 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3054 /* Confirm the buffer allocated is of correct size */
3055 if (size != smu->stb_context.stb_buf_size)
3059 * No need to lock smu mutex as we access STB directly through MMIO
3060 * and not going through SMU messaging route (for now at least).
3061 * For registers access rely on implementation internal locking.
3063 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3066 #if defined(CONFIG_DEBUG_FS)
3068 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3070 struct amdgpu_device *adev = filp->f_inode->i_private;
3071 struct smu_context *smu = adev->powerplay.pp_handle;
3075 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3079 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3083 filp->private_data = buf;
3092 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3095 struct amdgpu_device *adev = filp->f_inode->i_private;
3096 struct smu_context *smu = adev->powerplay.pp_handle;
3099 if (!filp->private_data)
3102 return simple_read_from_buffer(buf,
3104 pos, filp->private_data,
3105 smu->stb_context.stb_buf_size);
3108 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3110 kvfree(filp->private_data);
3111 filp->private_data = NULL;
3117 * We have to define not only read method but also
3118 * open and release because .read takes up to PAGE_SIZE
3119 * data each time so and so is invoked multiple times.
3120 * We allocate the STB buffer in .open and release it
3123 static const struct file_operations smu_stb_debugfs_fops = {
3124 .owner = THIS_MODULE,
3125 .open = smu_stb_debugfs_open,
3126 .read = smu_stb_debugfs_read,
3127 .release = smu_stb_debugfs_release,
3128 .llseek = default_llseek,
3133 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3135 #if defined(CONFIG_DEBUG_FS)
3137 struct smu_context *smu = adev->powerplay.pp_handle;
3139 if (!smu || (!smu->stb_context.stb_buf_size))
3142 debugfs_create_file_size("amdgpu_smu_stb_dump",
3144 adev_to_drm(adev)->primary->debugfs_root,
3146 &smu_stb_debugfs_fops,
3147 smu->stb_context.stb_buf_size);
3151 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3155 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3156 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3161 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3165 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3166 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);