drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomfwctrl.h"
  33 #include "atomfirmware.h"
  34 #include "cgs_common.h"
  35 #include "vega10_powertune.h"
  36 #include "smu9.h"
  37 #include "smu9_driver_if.h"
  38 #include "vega10_inc.h"
  39 #include "soc15_common.h"
  40 #include "pppcielanes.h"
  41 #include "vega10_hwmgr.h"
  42 #include "vega10_smumgr.h"
  43 #include "vega10_processpptables.h"
  44 #include "vega10_pptable.h"
  45 #include "vega10_thermal.h"
  46 #include "pp_debug.h"
  47 #include "amd_pcie_helpers.h"
  48 #include "ppinterrupt.h"
  49 #include "pp_overdriver.h"
  50 #include "pp_thermal.h"
  51 #include "vega10_baco.h"
  52
  53 #include "smuio/smuio_9_0_offset.h"
  54 #include "smuio/smuio_9_0_sh_mask.h"
  55
  56 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  57 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  58
  59 #define HBM_MEMORY_CHANNEL_WIDTH    128
  60
  61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  62
  63 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  64 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  65
  66 //DF_CS_AON0_DramBaseAddress0
  67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  72 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  73 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  74 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  75 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  76 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  77
  78 typedef enum {
  79         CLK_SMNCLK = 0,
  80         CLK_SOCCLK,
  81         CLK_MP0CLK,
  82         CLK_MP1CLK,
  83         CLK_LCLK,
  84         CLK_DCEFCLK,
  85         CLK_VCLK,
  86         CLK_DCLK,
  87         CLK_ECLK,
  88         CLK_UCLK,
  89         CLK_GFXCLK,
  90         CLK_COUNT,
  91 } CLOCK_ID_e;
  92
  93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
  94
  95 static struct vega10_power_state *cast_phw_vega10_power_state(
  96                                   struct pp_hw_power_state *hw_ps)
  97 {
  98         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  99                                 "Invalid Powerstate Type!",
 100                                  return NULL;);
 101
 102         return (struct vega10_power_state *)hw_ps;
 103 }
 104
 105 static const struct vega10_power_state *cast_const_phw_vega10_power_state(
 106                                  const struct pp_hw_power_state *hw_ps)
 107 {
 108         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
 109                                 "Invalid Powerstate Type!",
 110                                  return NULL;);
 111
 112         return (const struct vega10_power_state *)hw_ps;
 113 }
 114
 115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
 116 {
 117         struct vega10_hwmgr *data = hwmgr->backend;
 118
 119         data->registry_data.sclk_dpm_key_disabled =
 120                         hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
 121         data->registry_data.socclk_dpm_key_disabled =
 122                         hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
 123         data->registry_data.mclk_dpm_key_disabled =
 124                         hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
 125         data->registry_data.pcie_dpm_key_disabled =
 126                         hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
 127
 128         data->registry_data.dcefclk_dpm_key_disabled =
 129                         hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
 130
 131         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 132                 data->registry_data.power_containment_support = 1;
 133                 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
 134                 data->registry_data.enable_tdc_limit_feature = 1;
 135         }
 136
 137         data->registry_data.clock_stretcher_support =
 138                         hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 139
 140         data->registry_data.ulv_support =
 141                         hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 142
 143         data->registry_data.sclk_deep_sleep_support =
 144                         hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
 145
 146         data->registry_data.disable_water_mark = 0;
 147
 148         data->registry_data.fan_control_support = 1;
 149         data->registry_data.thermal_support = 1;
 150         data->registry_data.fw_ctf_enabled = 1;
 151
 152         data->registry_data.avfs_support =
 153                 hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
 154         data->registry_data.led_dpm_enabled = 1;
 155
 156         data->registry_data.vr0hot_enabled = 1;
 157         data->registry_data.vr1hot_enabled = 1;
 158         data->registry_data.regulator_hot_gpio_support = 1;
 159
 160         data->registry_data.didt_support = 1;
 161         if (data->registry_data.didt_support) {
 162                 data->registry_data.didt_mode = 6;
 163                 data->registry_data.sq_ramping_support = 1;
 164                 data->registry_data.db_ramping_support = 0;
 165                 data->registry_data.td_ramping_support = 0;
 166                 data->registry_data.tcp_ramping_support = 0;
 167                 data->registry_data.dbr_ramping_support = 0;
 168                 data->registry_data.edc_didt_support = 1;
 169                 data->registry_data.gc_didt_support = 0;
 170                 data->registry_data.psm_didt_support = 0;
 171         }
 172
 173         data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
 174         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 175         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 176         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 177         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 178         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 179         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 180         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 181         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 182         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 183         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 184         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 185         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 186
 187         data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
 188         data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
 189         data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
 190         data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
 191 }
 192
 193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 194 {
 195         struct vega10_hwmgr *data = hwmgr->backend;
 196         struct phm_ppt_v2_information *table_info =
 197                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 198         struct amdgpu_device *adev = hwmgr->adev;
 199
 200         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 201                         PHM_PlatformCaps_SclkDeepSleep);
 202
 203         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 204                         PHM_PlatformCaps_DynamicPatchPowerState);
 205
 206         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
 207                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 208                                 PHM_PlatformCaps_ControlVDDCI);
 209
 210         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 211                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 212
 213         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 214                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 215                                 PHM_PlatformCaps_UVDPowerGating);
 216
 217         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 218                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 219                                 PHM_PlatformCaps_VCEPowerGating);
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                         PHM_PlatformCaps_UnTabledHardwareInterface);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 226
 227         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 229
 230         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 231                                 PHM_PlatformCaps_DynamicPowerManagement);
 232
 233         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 234                         PHM_PlatformCaps_SMC);
 235
 236         /* power tune caps */
 237         /* assume disabled */
 238         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 239                         PHM_PlatformCaps_PowerContainment);
 240         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 241                         PHM_PlatformCaps_DiDtSupport);
 242         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 243                         PHM_PlatformCaps_SQRamping);
 244         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_DBRamping);
 246         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 247                         PHM_PlatformCaps_TDRamping);
 248         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 249                         PHM_PlatformCaps_TCPRamping);
 250         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 251                         PHM_PlatformCaps_DBRRamping);
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                         PHM_PlatformCaps_DiDtEDCEnable);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                         PHM_PlatformCaps_GCEDC);
 256         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 257                         PHM_PlatformCaps_PSM);
 258
 259         if (data->registry_data.didt_support) {
 260                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 261                 if (data->registry_data.sq_ramping_support)
 262                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 263                 if (data->registry_data.db_ramping_support)
 264                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 265                 if (data->registry_data.td_ramping_support)
 266                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 267                 if (data->registry_data.tcp_ramping_support)
 268                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 269                 if (data->registry_data.dbr_ramping_support)
 270                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 271                 if (data->registry_data.edc_didt_support)
 272                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 273                 if (data->registry_data.gc_didt_support)
 274                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 275                 if (data->registry_data.psm_didt_support)
 276                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 277         }
 278
 279         if (data->registry_data.power_containment_support)
 280                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 281                                 PHM_PlatformCaps_PowerContainment);
 282         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 283                         PHM_PlatformCaps_CAC);
 284
 285         if (table_info->tdp_table->usClockStretchAmount &&
 286                         data->registry_data.clock_stretcher_support)
 287                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 288                                 PHM_PlatformCaps_ClockStretcher);
 289
 290         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 291                         PHM_PlatformCaps_RegulatorHot);
 292         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 293                         PHM_PlatformCaps_AutomaticDCTransition);
 294
 295         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 296                         PHM_PlatformCaps_UVDDPM);
 297         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 298                         PHM_PlatformCaps_VCEDPM);
 299
 300         return 0;
 301 }
 302
 303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 304 {
 305         struct vega10_hwmgr *data = hwmgr->backend;
 306         struct phm_ppt_v2_information *table_info =
 307                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 308         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 309         struct vega10_odn_vddc_lookup_table *od_lookup_table;
 310         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 311         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
 312         struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
 313         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
 314         uint32_t i;
 315         int result;
 316
 317         result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
 318         if (!result) {
 319                 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
 320                 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
 321         }
 322
 323         od_lookup_table = &odn_table->vddc_lookup_table;
 324         vddc_lookup_table = table_info->vddc_lookup_table;
 325
 326         for (i = 0; i < vddc_lookup_table->count; i++)
 327                 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
 328
 329         od_lookup_table->count = vddc_lookup_table->count;
 330
 331         dep_table[0] = table_info->vdd_dep_on_sclk;
 332         dep_table[1] = table_info->vdd_dep_on_mclk;
 333         dep_table[2] = table_info->vdd_dep_on_socclk;
 334         od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
 335         od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
 336         od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
 337
 338         for (i = 0; i < 3; i++)
 339                 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
 340
 341         if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
 342                 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
 343         if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
 344                 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
 345
 346         i = od_table[2]->count - 1;
 347         od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
 348                                         hwmgr->platform_descriptor.overdriveLimit.memoryClock :
 349                                         od_table[2]->entries[i].clk;
 350         od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
 351                                         odn_table->max_vddc :
 352                                         od_table[2]->entries[i].vddc;
 353
 354         return 0;
 355 }
 356
 357 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 358 {
 359         struct vega10_hwmgr *data = hwmgr->backend;
 360         int i;
 361         uint32_t sub_vendor_id, hw_revision;
 362         uint32_t top32, bottom32;
 363         struct amdgpu_device *adev = hwmgr->adev;
 364
 365         vega10_initialize_power_tune_defaults(hwmgr);
 366
 367         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 368                 data->smu_features[i].smu_feature_id = 0xffff;
 369                 data->smu_features[i].smu_feature_bitmap = 1 << i;
 370                 data->smu_features[i].enabled = false;
 371                 data->smu_features[i].supported = false;
 372         }
 373
 374         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 375                         FEATURE_DPM_PREFETCHER_BIT;
 376         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 377                         FEATURE_DPM_GFXCLK_BIT;
 378         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 379                         FEATURE_DPM_UCLK_BIT;
 380         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 381                         FEATURE_DPM_SOCCLK_BIT;
 382         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 383                         FEATURE_DPM_UVD_BIT;
 384         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 385                         FEATURE_DPM_VCE_BIT;
 386         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 387                         FEATURE_DPM_MP0CLK_BIT;
 388         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 389                         FEATURE_DPM_LINK_BIT;
 390         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 391                         FEATURE_DPM_DCEFCLK_BIT;
 392         data->smu_features[GNLD_ULV].smu_feature_id =
 393                         FEATURE_ULV_BIT;
 394         data->smu_features[GNLD_AVFS].smu_feature_id =
 395                         FEATURE_AVFS_BIT;
 396         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 397                         FEATURE_DS_GFXCLK_BIT;
 398         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 399                         FEATURE_DS_SOCCLK_BIT;
 400         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 401                         FEATURE_DS_LCLK_BIT;
 402         data->smu_features[GNLD_PPT].smu_feature_id =
 403                         FEATURE_PPT_BIT;
 404         data->smu_features[GNLD_TDC].smu_feature_id =
 405                         FEATURE_TDC_BIT;
 406         data->smu_features[GNLD_THERMAL].smu_feature_id =
 407                         FEATURE_THERMAL_BIT;
 408         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 409                         FEATURE_GFX_PER_CU_CG_BIT;
 410         data->smu_features[GNLD_RM].smu_feature_id =
 411                         FEATURE_RM_BIT;
 412         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 413                         FEATURE_DS_DCEFCLK_BIT;
 414         data->smu_features[GNLD_ACDC].smu_feature_id =
 415                         FEATURE_ACDC_BIT;
 416         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 417                         FEATURE_VR0HOT_BIT;
 418         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 419                         FEATURE_VR1HOT_BIT;
 420         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 421                         FEATURE_FW_CTF_BIT;
 422         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 423                         FEATURE_LED_DISPLAY_BIT;
 424         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 425                         FEATURE_FAN_CONTROL_BIT;
 426         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 427         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 428         data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
 429
 430         if (!data->registry_data.prefetcher_dpm_key_disabled)
 431                 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
 432
 433         if (!data->registry_data.sclk_dpm_key_disabled)
 434                 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
 435
 436         if (!data->registry_data.mclk_dpm_key_disabled)
 437                 data->smu_features[GNLD_DPM_UCLK].supported = true;
 438
 439         if (!data->registry_data.socclk_dpm_key_disabled)
 440                 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
 441
 442         if (PP_CAP(PHM_PlatformCaps_UVDDPM))
 443                 data->smu_features[GNLD_DPM_UVD].supported = true;
 444
 445         if (PP_CAP(PHM_PlatformCaps_VCEDPM))
 446                 data->smu_features[GNLD_DPM_VCE].supported = true;
 447
 448         data->smu_features[GNLD_DPM_LINK].supported = true;
 449
 450         if (!data->registry_data.dcefclk_dpm_key_disabled)
 451                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
 452
 453         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
 454             data->registry_data.sclk_deep_sleep_support) {
 455                 data->smu_features[GNLD_DS_GFXCLK].supported = true;
 456                 data->smu_features[GNLD_DS_SOCCLK].supported = true;
 457                 data->smu_features[GNLD_DS_LCLK].supported = true;
 458                 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
 459         }
 460
 461         if (data->registry_data.enable_pkg_pwr_tracking_feature)
 462                 data->smu_features[GNLD_PPT].supported = true;
 463
 464         if (data->registry_data.enable_tdc_limit_feature)
 465                 data->smu_features[GNLD_TDC].supported = true;
 466
 467         if (data->registry_data.thermal_support)
 468                 data->smu_features[GNLD_THERMAL].supported = true;
 469
 470         if (data->registry_data.fan_control_support)
 471                 data->smu_features[GNLD_FAN_CONTROL].supported = true;
 472
 473         if (data->registry_data.fw_ctf_enabled)
 474                 data->smu_features[GNLD_FW_CTF].supported = true;
 475
 476         if (data->registry_data.avfs_support)
 477                 data->smu_features[GNLD_AVFS].supported = true;
 478
 479         if (data->registry_data.led_dpm_enabled)
 480                 data->smu_features[GNLD_LED_DISPLAY].supported = true;
 481
 482         if (data->registry_data.vr1hot_enabled)
 483                 data->smu_features[GNLD_VR1HOT].supported = true;
 484
 485         if (data->registry_data.vr0hot_enabled)
 486                 data->smu_features[GNLD_VR0HOT].supported = true;
 487
 488         smum_send_msg_to_smc(hwmgr,
 489                         PPSMC_MSG_GetSmuVersion,
 490                         &hwmgr->smu_version);
 491                 /* ACG firmware has major version 5 */
 492         if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
 493                 data->smu_features[GNLD_ACG].supported = true;
 494         if (data->registry_data.didt_support)
 495                 data->smu_features[GNLD_DIDT].supported = true;
 496
 497         hw_revision = adev->pdev->revision;
 498         sub_vendor_id = adev->pdev->subsystem_vendor;
 499
 500         if ((hwmgr->chip_id == 0x6862 ||
 501                 hwmgr->chip_id == 0x6861 ||
 502                 hwmgr->chip_id == 0x6868) &&
 503                 (hw_revision == 0) &&
 504                 (sub_vendor_id != 0x1002))
 505                 data->smu_features[GNLD_PCC_LIMIT].supported = true;
 506
 507         /* Get the SN to turn into a Unique ID */
 508         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
 509         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
 510
 511         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 512 }
 513
 514 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 515 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 516         phm_ppt_v1_voltage_lookup_table *lookup_table,
 517         uint16_t virtual_voltage_id, int32_t *socclk)
 518 {
 519         uint8_t entry_id;
 520         uint8_t voltage_id;
 521         struct phm_ppt_v2_information *table_info =
 522                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 523
 524         PP_ASSERT_WITH_CODE(lookup_table->count != 0,
 525                         "Lookup table is empty",
 526                         return -EINVAL);
 527
 528         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
 529         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 530                 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
 531                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 532                         break;
 533         }
 534
 535         PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
 536                         "Can't find requested voltage id in vdd_dep_on_socclk table!",
 537                         return -EINVAL);
 538
 539         *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
 540
 541         return 0;
 542 }
 543
 544 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 545 /**
 546  * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID.
 547  *
 548  * @hwmgr:  the address of the powerplay hardware manager.
 549  * return:  always 0.
 550  */
 551 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 552 {
 553         struct vega10_hwmgr *data = hwmgr->backend;
 554         uint16_t vv_id;
 555         uint32_t vddc = 0;
 556         uint16_t i, j;
 557         uint32_t sclk = 0;
 558         struct phm_ppt_v2_information *table_info =
 559                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 560         struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
 561                         table_info->vdd_dep_on_socclk;
 562         int result;
 563
 564         for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
 565                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 566
 567                 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
 568                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 569                         if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
 570                                 for (j = 1; j < socclk_table->count; j++) {
 571                                         if (socclk_table->entries[j].clk == sclk &&
 572                                                         socclk_table->entries[j].cks_enable == 0) {
 573                                                 sclk += 5000;
 574                                                 break;
 575                                         }
 576                                 }
 577                         }
 578
 579                         PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
 580                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
 581                                         "Error retrieving EVV voltage value!",
 582                                         continue);
 583
 584
 585                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 586                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
 587                                         "Invalid VDDC value", result = -EINVAL;);
 588
 589                         /* the voltage should not be zero nor equal to leakage ID */
 590                         if (vddc != 0 && vddc != vv_id) {
 591                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
 592                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
 593                                 data->vddc_leakage.count++;
 594                         }
 595                 }
 596         }
 597
 598         return 0;
 599 }
 600
 601 /**
 602  * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value.
 603  *
 604  * @hwmgr:         the address of the powerplay hardware manager.
 605  * @voltage:       pointer to changing voltage
 606  * @leakage_table: pointer to leakage table
 607  */
 608 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 609                 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
 610 {
 611         uint32_t index;
 612
 613         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 614         for (index = 0; index < leakage_table->count; index++) {
 615                 /* if this voltage matches a leakage voltage ID */
 616                 /* patch with actual leakage voltage */
 617                 if (leakage_table->leakage_id[index] == *voltage) {
 618                         *voltage = leakage_table->actual_voltage[index];
 619                         break;
 620                 }
 621         }
 622
 623         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 624                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
 625 }
 626
 627 /**
 628  * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
 629  *
 630  * @hwmgr:         the address of the powerplay hardware manager.
 631  * @lookup_table:  pointer to voltage lookup table
 632  * @leakage_table: pointer to leakage table
 633  * return:         always 0
 634  */
 635 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 636                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 637                 struct vega10_leakage_voltage *leakage_table)
 638 {
 639         uint32_t i;
 640
 641         for (i = 0; i < lookup_table->count; i++)
 642                 vega10_patch_with_vdd_leakage(hwmgr,
 643                                 &lookup_table->entries[i].us_vdd, leakage_table);
 644
 645         return 0;
 646 }
 647
 648 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
 649                 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
 650                 uint16_t *vddc)
 651 {
 652         vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 653
 654         return 0;
 655 }
 656 #endif
 657
 658 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
 659                 struct pp_hwmgr *hwmgr)
 660 {
 661         uint8_t entry_id, voltage_id;
 662         unsigned i;
 663         struct phm_ppt_v2_information *table_info =
 664                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 665         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 666                         table_info->mm_dep_table;
 667         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 668                         table_info->vdd_dep_on_mclk;
 669
 670         for (i = 0; i < 6; i++) {
 671                 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
 672                 switch (i) {
 673                         case 0: vdt = table_info->vdd_dep_on_socclk; break;
 674                         case 1: vdt = table_info->vdd_dep_on_sclk; break;
 675                         case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
 676                         case 3: vdt = table_info->vdd_dep_on_pixclk; break;
 677                         case 4: vdt = table_info->vdd_dep_on_dispclk; break;
 678                         case 5: vdt = table_info->vdd_dep_on_phyclk; break;
 679                 }
 680
 681                 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
 682                         voltage_id = vdt->entries[entry_id].vddInd;
 683                         vdt->entries[entry_id].vddc =
 684                                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 685                 }
 686         }
 687
 688         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
 689                 voltage_id = mm_table->entries[entry_id].vddcInd;
 690                 mm_table->entries[entry_id].vddc =
 691                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 692         }
 693
 694         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
 695                 voltage_id = mclk_table->entries[entry_id].vddInd;
 696                 mclk_table->entries[entry_id].vddc =
 697                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 698                 voltage_id = mclk_table->entries[entry_id].vddciInd;
 699                 mclk_table->entries[entry_id].vddci =
 700                                 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
 701                 voltage_id = mclk_table->entries[entry_id].mvddInd;
 702                 mclk_table->entries[entry_id].mvdd =
 703                                 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
 704         }
 705
 706
 707         return 0;
 708
 709 }
 710
 711 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
 712                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 713 {
 714         uint32_t table_size, i, j;
 715
 716         PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
 717                 "Lookup table is empty", return -EINVAL);
 718
 719         table_size = lookup_table->count;
 720
 721         /* Sorting voltages */
 722         for (i = 0; i < table_size - 1; i++) {
 723                 for (j = i + 1; j > 0; j--) {
 724                         if (lookup_table->entries[j].us_vdd <
 725                                         lookup_table->entries[j - 1].us_vdd) {
 726                                 swap(lookup_table->entries[j - 1],
 727                                      lookup_table->entries[j]);
 728                         }
 729                 }
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 736 {
 737         int result = 0;
 738         int tmp_result;
 739         struct phm_ppt_v2_information *table_info =
 740                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 741 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 742         struct vega10_hwmgr *data = hwmgr->backend;
 743
 744         tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
 745                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 746         if (tmp_result)
 747                 result = tmp_result;
 748
 749         tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 750                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 751         if (tmp_result)
 752                 result = tmp_result;
 753 #endif
 754
 755         tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 756         if (tmp_result)
 757                 result = tmp_result;
 758
 759         tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 760         if (tmp_result)
 761                 result = tmp_result;
 762
 763         return result;
 764 }
 765
 766 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 767 {
 768         struct phm_ppt_v2_information *table_info =
 769                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 770         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 771                         table_info->vdd_dep_on_socclk;
 772         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 773                         table_info->vdd_dep_on_mclk;
 774
 775         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
 776                 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
 777         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 778                 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
 779
 780         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
 781                 "VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
 782         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 783                 "VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
 784
 785         table_info->max_clock_voltage_on_ac.sclk =
 786                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 787         table_info->max_clock_voltage_on_ac.mclk =
 788                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 789         table_info->max_clock_voltage_on_ac.vddc =
 790                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 791         table_info->max_clock_voltage_on_ac.vddci =
 792                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 793
 794         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 795                 table_info->max_clock_voltage_on_ac.sclk;
 796         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 797                 table_info->max_clock_voltage_on_ac.mclk;
 798         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 799                 table_info->max_clock_voltage_on_ac.vddc;
 800         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 801                 table_info->max_clock_voltage_on_ac.vddci;
 802
 803         return 0;
 804 }
 805
 806 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 807 {
 808         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 809         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 810
 811         kfree(hwmgr->backend);
 812         hwmgr->backend = NULL;
 813
 814         return 0;
 815 }
 816
 817 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 818 {
 819         int result = 0;
 820         struct vega10_hwmgr *data;
 821         uint32_t config_telemetry = 0;
 822         struct pp_atomfwctrl_voltage_table vol_table;
 823         struct amdgpu_device *adev = hwmgr->adev;
 824
 825         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
 826         if (data == NULL)
 827                 return -ENOMEM;
 828
 829         hwmgr->backend = data;
 830
 831         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 832         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 833         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 834
 835         vega10_set_default_registry_data(hwmgr);
 836         data->disable_dpm_mask = 0xff;
 837
 838         /* need to set voltage control types before EVV patching */
 839         data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
 840         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
 841         data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
 842
 843         /* VDDCR_SOC */
 844         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 845                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
 846                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 847                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
 848                                 &vol_table)) {
 849                         config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
 850                                         (vol_table.telemetry_offset & 0xff);
 851                         data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 852                 }
 853         } else {
 854                 kfree(hwmgr->backend);
 855                 hwmgr->backend = NULL;
 856                 PP_ASSERT_WITH_CODE(false,
 857                                 "VDDCR_SOC is not SVID2!",
 858                                 return -1);
 859         }
 860
 861         /* MVDDC */
 862         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 863                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
 864                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 865                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
 866                                 &vol_table)) {
 867                         config_telemetry |=
 868                                         ((vol_table.telemetry_slope << 24) & 0xff000000) |
 869                                         ((vol_table.telemetry_offset << 16) & 0xff0000);
 870                         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 871                 }
 872         }
 873
 874          /* VDDCI_MEM */
 875         if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
 876                 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 877                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 878                         data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
 879         }
 880
 881         data->config_telemetry = config_telemetry;
 882
 883         vega10_set_features_platform_caps(hwmgr);
 884
 885         vega10_init_dpm_defaults(hwmgr);
 886
 887 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 888         /* Get leakage voltage based on leakage ID. */
 889         PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
 890                         "Get EVV Voltage Failed.  Abort Driver loading!",
 891                         return -1);
 892 #endif
 893
 894         /* Patch our voltage dependency table with actual leakage voltage
 895          * We need to perform leakage translation before it's used by other functions
 896          */
 897         vega10_complete_dependency_tables(hwmgr);
 898
 899         /* Parse pptable data read from VBIOS */
 900         vega10_set_private_data_based_on_pptable(hwmgr);
 901
 902         data->is_tlu_enabled = false;
 903
 904         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 905                         VEGA10_MAX_HARDWARE_POWERLEVELS;
 906         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 907         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 908
 909         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 910         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 911         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 912         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 913
 914         data->total_active_cus = adev->gfx.cu_info.number;
 915         if (!hwmgr->not_vf)
 916                 return result;
 917
 918         /* Setup default Overdrive Fan control settings */
 919         data->odn_fan_table.target_fan_speed =
 920                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 921         data->odn_fan_table.target_temperature =
 922                         hwmgr->thermal_controller.
 923                         advanceFanControlParameters.ucTargetTemperature;
 924         data->odn_fan_table.min_performance_clock =
 925                         hwmgr->thermal_controller.advanceFanControlParameters.
 926                         ulMinFanSCLKAcousticLimit;
 927         data->odn_fan_table.min_fan_limit =
 928                         hwmgr->thermal_controller.
 929                         advanceFanControlParameters.usFanPWMMinLimit *
 930                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 931
 932         data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
 933                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
 934                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 935         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
 936                         "Mem Channel Index Exceeded maximum!",
 937                         return -EINVAL);
 938
 939         return result;
 940 }
 941
 942 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 943 {
 944         struct vega10_hwmgr *data = hwmgr->backend;
 945
 946         data->low_sclk_interrupt_threshold = 0;
 947
 948         return 0;
 949 }
 950
 951 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
 952 {
 953         struct vega10_hwmgr *data = hwmgr->backend;
 954         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 955
 956         struct pp_atomfwctrl_voltage_table table;
 957         uint8_t i, j;
 958         uint32_t mask = 0;
 959         uint32_t tmp;
 960         int32_t ret = 0;
 961
 962         ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
 963                                                 VOLTAGE_OBJ_GPIO_LUT, &table);
 964
 965         if (!ret) {
 966                 tmp = table.mask_low;
 967                 for (i = 0, j = 0; i < 32; i++) {
 968                         if (tmp & 1) {
 969                                 mask |= (uint32_t)(i << (8 * j));
 970                                 if (++j >= 3)
 971                                         break;
 972                         }
 973                         tmp >>= 1;
 974                 }
 975         }
 976
 977         pp_table->LedPin0 = (uint8_t)(mask & 0xff);
 978         pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
 979         pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
 980         return 0;
 981 }
 982
 983 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 984 {
 985         if (!hwmgr->not_vf)
 986                 return 0;
 987
 988         PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
 989                         "Failed to init sclk threshold!",
 990                         return -EINVAL);
 991
 992         PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
 993                         "Failed to set up led dpm config!",
 994                         return -EINVAL);
 995
 996         smum_send_msg_to_smc_with_parameter(hwmgr,
 997                                 PPSMC_MSG_NumOfDisplays,
 998                                 0,
 999                                 NULL);
1000
1001         return 0;
1002 }
1003
1004 /**
1005  * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values.
1006  *
1007  * @hwmgr:      the address of the powerplay hardware manager.
1008  * @vol_table:  the pointer to changing voltage table
1009  * return:      0 in success
1010  */
1011 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
1012                 struct pp_atomfwctrl_voltage_table *vol_table)
1013 {
1014         uint32_t i, j;
1015         uint16_t vvalue;
1016         bool found = false;
1017         struct pp_atomfwctrl_voltage_table *table;
1018
1019         PP_ASSERT_WITH_CODE(vol_table,
1020                         "Voltage Table empty.", return -EINVAL);
1021         table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
1022                         GFP_KERNEL);
1023
1024         if (!table)
1025                 return -ENOMEM;
1026
1027         table->mask_low = vol_table->mask_low;
1028         table->phase_delay = vol_table->phase_delay;
1029
1030         for (i = 0; i < vol_table->count; i++) {
1031                 vvalue = vol_table->entries[i].value;
1032                 found = false;
1033
1034                 for (j = 0; j < table->count; j++) {
1035                         if (vvalue == table->entries[j].value) {
1036                                 found = true;
1037                                 break;
1038                         }
1039                 }
1040
1041                 if (!found) {
1042                         table->entries[table->count].value = vvalue;
1043                         table->entries[table->count].smio_low =
1044                                         vol_table->entries[i].smio_low;
1045                         table->count++;
1046                 }
1047         }
1048
1049         memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1050         kfree(table);
1051
1052         return 0;
1053 }
1054
1055 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1056                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1057                 struct pp_atomfwctrl_voltage_table *vol_table)
1058 {
1059         int i;
1060
1061         PP_ASSERT_WITH_CODE(dep_table->count,
1062                         "Voltage Dependency Table empty.",
1063                         return -EINVAL);
1064
1065         vol_table->mask_low = 0;
1066         vol_table->phase_delay = 0;
1067         vol_table->count = dep_table->count;
1068
1069         for (i = 0; i < vol_table->count; i++) {
1070                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1071                 vol_table->entries[i].smio_low = 0;
1072         }
1073
1074         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1075                         vol_table),
1076                         "Failed to trim MVDD Table!",
1077                         return -1);
1078
1079         return 0;
1080 }
1081
1082 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1083                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1084                 struct pp_atomfwctrl_voltage_table *vol_table)
1085 {
1086         uint32_t i;
1087
1088         PP_ASSERT_WITH_CODE(dep_table->count,
1089                         "Voltage Dependency Table empty.",
1090                         return -EINVAL);
1091
1092         vol_table->mask_low = 0;
1093         vol_table->phase_delay = 0;
1094         vol_table->count = dep_table->count;
1095
1096         for (i = 0; i < dep_table->count; i++) {
1097                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1098                 vol_table->entries[i].smio_low = 0;
1099         }
1100
1101         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1102                         "Failed to trim VDDCI table.",
1103                         return -1);
1104
1105         return 0;
1106 }
1107
1108 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1109                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1110                 struct pp_atomfwctrl_voltage_table *vol_table)
1111 {
1112         int i;
1113
1114         PP_ASSERT_WITH_CODE(dep_table->count,
1115                         "Voltage Dependency Table empty.",
1116                         return -EINVAL);
1117
1118         vol_table->mask_low = 0;
1119         vol_table->phase_delay = 0;
1120         vol_table->count = dep_table->count;
1121
1122         for (i = 0; i < vol_table->count; i++) {
1123                 vol_table->entries[i].value = dep_table->entries[i].vddc;
1124                 vol_table->entries[i].smio_low = 0;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /* ---- Voltage Tables ----
1131  * If the voltage table would be bigger than
1132  * what will fit into the state table on
1133  * the SMC keep only the higher entries.
1134  */
1135 static void vega10_trim_voltage_table_to_fit_state_table(
1136                 struct pp_hwmgr *hwmgr,
1137                 uint32_t max_vol_steps,
1138                 struct pp_atomfwctrl_voltage_table *vol_table)
1139 {
1140         unsigned int i, diff;
1141
1142         if (vol_table->count <= max_vol_steps)
1143                 return;
1144
1145         diff = vol_table->count - max_vol_steps;
1146
1147         for (i = 0; i < max_vol_steps; i++)
1148                 vol_table->entries[i] = vol_table->entries[i + diff];
1149
1150         vol_table->count = max_vol_steps;
1151 }
1152
1153 /**
1154  * vega10_construct_voltage_tables - Create Voltage Tables.
1155  *
1156  * @hwmgr:  the address of the powerplay hardware manager.
1157  * return:  always 0
1158  */
1159 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1160 {
1161         struct vega10_hwmgr *data = hwmgr->backend;
1162         struct phm_ppt_v2_information *table_info =
1163                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1164         int result;
1165
1166         if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1167                         data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1168                 result = vega10_get_mvdd_voltage_table(hwmgr,
1169                                 table_info->vdd_dep_on_mclk,
1170                                 &(data->mvdd_voltage_table));
1171                 PP_ASSERT_WITH_CODE(!result,
1172                                 "Failed to retrieve MVDDC table!",
1173                                 return result);
1174         }
1175
1176         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1177                 result = vega10_get_vddci_voltage_table(hwmgr,
1178                                 table_info->vdd_dep_on_mclk,
1179                                 &(data->vddci_voltage_table));
1180                 PP_ASSERT_WITH_CODE(!result,
1181                                 "Failed to retrieve VDDCI_MEM table!",
1182                                 return result);
1183         }
1184
1185         if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1186                         data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1187                 result = vega10_get_vdd_voltage_table(hwmgr,
1188                                 table_info->vdd_dep_on_sclk,
1189                                 &(data->vddc_voltage_table));
1190                 PP_ASSERT_WITH_CODE(!result,
1191                                 "Failed to retrieve VDDCR_SOC table!",
1192                                 return result);
1193         }
1194
1195         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1196                         "Too many voltage values for VDDC. Trimming to fit state table.",
1197                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1198                                         16, &(data->vddc_voltage_table)));
1199
1200         PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1201                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1202                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1203                                         16, &(data->vddci_voltage_table)));
1204
1205         PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1206                         "Too many voltage values for MVDD. Trimming to fit state table.",
1207                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1208                                         16, &(data->mvdd_voltage_table)));
1209
1210
1211         return 0;
1212 }
1213
1214 /*
1215  * vega10_init_dpm_state
1216  * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1217  *
1218  * @dpm_state: - the address of the DPM Table to initiailize.
1219  * return:   None.
1220  */
1221 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1222 {
1223         dpm_state->soft_min_level = 0xff;
1224         dpm_state->soft_max_level = 0xff;
1225         dpm_state->hard_min_level = 0xff;
1226         dpm_state->hard_max_level = 0xff;
1227 }
1228
1229 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1230                 struct vega10_single_dpm_table *dpm_table,
1231                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1232 {
1233         int i;
1234
1235         dpm_table->count = 0;
1236
1237         for (i = 0; i < dep_table->count; i++) {
1238                 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1239                                 dep_table->entries[i].clk) {
1240                         dpm_table->dpm_levels[dpm_table->count].value =
1241                                         dep_table->entries[i].clk;
1242                         dpm_table->dpm_levels[dpm_table->count].enabled = true;
1243                         dpm_table->count++;
1244                 }
1245         }
1246 }
1247 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1248 {
1249         struct vega10_hwmgr *data = hwmgr->backend;
1250         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1251         struct phm_ppt_v2_information *table_info =
1252                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1253         struct phm_ppt_v1_pcie_table *bios_pcie_table =
1254                         table_info->pcie_table;
1255         uint32_t i;
1256
1257         PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1258                         "Incorrect number of PCIE States from VBIOS!",
1259                         return -1);
1260
1261         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1262                 if (data->registry_data.pcieSpeedOverride)
1263                         pcie_table->pcie_gen[i] =
1264                                         data->registry_data.pcieSpeedOverride;
1265                 else
1266                         pcie_table->pcie_gen[i] =
1267                                         bios_pcie_table->entries[i].gen_speed;
1268
1269                 if (data->registry_data.pcieLaneOverride)
1270                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1271                                         data->registry_data.pcieLaneOverride);
1272                 else
1273                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1274                                                         bios_pcie_table->entries[i].lane_width);
1275                 if (data->registry_data.pcieClockOverride)
1276                         pcie_table->lclk[i] =
1277                                         data->registry_data.pcieClockOverride;
1278                 else
1279                         pcie_table->lclk[i] =
1280                                         bios_pcie_table->entries[i].pcie_sclk;
1281         }
1282
1283         pcie_table->count = NUM_LINK_LEVELS;
1284
1285         return 0;
1286 }
1287
1288 /*
1289  * This function is to initialize all DPM state tables
1290  * for SMU based on the dependency table.
1291  * Dynamic state patching function will then trim these
1292  * state tables to the allowed range based
1293  * on the power policy or external client requests,
1294  * such as UVD request, etc.
1295  */
1296 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1297 {
1298         struct vega10_hwmgr *data = hwmgr->backend;
1299         struct phm_ppt_v2_information *table_info =
1300                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1301         struct vega10_single_dpm_table *dpm_table;
1302         uint32_t i;
1303
1304         struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1305                         table_info->vdd_dep_on_socclk;
1306         struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1307                         table_info->vdd_dep_on_sclk;
1308         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1309                         table_info->vdd_dep_on_mclk;
1310         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1311                         table_info->mm_dep_table;
1312         struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1313                         table_info->vdd_dep_on_dcefclk;
1314         struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1315                         table_info->vdd_dep_on_pixclk;
1316         struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1317                         table_info->vdd_dep_on_dispclk;
1318         struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1319                         table_info->vdd_dep_on_phyclk;
1320
1321         PP_ASSERT_WITH_CODE(dep_soc_table,
1322                         "SOCCLK dependency table is missing. This table is mandatory",
1323                         return -EINVAL);
1324         PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1325                         "SOCCLK dependency table is empty. This table is mandatory",
1326                         return -EINVAL);
1327
1328         PP_ASSERT_WITH_CODE(dep_gfx_table,
1329                         "GFXCLK dependency table is missing. This table is mandatory",
1330                         return -EINVAL);
1331         PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1332                         "GFXCLK dependency table is empty. This table is mandatory",
1333                         return -EINVAL);
1334
1335         PP_ASSERT_WITH_CODE(dep_mclk_table,
1336                         "MCLK dependency table is missing. This table is mandatory",
1337                         return -EINVAL);
1338         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1339                         "MCLK dependency table has to have is missing. This table is mandatory",
1340                         return -EINVAL);
1341
1342         /* Initialize Sclk DPM table based on allow Sclk values */
1343         dpm_table = &(data->dpm_table.soc_table);
1344         vega10_setup_default_single_dpm_table(hwmgr,
1345                         dpm_table,
1346                         dep_soc_table);
1347
1348         vega10_init_dpm_state(&(dpm_table->dpm_state));
1349
1350         dpm_table = &(data->dpm_table.gfx_table);
1351         vega10_setup_default_single_dpm_table(hwmgr,
1352                         dpm_table,
1353                         dep_gfx_table);
1354         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1355                 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1356                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1357         vega10_init_dpm_state(&(dpm_table->dpm_state));
1358
1359         /* Initialize Mclk DPM table based on allow Mclk values */
1360         data->dpm_table.mem_table.count = 0;
1361         dpm_table = &(data->dpm_table.mem_table);
1362         vega10_setup_default_single_dpm_table(hwmgr,
1363                         dpm_table,
1364                         dep_mclk_table);
1365         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1366                 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1367                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1368         vega10_init_dpm_state(&(dpm_table->dpm_state));
1369
1370         data->dpm_table.eclk_table.count = 0;
1371         dpm_table = &(data->dpm_table.eclk_table);
1372         for (i = 0; i < dep_mm_table->count; i++) {
1373                 if (i == 0 || dpm_table->dpm_levels
1374                                 [dpm_table->count - 1].value <=
1375                                                 dep_mm_table->entries[i].eclk) {
1376                         dpm_table->dpm_levels[dpm_table->count].value =
1377                                         dep_mm_table->entries[i].eclk;
1378                         dpm_table->dpm_levels[dpm_table->count].enabled = i == 0;
1379                         dpm_table->count++;
1380                 }
1381         }
1382         vega10_init_dpm_state(&(dpm_table->dpm_state));
1383
1384         data->dpm_table.vclk_table.count = 0;
1385         data->dpm_table.dclk_table.count = 0;
1386         dpm_table = &(data->dpm_table.vclk_table);
1387         for (i = 0; i < dep_mm_table->count; i++) {
1388                 if (i == 0 || dpm_table->dpm_levels
1389                                 [dpm_table->count - 1].value <=
1390                                                 dep_mm_table->entries[i].vclk) {
1391                         dpm_table->dpm_levels[dpm_table->count].value =
1392                                         dep_mm_table->entries[i].vclk;
1393                         dpm_table->dpm_levels[dpm_table->count].enabled = i == 0;
1394                         dpm_table->count++;
1395                 }
1396         }
1397         vega10_init_dpm_state(&(dpm_table->dpm_state));
1398
1399         dpm_table = &(data->dpm_table.dclk_table);
1400         for (i = 0; i < dep_mm_table->count; i++) {
1401                 if (i == 0 || dpm_table->dpm_levels
1402                                 [dpm_table->count - 1].value <=
1403                                                 dep_mm_table->entries[i].dclk) {
1404                         dpm_table->dpm_levels[dpm_table->count].value =
1405                                         dep_mm_table->entries[i].dclk;
1406                         dpm_table->dpm_levels[dpm_table->count].enabled = i == 0;
1407                         dpm_table->count++;
1408                 }
1409         }
1410         vega10_init_dpm_state(&(dpm_table->dpm_state));
1411
1412         /* Assume there is no headless Vega10 for now */
1413         dpm_table = &(data->dpm_table.dcef_table);
1414         vega10_setup_default_single_dpm_table(hwmgr,
1415                         dpm_table,
1416                         dep_dcef_table);
1417
1418         vega10_init_dpm_state(&(dpm_table->dpm_state));
1419
1420         dpm_table = &(data->dpm_table.pixel_table);
1421         vega10_setup_default_single_dpm_table(hwmgr,
1422                         dpm_table,
1423                         dep_pix_table);
1424
1425         vega10_init_dpm_state(&(dpm_table->dpm_state));
1426
1427         dpm_table = &(data->dpm_table.display_table);
1428         vega10_setup_default_single_dpm_table(hwmgr,
1429                         dpm_table,
1430                         dep_disp_table);
1431
1432         vega10_init_dpm_state(&(dpm_table->dpm_state));
1433
1434         dpm_table = &(data->dpm_table.phy_table);
1435         vega10_setup_default_single_dpm_table(hwmgr,
1436                         dpm_table,
1437                         dep_phy_table);
1438
1439         vega10_init_dpm_state(&(dpm_table->dpm_state));
1440
1441         vega10_setup_default_pcie_table(hwmgr);
1442
1443         /* Zero out the saved copy of the CUSTOM profile
1444          * This will be checked when trying to set the profile
1445          * and will require that new values be passed in
1446          */
1447         data->custom_profile_mode[0] = 0;
1448         data->custom_profile_mode[1] = 0;
1449         data->custom_profile_mode[2] = 0;
1450         data->custom_profile_mode[3] = 0;
1451
1452         /* save a copy of the default DPM table */
1453         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1454                         sizeof(struct vega10_dpm_table));
1455
1456         return 0;
1457 }
1458
1459 /*
1460  * vega10_populate_ulv_state
1461  * Function to provide parameters for Utral Low Voltage state to SMC.
1462  *
1463  * @hwmgr: - the address of the hardware manager.
1464  * return:   Always 0.
1465  */
1466 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1467 {
1468         struct vega10_hwmgr *data = hwmgr->backend;
1469         struct phm_ppt_v2_information *table_info =
1470                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1471
1472         data->smc_state_table.pp_table.UlvOffsetVid =
1473                         (uint8_t)table_info->us_ulv_voltage_offset;
1474
1475         data->smc_state_table.pp_table.UlvSmnclkDid =
1476                         (uint8_t)(table_info->us_ulv_smnclk_did);
1477         data->smc_state_table.pp_table.UlvMp1clkDid =
1478                         (uint8_t)(table_info->us_ulv_mp1clk_did);
1479         data->smc_state_table.pp_table.UlvGfxclkBypass =
1480                         (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1481         data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1482                         (uint8_t)(data->vddc_voltage_table.psi0_enable);
1483         data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1484                         (uint8_t)(data->vddc_voltage_table.psi1_enable);
1485
1486         return 0;
1487 }
1488
1489 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1490                 uint32_t lclock, uint8_t *curr_lclk_did)
1491 {
1492         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1493
1494         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1495                         hwmgr,
1496                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1497                         lclock, &dividers),
1498                         "Failed to get LCLK clock settings from VBIOS!",
1499                         return -1);
1500
1501         *curr_lclk_did = dividers.ulDid;
1502
1503         return 0;
1504 }
1505
1506 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr)
1507 {
1508         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
1509         struct vega10_hwmgr *data =
1510                         (struct vega10_hwmgr *)(hwmgr->backend);
1511         uint32_t pcie_gen = 0, pcie_width = 0;
1512         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1513         int i;
1514
1515         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1516                 pcie_gen = 3;
1517         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1518                 pcie_gen = 2;
1519         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1520                 pcie_gen = 1;
1521         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1522                 pcie_gen = 0;
1523
1524         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1525                 pcie_width = 6;
1526         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1527                 pcie_width = 5;
1528         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1529                 pcie_width = 4;
1530         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1531                 pcie_width = 3;
1532         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1533                 pcie_width = 2;
1534         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1535                 pcie_width = 1;
1536
1537         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1538                 if (pp_table->PcieGenSpeed[i] > pcie_gen)
1539                         pp_table->PcieGenSpeed[i] = pcie_gen;
1540
1541                 if (pp_table->PcieLaneCount[i] > pcie_width)
1542                         pp_table->PcieLaneCount[i] = pcie_width;
1543         }
1544
1545         if (data->registry_data.pcie_dpm_key_disabled) {
1546                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1547                         pp_table->PcieGenSpeed[i] = pcie_gen;
1548                         pp_table->PcieLaneCount[i] = pcie_width;
1549                 }
1550         }
1551
1552         return 0;
1553 }
1554
1555 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1556 {
1557         int result = -1;
1558         struct vega10_hwmgr *data = hwmgr->backend;
1559         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1560         struct vega10_pcie_table *pcie_table =
1561                         &(data->dpm_table.pcie_table);
1562         uint32_t i, j;
1563
1564         for (i = 0; i < pcie_table->count; i++) {
1565                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1566                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1567
1568                 result = vega10_populate_single_lclk_level(hwmgr,
1569                                 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1570                 if (result) {
1571                         pr_info("Populate LClock Level %d Failed!\n", i);
1572                         return result;
1573                 }
1574         }
1575
1576         j = i - 1;
1577         while (i < NUM_LINK_LEVELS) {
1578                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1579                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1580
1581                 result = vega10_populate_single_lclk_level(hwmgr,
1582                                 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1583                 if (result) {
1584                         pr_info("Populate LClock Level %d Failed!\n", i);
1585                         return result;
1586                 }
1587                 i++;
1588         }
1589
1590         return result;
1591 }
1592
1593 /**
1594  * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure
1595  *                                    using the provided engine clock
1596  *
1597  * @hwmgr:      the address of the hardware manager
1598  * @gfx_clock:  the GFX clock to use to populate the structure.
1599  * @current_gfxclk_level:  location in PPTable for the SMC GFXCLK structure.
1600  * @acg_freq:   ACG frequenty to return (MHz)
1601  */
1602 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1603                 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1604                 uint32_t *acg_freq)
1605 {
1606         struct phm_ppt_v2_information *table_info =
1607                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1608         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1609         struct vega10_hwmgr *data = hwmgr->backend;
1610         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1611         uint32_t gfx_max_clock =
1612                         hwmgr->platform_descriptor.overdriveLimit.engineClock;
1613         uint32_t i = 0;
1614
1615         if (hwmgr->od_enabled)
1616                 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1617                                                 &(data->odn_dpm_table.vdd_dep_on_sclk);
1618         else
1619                 dep_on_sclk = table_info->vdd_dep_on_sclk;
1620
1621         PP_ASSERT_WITH_CODE(dep_on_sclk,
1622                         "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1623                         return -EINVAL);
1624
1625         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1626                 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1627         else {
1628                 for (i = 0; i < dep_on_sclk->count; i++) {
1629                         if (dep_on_sclk->entries[i].clk == gfx_clock)
1630                                 break;
1631                 }
1632                 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1633                                 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1634                                 return -EINVAL);
1635         }
1636
1637         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1638                         COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1639                         gfx_clock, &dividers),
1640                         "Failed to get GFX Clock settings from VBIOS!",
1641                         return -EINVAL);
1642
1643         /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1644         current_gfxclk_level->FbMult =
1645                         cpu_to_le32(dividers.ulPll_fb_mult);
1646         /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1647         current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1648         current_gfxclk_level->SsFbMult =
1649                         cpu_to_le32(dividers.ulPll_ss_fbsmult);
1650         current_gfxclk_level->SsSlewFrac =
1651                         cpu_to_le16(dividers.usPll_ss_slew_frac);
1652         current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1653
1654         *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1655
1656         return 0;
1657 }
1658
1659 /**
1660  * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure
1661  *                                    using the provided clock.
1662  *
1663  * @hwmgr:     the address of the hardware manager.
1664  * @soc_clock: the SOC clock to use to populate the structure.
1665  * @current_soc_did:   DFS divider to pass back to caller
1666  * @current_vol_index: index of current VDD to pass back to caller
1667  * return:      0 on success
1668  */
1669 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1670                 uint32_t soc_clock, uint8_t *current_soc_did,
1671                 uint8_t *current_vol_index)
1672 {
1673         struct vega10_hwmgr *data = hwmgr->backend;
1674         struct phm_ppt_v2_information *table_info =
1675                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1676         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1677         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1678         uint32_t i;
1679
1680         if (hwmgr->od_enabled) {
1681                 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1682                                                 &data->odn_dpm_table.vdd_dep_on_socclk;
1683                 for (i = 0; i < dep_on_soc->count; i++) {
1684                         if (dep_on_soc->entries[i].clk >= soc_clock)
1685                                 break;
1686                 }
1687         } else {
1688                 dep_on_soc = table_info->vdd_dep_on_socclk;
1689                 for (i = 0; i < dep_on_soc->count; i++) {
1690                         if (dep_on_soc->entries[i].clk == soc_clock)
1691                                 break;
1692                 }
1693         }
1694
1695         PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1696                         "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1697                         return -EINVAL);
1698
1699         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1700                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1701                         soc_clock, &dividers),
1702                         "Failed to get SOC Clock settings from VBIOS!",
1703                         return -EINVAL);
1704
1705         *current_soc_did = (uint8_t)dividers.ulDid;
1706         *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1707         return 0;
1708 }
1709
1710 /**
1711  * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure
1712  *                                      based on the trimmed allowed dpm engine clock states
1713  *
1714  * @hwmgr:      the address of the hardware manager
1715  */
1716 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1717 {
1718         struct vega10_hwmgr *data = hwmgr->backend;
1719         struct phm_ppt_v2_information *table_info =
1720                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1721         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1722         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1723         int result = 0;
1724         uint32_t i, j;
1725
1726         for (i = 0; i < dpm_table->count; i++) {
1727                 result = vega10_populate_single_gfx_level(hwmgr,
1728                                 dpm_table->dpm_levels[i].value,
1729                                 &(pp_table->GfxclkLevel[i]),
1730                                 &(pp_table->AcgFreqTable[i]));
1731                 if (result)
1732                         return result;
1733         }
1734
1735         j = i - 1;
1736         while (i < NUM_GFXCLK_DPM_LEVELS) {
1737                 result = vega10_populate_single_gfx_level(hwmgr,
1738                                 dpm_table->dpm_levels[j].value,
1739                                 &(pp_table->GfxclkLevel[i]),
1740                                 &(pp_table->AcgFreqTable[i]));
1741                 if (result)
1742                         return result;
1743                 i++;
1744         }
1745
1746         pp_table->GfxclkSlewRate =
1747                         cpu_to_le16(table_info->us_gfxclk_slew_rate);
1748
1749         dpm_table = &(data->dpm_table.soc_table);
1750         for (i = 0; i < dpm_table->count; i++) {
1751                 result = vega10_populate_single_soc_level(hwmgr,
1752                                 dpm_table->dpm_levels[i].value,
1753                                 &(pp_table->SocclkDid[i]),
1754                                 &(pp_table->SocDpmVoltageIndex[i]));
1755                 if (result)
1756                         return result;
1757         }
1758
1759         j = i - 1;
1760         while (i < NUM_SOCCLK_DPM_LEVELS) {
1761                 result = vega10_populate_single_soc_level(hwmgr,
1762                                 dpm_table->dpm_levels[j].value,
1763                                 &(pp_table->SocclkDid[i]),
1764                                 &(pp_table->SocDpmVoltageIndex[i]));
1765                 if (result)
1766                         return result;
1767                 i++;
1768         }
1769
1770         return result;
1771 }
1772
1773 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1774 {
1775         struct vega10_hwmgr *data = hwmgr->backend;
1776         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1777         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1778         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1779
1780         uint8_t soc_vid = 0;
1781         uint32_t i, max_vddc_level;
1782
1783         if (hwmgr->od_enabled)
1784                 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1785         else
1786                 vddc_lookup_table = table_info->vddc_lookup_table;
1787
1788         max_vddc_level = vddc_lookup_table->count;
1789         for (i = 0; i < max_vddc_level; i++) {
1790                 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1791                 pp_table->SocVid[i] = soc_vid;
1792         }
1793         while (i < MAX_REGULAR_DPM_NUMBER) {
1794                 pp_table->SocVid[i] = soc_vid;
1795                 i++;
1796         }
1797 }
1798
1799 /*
1800  * Populates single SMC GFXCLK structure using the provided clock.
1801  *
1802  * @hwmgr:     the address of the hardware manager.
1803  * @mem_clock: the memory clock to use to populate the structure.
1804  * return:     0 on success..
1805  */
1806 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1807                 uint32_t mem_clock, uint8_t *current_mem_vid,
1808                 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1809 {
1810         struct vega10_hwmgr *data = hwmgr->backend;
1811         struct phm_ppt_v2_information *table_info =
1812                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1813         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1814         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1815         uint32_t mem_max_clock =
1816                         hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1817         uint32_t i = 0;
1818
1819         if (hwmgr->od_enabled)
1820                 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1821                                         &data->odn_dpm_table.vdd_dep_on_mclk;
1822         else
1823                 dep_on_mclk = table_info->vdd_dep_on_mclk;
1824
1825         PP_ASSERT_WITH_CODE(dep_on_mclk,
1826                         "Invalid SOC_VDD-UCLK Dependency Table!",
1827                         return -EINVAL);
1828
1829         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1830                 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1831         } else {
1832                 for (i = 0; i < dep_on_mclk->count; i++) {
1833                         if (dep_on_mclk->entries[i].clk == mem_clock)
1834                                 break;
1835                 }
1836                 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1837                                 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1838                                 return -EINVAL);
1839         }
1840
1841         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1842                         hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1843                         "Failed to get UCLK settings from VBIOS!",
1844                         return -1);
1845
1846         *current_mem_vid =
1847                         (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1848         *current_mem_soc_vind =
1849                         (uint8_t)(dep_on_mclk->entries[i].vddInd);
1850         current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1851         current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1852
1853         PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1854                         "Invalid Divider ID!",
1855                         return -EINVAL);
1856
1857         return 0;
1858 }
1859
1860 /**
1861  * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure
1862  *                                     based on the trimmed allowed dpm memory clock states.
1863  *
1864  * @hwmgr:  the address of the hardware manager.
1865  * return:   PP_Result_OK on success.
1866  */
1867 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1868 {
1869         struct vega10_hwmgr *data = hwmgr->backend;
1870         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1871         struct vega10_single_dpm_table *dpm_table =
1872                         &(data->dpm_table.mem_table);
1873         int result = 0;
1874         uint32_t i, j;
1875
1876         for (i = 0; i < dpm_table->count; i++) {
1877                 result = vega10_populate_single_memory_level(hwmgr,
1878                                 dpm_table->dpm_levels[i].value,
1879                                 &(pp_table->MemVid[i]),
1880                                 &(pp_table->UclkLevel[i]),
1881                                 &(pp_table->MemSocVoltageIndex[i]));
1882                 if (result)
1883                         return result;
1884         }
1885
1886         j = i - 1;
1887         while (i < NUM_UCLK_DPM_LEVELS) {
1888                 result = vega10_populate_single_memory_level(hwmgr,
1889                                 dpm_table->dpm_levels[j].value,
1890                                 &(pp_table->MemVid[i]),
1891                                 &(pp_table->UclkLevel[i]),
1892                                 &(pp_table->MemSocVoltageIndex[i]));
1893                 if (result)
1894                         return result;
1895                 i++;
1896         }
1897
1898         pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1899         pp_table->MemoryChannelWidth =
1900                         (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1901                                         channel_number[data->mem_channels]);
1902
1903         pp_table->LowestUclkReservedForUlv =
1904                         (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1905
1906         return result;
1907 }
1908
1909 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1910                 DSPCLK_e disp_clock)
1911 {
1912         struct vega10_hwmgr *data = hwmgr->backend;
1913         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1914         struct phm_ppt_v2_information *table_info =
1915                         (struct phm_ppt_v2_information *)
1916                         (hwmgr->pptable);
1917         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1918         uint32_t i;
1919         uint16_t clk = 0, vddc = 0;
1920         uint8_t vid = 0;
1921
1922         switch (disp_clock) {
1923         case DSPCLK_DCEFCLK:
1924                 dep_table = table_info->vdd_dep_on_dcefclk;
1925                 break;
1926         case DSPCLK_DISPCLK:
1927                 dep_table = table_info->vdd_dep_on_dispclk;
1928                 break;
1929         case DSPCLK_PIXCLK:
1930                 dep_table = table_info->vdd_dep_on_pixclk;
1931                 break;
1932         case DSPCLK_PHYCLK:
1933                 dep_table = table_info->vdd_dep_on_phyclk;
1934                 break;
1935         default:
1936                 return -1;
1937         }
1938
1939         PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1940                         "Number Of Entries Exceeded maximum!",
1941                         return -1);
1942
1943         for (i = 0; i < dep_table->count; i++) {
1944                 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1945                 vddc = table_info->vddc_lookup_table->
1946                                 entries[dep_table->entries[i].vddInd].us_vdd;
1947                 vid = (uint8_t)convert_to_vid(vddc);
1948                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1949                                 cpu_to_le16(clk);
1950                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1951                                 cpu_to_le16(vid);
1952         }
1953
1954         while (i < NUM_DSPCLK_LEVELS) {
1955                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1956                                 cpu_to_le16(clk);
1957                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1958                                 cpu_to_le16(vid);
1959                 i++;
1960         }
1961
1962         return 0;
1963 }
1964
1965 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1966 {
1967         uint32_t i;
1968
1969         for (i = 0; i < DSPCLK_COUNT; i++) {
1970                 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1971                                 "Failed to populate Clock in DisplayClockTable!",
1972                                 return -1);
1973         }
1974
1975         return 0;
1976 }
1977
1978 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1979                 uint32_t eclock, uint8_t *current_eclk_did,
1980                 uint8_t *current_soc_vol)
1981 {
1982         struct phm_ppt_v2_information *table_info =
1983                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1984         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1985                         table_info->mm_dep_table;
1986         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1987         uint32_t i;
1988
1989         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1990                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1991                         eclock, &dividers),
1992                         "Failed to get ECLK clock settings from VBIOS!",
1993                         return -1);
1994
1995         *current_eclk_did = (uint8_t)dividers.ulDid;
1996
1997         for (i = 0; i < dep_table->count; i++) {
1998                 if (dep_table->entries[i].eclk == eclock)
1999                         *current_soc_vol = dep_table->entries[i].vddcInd;
2000         }
2001
2002         return 0;
2003 }
2004
2005 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
2006 {
2007         struct vega10_hwmgr *data = hwmgr->backend;
2008         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2009         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
2010         int result = -EINVAL;
2011         uint32_t i, j;
2012
2013         for (i = 0; i < dpm_table->count; i++) {
2014                 result = vega10_populate_single_eclock_level(hwmgr,
2015                                 dpm_table->dpm_levels[i].value,
2016                                 &(pp_table->EclkDid[i]),
2017                                 &(pp_table->VceDpmVoltageIndex[i]));
2018                 if (result)
2019                         return result;
2020         }
2021
2022         j = i - 1;
2023         while (i < NUM_VCE_DPM_LEVELS) {
2024                 result = vega10_populate_single_eclock_level(hwmgr,
2025                                 dpm_table->dpm_levels[j].value,
2026                                 &(pp_table->EclkDid[i]),
2027                                 &(pp_table->VceDpmVoltageIndex[i]));
2028                 if (result)
2029                         return result;
2030                 i++;
2031         }
2032
2033         return result;
2034 }
2035
2036 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
2037                 uint32_t vclock, uint8_t *current_vclk_did)
2038 {
2039         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2040
2041         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2042                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2043                         vclock, &dividers),
2044                         "Failed to get VCLK clock settings from VBIOS!",
2045                         return -EINVAL);
2046
2047         *current_vclk_did = (uint8_t)dividers.ulDid;
2048
2049         return 0;
2050 }
2051
2052 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
2053                 uint32_t dclock, uint8_t *current_dclk_did)
2054 {
2055         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2056
2057         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2058                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2059                         dclock, &dividers),
2060                         "Failed to get DCLK clock settings from VBIOS!",
2061                         return -EINVAL);
2062
2063         *current_dclk_did = (uint8_t)dividers.ulDid;
2064
2065         return 0;
2066 }
2067
2068 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
2069 {
2070         struct vega10_hwmgr *data = hwmgr->backend;
2071         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2072         struct vega10_single_dpm_table *vclk_dpm_table =
2073                         &(data->dpm_table.vclk_table);
2074         struct vega10_single_dpm_table *dclk_dpm_table =
2075                         &(data->dpm_table.dclk_table);
2076         struct phm_ppt_v2_information *table_info =
2077                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2078         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
2079                         table_info->mm_dep_table;
2080         int result = -EINVAL;
2081         uint32_t i, j;
2082
2083         for (i = 0; i < vclk_dpm_table->count; i++) {
2084                 result = vega10_populate_single_vclock_level(hwmgr,
2085                                 vclk_dpm_table->dpm_levels[i].value,
2086                                 &(pp_table->VclkDid[i]));
2087                 if (result)
2088                         return result;
2089         }
2090
2091         j = i - 1;
2092         while (i < NUM_UVD_DPM_LEVELS) {
2093                 result = vega10_populate_single_vclock_level(hwmgr,
2094                                 vclk_dpm_table->dpm_levels[j].value,
2095                                 &(pp_table->VclkDid[i]));
2096                 if (result)
2097                         return result;
2098                 i++;
2099         }
2100
2101         for (i = 0; i < dclk_dpm_table->count; i++) {
2102                 result = vega10_populate_single_dclock_level(hwmgr,
2103                                 dclk_dpm_table->dpm_levels[i].value,
2104                                 &(pp_table->DclkDid[i]));
2105                 if (result)
2106                         return result;
2107         }
2108
2109         j = i - 1;
2110         while (i < NUM_UVD_DPM_LEVELS) {
2111                 result = vega10_populate_single_dclock_level(hwmgr,
2112                                 dclk_dpm_table->dpm_levels[j].value,
2113                                 &(pp_table->DclkDid[i]));
2114                 if (result)
2115                         return result;
2116                 i++;
2117         }
2118
2119         for (i = 0; i < dep_table->count; i++) {
2120                 if (dep_table->entries[i].vclk ==
2121                                 vclk_dpm_table->dpm_levels[i].value &&
2122                         dep_table->entries[i].dclk ==
2123                                 dclk_dpm_table->dpm_levels[i].value)
2124                         pp_table->UvdDpmVoltageIndex[i] =
2125                                         dep_table->entries[i].vddcInd;
2126                 else
2127                         return -1;
2128         }
2129
2130         j = i - 1;
2131         while (i < NUM_UVD_DPM_LEVELS) {
2132                 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2133                 i++;
2134         }
2135
2136         return 0;
2137 }
2138
2139 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2140 {
2141         struct vega10_hwmgr *data = hwmgr->backend;
2142         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2143         struct phm_ppt_v2_information *table_info =
2144                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2145         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2146                         table_info->vdd_dep_on_sclk;
2147         uint32_t i;
2148
2149         for (i = 0; i < dep_table->count; i++) {
2150                 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2151                 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2152                                 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2153         }
2154
2155         return 0;
2156 }
2157
2158 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2159 {
2160         struct vega10_hwmgr *data = hwmgr->backend;
2161         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2162         struct phm_ppt_v2_information *table_info =
2163                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2164         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2165                         table_info->vdd_dep_on_sclk;
2166         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2167         int result = 0;
2168         uint32_t i;
2169
2170         pp_table->MinVoltageVid = (uint8_t)0xff;
2171         pp_table->MaxVoltageVid = (uint8_t)0;
2172
2173         if (data->smu_features[GNLD_AVFS].supported) {
2174                 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2175                 if (!result) {
2176                         pp_table->MinVoltageVid = (uint8_t)
2177                                         convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2178                         pp_table->MaxVoltageVid = (uint8_t)
2179                                         convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2180
2181                         pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2182                         pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2183                         pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2184                         pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2185                         pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2186                         pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2187                         pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2188
2189                         pp_table->BtcGbVdroopTableCksOff.a0 =
2190                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2191                         pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2192                         pp_table->BtcGbVdroopTableCksOff.a1 =
2193                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2194                         pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2195                         pp_table->BtcGbVdroopTableCksOff.a2 =
2196                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2197                         pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2198
2199                         pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2200                         pp_table->BtcGbVdroopTableCksOn.a0 =
2201                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2202                         pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2203                         pp_table->BtcGbVdroopTableCksOn.a1 =
2204                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2205                         pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2206                         pp_table->BtcGbVdroopTableCksOn.a2 =
2207                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2208                         pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2209
2210                         pp_table->AvfsGbCksOn.m1 =
2211                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2212                         pp_table->AvfsGbCksOn.m2 =
2213                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2214                         pp_table->AvfsGbCksOn.b =
2215                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2216                         pp_table->AvfsGbCksOn.m1_shift = 24;
2217                         pp_table->AvfsGbCksOn.m2_shift = 12;
2218                         pp_table->AvfsGbCksOn.b_shift = 0;
2219
2220                         pp_table->OverrideAvfsGbCksOn =
2221                                         avfs_params.ucEnableGbFuseTableCkson;
2222                         pp_table->AvfsGbCksOff.m1 =
2223                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2224                         pp_table->AvfsGbCksOff.m2 =
2225                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2226                         pp_table->AvfsGbCksOff.b =
2227                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2228                         pp_table->AvfsGbCksOff.m1_shift = 24;
2229                         pp_table->AvfsGbCksOff.m2_shift = 12;
2230                         pp_table->AvfsGbCksOff.b_shift = 0;
2231
2232                         for (i = 0; i < dep_table->count; i++)
2233                                 pp_table->StaticVoltageOffsetVid[i] =
2234                                                 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2235
2236                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2237                                         data->disp_clk_quad_eqn_a) &&
2238                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2239                                         data->disp_clk_quad_eqn_b)) {
2240                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2241                                                 (int32_t)data->disp_clk_quad_eqn_a;
2242                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2243                                                 (int32_t)data->disp_clk_quad_eqn_b;
2244                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2245                                                 (int32_t)data->disp_clk_quad_eqn_c;
2246                         } else {
2247                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2248                                                 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2249                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2250                                                 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2251                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2252                                                 (int32_t)avfs_params.ulDispclk2GfxclkB;
2253                         }
2254
2255                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2256                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2257                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2258
2259                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2260                                         data->dcef_clk_quad_eqn_a) &&
2261                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2262                                         data->dcef_clk_quad_eqn_b)) {
2263                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2264                                                 (int32_t)data->dcef_clk_quad_eqn_a;
2265                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2266                                                 (int32_t)data->dcef_clk_quad_eqn_b;
2267                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2268                                                 (int32_t)data->dcef_clk_quad_eqn_c;
2269                         } else {
2270                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2271                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2272                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2273                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2274                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2275                                                 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2276                         }
2277
2278                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2279                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2280                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2281
2282                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2283                                         data->pixel_clk_quad_eqn_a) &&
2284                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2285                                         data->pixel_clk_quad_eqn_b)) {
2286                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2287                                                 (int32_t)data->pixel_clk_quad_eqn_a;
2288                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2289                                                 (int32_t)data->pixel_clk_quad_eqn_b;
2290                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2291                                                 (int32_t)data->pixel_clk_quad_eqn_c;
2292                         } else {
2293                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2294                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2295                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2296                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2297                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2298                                                 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2299                         }
2300
2301                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2302                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2303                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2304                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2305                                         data->phy_clk_quad_eqn_a) &&
2306                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2307                                         data->phy_clk_quad_eqn_b)) {
2308                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2309                                                 (int32_t)data->phy_clk_quad_eqn_a;
2310                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2311                                                 (int32_t)data->phy_clk_quad_eqn_b;
2312                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2313                                                 (int32_t)data->phy_clk_quad_eqn_c;
2314                         } else {
2315                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2316                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2317                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2318                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2319                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2320                                                 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2321                         }
2322
2323                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2324                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2325                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2326
2327                         pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2328                         pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2329                         pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2330                         pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2331                         pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2332                         pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2333
2334                         pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2335                         pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2336                         pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2337                         pp_table->AcgAvfsGb.m1_shift             = 24;
2338                         pp_table->AcgAvfsGb.m2_shift             = 12;
2339                         pp_table->AcgAvfsGb.b_shift              = 0;
2340
2341                 } else {
2342                         data->smu_features[GNLD_AVFS].supported = false;
2343                 }
2344         }
2345
2346         return 0;
2347 }
2348
2349 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2350 {
2351         struct vega10_hwmgr *data = hwmgr->backend;
2352         uint32_t agc_btc_response;
2353
2354         if (data->smu_features[GNLD_ACG].supported) {
2355                 if (0 == vega10_enable_smc_features(hwmgr, true,
2356                                         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2357                         data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2358
2359                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL);
2360
2361                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response);
2362
2363                 if (1 == agc_btc_response) {
2364                         if (1 == data->acg_loop_state)
2365                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL);
2366                         else if (2 == data->acg_loop_state)
2367                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL);
2368                         if (0 == vega10_enable_smc_features(hwmgr, true,
2369                                 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2370                                         data->smu_features[GNLD_ACG].enabled = true;
2371                 } else {
2372                         pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2373                         data->smu_features[GNLD_ACG].enabled = false;
2374                 }
2375         }
2376
2377         return 0;
2378 }
2379
2380 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2381 {
2382         struct vega10_hwmgr *data = hwmgr->backend;
2383
2384         if (data->smu_features[GNLD_ACG].supported &&
2385             data->smu_features[GNLD_ACG].enabled)
2386                 if (!vega10_enable_smc_features(hwmgr, false,
2387                         data->smu_features[GNLD_ACG].smu_feature_bitmap))
2388                         data->smu_features[GNLD_ACG].enabled = false;
2389
2390         return 0;
2391 }
2392
2393 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2394 {
2395         struct vega10_hwmgr *data = hwmgr->backend;
2396         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2397         struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2398         int result;
2399
2400         result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2401         if (!result) {
2402                 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2403                     data->registry_data.regulator_hot_gpio_support) {
2404                         pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2405                         pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2406                         pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2407                         pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2408                 } else {
2409                         pp_table->VR0HotGpio = 0;
2410                         pp_table->VR0HotPolarity = 0;
2411                         pp_table->VR1HotGpio = 0;
2412                         pp_table->VR1HotPolarity = 0;
2413                 }
2414
2415                 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2416                     data->registry_data.ac_dc_switch_gpio_support) {
2417                         pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2418                         pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2419                 } else {
2420                         pp_table->AcDcGpio = 0;
2421                         pp_table->AcDcPolarity = 0;
2422                 }
2423         }
2424
2425         return result;
2426 }
2427
2428 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2429 {
2430         struct vega10_hwmgr *data = hwmgr->backend;
2431
2432         if (data->smu_features[GNLD_AVFS].supported) {
2433                 /* Already enabled or disabled */
2434                 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
2435                         return 0;
2436
2437                 if (enable) {
2438                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2439                                         true,
2440                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2441                                         "[avfs_control] Attempt to Enable AVFS feature Failed!",
2442                                         return -1);
2443                         data->smu_features[GNLD_AVFS].enabled = true;
2444                 } else {
2445                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2446                                         false,
2447                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2448                                         "[avfs_control] Attempt to Disable AVFS feature Failed!",
2449                                         return -1);
2450                         data->smu_features[GNLD_AVFS].enabled = false;
2451                 }
2452         }
2453
2454         return 0;
2455 }
2456
2457 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2458 {
2459         struct vega10_hwmgr *data = hwmgr->backend;
2460
2461         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2462                 vega10_avfs_enable(hwmgr, false);
2463         } else if (data->need_update_dpm_table) {
2464                 vega10_avfs_enable(hwmgr, false);
2465                 vega10_avfs_enable(hwmgr, true);
2466         } else {
2467                 vega10_avfs_enable(hwmgr, true);
2468         }
2469
2470         return 0;
2471 }
2472
2473 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2474 {
2475         int result = 0;
2476
2477         uint64_t serial_number = 0;
2478         uint32_t top32, bottom32;
2479         struct phm_fuses_default fuse;
2480
2481         struct vega10_hwmgr *data = hwmgr->backend;
2482         AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2483
2484         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
2485
2486         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
2487
2488         serial_number = ((uint64_t)bottom32 << 32) | top32;
2489
2490         if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2491                 avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2492                 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2493                 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2494                 avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2495                 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2496                 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2497                 avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2498                 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2499                 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2500                 result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2501                                                 AVFSFUSETABLE, false);
2502                 PP_ASSERT_WITH_CODE(!result,
2503                         "Failed to upload FuseOVerride!",
2504                         );
2505         }
2506
2507         return result;
2508 }
2509
2510 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2511 {
2512         struct vega10_hwmgr *data = hwmgr->backend;
2513         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2514         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2515         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2516         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2517         uint32_t i;
2518
2519         dep_table = table_info->vdd_dep_on_mclk;
2520         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2521
2522         for (i = 0; i < dep_table->count; i++) {
2523                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2524                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2525                         return;
2526                 }
2527         }
2528
2529         dep_table = table_info->vdd_dep_on_sclk;
2530         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2531         for (i = 0; i < dep_table->count; i++) {
2532                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2533                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2534                         return;
2535                 }
2536         }
2537 }
2538
2539 /**
2540  * vega10_init_smc_table - Initializes the SMC table and uploads it
2541  *
2542  * @hwmgr:  the address of the powerplay hardware manager.
2543  * return:  always 0
2544  */
2545 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2546 {
2547         int result;
2548         struct vega10_hwmgr *data = hwmgr->backend;
2549         struct phm_ppt_v2_information *table_info =
2550                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2551         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2552         struct pp_atomfwctrl_voltage_table voltage_table;
2553         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2554         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2555
2556         result = vega10_setup_default_dpm_tables(hwmgr);
2557         PP_ASSERT_WITH_CODE(!result,
2558                         "Failed to setup default DPM tables!",
2559                         return result);
2560
2561         if (!hwmgr->not_vf)
2562                 return 0;
2563
2564         /* initialize ODN table */
2565         if (hwmgr->od_enabled) {
2566                 if (odn_table->max_vddc) {
2567                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2568                         vega10_check_dpm_table_updated(hwmgr);
2569                 } else {
2570                         vega10_odn_initial_default_setting(hwmgr);
2571                 }
2572         }
2573
2574         pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2575                         VOLTAGE_OBJ_SVID2,  &voltage_table);
2576         pp_table->MaxVidStep = voltage_table.max_vid_step;
2577
2578         pp_table->GfxDpmVoltageMode =
2579                         (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2580         pp_table->SocDpmVoltageMode =
2581                         (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2582         pp_table->UclkDpmVoltageMode =
2583                         (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2584         pp_table->UvdDpmVoltageMode =
2585                         (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2586         pp_table->VceDpmVoltageMode =
2587                         (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2588         pp_table->Mp0DpmVoltageMode =
2589                         (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2590
2591         pp_table->DisplayDpmVoltageMode =
2592                         (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2593
2594         data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2595         data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2596
2597         if (data->registry_data.ulv_support &&
2598                         table_info->us_ulv_voltage_offset) {
2599                 result = vega10_populate_ulv_state(hwmgr);
2600                 PP_ASSERT_WITH_CODE(!result,
2601                                 "Failed to initialize ULV state!",
2602                                 return result);
2603         }
2604
2605         result = vega10_populate_smc_link_levels(hwmgr);
2606         PP_ASSERT_WITH_CODE(!result,
2607                         "Failed to initialize Link Level!",
2608                         return result);
2609
2610         result = vega10_override_pcie_parameters(hwmgr);
2611         PP_ASSERT_WITH_CODE(!result,
2612                         "Failed to override pcie parameters!",
2613                         return result);
2614
2615         result = vega10_populate_all_graphic_levels(hwmgr);
2616         PP_ASSERT_WITH_CODE(!result,
2617                         "Failed to initialize Graphics Level!",
2618                         return result);
2619
2620         result = vega10_populate_all_memory_levels(hwmgr);
2621         PP_ASSERT_WITH_CODE(!result,
2622                         "Failed to initialize Memory Level!",
2623                         return result);
2624
2625         vega10_populate_vddc_soc_levels(hwmgr);
2626
2627         result = vega10_populate_all_display_clock_levels(hwmgr);
2628         PP_ASSERT_WITH_CODE(!result,
2629                         "Failed to initialize Display Level!",
2630                         return result);
2631
2632         result = vega10_populate_smc_vce_levels(hwmgr);
2633         PP_ASSERT_WITH_CODE(!result,
2634                         "Failed to initialize VCE Level!",
2635                         return result);
2636
2637         result = vega10_populate_smc_uvd_levels(hwmgr);
2638         PP_ASSERT_WITH_CODE(!result,
2639                         "Failed to initialize UVD Level!",
2640                         return result);
2641
2642         if (data->registry_data.clock_stretcher_support) {
2643                 result = vega10_populate_clock_stretcher_table(hwmgr);
2644                 PP_ASSERT_WITH_CODE(!result,
2645                                 "Failed to populate Clock Stretcher Table!",
2646                                 return result);
2647         }
2648
2649         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2650         if (!result) {
2651                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2652                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2653                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2654                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2655                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2656                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2657                                 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk);
2658
2659                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2660                                 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk);
2661
2662                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2663                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2664                 if (0 != boot_up_values.usVddc) {
2665                         smum_send_msg_to_smc_with_parameter(hwmgr,
2666                                                 PPSMC_MSG_SetFloorSocVoltage,
2667                                                 (boot_up_values.usVddc * 4),
2668                                                 NULL);
2669                         data->vbios_boot_state.bsoc_vddc_lock = true;
2670                 } else {
2671                         data->vbios_boot_state.bsoc_vddc_lock = false;
2672                 }
2673                 smum_send_msg_to_smc_with_parameter(hwmgr,
2674                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
2675                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
2676                                 NULL);
2677         }
2678
2679         result = vega10_populate_avfs_parameters(hwmgr);
2680         PP_ASSERT_WITH_CODE(!result,
2681                         "Failed to initialize AVFS Parameters!",
2682                         return result);
2683
2684         result = vega10_populate_gpio_parameters(hwmgr);
2685         PP_ASSERT_WITH_CODE(!result,
2686                         "Failed to initialize GPIO Parameters!",
2687                         return result);
2688
2689         pp_table->GfxclkAverageAlpha = (uint8_t)
2690                         (data->gfxclk_average_alpha);
2691         pp_table->SocclkAverageAlpha = (uint8_t)
2692                         (data->socclk_average_alpha);
2693         pp_table->UclkAverageAlpha = (uint8_t)
2694                         (data->uclk_average_alpha);
2695         pp_table->GfxActivityAverageAlpha = (uint8_t)
2696                         (data->gfx_activity_average_alpha);
2697
2698         vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2699
2700         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2701
2702         PP_ASSERT_WITH_CODE(!result,
2703                         "Failed to upload PPtable!", return result);
2704
2705         result = vega10_avfs_enable(hwmgr, true);
2706         PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2707                                         return result);
2708         vega10_acg_enable(hwmgr);
2709
2710         return 0;
2711 }
2712
2713 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2714 {
2715         struct vega10_hwmgr *data = hwmgr->backend;
2716
2717         if (data->smu_features[GNLD_THERMAL].supported) {
2718                 if (data->smu_features[GNLD_THERMAL].enabled)
2719                         pr_info("THERMAL Feature Already enabled!");
2720
2721                 PP_ASSERT_WITH_CODE(
2722                                 !vega10_enable_smc_features(hwmgr,
2723                                 true,
2724                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2725                                 "Enable THERMAL Feature Failed!",
2726                                 return -1);
2727                 data->smu_features[GNLD_THERMAL].enabled = true;
2728         }
2729
2730         return 0;
2731 }
2732
2733 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2734 {
2735         struct vega10_hwmgr *data = hwmgr->backend;
2736
2737         if (data->smu_features[GNLD_THERMAL].supported) {
2738                 if (!data->smu_features[GNLD_THERMAL].enabled)
2739                         pr_info("THERMAL Feature Already disabled!");
2740
2741                 PP_ASSERT_WITH_CODE(
2742                                 !vega10_enable_smc_features(hwmgr,
2743                                 false,
2744                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2745                                 "disable THERMAL Feature Failed!",
2746                                 return -1);
2747                 data->smu_features[GNLD_THERMAL].enabled = false;
2748         }
2749
2750         return 0;
2751 }
2752
2753 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2754 {
2755         struct vega10_hwmgr *data = hwmgr->backend;
2756
2757         if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2758                 if (data->smu_features[GNLD_VR0HOT].supported) {
2759                         PP_ASSERT_WITH_CODE(
2760                                         !vega10_enable_smc_features(hwmgr,
2761                                         true,
2762                                         data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2763                                         "Attempt to Enable VR0 Hot feature Failed!",
2764                                         return -1);
2765                         data->smu_features[GNLD_VR0HOT].enabled = true;
2766                 } else {
2767                         if (data->smu_features[GNLD_VR1HOT].supported) {
2768                                 PP_ASSERT_WITH_CODE(
2769                                                 !vega10_enable_smc_features(hwmgr,
2770                                                 true,
2771                                                 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2772                                                 "Attempt to Enable VR0 Hot feature Failed!",
2773                                                 return -1);
2774                                 data->smu_features[GNLD_VR1HOT].enabled = true;
2775                         }
2776                 }
2777         }
2778         return 0;
2779 }
2780
2781 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2782 {
2783         struct vega10_hwmgr *data = hwmgr->backend;
2784
2785         if (data->registry_data.ulv_support) {
2786                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2787                                 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2788                                 "Enable ULV Feature Failed!",
2789                                 return -1);
2790                 data->smu_features[GNLD_ULV].enabled = true;
2791         }
2792
2793         return 0;
2794 }
2795
2796 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2797 {
2798         struct vega10_hwmgr *data = hwmgr->backend;
2799
2800         if (data->registry_data.ulv_support) {
2801                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2802                                 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2803                                 "disable ULV Feature Failed!",
2804                                 return -EINVAL);
2805                 data->smu_features[GNLD_ULV].enabled = false;
2806         }
2807
2808         return 0;
2809 }
2810
2811 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2812 {
2813         struct vega10_hwmgr *data = hwmgr->backend;
2814
2815         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2816                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2817                                 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2818                                 "Attempt to Enable DS_GFXCLK Feature Failed!",
2819                                 return -EINVAL);
2820                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2821         }
2822
2823         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2824                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2825                                 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2826                                 "Attempt to Enable DS_SOCCLK Feature Failed!",
2827                                 return -EINVAL);
2828                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2829         }
2830
2831         if (data->smu_features[GNLD_DS_LCLK].supported) {
2832                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2833                                 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2834                                 "Attempt to Enable DS_LCLK Feature Failed!",
2835                                 return -EINVAL);
2836                 data->smu_features[GNLD_DS_LCLK].enabled = true;
2837         }
2838
2839         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2840                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2841                                 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2842                                 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2843                                 return -EINVAL);
2844                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2845         }
2846
2847         return 0;
2848 }
2849
2850 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2851 {
2852         struct vega10_hwmgr *data = hwmgr->backend;
2853
2854         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2855                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2856                                 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2857                                 "Attempt to disable DS_GFXCLK Feature Failed!",
2858                                 return -EINVAL);
2859                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2860         }
2861
2862         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2863                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2864                                 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2865                                 "Attempt to disable DS_ Feature Failed!",
2866                                 return -EINVAL);
2867                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2868         }
2869
2870         if (data->smu_features[GNLD_DS_LCLK].supported) {
2871                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2872                                 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2873                                 "Attempt to disable DS_LCLK Feature Failed!",
2874                                 return -EINVAL);
2875                 data->smu_features[GNLD_DS_LCLK].enabled = false;
2876         }
2877
2878         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2879                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2880                                 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2881                                 "Attempt to disable DS_DCEFCLK Feature Failed!",
2882                                 return -EINVAL);
2883                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2884         }
2885
2886         return 0;
2887 }
2888
2889 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2890 {
2891         struct vega10_hwmgr *data = hwmgr->backend;
2892         uint32_t i, feature_mask = 0;
2893
2894         if (!hwmgr->not_vf)
2895                 return 0;
2896
2897         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2898                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2899                                 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2900                 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2901                 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2902         }
2903
2904         for (i = 0; i < GNLD_DPM_MAX; i++) {
2905                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2906                         if (data->smu_features[i].supported) {
2907                                 if (data->smu_features[i].enabled) {
2908                                         feature_mask |= data->smu_features[i].
2909                                                         smu_feature_bitmap;
2910                                         data->smu_features[i].enabled = false;
2911                                 }
2912                         }
2913                 }
2914         }
2915
2916         vega10_enable_smc_features(hwmgr, false, feature_mask);
2917
2918         return 0;
2919 }
2920
2921 /**
2922  * vega10_start_dpm - Tell SMC to enabled the supported DPMs.
2923  *
2924  * @hwmgr:   the address of the powerplay hardware manager.
2925  * @bitmap:  bitmap for the features to enabled.
2926  * return:  0 on at least one DPM is successfully enabled.
2927  */
2928 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2929 {
2930         struct vega10_hwmgr *data = hwmgr->backend;
2931         uint32_t i, feature_mask = 0;
2932
2933         for (i = 0; i < GNLD_DPM_MAX; i++) {
2934                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2935                         if (data->smu_features[i].supported) {
2936                                 if (!data->smu_features[i].enabled) {
2937                                         feature_mask |= data->smu_features[i].
2938                                                         smu_feature_bitmap;
2939                                         data->smu_features[i].enabled = true;
2940                                 }
2941                         }
2942                 }
2943         }
2944
2945         if (vega10_enable_smc_features(hwmgr,
2946                         true, feature_mask)) {
2947                 for (i = 0; i < GNLD_DPM_MAX; i++) {
2948                         if (data->smu_features[i].smu_feature_bitmap &
2949                                         feature_mask)
2950                                 data->smu_features[i].enabled = false;
2951                 }
2952         }
2953
2954         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2955                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2956                                 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2957                 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2958                 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2959         }
2960
2961         if (data->vbios_boot_state.bsoc_vddc_lock) {
2962                 smum_send_msg_to_smc_with_parameter(hwmgr,
2963                                                 PPSMC_MSG_SetFloorSocVoltage, 0,
2964                                                 NULL);
2965                 data->vbios_boot_state.bsoc_vddc_lock = false;
2966         }
2967
2968         if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2969                 if (data->smu_features[GNLD_ACDC].supported) {
2970                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2971                                         true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2972                                         "Attempt to Enable DS_GFXCLK Feature Failed!",
2973                                         return -1);
2974                         data->smu_features[GNLD_ACDC].enabled = true;
2975                 }
2976         }
2977
2978         if (data->registry_data.pcie_dpm_key_disabled) {
2979                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2980                                 false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap),
2981                 "Attempt to Disable Link DPM feature Failed!", return -EINVAL);
2982                 data->smu_features[GNLD_DPM_LINK].enabled = false;
2983                 data->smu_features[GNLD_DPM_LINK].supported = false;
2984         }
2985
2986         return 0;
2987 }
2988
2989
2990 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2991 {
2992         struct vega10_hwmgr *data = hwmgr->backend;
2993
2994         if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2995                 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2996                         pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
2997                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2998                                 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
2999                                 "Attempt to Enable PCC Limit feature Failed!",
3000                                 return -EINVAL);
3001                 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
3002         }
3003
3004         return 0;
3005 }
3006
3007 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
3008 {
3009         struct phm_ppt_v2_information *table_info =
3010                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3011
3012         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
3013             table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
3014                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
3015                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
3016         } else {
3017                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3018                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk;
3019         }
3020
3021         hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk;
3022         hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk;
3023
3024         /* make sure the output is in Mhz */
3025         hwmgr->pstate_sclk /= 100;
3026         hwmgr->pstate_mclk /= 100;
3027         hwmgr->pstate_sclk_peak /= 100;
3028         hwmgr->pstate_mclk_peak /= 100;
3029 }
3030
3031 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3032 {
3033         struct vega10_hwmgr *data = hwmgr->backend;
3034         int tmp_result, result = 0;
3035
3036         if (hwmgr->not_vf) {
3037                 vega10_enable_disable_PCC_limit_feature(hwmgr, true);
3038
3039                 smum_send_msg_to_smc_with_parameter(hwmgr,
3040                         PPSMC_MSG_ConfigureTelemetry, data->config_telemetry,
3041                         NULL);
3042
3043                 tmp_result = vega10_construct_voltage_tables(hwmgr);
3044                 PP_ASSERT_WITH_CODE(!tmp_result,
3045                                     "Failed to construct voltage tables!",
3046                                     result = tmp_result);
3047         }
3048
3049         if (hwmgr->not_vf || hwmgr->pp_one_vf) {
3050                 tmp_result = vega10_init_smc_table(hwmgr);
3051                 PP_ASSERT_WITH_CODE(!tmp_result,
3052                                     "Failed to initialize SMC table!",
3053                                     result = tmp_result);
3054         }
3055
3056         if (hwmgr->not_vf) {
3057                 if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
3058                         tmp_result = vega10_enable_thermal_protection(hwmgr);
3059                         PP_ASSERT_WITH_CODE(!tmp_result,
3060                                             "Failed to enable thermal protection!",
3061                                             result = tmp_result);
3062                 }
3063
3064                 tmp_result = vega10_enable_vrhot_feature(hwmgr);
3065                 PP_ASSERT_WITH_CODE(!tmp_result,
3066                                     "Failed to enable VR hot feature!",
3067                                     result = tmp_result);
3068
3069                 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
3070                 PP_ASSERT_WITH_CODE(!tmp_result,
3071                                     "Failed to enable deep sleep master switch!",
3072                                     result = tmp_result);
3073         }
3074
3075         if (hwmgr->not_vf) {
3076                 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
3077                 PP_ASSERT_WITH_CODE(!tmp_result,
3078                                     "Failed to start DPM!", result = tmp_result);
3079         }
3080
3081         if (hwmgr->not_vf) {
3082                 /* enable didt, do not abort if failed didt */
3083                 tmp_result = vega10_enable_didt_config(hwmgr);
3084                 PP_ASSERT(!tmp_result,
3085                           "Failed to enable didt config!");
3086         }
3087
3088         tmp_result = vega10_enable_power_containment(hwmgr);
3089         PP_ASSERT_WITH_CODE(!tmp_result,
3090                             "Failed to enable power containment!",
3091                             result = tmp_result);
3092
3093         if (hwmgr->not_vf) {
3094                 tmp_result = vega10_power_control_set_level(hwmgr);
3095                 PP_ASSERT_WITH_CODE(!tmp_result,
3096                                     "Failed to power control set level!",
3097                                     result = tmp_result);
3098
3099                 tmp_result = vega10_enable_ulv(hwmgr);
3100                 PP_ASSERT_WITH_CODE(!tmp_result,
3101                                     "Failed to enable ULV!",
3102                                     result = tmp_result);
3103         }
3104
3105         vega10_populate_umdpstate_clocks(hwmgr);
3106
3107         return result;
3108 }
3109
3110 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
3111 {
3112         return sizeof(struct vega10_power_state);
3113 }
3114
3115 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3116                 void *state, struct pp_power_state *power_state,
3117                 void *pp_table, uint32_t classification_flag)
3118 {
3119         ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
3120         struct vega10_power_state *vega10_ps =
3121                         cast_phw_vega10_power_state(&(power_state->hardware));
3122         struct vega10_performance_level *performance_level;
3123         ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
3124         ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
3125                         (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
3126         ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
3127                         (ATOM_Vega10_SOCCLK_Dependency_Table *)
3128                         (((unsigned long)powerplay_table) +
3129                         le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
3130         ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
3131                         (ATOM_Vega10_GFXCLK_Dependency_Table *)
3132                         (((unsigned long)powerplay_table) +
3133                         le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
3134         ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
3135                         (ATOM_Vega10_MCLK_Dependency_Table *)
3136                         (((unsigned long)powerplay_table) +
3137                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3138
3139
3140         /* The following fields are not initialized here:
3141          * id orderedList allStatesList
3142          */
3143         power_state->classification.ui_label =
3144                         (le16_to_cpu(state_entry->usClassification) &
3145                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3146                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3147         power_state->classification.flags = classification_flag;
3148         /* NOTE: There is a classification2 flag in BIOS
3149          * that is not being used right now
3150          */
3151         power_state->classification.temporary_state = false;
3152         power_state->classification.to_be_deleted = false;
3153
3154         power_state->validation.disallowOnDC =
3155                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3156                                         ATOM_Vega10_DISALLOW_ON_DC) != 0);
3157
3158         power_state->display.disableFrameModulation = false;
3159         power_state->display.limitRefreshrate = false;
3160         power_state->display.enableVariBright =
3161                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3162                                         ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3163
3164         power_state->validation.supportedPowerLevels = 0;
3165         power_state->uvd_clocks.VCLK = 0;
3166         power_state->uvd_clocks.DCLK = 0;
3167         power_state->temperatures.min = 0;
3168         power_state->temperatures.max = 0;
3169
3170         performance_level = &(vega10_ps->performance_levels
3171                         [vega10_ps->performance_level_count++]);
3172
3173         PP_ASSERT_WITH_CODE(
3174                         (vega10_ps->performance_level_count <
3175                                         NUM_GFXCLK_DPM_LEVELS),
3176                         "Performance levels exceeds SMC limit!",
3177                         return -1);
3178
3179         PP_ASSERT_WITH_CODE(
3180                         (vega10_ps->performance_level_count <
3181                                         hwmgr->platform_descriptor.
3182                                         hardwareActivityPerformanceLevels),
3183                         "Performance levels exceeds Driver limit!",
3184                         return -1);
3185
3186         /* Performance levels are arranged from low to high. */
3187         performance_level->soc_clock = socclk_dep_table->entries
3188                         [state_entry->ucSocClockIndexLow].ulClk;
3189         performance_level->gfx_clock = gfxclk_dep_table->entries
3190                         [state_entry->ucGfxClockIndexLow].ulClk;
3191         performance_level->mem_clock = mclk_dep_table->entries
3192                         [state_entry->ucMemClockIndexLow].ulMemClk;
3193
3194         performance_level = &(vega10_ps->performance_levels
3195                                 [vega10_ps->performance_level_count++]);
3196         performance_level->soc_clock = socclk_dep_table->entries
3197                                 [state_entry->ucSocClockIndexHigh].ulClk;
3198         if (gfxclk_dep_table->ucRevId == 0) {
3199                 /* under vega10 pp one vf mode, the gfx clk dpm need be lower
3200                  * to level-4 due to the limited 110w-power
3201                  */
3202                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3203                         performance_level->gfx_clock =
3204                                 gfxclk_dep_table->entries[4].ulClk;
3205                 else
3206                         performance_level->gfx_clock = gfxclk_dep_table->entries
3207                                 [state_entry->ucGfxClockIndexHigh].ulClk;
3208         } else if (gfxclk_dep_table->ucRevId == 1) {
3209                 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3210                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3211                         performance_level->gfx_clock = patom_record_V2[4].ulClk;
3212                 else
3213                         performance_level->gfx_clock =
3214                                 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3215         }
3216
3217         performance_level->mem_clock = mclk_dep_table->entries
3218                         [state_entry->ucMemClockIndexHigh].ulMemClk;
3219         return 0;
3220 }
3221
3222 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3223                 unsigned long entry_index, struct pp_power_state *state)
3224 {
3225         int result;
3226         struct vega10_power_state *vega10_ps;
3227
3228         state->hardware.magic = PhwVega10_Magic;
3229
3230         vega10_ps = cast_phw_vega10_power_state(&state->hardware);
3231
3232         result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3233                         vega10_get_pp_table_entry_callback_func);
3234         if (result)
3235                 return result;
3236
3237         /*
3238          * This is the earliest time we have all the dependency table
3239          * and the VBIOS boot state
3240          */
3241         /* set DC compatible flag if this state supports DC */
3242         if (!state->validation.disallowOnDC)
3243                 vega10_ps->dc_compatible = true;
3244
3245         vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3246         vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3247
3248         return 0;
3249 }
3250
3251 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3252              struct pp_hw_power_state *hw_ps)
3253 {
3254         return 0;
3255 }
3256
3257 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3258                                 struct pp_power_state  *request_ps,
3259                         const struct pp_power_state *current_ps)
3260 {
3261         struct amdgpu_device *adev = hwmgr->adev;
3262         struct vega10_power_state *vega10_ps =
3263                                 cast_phw_vega10_power_state(&request_ps->hardware);
3264         uint32_t sclk;
3265         uint32_t mclk;
3266         struct PP_Clocks minimum_clocks = {0};
3267         bool disable_mclk_switching;
3268         bool disable_mclk_switching_for_frame_lock;
3269         bool disable_mclk_switching_for_vr;
3270         bool force_mclk_high;
3271         const struct phm_clock_and_voltage_limits *max_limits;
3272         uint32_t i;
3273         struct vega10_hwmgr *data = hwmgr->backend;
3274         struct phm_ppt_v2_information *table_info =
3275                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3276         int32_t count;
3277         uint32_t stable_pstate_sclk_dpm_percentage;
3278         uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3279         uint32_t latency;
3280
3281         data->battery_state = (PP_StateUILabel_Battery ==
3282                         request_ps->classification.ui_label);
3283
3284         if (vega10_ps->performance_level_count != 2)
3285                 pr_info("VI should always have 2 performance levels");
3286
3287         max_limits = adev->pm.ac_power ?
3288                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3289                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3290
3291         /* Cap clock DPM tables at DC MAX if it is in DC. */
3292         if (!adev->pm.ac_power) {
3293                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3294                         if (vega10_ps->performance_levels[i].mem_clock >
3295                                 max_limits->mclk)
3296                                 vega10_ps->performance_levels[i].mem_clock =
3297                                                 max_limits->mclk;
3298                         if (vega10_ps->performance_levels[i].gfx_clock >
3299                                 max_limits->sclk)
3300                                 vega10_ps->performance_levels[i].gfx_clock =
3301                                                 max_limits->sclk;
3302                 }
3303         }
3304
3305         /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3306         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3307         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3308
3309         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3310                 stable_pstate_sclk_dpm_percentage =
3311                         data->registry_data.stable_pstate_sclk_dpm_percentage;
3312                 PP_ASSERT_WITH_CODE(
3313                         data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3314                         data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3315                         "percent sclk value must range from 1% to 100%, setting default value",
3316                         stable_pstate_sclk_dpm_percentage = 75);
3317
3318                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3319                 stable_pstate_sclk = (max_limits->sclk *
3320                                 stable_pstate_sclk_dpm_percentage) / 100;
3321
3322                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3323                                 count >= 0; count--) {
3324                         if (stable_pstate_sclk >=
3325                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3326                                 stable_pstate_sclk =
3327                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3328                                 break;
3329                         }
3330                 }
3331
3332                 if (count < 0)
3333                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3334
3335                 stable_pstate_mclk = max_limits->mclk;
3336
3337                 minimum_clocks.engineClock = stable_pstate_sclk;
3338                 minimum_clocks.memoryClock = stable_pstate_mclk;
3339         }
3340
3341         disable_mclk_switching_for_frame_lock =
3342                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3343         disable_mclk_switching_for_vr =
3344                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3345         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3346
3347         if (hwmgr->display_config->num_display == 0)
3348                 disable_mclk_switching = false;
3349         else
3350                 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3351                                           !hwmgr->display_config->multi_monitor_in_sync) ||
3352                         disable_mclk_switching_for_frame_lock ||
3353                         disable_mclk_switching_for_vr ||
3354                         force_mclk_high;
3355
3356         sclk = vega10_ps->performance_levels[0].gfx_clock;
3357         mclk = vega10_ps->performance_levels[0].mem_clock;
3358
3359         if (sclk < minimum_clocks.engineClock)
3360                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3361                                 max_limits->sclk : minimum_clocks.engineClock;
3362
3363         if (mclk < minimum_clocks.memoryClock)
3364                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3365                                 max_limits->mclk : minimum_clocks.memoryClock;
3366
3367         vega10_ps->performance_levels[0].gfx_clock = sclk;
3368         vega10_ps->performance_levels[0].mem_clock = mclk;
3369
3370         if (vega10_ps->performance_levels[1].gfx_clock <
3371                         vega10_ps->performance_levels[0].gfx_clock)
3372                 vega10_ps->performance_levels[0].gfx_clock =
3373                                 vega10_ps->performance_levels[1].gfx_clock;
3374
3375         if (disable_mclk_switching) {
3376                 /* Set Mclk the max of level 0 and level 1 */
3377                 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3378                         mclk = vega10_ps->performance_levels[1].mem_clock;
3379
3380                 /* Find the lowest MCLK frequency that is within
3381                  * the tolerable latency defined in DAL
3382                  */
3383                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3384                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3385                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3386                                 (data->mclk_latency_table.entries[i].frequency >=
3387                                                 vega10_ps->performance_levels[0].mem_clock) &&
3388                                 (data->mclk_latency_table.entries[i].frequency <=
3389                                                 vega10_ps->performance_levels[1].mem_clock))
3390                                 mclk = data->mclk_latency_table.entries[i].frequency;
3391                 }
3392                 vega10_ps->performance_levels[0].mem_clock = mclk;
3393         } else {
3394                 if (vega10_ps->performance_levels[1].mem_clock <
3395                                 vega10_ps->performance_levels[0].mem_clock)
3396                         vega10_ps->performance_levels[0].mem_clock =
3397                                         vega10_ps->performance_levels[1].mem_clock;
3398         }
3399
3400         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3401                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3402                         vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3403                         vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3404                 }
3405         }
3406
3407         return 0;
3408 }
3409
3410 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3411 {
3412         struct vega10_hwmgr *data = hwmgr->backend;
3413         const struct phm_set_power_state_input *states =
3414                         (const struct phm_set_power_state_input *)input;
3415         const struct vega10_power_state *vega10_ps =
3416                         cast_const_phw_vega10_power_state(states->pnew_state);
3417         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
3418         uint32_t sclk = vega10_ps->performance_levels
3419                         [vega10_ps->performance_level_count - 1].gfx_clock;
3420         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
3421         uint32_t mclk = vega10_ps->performance_levels
3422                         [vega10_ps->performance_level_count - 1].mem_clock;
3423         uint32_t i;
3424
3425         for (i = 0; i < sclk_table->count; i++) {
3426                 if (sclk == sclk_table->dpm_levels[i].value)
3427                         break;
3428         }
3429
3430         if (i >= sclk_table->count) {
3431                 if (sclk > sclk_table->dpm_levels[i-1].value) {
3432                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3433                         sclk_table->dpm_levels[i-1].value = sclk;
3434                 }
3435         }
3436
3437         for (i = 0; i < mclk_table->count; i++) {
3438                 if (mclk == mclk_table->dpm_levels[i].value)
3439                         break;
3440         }
3441
3442         if (i >= mclk_table->count) {
3443                 if (mclk > mclk_table->dpm_levels[i-1].value) {
3444                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3445                         mclk_table->dpm_levels[i-1].value = mclk;
3446                 }
3447         }
3448
3449         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3450                 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3451
3452         return 0;
3453 }
3454
3455 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3456                 struct pp_hwmgr *hwmgr, const void *input)
3457 {
3458         int result = 0;
3459         struct vega10_hwmgr *data = hwmgr->backend;
3460         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3461         struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3462         struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3463         int count;
3464
3465         if (!data->need_update_dpm_table)
3466                 return 0;
3467
3468         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3469                 for (count = 0; count < dpm_table->gfx_table.count; count++)
3470                         dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3471         }
3472
3473         odn_clk_table = &odn_table->vdd_dep_on_mclk;
3474         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3475                 for (count = 0; count < dpm_table->mem_table.count; count++)
3476                         dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3477         }
3478
3479         if (data->need_update_dpm_table &
3480                         (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) {
3481                 result = vega10_populate_all_graphic_levels(hwmgr);
3482                 PP_ASSERT_WITH_CODE((0 == result),
3483                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3484                                 return result);
3485         }
3486
3487         if (data->need_update_dpm_table &
3488                         (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3489                 result = vega10_populate_all_memory_levels(hwmgr);
3490                 PP_ASSERT_WITH_CODE((0 == result),
3491                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3492                                 return result);
3493         }
3494
3495         vega10_populate_vddc_soc_levels(hwmgr);
3496
3497         return result;
3498 }
3499
3500 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3501                 struct vega10_single_dpm_table *dpm_table,
3502                 uint32_t low_limit, uint32_t high_limit)
3503 {
3504         uint32_t i;
3505
3506         for (i = 0; i < dpm_table->count; i++) {
3507                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3508                     (dpm_table->dpm_levels[i].value > high_limit))
3509                         dpm_table->dpm_levels[i].enabled = false;
3510                 else
3511                         dpm_table->dpm_levels[i].enabled = true;
3512         }
3513         return 0;
3514 }
3515
3516 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3517                 struct vega10_single_dpm_table *dpm_table,
3518                 uint32_t low_limit, uint32_t high_limit,
3519                 uint32_t disable_dpm_mask)
3520 {
3521         uint32_t i;
3522
3523         for (i = 0; i < dpm_table->count; i++) {
3524                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3525                     (dpm_table->dpm_levels[i].value > high_limit))
3526                         dpm_table->dpm_levels[i].enabled = false;
3527                 else if (!((1 << i) & disable_dpm_mask))
3528                         dpm_table->dpm_levels[i].enabled = false;
3529                 else
3530                         dpm_table->dpm_levels[i].enabled = true;
3531         }
3532         return 0;
3533 }
3534
3535 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3536                 const struct vega10_power_state *vega10_ps)
3537 {
3538         struct vega10_hwmgr *data = hwmgr->backend;
3539         uint32_t high_limit_count;
3540
3541         PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3542                         "power state did not have any performance level",
3543                         return -1);
3544
3545         high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3546
3547         vega10_trim_single_dpm_states(hwmgr,
3548                         &(data->dpm_table.soc_table),
3549                         vega10_ps->performance_levels[0].soc_clock,
3550                         vega10_ps->performance_levels[high_limit_count].soc_clock);
3551
3552         vega10_trim_single_dpm_states_with_mask(hwmgr,
3553                         &(data->dpm_table.gfx_table),
3554                         vega10_ps->performance_levels[0].gfx_clock,
3555                         vega10_ps->performance_levels[high_limit_count].gfx_clock,
3556                         data->disable_dpm_mask);
3557
3558         vega10_trim_single_dpm_states(hwmgr,
3559                         &(data->dpm_table.mem_table),
3560                         vega10_ps->performance_levels[0].mem_clock,
3561                         vega10_ps->performance_levels[high_limit_count].mem_clock);
3562
3563         return 0;
3564 }
3565
3566 static uint32_t vega10_find_lowest_dpm_level(
3567                 struct vega10_single_dpm_table *table)
3568 {
3569         uint32_t i;
3570
3571         for (i = 0; i < table->count; i++) {
3572                 if (table->dpm_levels[i].enabled)
3573                         break;
3574         }
3575
3576         return i;
3577 }
3578
3579 static uint32_t vega10_find_highest_dpm_level(
3580                 struct vega10_single_dpm_table *table)
3581 {
3582         uint32_t i = 0;
3583
3584         if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3585                 for (i = table->count; i > 0; i--) {
3586                         if (table->dpm_levels[i - 1].enabled)
3587                                 return i - 1;
3588                 }
3589         } else {
3590                 pr_info("DPM Table Has Too Many Entries!");
3591                 return MAX_REGULAR_DPM_NUMBER - 1;
3592         }
3593
3594         return i;
3595 }
3596
3597 static void vega10_apply_dal_minimum_voltage_request(
3598                 struct pp_hwmgr *hwmgr)
3599 {
3600         return;
3601 }
3602
3603 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3604 {
3605         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3606         struct phm_ppt_v2_information *table_info =
3607                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3608
3609         vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3610
3611         return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3612 }
3613
3614 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3615 {
3616         struct vega10_hwmgr *data = hwmgr->backend;
3617         uint32_t socclk_idx;
3618
3619         vega10_apply_dal_minimum_voltage_request(hwmgr);
3620
3621         if (!data->registry_data.sclk_dpm_key_disabled) {
3622                 if (data->smc_state_table.gfx_boot_level !=
3623                                 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3624                         smum_send_msg_to_smc_with_parameter(hwmgr,
3625                                 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3626                                 data->smc_state_table.gfx_boot_level,
3627                                 NULL);
3628
3629                         data->dpm_table.gfx_table.dpm_state.soft_min_level =
3630                                         data->smc_state_table.gfx_boot_level;
3631                 }
3632         }
3633
3634         if (!data->registry_data.mclk_dpm_key_disabled) {
3635                 if (data->smc_state_table.mem_boot_level !=
3636                                 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3637                         if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
3638                             && hwmgr->not_vf) {
3639                                 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3640                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3641                                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3642                                                 socclk_idx,
3643                                                 NULL);
3644                         } else {
3645                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3646                                                 PPSMC_MSG_SetSoftMinUclkByIndex,
3647                                                 data->smc_state_table.mem_boot_level,
3648                                                 NULL);
3649                         }
3650                         data->dpm_table.mem_table.dpm_state.soft_min_level =
3651                                         data->smc_state_table.mem_boot_level;
3652                 }
3653         }
3654
3655         if (!hwmgr->not_vf)
3656                 return 0;
3657
3658         if (!data->registry_data.socclk_dpm_key_disabled) {
3659                 if (data->smc_state_table.soc_boot_level !=
3660                                 data->dpm_table.soc_table.dpm_state.soft_min_level) {
3661                         smum_send_msg_to_smc_with_parameter(hwmgr,
3662                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3663                                 data->smc_state_table.soc_boot_level,
3664                                 NULL);
3665                         data->dpm_table.soc_table.dpm_state.soft_min_level =
3666                                         data->smc_state_table.soc_boot_level;
3667                 }
3668         }
3669
3670         return 0;
3671 }
3672
3673 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3674 {
3675         struct vega10_hwmgr *data = hwmgr->backend;
3676
3677         vega10_apply_dal_minimum_voltage_request(hwmgr);
3678
3679         if (!data->registry_data.sclk_dpm_key_disabled) {
3680                 if (data->smc_state_table.gfx_max_level !=
3681                         data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3682                         smum_send_msg_to_smc_with_parameter(hwmgr,
3683                                 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3684                                 data->smc_state_table.gfx_max_level,
3685                                 NULL);
3686                         data->dpm_table.gfx_table.dpm_state.soft_max_level =
3687                                         data->smc_state_table.gfx_max_level;
3688                 }
3689         }
3690
3691         if (!data->registry_data.mclk_dpm_key_disabled) {
3692                 if (data->smc_state_table.mem_max_level !=
3693                         data->dpm_table.mem_table.dpm_state.soft_max_level) {
3694                         smum_send_msg_to_smc_with_parameter(hwmgr,
3695                                         PPSMC_MSG_SetSoftMaxUclkByIndex,
3696                                         data->smc_state_table.mem_max_level,
3697                                         NULL);
3698                         data->dpm_table.mem_table.dpm_state.soft_max_level =
3699                                         data->smc_state_table.mem_max_level;
3700                 }
3701         }
3702
3703         if (!hwmgr->not_vf)
3704                 return 0;
3705
3706         if (!data->registry_data.socclk_dpm_key_disabled) {
3707                 if (data->smc_state_table.soc_max_level !=
3708                         data->dpm_table.soc_table.dpm_state.soft_max_level) {
3709                         smum_send_msg_to_smc_with_parameter(hwmgr,
3710                                 PPSMC_MSG_SetSoftMaxSocclkByIndex,
3711                                 data->smc_state_table.soc_max_level,
3712                                 NULL);
3713                         data->dpm_table.soc_table.dpm_state.soft_max_level =
3714                                         data->smc_state_table.soc_max_level;
3715                 }
3716         }
3717
3718         return 0;
3719 }
3720
3721 static int vega10_generate_dpm_level_enable_mask(
3722                 struct pp_hwmgr *hwmgr, const void *input)
3723 {
3724         struct vega10_hwmgr *data = hwmgr->backend;
3725         const struct phm_set_power_state_input *states =
3726                         (const struct phm_set_power_state_input *)input;
3727         const struct vega10_power_state *vega10_ps =
3728                         cast_const_phw_vega10_power_state(states->pnew_state);
3729         int i;
3730
3731         PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3732                         "Attempt to Trim DPM States Failed!",
3733                         return -1);
3734
3735         data->smc_state_table.gfx_boot_level =
3736                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3737         data->smc_state_table.gfx_max_level =
3738                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3739         data->smc_state_table.mem_boot_level =
3740                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3741         data->smc_state_table.mem_max_level =
3742                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3743         data->smc_state_table.soc_boot_level =
3744                         vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
3745         data->smc_state_table.soc_max_level =
3746                         vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
3747
3748         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3749                         "Attempt to upload DPM Bootup Levels Failed!",
3750                         return -1);
3751         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3752                         "Attempt to upload DPM Max Levels Failed!",
3753                         return -1);
3754         for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3755                 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3756
3757
3758         for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3759                 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3760
3761         for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)
3762                 data->dpm_table.soc_table.dpm_levels[i].enabled = true;
3763
3764         return 0;
3765 }
3766
3767 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3768 {
3769         struct vega10_hwmgr *data = hwmgr->backend;
3770
3771         if (data->smu_features[GNLD_DPM_VCE].supported) {
3772                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3773                                 enable,
3774                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3775                                 "Attempt to Enable/Disable DPM VCE Failed!",
3776                                 return -1);
3777                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3778         }
3779
3780         return 0;
3781 }
3782
3783 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3784 {
3785         struct vega10_hwmgr *data = hwmgr->backend;
3786         uint32_t low_sclk_interrupt_threshold = 0;
3787
3788         if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3789                 (data->low_sclk_interrupt_threshold != 0)) {
3790                 low_sclk_interrupt_threshold =
3791                                 data->low_sclk_interrupt_threshold;
3792
3793                 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3794                                 cpu_to_le32(low_sclk_interrupt_threshold);
3795
3796                 /* This message will also enable SmcToHost Interrupt */
3797                 smum_send_msg_to_smc_with_parameter(hwmgr,
3798                                 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3799                                 (uint32_t)low_sclk_interrupt_threshold,
3800                                 NULL);
3801         }
3802
3803         return 0;
3804 }
3805
3806 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3807                 const void *input)
3808 {
3809         int tmp_result, result = 0;
3810         struct vega10_hwmgr *data = hwmgr->backend;
3811         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3812
3813         tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3814         PP_ASSERT_WITH_CODE(!tmp_result,
3815                         "Failed to find DPM states clocks in DPM table!",
3816                         result = tmp_result);
3817
3818         tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3819         PP_ASSERT_WITH_CODE(!tmp_result,
3820                         "Failed to populate and upload SCLK MCLK DPM levels!",
3821                         result = tmp_result);
3822
3823         tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3824         PP_ASSERT_WITH_CODE(!tmp_result,
3825                         "Failed to generate DPM level enabled mask!",
3826                         result = tmp_result);
3827
3828         tmp_result = vega10_update_sclk_threshold(hwmgr);
3829         PP_ASSERT_WITH_CODE(!tmp_result,
3830                         "Failed to update SCLK threshold!",
3831                         result = tmp_result);
3832
3833         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3834         PP_ASSERT_WITH_CODE(!result,
3835                         "Failed to upload PPtable!", return result);
3836
3837         /*
3838          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
3839          * That effectively disables AVFS feature.
3840          */
3841         if(hwmgr->hardcode_pp_table != NULL)
3842                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
3843
3844         vega10_update_avfs(hwmgr);
3845
3846         /*
3847          * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC.
3848          * That will help to keep AVFS disabled.
3849          */
3850         data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3851
3852         return 0;
3853 }
3854
3855 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3856 {
3857         struct pp_power_state *ps;
3858         struct vega10_power_state *vega10_ps;
3859
3860         if (hwmgr == NULL)
3861                 return -EINVAL;
3862
3863         ps = hwmgr->request_ps;
3864
3865         if (ps == NULL)
3866                 return -EINVAL;
3867
3868         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3869
3870         if (low)
3871                 return vega10_ps->performance_levels[0].gfx_clock;
3872         else
3873                 return vega10_ps->performance_levels
3874                                 [vega10_ps->performance_level_count - 1].gfx_clock;
3875 }
3876
3877 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3878 {
3879         struct pp_power_state *ps;
3880         struct vega10_power_state *vega10_ps;
3881
3882         if (hwmgr == NULL)
3883                 return -EINVAL;
3884
3885         ps = hwmgr->request_ps;
3886
3887         if (ps == NULL)
3888                 return -EINVAL;
3889
3890         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3891
3892         if (low)
3893                 return vega10_ps->performance_levels[0].mem_clock;
3894         else
3895                 return vega10_ps->performance_levels
3896                                 [vega10_ps->performance_level_count-1].mem_clock;
3897 }
3898
3899 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3900                 uint32_t *query)
3901 {
3902         uint32_t value;
3903
3904         if (!query)
3905                 return -EINVAL;
3906
3907         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value);
3908
3909         /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3910         *query = value << 8;
3911
3912         return 0;
3913 }
3914
3915 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3916                               void *value, int *size)
3917 {
3918         struct amdgpu_device *adev = hwmgr->adev;
3919         uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3920         struct vega10_hwmgr *data = hwmgr->backend;
3921         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3922         int ret = 0;
3923         uint32_t val_vid;
3924
3925         switch (idx) {
3926         case AMDGPU_PP_SENSOR_GFX_SCLK:
3927                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz);
3928                 *((uint32_t *)value) = sclk_mhz * 100;
3929                 break;
3930         case AMDGPU_PP_SENSOR_GFX_MCLK:
3931                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx);
3932                 if (mclk_idx < dpm_table->mem_table.count) {
3933                         *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3934                         *size = 4;
3935                 } else {
3936                         ret = -EINVAL;
3937                 }
3938                 break;
3939         case AMDGPU_PP_SENSOR_GPU_LOAD:
3940                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0,
3941                                                 &activity_percent);
3942                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3943                 *size = 4;
3944                 break;
3945         case AMDGPU_PP_SENSOR_GPU_TEMP:
3946                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3947                 *size = 4;
3948                 break;
3949         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3950                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value);
3951                 *((uint32_t *)value) = *((uint32_t *)value) *
3952                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3953                 *size = 4;
3954                 break;
3955         case AMDGPU_PP_SENSOR_MEM_TEMP:
3956                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value);
3957                 *((uint32_t *)value) = *((uint32_t *)value) *
3958                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3959                 *size = 4;
3960                 break;
3961         case AMDGPU_PP_SENSOR_UVD_POWER:
3962                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3963                 *size = 4;
3964                 break;
3965         case AMDGPU_PP_SENSOR_VCE_POWER:
3966                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3967                 *size = 4;
3968                 break;
3969         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
3970                 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3971                 break;
3972         case AMDGPU_PP_SENSOR_VDDGFX:
3973                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3974                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3975                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3976                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3977                 return 0;
3978         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3979                 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
3980                 if (!ret)
3981                         *size = 8;
3982                 break;
3983         default:
3984                 ret = -EOPNOTSUPP;
3985                 break;
3986         }
3987
3988         return ret;
3989 }
3990
3991 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3992                 bool has_disp)
3993 {
3994         smum_send_msg_to_smc_with_parameter(hwmgr,
3995                         PPSMC_MSG_SetUclkFastSwitch,
3996                         has_disp ? 1 : 0,
3997                         NULL);
3998 }
3999
4000 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
4001                 struct pp_display_clock_request *clock_req)
4002 {
4003         int result = 0;
4004         enum amd_pp_clock_type clk_type = clock_req->clock_type;
4005         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
4006         DSPCLK_e clk_select = 0;
4007         uint32_t clk_request = 0;
4008
4009         switch (clk_type) {
4010         case amd_pp_dcef_clock:
4011                 clk_select = DSPCLK_DCEFCLK;
4012                 break;
4013         case amd_pp_disp_clock:
4014                 clk_select = DSPCLK_DISPCLK;
4015                 break;
4016         case amd_pp_pixel_clock:
4017                 clk_select = DSPCLK_PIXCLK;
4018                 break;
4019         case amd_pp_phy_clock:
4020                 clk_select = DSPCLK_PHYCLK;
4021                 break;
4022         default:
4023                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
4024                 result = -1;
4025                 break;
4026         }
4027
4028         if (!result) {
4029                 clk_request = (clk_freq << 16) | clk_select;
4030                 smum_send_msg_to_smc_with_parameter(hwmgr,
4031                                 PPSMC_MSG_RequestDisplayClockByFreq,
4032                                 clk_request,
4033                                 NULL);
4034         }
4035
4036         return result;
4037 }
4038
4039 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
4040                         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
4041                                                 uint32_t frequency)
4042 {
4043         uint8_t count;
4044         uint8_t i;
4045
4046         if (mclk_table == NULL || mclk_table->count == 0)
4047                 return 0;
4048
4049         count = (uint8_t)(mclk_table->count);
4050
4051         for(i = 0; i < count; i++) {
4052                 if(mclk_table->entries[i].clk >= frequency)
4053                         return i;
4054         }
4055
4056         return i-1;
4057 }
4058
4059 static int vega10_notify_smc_display_config_after_ps_adjustment(
4060                 struct pp_hwmgr *hwmgr)
4061 {
4062         struct vega10_hwmgr *data = hwmgr->backend;
4063         struct vega10_single_dpm_table *dpm_table =
4064                         &data->dpm_table.dcef_table;
4065         struct phm_ppt_v2_information *table_info =
4066                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4067         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
4068         uint32_t idx;
4069         struct PP_Clocks min_clocks = {0};
4070         uint32_t i;
4071         struct pp_display_clock_request clock_req;
4072
4073         if ((hwmgr->display_config->num_display > 1) &&
4074              !hwmgr->display_config->multi_monitor_in_sync &&
4075              !hwmgr->display_config->nb_pstate_switch_disable)
4076                 vega10_notify_smc_display_change(hwmgr, false);
4077         else
4078                 vega10_notify_smc_display_change(hwmgr, true);
4079
4080         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
4081         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
4082         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
4083
4084         for (i = 0; i < dpm_table->count; i++) {
4085                 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4086                         break;
4087         }
4088
4089         if (i < dpm_table->count) {
4090                 clock_req.clock_type = amd_pp_dcef_clock;
4091                 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
4092                 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
4093                         smum_send_msg_to_smc_with_parameter(
4094                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
4095                                         min_clocks.dcefClockInSR / 100,
4096                                         NULL);
4097                 } else {
4098                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
4099                 }
4100         } else {
4101                 pr_debug("Cannot find requested DCEFCLK!");
4102         }
4103
4104         if (min_clocks.memoryClock != 0) {
4105                 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
4106                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx,
4107                                                 NULL);
4108                 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
4109         }
4110
4111         return 0;
4112 }
4113
4114 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
4115 {
4116         struct vega10_hwmgr *data = hwmgr->backend;
4117
4118         data->smc_state_table.gfx_boot_level =
4119         data->smc_state_table.gfx_max_level =
4120                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4121         data->smc_state_table.mem_boot_level =
4122         data->smc_state_table.mem_max_level =
4123                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4124
4125         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4126                         "Failed to upload boot level to highest!",
4127                         return -1);
4128
4129         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4130                         "Failed to upload dpm max level to highest!",
4131                         return -1);
4132
4133         return 0;
4134 }
4135
4136 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
4137 {
4138         struct vega10_hwmgr *data = hwmgr->backend;
4139
4140         data->smc_state_table.gfx_boot_level =
4141         data->smc_state_table.gfx_max_level =
4142                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4143         data->smc_state_table.mem_boot_level =
4144         data->smc_state_table.mem_max_level =
4145                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4146
4147         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4148                         "Failed to upload boot level to highest!",
4149                         return -1);
4150
4151         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4152                         "Failed to upload dpm max level to highest!",
4153                         return -1);
4154
4155         return 0;
4156
4157 }
4158
4159 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4160 {
4161         struct vega10_hwmgr *data = hwmgr->backend;
4162
4163         data->smc_state_table.gfx_boot_level =
4164                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4165         data->smc_state_table.gfx_max_level =
4166                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4167         data->smc_state_table.mem_boot_level =
4168                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4169         data->smc_state_table.mem_max_level =
4170                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4171
4172         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4173                         "Failed to upload DPM Bootup Levels!",
4174                         return -1);
4175
4176         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4177                         "Failed to upload DPM Max Levels!",
4178                         return -1);
4179         return 0;
4180 }
4181
4182 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
4183                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4184 {
4185         struct phm_ppt_v2_information *table_info =
4186                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
4187
4188         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
4189                 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
4190                 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
4191                 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
4192                 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4193                 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4194         }
4195
4196         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
4197                 *sclk_mask = 0;
4198         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
4199                 *mclk_mask = 0;
4200         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
4201                 /* under vega10  pp one vf mode, the gfx clk dpm need be lower
4202                  * to level-4 due to the limited power
4203                  */
4204                 if (hwmgr->pp_one_vf)
4205                         *sclk_mask = 4;
4206                 else
4207                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
4208                 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4209                 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4210         }
4211
4212         return 0;
4213 }
4214
4215 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4216 {
4217         if (!hwmgr->not_vf)
4218                 return;
4219
4220         switch (mode) {
4221         case AMD_FAN_CTRL_NONE:
4222                 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
4223                 break;
4224         case AMD_FAN_CTRL_MANUAL:
4225                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4226                         vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
4227                 break;
4228         case AMD_FAN_CTRL_AUTO:
4229                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4230                         vega10_fan_ctrl_start_smc_fan_control(hwmgr);
4231                 break;
4232         default:
4233                 break;
4234         }
4235 }
4236
4237 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4238                 enum pp_clock_type type, uint32_t mask)
4239 {
4240         struct vega10_hwmgr *data = hwmgr->backend;
4241
4242         switch (type) {
4243         case PP_SCLK:
4244                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
4245                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
4246
4247                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4248                         "Failed to upload boot level to lowest!",
4249                         return -EINVAL);
4250
4251                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4252                         "Failed to upload dpm max level to highest!",
4253                         return -EINVAL);
4254                 break;
4255
4256         case PP_MCLK:
4257                 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
4258                 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
4259
4260                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4261                         "Failed to upload boot level to lowest!",
4262                         return -EINVAL);
4263
4264                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4265                         "Failed to upload dpm max level to highest!",
4266                         return -EINVAL);
4267
4268                 break;
4269
4270         case PP_SOCCLK:
4271                 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
4272                 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
4273
4274                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4275                         "Failed to upload boot level to lowest!",
4276                         return -EINVAL);
4277
4278                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4279                         "Failed to upload dpm max level to highest!",
4280                         return -EINVAL);
4281
4282                 break;
4283
4284         case PP_DCEFCLK:
4285                 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
4286                 break;
4287
4288         case PP_PCIE:
4289         default:
4290                 break;
4291         }
4292
4293         return 0;
4294 }
4295
4296 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4297                                 enum amd_dpm_forced_level level)
4298 {
4299         int ret = 0;
4300         uint32_t sclk_mask = 0;
4301         uint32_t mclk_mask = 0;
4302         uint32_t soc_mask = 0;
4303
4304         switch (level) {
4305         case AMD_DPM_FORCED_LEVEL_HIGH:
4306                 ret = vega10_force_dpm_highest(hwmgr);
4307                 break;
4308         case AMD_DPM_FORCED_LEVEL_LOW:
4309                 ret = vega10_force_dpm_lowest(hwmgr);
4310                 break;
4311         case AMD_DPM_FORCED_LEVEL_AUTO:
4312                 ret = vega10_unforce_dpm_levels(hwmgr);
4313                 break;
4314         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4315         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4316         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4317         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4318                 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4319                 if (ret)
4320                         return ret;
4321                 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4322                 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4323                 break;
4324         case AMD_DPM_FORCED_LEVEL_MANUAL:
4325         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4326         default:
4327                 break;
4328         }
4329
4330         if (!hwmgr->not_vf)
4331                 return ret;
4332
4333         if (!ret) {
4334                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4335                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4336                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4337                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4338         }
4339
4340         return ret;
4341 }
4342
4343 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4344 {
4345         struct vega10_hwmgr *data = hwmgr->backend;
4346
4347         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4348                 return AMD_FAN_CTRL_MANUAL;
4349         else
4350                 return AMD_FAN_CTRL_AUTO;
4351 }
4352
4353 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4354                 struct amd_pp_simple_clock_info *info)
4355 {
4356         struct phm_ppt_v2_information *table_info =
4357                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4358         struct phm_clock_and_voltage_limits *max_limits =
4359                         &table_info->max_clock_voltage_on_ac;
4360
4361         info->engine_max_clock = max_limits->sclk;
4362         info->memory_max_clock = max_limits->mclk;
4363
4364         return 0;
4365 }
4366
4367 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4368                 struct pp_clock_levels_with_latency *clocks)
4369 {
4370         struct phm_ppt_v2_information *table_info =
4371                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4372         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4373                         table_info->vdd_dep_on_sclk;
4374         uint32_t i;
4375
4376         clocks->num_levels = 0;
4377         for (i = 0; i < dep_table->count; i++) {
4378                 if (dep_table->entries[i].clk) {
4379                         clocks->data[clocks->num_levels].clocks_in_khz =
4380                                         dep_table->entries[i].clk * 10;
4381                         clocks->num_levels++;
4382                 }
4383         }
4384
4385 }
4386
4387 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4388                 struct pp_clock_levels_with_latency *clocks)
4389 {
4390         struct phm_ppt_v2_information *table_info =
4391                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4392         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4393                         table_info->vdd_dep_on_mclk;
4394         struct vega10_hwmgr *data = hwmgr->backend;
4395         uint32_t j = 0;
4396         uint32_t i;
4397
4398         for (i = 0; i < dep_table->count; i++) {
4399                 if (dep_table->entries[i].clk) {
4400
4401                         clocks->data[j].clocks_in_khz =
4402                                                 dep_table->entries[i].clk * 10;
4403                         data->mclk_latency_table.entries[j].frequency =
4404                                                         dep_table->entries[i].clk;
4405                         clocks->data[j].latency_in_us =
4406                                 data->mclk_latency_table.entries[j].latency = 25;
4407                         j++;
4408                 }
4409         }
4410         clocks->num_levels = data->mclk_latency_table.count = j;
4411 }
4412
4413 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4414                 struct pp_clock_levels_with_latency *clocks)
4415 {
4416         struct phm_ppt_v2_information *table_info =
4417                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4418         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4419                         table_info->vdd_dep_on_dcefclk;
4420         uint32_t i;
4421
4422         for (i = 0; i < dep_table->count; i++) {
4423                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4424                 clocks->data[i].latency_in_us = 0;
4425                 clocks->num_levels++;
4426         }
4427 }
4428
4429 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4430                 struct pp_clock_levels_with_latency *clocks)
4431 {
4432         struct phm_ppt_v2_information *table_info =
4433                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4434         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4435                         table_info->vdd_dep_on_socclk;
4436         uint32_t i;
4437
4438         for (i = 0; i < dep_table->count; i++) {
4439                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4440                 clocks->data[i].latency_in_us = 0;
4441                 clocks->num_levels++;
4442         }
4443 }
4444
4445 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4446                 enum amd_pp_clock_type type,
4447                 struct pp_clock_levels_with_latency *clocks)
4448 {
4449         switch (type) {
4450         case amd_pp_sys_clock:
4451                 vega10_get_sclks(hwmgr, clocks);
4452                 break;
4453         case amd_pp_mem_clock:
4454                 vega10_get_memclocks(hwmgr, clocks);
4455                 break;
4456         case amd_pp_dcef_clock:
4457                 vega10_get_dcefclocks(hwmgr, clocks);
4458                 break;
4459         case amd_pp_soc_clock:
4460                 vega10_get_socclocks(hwmgr, clocks);
4461                 break;
4462         default:
4463                 return -1;
4464         }
4465
4466         return 0;
4467 }
4468
4469 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4470                 enum amd_pp_clock_type type,
4471                 struct pp_clock_levels_with_voltage *clocks)
4472 {
4473         struct phm_ppt_v2_information *table_info =
4474                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4475         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4476         uint32_t i;
4477
4478         switch (type) {
4479         case amd_pp_mem_clock:
4480                 dep_table = table_info->vdd_dep_on_mclk;
4481                 break;
4482         case amd_pp_dcef_clock:
4483                 dep_table = table_info->vdd_dep_on_dcefclk;
4484                 break;
4485         case amd_pp_disp_clock:
4486                 dep_table = table_info->vdd_dep_on_dispclk;
4487                 break;
4488         case amd_pp_pixel_clock:
4489                 dep_table = table_info->vdd_dep_on_pixclk;
4490                 break;
4491         case amd_pp_phy_clock:
4492                 dep_table = table_info->vdd_dep_on_phyclk;
4493                 break;
4494         default:
4495                 return -1;
4496         }
4497
4498         for (i = 0; i < dep_table->count; i++) {
4499                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
4500                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4501                                 entries[dep_table->entries[i].vddInd].us_vdd);
4502                 clocks->num_levels++;
4503         }
4504
4505         if (i < dep_table->count)
4506                 return -1;
4507
4508         return 0;
4509 }
4510
4511 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4512                                                         void *clock_range)
4513 {
4514         struct vega10_hwmgr *data = hwmgr->backend;
4515         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4516         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4517
4518         if (!data->registry_data.disable_water_mark) {
4519                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4520                 data->water_marks_bitmap = WaterMarksExist;
4521         }
4522
4523         return 0;
4524 }
4525
4526 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
4527 {
4528         static const char *ppfeature_name[] = {
4529                                 "DPM_PREFETCHER",
4530                                 "GFXCLK_DPM",
4531                                 "UCLK_DPM",
4532                                 "SOCCLK_DPM",
4533                                 "UVD_DPM",
4534                                 "VCE_DPM",
4535                                 "ULV",
4536                                 "MP0CLK_DPM",
4537                                 "LINK_DPM",
4538                                 "DCEFCLK_DPM",
4539                                 "AVFS",
4540                                 "GFXCLK_DS",
4541                                 "SOCCLK_DS",
4542                                 "LCLK_DS",
4543                                 "PPT",
4544                                 "TDC",
4545                                 "THERMAL",
4546                                 "GFX_PER_CU_CG",
4547                                 "RM",
4548                                 "DCEFCLK_DS",
4549                                 "ACDC",
4550                                 "VR0HOT",
4551                                 "VR1HOT",
4552                                 "FW_CTF",
4553                                 "LED_DISPLAY",
4554                                 "FAN_CONTROL",
4555                                 "FAST_PPT",
4556                                 "DIDT",
4557                                 "ACG",
4558                                 "PCC_LIMIT"};
4559         static const char *output_title[] = {
4560                                 "FEATURES",
4561                                 "BITMASK",
4562                                 "ENABLEMENT"};
4563         uint64_t features_enabled;
4564         int i;
4565         int ret = 0;
4566         int size = 0;
4567
4568         phm_get_sysfs_buf(&buf, &size);
4569
4570         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4571         PP_ASSERT_WITH_CODE(!ret,
4572                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
4573                         return ret);
4574
4575         size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
4576         size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
4577                                 output_title[0],
4578                                 output_title[1],
4579                                 output_title[2]);
4580         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
4581                 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
4582                                         ppfeature_name[i],
4583                                         1ULL << i,
4584                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
4585         }
4586
4587         return size;
4588 }
4589
4590 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
4591 {
4592         uint64_t features_enabled;
4593         uint64_t features_to_enable;
4594         uint64_t features_to_disable;
4595         int ret = 0;
4596
4597         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
4598                 return -EINVAL;
4599
4600         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4601         if (ret)
4602                 return ret;
4603
4604         features_to_disable =
4605                 features_enabled & ~new_ppfeature_masks;
4606         features_to_enable =
4607                 ~features_enabled & new_ppfeature_masks;
4608
4609         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
4610         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
4611
4612         if (features_to_disable) {
4613                 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
4614                 if (ret)
4615                         return ret;
4616         }
4617
4618         if (features_to_enable) {
4619                 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
4620                 if (ret)
4621                         return ret;
4622         }
4623
4624         return 0;
4625 }
4626
4627 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
4628 {
4629         struct amdgpu_device *adev = hwmgr->adev;
4630
4631         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
4632                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
4633                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4634 }
4635
4636 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
4637 {
4638         struct amdgpu_device *adev = hwmgr->adev;
4639
4640         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
4641                 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
4642                 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4643 }
4644
4645 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr,
4646                                     enum pp_clock_type type, char *buf, int *offset)
4647 {
4648         struct vega10_hwmgr *data = hwmgr->backend;
4649         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4650         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4651         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4652         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4653         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4654         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4655         PPTable_t *pptable = &(data->smc_state_table.pp_table);
4656
4657         uint32_t i, now, count = 0;
4658         int ret = 0;
4659
4660         switch (type) {
4661         case PP_SCLK:
4662                 if (data->registry_data.sclk_dpm_key_disabled)
4663                         return -EOPNOTSUPP;
4664
4665                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4666                 if (unlikely(ret != 0))
4667                         return ret;
4668
4669                 if (hwmgr->pp_one_vf &&
4670                     (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4671                         count = 5;
4672                 else
4673                         count = sclk_table->count;
4674                 for (i = 0; i < count; i++)
4675                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4676                                         i, sclk_table->dpm_levels[i].value / 100,
4677                                         (i == now) ? "*" : "");
4678                 break;
4679         case PP_MCLK:
4680                 if (data->registry_data.mclk_dpm_key_disabled)
4681                         return -EOPNOTSUPP;
4682
4683                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4684                 if (unlikely(ret != 0))
4685                         return ret;
4686
4687                 for (i = 0; i < mclk_table->count; i++)
4688                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4689                                         i, mclk_table->dpm_levels[i].value / 100,
4690                                         (i == now) ? "*" : "");
4691                 break;
4692         case PP_SOCCLK:
4693                 if (data->registry_data.socclk_dpm_key_disabled)
4694                         return -EOPNOTSUPP;
4695
4696                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4697                 if (unlikely(ret != 0))
4698                         return ret;
4699
4700                 for (i = 0; i < soc_table->count; i++)
4701                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4702                                         i, soc_table->dpm_levels[i].value / 100,
4703                                         (i == now) ? "*" : "");
4704                 break;
4705         case PP_DCEFCLK:
4706                 if (data->registry_data.dcefclk_dpm_key_disabled)
4707                         return -EOPNOTSUPP;
4708
4709                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4710                                                           PPSMC_MSG_GetClockFreqMHz,
4711                                                           CLK_DCEFCLK, &now);
4712                 if (unlikely(ret != 0))
4713                         return ret;
4714
4715                 for (i = 0; i < dcef_table->count; i++)
4716                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4717                                         i, dcef_table->dpm_levels[i].value / 100,
4718                                         (dcef_table->dpm_levels[i].value / 100 == now) ?
4719                                         "*" : "");
4720                 break;
4721         case PP_PCIE:
4722                 current_gen_speed =
4723                         vega10_get_current_pcie_link_speed_level(hwmgr);
4724                 current_lane_width =
4725                         vega10_get_current_pcie_link_width_level(hwmgr);
4726                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
4727                         gen_speed = pptable->PcieGenSpeed[i];
4728                         lane_width = pptable->PcieLaneCount[i];
4729
4730                         *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i,
4731                                         (gen_speed == 0) ? "2.5GT/s," :
4732                                         (gen_speed == 1) ? "5.0GT/s," :
4733                                         (gen_speed == 2) ? "8.0GT/s," :
4734                                         (gen_speed == 3) ? "16.0GT/s," : "",
4735                                         (lane_width == 1) ? "x1" :
4736                                         (lane_width == 2) ? "x2" :
4737                                         (lane_width == 3) ? "x4" :
4738                                         (lane_width == 4) ? "x8" :
4739                                         (lane_width == 5) ? "x12" :
4740                                         (lane_width == 6) ? "x16" : "",
4741                                         (current_gen_speed == gen_speed) &&
4742                                         (current_lane_width == lane_width) ?
4743                                         "*" : "");
4744                 }
4745                 break;
4746
4747         case OD_SCLK:
4748                 if (!hwmgr->od_enabled)
4749                         return -EOPNOTSUPP;
4750
4751                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK");
4752                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4753                 for (i = 0; i < podn_vdd_dep->count; i++)
4754                         *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4755                                                  i, podn_vdd_dep->entries[i].clk / 100,
4756                                                  podn_vdd_dep->entries[i].vddc);
4757                 break;
4758         case OD_MCLK:
4759                 if (!hwmgr->od_enabled)
4760                         return -EOPNOTSUPP;
4761
4762                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK");
4763                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4764                 for (i = 0; i < podn_vdd_dep->count; i++)
4765                         *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4766                                                  i, podn_vdd_dep->entries[i].clk/100,
4767                                                  podn_vdd_dep->entries[i].vddc);
4768                 break;
4769         case OD_RANGE:
4770                 if (!hwmgr->od_enabled)
4771                         return -EOPNOTSUPP;
4772
4773                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
4774                 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n",
4775                                          data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4776                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4777                 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n",
4778                                          data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4779                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4780                 *offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n",
4781                                          data->odn_dpm_table.min_vddc,
4782                                          data->odn_dpm_table.max_vddc);
4783                 break;
4784         default:
4785                 ret = -ENOENT;
4786                 break;
4787         }
4788         return ret;
4789 }
4790
4791 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4792                 enum pp_clock_type type, char *buf)
4793 {
4794         struct vega10_hwmgr *data = hwmgr->backend;
4795         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4796         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4797         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4798         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4799         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4800         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4801         PPTable_t *pptable = &(data->smc_state_table.pp_table);
4802
4803         int i, now, size = 0, count = 0;
4804
4805         switch (type) {
4806         case PP_SCLK:
4807                 if (data->registry_data.sclk_dpm_key_disabled)
4808                         break;
4809
4810                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4811
4812                 if (hwmgr->pp_one_vf &&
4813                     (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4814                         count = 5;
4815                 else
4816                         count = sclk_table->count;
4817                 for (i = 0; i < count; i++)
4818                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4819                                         i, sclk_table->dpm_levels[i].value / 100,
4820                                         (i == now) ? "*" : "");
4821                 break;
4822         case PP_MCLK:
4823                 if (data->registry_data.mclk_dpm_key_disabled)
4824                         break;
4825
4826                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4827
4828                 for (i = 0; i < mclk_table->count; i++)
4829                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4830                                         i, mclk_table->dpm_levels[i].value / 100,
4831                                         (i == now) ? "*" : "");
4832                 break;
4833         case PP_SOCCLK:
4834                 if (data->registry_data.socclk_dpm_key_disabled)
4835                         break;
4836
4837                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4838
4839                 for (i = 0; i < soc_table->count; i++)
4840                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4841                                         i, soc_table->dpm_levels[i].value / 100,
4842                                         (i == now) ? "*" : "");
4843                 break;
4844         case PP_DCEFCLK:
4845                 if (data->registry_data.dcefclk_dpm_key_disabled)
4846                         break;
4847
4848                 smum_send_msg_to_smc_with_parameter(hwmgr,
4849                                 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now);
4850
4851                 for (i = 0; i < dcef_table->count; i++)
4852                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4853                                         i, dcef_table->dpm_levels[i].value / 100,
4854                                         (dcef_table->dpm_levels[i].value / 100 == now) ?
4855                                         "*" : "");
4856                 break;
4857         case PP_PCIE:
4858                 current_gen_speed =
4859                         vega10_get_current_pcie_link_speed_level(hwmgr);
4860                 current_lane_width =
4861                         vega10_get_current_pcie_link_width_level(hwmgr);
4862                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
4863                         gen_speed = pptable->PcieGenSpeed[i];
4864                         lane_width = pptable->PcieLaneCount[i];
4865
4866                         size += sprintf(buf + size, "%d: %s %s %s\n", i,
4867                                         (gen_speed == 0) ? "2.5GT/s," :
4868                                         (gen_speed == 1) ? "5.0GT/s," :
4869                                         (gen_speed == 2) ? "8.0GT/s," :
4870                                         (gen_speed == 3) ? "16.0GT/s," : "",
4871                                         (lane_width == 1) ? "x1" :
4872                                         (lane_width == 2) ? "x2" :
4873                                         (lane_width == 3) ? "x4" :
4874                                         (lane_width == 4) ? "x8" :
4875                                         (lane_width == 5) ? "x12" :
4876                                         (lane_width == 6) ? "x16" : "",
4877                                         (current_gen_speed == gen_speed) &&
4878                                         (current_lane_width == lane_width) ?
4879                                         "*" : "");
4880                 }
4881                 break;
4882
4883         case OD_SCLK:
4884                 if (hwmgr->od_enabled) {
4885                         size += sprintf(buf + size, "%s:\n", "OD_SCLK");
4886                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4887                         for (i = 0; i < podn_vdd_dep->count; i++)
4888                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4889                                         i, podn_vdd_dep->entries[i].clk / 100,
4890                                                 podn_vdd_dep->entries[i].vddc);
4891                 }
4892                 break;
4893         case OD_MCLK:
4894                 if (hwmgr->od_enabled) {
4895                         size += sprintf(buf + size, "%s:\n", "OD_MCLK");
4896                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4897                         for (i = 0; i < podn_vdd_dep->count; i++)
4898                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4899                                         i, podn_vdd_dep->entries[i].clk/100,
4900                                                 podn_vdd_dep->entries[i].vddc);
4901                 }
4902                 break;
4903         case OD_RANGE:
4904                 if (hwmgr->od_enabled) {
4905                         size += sprintf(buf + size, "%s:\n", "OD_RANGE");
4906                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4907                                 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4908                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4909                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4910                                 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4911                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4912                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4913                                 data->odn_dpm_table.min_vddc,
4914                                 data->odn_dpm_table.max_vddc);
4915                 }
4916                 break;
4917         default:
4918                 break;
4919         }
4920         return size;
4921 }
4922
4923 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4924 {
4925         struct vega10_hwmgr *data = hwmgr->backend;
4926         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4927         int result = 0;
4928
4929         if ((data->water_marks_bitmap & WaterMarksExist) &&
4930                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
4931                 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4932                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
4933                 data->water_marks_bitmap |= WaterMarksLoaded;
4934         }
4935
4936         if (data->water_marks_bitmap & WaterMarksLoaded) {
4937                 smum_send_msg_to_smc_with_parameter(hwmgr,
4938                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
4939                         NULL);
4940         }
4941
4942         return result;
4943 }
4944
4945 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4946 {
4947         struct vega10_hwmgr *data = hwmgr->backend;
4948
4949         if (data->smu_features[GNLD_DPM_UVD].supported) {
4950                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4951                                 enable,
4952                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4953                                 "Attempt to Enable/Disable DPM UVD Failed!",
4954                                 return -1);
4955                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4956         }
4957         return 0;
4958 }
4959
4960 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4961 {
4962         struct vega10_hwmgr *data = hwmgr->backend;
4963
4964         data->vce_power_gated = bgate;
4965         vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4966 }
4967
4968 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4969 {
4970         struct vega10_hwmgr *data = hwmgr->backend;
4971
4972         data->uvd_power_gated = bgate;
4973         vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4974 }
4975
4976 static inline bool vega10_are_power_levels_equal(
4977                                 const struct vega10_performance_level *pl1,
4978                                 const struct vega10_performance_level *pl2)
4979 {
4980         return ((pl1->soc_clock == pl2->soc_clock) &&
4981                         (pl1->gfx_clock == pl2->gfx_clock) &&
4982                         (pl1->mem_clock == pl2->mem_clock));
4983 }
4984
4985 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4986                                 const struct pp_hw_power_state *pstate1,
4987                         const struct pp_hw_power_state *pstate2, bool *equal)
4988 {
4989         const struct vega10_power_state *vega10_psa;
4990         const struct vega10_power_state *vega10_psb;
4991         int i;
4992
4993         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4994                 return -EINVAL;
4995
4996         vega10_psa = cast_const_phw_vega10_power_state(pstate1);
4997         vega10_psb = cast_const_phw_vega10_power_state(pstate2);
4998
4999         /* If the two states don't even have the same number of performance levels
5000          * they cannot be the same state.
5001          */
5002         if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) {
5003                 *equal = false;
5004                 return 0;
5005         }
5006
5007         for (i = 0; i < vega10_psa->performance_level_count; i++) {
5008                 if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]),
5009                                                    &(vega10_psb->performance_levels[i]))) {
5010                         /* If we have found even one performance level pair
5011                          * that is different the states are different.
5012                          */
5013                         *equal = false;
5014                         return 0;
5015                 }
5016         }
5017
5018         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5019         *equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) &&
5020                   (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk));
5021         *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) &&
5022                    (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk));
5023         *equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold);
5024
5025         return 0;
5026 }
5027
5028 static bool
5029 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5030 {
5031         struct vega10_hwmgr *data = hwmgr->backend;
5032         bool is_update_required = false;
5033
5034         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
5035                 is_update_required = true;
5036
5037         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
5038                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
5039                         is_update_required = true;
5040         }
5041
5042         return is_update_required;
5043 }
5044
5045 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
5046 {
5047         int tmp_result, result = 0;
5048
5049         if (!hwmgr->not_vf)
5050                 return 0;
5051
5052         if (PP_CAP(PHM_PlatformCaps_ThermalController))
5053                 vega10_disable_thermal_protection(hwmgr);
5054
5055         tmp_result = vega10_disable_power_containment(hwmgr);
5056         PP_ASSERT_WITH_CODE((tmp_result == 0),
5057                         "Failed to disable power containment!", result = tmp_result);
5058
5059         tmp_result = vega10_disable_didt_config(hwmgr);
5060         PP_ASSERT_WITH_CODE((tmp_result == 0),
5061                         "Failed to disable didt config!", result = tmp_result);
5062
5063         tmp_result = vega10_avfs_enable(hwmgr, false);
5064         PP_ASSERT_WITH_CODE((tmp_result == 0),
5065                         "Failed to disable AVFS!", result = tmp_result);
5066
5067         tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
5068         PP_ASSERT_WITH_CODE((tmp_result == 0),
5069                         "Failed to stop DPM!", result = tmp_result);
5070
5071         tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
5072         PP_ASSERT_WITH_CODE((tmp_result == 0),
5073                         "Failed to disable deep sleep!", result = tmp_result);
5074
5075         tmp_result = vega10_disable_ulv(hwmgr);
5076         PP_ASSERT_WITH_CODE((tmp_result == 0),
5077                         "Failed to disable ulv!", result = tmp_result);
5078
5079         tmp_result =  vega10_acg_disable(hwmgr);
5080         PP_ASSERT_WITH_CODE((tmp_result == 0),
5081                         "Failed to disable acg!", result = tmp_result);
5082
5083         vega10_enable_disable_PCC_limit_feature(hwmgr, false);
5084         return result;
5085 }
5086
5087 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
5088 {
5089         struct vega10_hwmgr *data = hwmgr->backend;
5090         int result;
5091
5092         result = vega10_disable_dpm_tasks(hwmgr);
5093         PP_ASSERT_WITH_CODE((0 == result),
5094                         "[disable_dpm_tasks] Failed to disable DPM!",
5095                         );
5096         data->water_marks_bitmap &= ~(WaterMarksLoaded);
5097
5098         return result;
5099 }
5100
5101 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
5102 {
5103         struct vega10_hwmgr *data = hwmgr->backend;
5104         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
5105         struct vega10_single_dpm_table *golden_sclk_table =
5106                         &(data->golden_dpm_table.gfx_table);
5107         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
5108         int golden_value = golden_sclk_table->dpm_levels
5109                         [golden_sclk_table->count - 1].value;
5110
5111         value -= golden_value;
5112         value = DIV_ROUND_UP(value * 100, golden_value);
5113
5114         return value;
5115 }
5116
5117 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5118 {
5119         struct vega10_hwmgr *data = hwmgr->backend;
5120         struct vega10_single_dpm_table *golden_sclk_table =
5121                         &(data->golden_dpm_table.gfx_table);
5122         struct pp_power_state *ps;
5123         struct vega10_power_state *vega10_ps;
5124
5125         ps = hwmgr->request_ps;
5126
5127         if (ps == NULL)
5128                 return -EINVAL;
5129
5130         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5131
5132         vega10_ps->performance_levels
5133         [vega10_ps->performance_level_count - 1].gfx_clock =
5134                         golden_sclk_table->dpm_levels
5135                         [golden_sclk_table->count - 1].value *
5136                         value / 100 +
5137                         golden_sclk_table->dpm_levels
5138                         [golden_sclk_table->count - 1].value;
5139
5140         if (vega10_ps->performance_levels
5141                         [vega10_ps->performance_level_count - 1].gfx_clock >
5142                         hwmgr->platform_descriptor.overdriveLimit.engineClock) {
5143                 vega10_ps->performance_levels
5144                 [vega10_ps->performance_level_count - 1].gfx_clock =
5145                                 hwmgr->platform_descriptor.overdriveLimit.engineClock;
5146                 pr_warn("max sclk supported by vbios is %d\n",
5147                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
5148         }
5149         return 0;
5150 }
5151
5152 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
5153 {
5154         struct vega10_hwmgr *data = hwmgr->backend;
5155         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
5156         struct vega10_single_dpm_table *golden_mclk_table =
5157                         &(data->golden_dpm_table.mem_table);
5158         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
5159         int golden_value = golden_mclk_table->dpm_levels
5160                         [golden_mclk_table->count - 1].value;
5161
5162         value -= golden_value;
5163         value = DIV_ROUND_UP(value * 100, golden_value);
5164
5165         return value;
5166 }
5167
5168 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5169 {
5170         struct vega10_hwmgr *data = hwmgr->backend;
5171         struct vega10_single_dpm_table *golden_mclk_table =
5172                         &(data->golden_dpm_table.mem_table);
5173         struct pp_power_state  *ps;
5174         struct vega10_power_state  *vega10_ps;
5175
5176         ps = hwmgr->request_ps;
5177
5178         if (ps == NULL)
5179                 return -EINVAL;
5180
5181         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5182
5183         vega10_ps->performance_levels
5184         [vega10_ps->performance_level_count - 1].mem_clock =
5185                         golden_mclk_table->dpm_levels
5186                         [golden_mclk_table->count - 1].value *
5187                         value / 100 +
5188                         golden_mclk_table->dpm_levels
5189                         [golden_mclk_table->count - 1].value;
5190
5191         if (vega10_ps->performance_levels
5192                         [vega10_ps->performance_level_count - 1].mem_clock >
5193                         hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
5194                 vega10_ps->performance_levels
5195                 [vega10_ps->performance_level_count - 1].mem_clock =
5196                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
5197                 pr_warn("max mclk supported by vbios is %d\n",
5198                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
5199         }
5200
5201         return 0;
5202 }
5203
5204 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
5205                                         uint32_t virtual_addr_low,
5206                                         uint32_t virtual_addr_hi,
5207                                         uint32_t mc_addr_low,
5208                                         uint32_t mc_addr_hi,
5209                                         uint32_t size)
5210 {
5211         smum_send_msg_to_smc_with_parameter(hwmgr,
5212                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
5213                                         virtual_addr_hi,
5214                                         NULL);
5215         smum_send_msg_to_smc_with_parameter(hwmgr,
5216                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
5217                                         virtual_addr_low,
5218                                         NULL);
5219         smum_send_msg_to_smc_with_parameter(hwmgr,
5220                                         PPSMC_MSG_DramLogSetDramAddrHigh,
5221                                         mc_addr_hi,
5222                                         NULL);
5223
5224         smum_send_msg_to_smc_with_parameter(hwmgr,
5225                                         PPSMC_MSG_DramLogSetDramAddrLow,
5226                                         mc_addr_low,
5227                                         NULL);
5228
5229         smum_send_msg_to_smc_with_parameter(hwmgr,
5230                                         PPSMC_MSG_DramLogSetDramSize,
5231                                         size,
5232                                         NULL);
5233         return 0;
5234 }
5235
5236 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5237                 struct PP_TemperatureRange *thermal_data)
5238 {
5239         struct vega10_hwmgr *data = hwmgr->backend;
5240         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
5241         struct phm_ppt_v2_information *pp_table_info =
5242                 (struct phm_ppt_v2_information *)(hwmgr->pptable);
5243         struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
5244
5245         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
5246
5247         thermal_data->max = pp_table->TedgeLimit *
5248                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5249         thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
5250                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5251         thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
5252                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5253         thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
5254                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5255         thermal_data->mem_crit_max = pp_table->ThbmLimit *
5256                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5257         thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
5258                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5259
5260         if (tdp_table->usSoftwareShutdownTemp > pp_table->ThotspotLimit &&
5261             tdp_table->usSoftwareShutdownTemp < VEGA10_THERMAL_MAXIMUM_ALERT_TEMP)
5262                 thermal_data->sw_ctf_threshold = tdp_table->usSoftwareShutdownTemp;
5263         else
5264                 thermal_data->sw_ctf_threshold = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
5265         thermal_data->sw_ctf_threshold *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5266
5267         return 0;
5268 }
5269
5270 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5271 {
5272         struct vega10_hwmgr *data = hwmgr->backend;
5273         uint32_t i, size = 0;
5274         static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
5275                                                 {70, 60, 1, 3,},
5276                                                 {90, 60, 0, 0,},
5277                                                 {70, 60, 0, 0,},
5278                                                 {70, 90, 0, 0,},
5279                                                 {30, 60, 0, 6,},
5280                                                 };
5281         static const char *title[6] = {"NUM",
5282                         "MODE_NAME",
5283                         "BUSY_SET_POINT",
5284                         "FPS",
5285                         "USE_RLC_BUSY",
5286                         "MIN_ACTIVE_LEVEL"};
5287
5288         if (!buf)
5289                 return -EINVAL;
5290
5291         phm_get_sysfs_buf(&buf, &size);
5292
5293         size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0],
5294                         title[1], title[2], title[3], title[4], title[5]);
5295
5296         for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
5297                 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n",
5298                         i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5299                         profile_mode_setting[i][0], profile_mode_setting[i][1],
5300                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
5301
5302         size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
5303                         amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5304                         data->custom_profile_mode[0], data->custom_profile_mode[1],
5305                         data->custom_profile_mode[2], data->custom_profile_mode[3]);
5306         return size;
5307 }
5308
5309 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr)
5310 {
5311         struct amdgpu_device *adev = hwmgr->adev;
5312
5313         return (adev->pdev->device == 0x6860);
5314 }
5315
5316 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5317 {
5318         struct vega10_hwmgr *data = hwmgr->backend;
5319         uint8_t busy_set_point;
5320         uint8_t FPS;
5321         uint8_t use_rlc_busy;
5322         uint8_t min_active_level;
5323         uint32_t power_profile_mode = input[size];
5324
5325         if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
5326                 if (size != 0 && size != 4)
5327                         return -EINVAL;
5328
5329                 /* If size = 0 and the CUSTOM profile has been set already
5330                  * then just apply the profile. The copy stored in the hwmgr
5331                  * is zeroed out on init
5332                  */
5333                 if (size == 0) {
5334                         if (data->custom_profile_mode[0] != 0)
5335                                 goto out;
5336                         else
5337                                 return -EINVAL;
5338                 }
5339
5340                 data->custom_profile_mode[0] = busy_set_point = input[0];
5341                 data->custom_profile_mode[1] = FPS = input[1];
5342                 data->custom_profile_mode[2] = use_rlc_busy = input[2];
5343                 data->custom_profile_mode[3] = min_active_level = input[3];
5344                 smum_send_msg_to_smc_with_parameter(hwmgr,
5345                                         PPSMC_MSG_SetCustomGfxDpmParameters,
5346                                         busy_set_point | FPS<<8 |
5347                                         use_rlc_busy << 16 | min_active_level<<24,
5348                                         NULL);
5349         }
5350
5351 out:
5352         if (vega10_get_power_profile_mode_quirks(hwmgr))
5353                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5354                                                 1 << power_profile_mode,
5355                                                 NULL);
5356         else
5357                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5358                                                 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1),
5359                                                 NULL);
5360
5361         hwmgr->power_profile_mode = power_profile_mode;
5362
5363         return 0;
5364 }
5365
5366
5367 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5368                                         enum PP_OD_DPM_TABLE_COMMAND type,
5369                                         uint32_t clk,
5370                                         uint32_t voltage)
5371 {
5372         struct vega10_hwmgr *data = hwmgr->backend;
5373         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
5374         struct vega10_single_dpm_table *golden_table;
5375
5376         if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
5377                 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
5378                 return false;
5379         }
5380
5381         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5382                 golden_table = &(data->golden_dpm_table.gfx_table);
5383                 if (golden_table->dpm_levels[0].value > clk ||
5384                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5385                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5386                                 golden_table->dpm_levels[0].value/100,
5387                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5388                         return false;
5389                 }
5390         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5391                 golden_table = &(data->golden_dpm_table.mem_table);
5392                 if (golden_table->dpm_levels[0].value > clk ||
5393                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5394                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5395                                 golden_table->dpm_levels[0].value/100,
5396                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5397                         return false;
5398                 }
5399         } else {
5400                 return false;
5401         }
5402
5403         return true;
5404 }
5405
5406 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
5407 {
5408         struct vega10_hwmgr *data = hwmgr->backend;
5409         struct pp_power_state *ps = hwmgr->request_ps;
5410         struct vega10_power_state *vega10_ps;
5411         struct vega10_single_dpm_table *gfx_dpm_table =
5412                 &data->dpm_table.gfx_table;
5413         struct vega10_single_dpm_table *soc_dpm_table =
5414                 &data->dpm_table.soc_table;
5415         struct vega10_single_dpm_table *mem_dpm_table =
5416                 &data->dpm_table.mem_table;
5417         int max_level;
5418
5419         if (!ps)
5420                 return;
5421
5422         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5423         max_level = vega10_ps->performance_level_count - 1;
5424
5425         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5426             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5427                 vega10_ps->performance_levels[max_level].gfx_clock =
5428                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5429
5430         if (vega10_ps->performance_levels[max_level].soc_clock !=
5431             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5432                 vega10_ps->performance_levels[max_level].soc_clock =
5433                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5434
5435         if (vega10_ps->performance_levels[max_level].mem_clock !=
5436             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5437                 vega10_ps->performance_levels[max_level].mem_clock =
5438                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5439
5440         if (!hwmgr->ps)
5441                 return;
5442
5443         ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
5444         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5445         max_level = vega10_ps->performance_level_count - 1;
5446
5447         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5448             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5449                 vega10_ps->performance_levels[max_level].gfx_clock =
5450                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5451
5452         if (vega10_ps->performance_levels[max_level].soc_clock !=
5453             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5454                 vega10_ps->performance_levels[max_level].soc_clock =
5455                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5456
5457         if (vega10_ps->performance_levels[max_level].mem_clock !=
5458             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5459                 vega10_ps->performance_levels[max_level].mem_clock =
5460                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5461 }
5462
5463 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
5464                                                 enum PP_OD_DPM_TABLE_COMMAND type)
5465 {
5466         struct vega10_hwmgr *data = hwmgr->backend;
5467         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
5468         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
5469         struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table;
5470
5471         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
5472                                                         &data->odn_dpm_table.vdd_dep_on_socclk;
5473         struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
5474
5475         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
5476         uint8_t i, j;
5477
5478         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5479                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
5480                 for (i = 0; i < podn_vdd_dep->count; i++)
5481                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
5482         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5483                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5484                 for (i = 0; i < dpm_table->count; i++) {
5485                         for (j = 0; j < od_vddc_lookup_table->count; j++) {
5486                                 if (od_vddc_lookup_table->entries[j].us_vdd >
5487                                         podn_vdd_dep->entries[i].vddc)
5488                                         break;
5489                         }
5490                         if (j == od_vddc_lookup_table->count) {
5491                                 j = od_vddc_lookup_table->count - 1;
5492                                 od_vddc_lookup_table->entries[j].us_vdd =
5493                                         podn_vdd_dep->entries[i].vddc;
5494                                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
5495                         }
5496                         podn_vdd_dep->entries[i].vddInd = j;
5497                 }
5498                 dpm_table = &data->dpm_table.soc_table;
5499                 for (i = 0; i < dep_table->count; i++) {
5500                         if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd &&
5501                                         dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {
5502                                 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5503                                 for (; (i < dep_table->count) &&
5504                                        (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {
5505                                         podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;
5506                                         dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
5507                                 }
5508                                 break;
5509                         } else {
5510                                 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;
5511                                 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc;
5512                                 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd;
5513                                 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;
5514                         }
5515                 }
5516                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
5517                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {
5518                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5519                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =
5520                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5521                         dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value =
5522                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5523                 }
5524                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
5525                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) {
5526                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5527                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd =
5528                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
5529                 }
5530         }
5531         vega10_odn_update_power_state(hwmgr);
5532 }
5533
5534 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5535                                         enum PP_OD_DPM_TABLE_COMMAND type,
5536                                         long *input, uint32_t size)
5537 {
5538         struct vega10_hwmgr *data = hwmgr->backend;
5539         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
5540         struct vega10_single_dpm_table *dpm_table;
5541
5542         uint32_t input_clk;
5543         uint32_t input_vol;
5544         uint32_t input_level;
5545         uint32_t i;
5546
5547         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5548                                 return -EINVAL);
5549
5550         if (!hwmgr->od_enabled) {
5551                 pr_info("OverDrive feature not enabled\n");
5552                 return -EINVAL;
5553         }
5554
5555         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5556                 dpm_table = &data->dpm_table.gfx_table;
5557                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
5558                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5559         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5560                 dpm_table = &data->dpm_table.mem_table;
5561                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
5562                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5563         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5564                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
5565                 vega10_odn_initial_default_setting(hwmgr);
5566                 vega10_odn_update_power_state(hwmgr);
5567                 /* force to update all clock tables */
5568                 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK |
5569                                               DPMTABLE_UPDATE_MCLK |
5570                                               DPMTABLE_UPDATE_SOCCLK;
5571                 return 0;
5572         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5573                 vega10_check_dpm_table_updated(hwmgr);
5574                 return 0;
5575         } else {
5576                 return -EINVAL;
5577         }
5578
5579         for (i = 0; i < size; i += 3) {
5580                 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
5581                         pr_info("invalid clock voltage input\n");
5582                         return 0;
5583                 }
5584                 input_level = input[i];
5585                 input_clk = input[i+1] * 100;
5586                 input_vol = input[i+2];
5587
5588                 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5589                         dpm_table->dpm_levels[input_level].value = input_clk;
5590                         podn_vdd_dep_table->entries[input_level].clk = input_clk;
5591                         podn_vdd_dep_table->entries[input_level].vddc = input_vol;
5592                 } else {
5593                         return -EINVAL;
5594                 }
5595         }
5596         vega10_odn_update_soc_table(hwmgr, type);
5597         return 0;
5598 }
5599
5600 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
5601                                 enum pp_mp1_state mp1_state)
5602 {
5603         uint16_t msg;
5604         int ret;
5605
5606         switch (mp1_state) {
5607         case PP_MP1_STATE_UNLOAD:
5608                 msg = PPSMC_MSG_PrepareMp1ForUnload;
5609                 break;
5610         case PP_MP1_STATE_SHUTDOWN:
5611         case PP_MP1_STATE_RESET:
5612         case PP_MP1_STATE_NONE:
5613         default:
5614                 return 0;
5615         }
5616
5617         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
5618                             "[PrepareMp1] Failed!",
5619                             return ret);
5620
5621         return 0;
5622 }
5623
5624 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5625                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5626                                 PHM_PerformanceLevel *level)
5627 {
5628         const struct vega10_power_state *vega10_ps;
5629         uint32_t i;
5630
5631         if (level == NULL || hwmgr == NULL || state == NULL)
5632                 return -EINVAL;
5633
5634         vega10_ps = cast_const_phw_vega10_power_state(state);
5635
5636         i = index > vega10_ps->performance_level_count - 1 ?
5637                         vega10_ps->performance_level_count - 1 : index;
5638
5639         level->coreClock = vega10_ps->performance_levels[i].gfx_clock;
5640         level->memory_clock = vega10_ps->performance_levels[i].mem_clock;
5641
5642         return 0;
5643 }
5644
5645 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
5646 {
5647         struct vega10_hwmgr *data = hwmgr->backend;
5648         uint32_t feature_mask = 0;
5649
5650         if (disable) {
5651                 feature_mask |= data->smu_features[GNLD_ULV].enabled ?
5652                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5653                 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
5654                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5655                 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
5656                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5657                 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
5658                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5659                 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
5660                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5661         } else {
5662                 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
5663                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5664                 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
5665                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5666                 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
5667                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5668                 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
5669                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5670                 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
5671                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5672         }
5673
5674         if (feature_mask)
5675                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
5676                                 !disable, feature_mask),
5677                                 "enable/disable power features for compute performance Failed!",
5678                                 return -EINVAL);
5679
5680         if (disable) {
5681                 data->smu_features[GNLD_ULV].enabled = false;
5682                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
5683                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
5684                 data->smu_features[GNLD_DS_LCLK].enabled = false;
5685                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
5686         } else {
5687                 data->smu_features[GNLD_ULV].enabled = true;
5688                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
5689                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
5690                 data->smu_features[GNLD_DS_LCLK].enabled = true;
5691                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
5692         }
5693
5694         return 0;
5695
5696 }
5697
5698 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
5699         .backend_init = vega10_hwmgr_backend_init,
5700         .backend_fini = vega10_hwmgr_backend_fini,
5701         .asic_setup = vega10_setup_asic_task,
5702         .dynamic_state_management_enable = vega10_enable_dpm_tasks,
5703         .dynamic_state_management_disable = vega10_disable_dpm_tasks,
5704         .get_num_of_pp_table_entries =
5705                         vega10_get_number_of_powerplay_table_entries,
5706         .get_power_state_size = vega10_get_power_state_size,
5707         .get_pp_table_entry = vega10_get_pp_table_entry,
5708         .patch_boot_state = vega10_patch_boot_state,
5709         .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
5710         .power_state_set = vega10_set_power_state_tasks,
5711         .get_sclk = vega10_dpm_get_sclk,
5712         .get_mclk = vega10_dpm_get_mclk,
5713         .notify_smc_display_config_after_ps_adjustment =
5714                         vega10_notify_smc_display_config_after_ps_adjustment,
5715         .force_dpm_level = vega10_dpm_force_dpm_level,
5716         .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
5717         .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
5718         .get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm,
5719         .set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm,
5720         .reset_fan_speed_to_default =
5721                         vega10_fan_ctrl_reset_fan_speed_to_default,
5722         .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
5723         .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
5724         .uninitialize_thermal_controller =
5725                         vega10_thermal_ctrl_uninitialize_thermal_controller,
5726         .set_fan_control_mode = vega10_set_fan_control_mode,
5727         .get_fan_control_mode = vega10_get_fan_control_mode,
5728         .read_sensor = vega10_read_sensor,
5729         .get_dal_power_level = vega10_get_dal_power_level,
5730         .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
5731         .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
5732         .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
5733         .display_clock_voltage_request = vega10_display_clock_voltage_request,
5734         .force_clock_level = vega10_force_clock_level,
5735         .emit_clock_levels = vega10_emit_clock_levels,
5736         .print_clock_levels = vega10_print_clock_levels,
5737         .display_config_changed = vega10_display_configuration_changed_task,
5738         .powergate_uvd = vega10_power_gate_uvd,
5739         .powergate_vce = vega10_power_gate_vce,
5740         .check_states_equal = vega10_check_states_equal,
5741         .check_smc_update_required_for_display_configuration =
5742                         vega10_check_smc_update_required_for_display_configuration,
5743         .power_off_asic = vega10_power_off_asic,
5744         .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
5745         .get_sclk_od = vega10_get_sclk_od,
5746         .set_sclk_od = vega10_set_sclk_od,
5747         .get_mclk_od = vega10_get_mclk_od,
5748         .set_mclk_od = vega10_set_mclk_od,
5749         .avfs_control = vega10_avfs_enable,
5750         .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
5751         .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
5752         .register_irq_handlers = smu9_register_irq_handlers,
5753         .start_thermal_controller = vega10_start_thermal_controller,
5754         .get_power_profile_mode = vega10_get_power_profile_mode,
5755         .set_power_profile_mode = vega10_set_power_profile_mode,
5756         .set_power_limit = vega10_set_power_limit,
5757         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
5758         .get_performance_level = vega10_get_performance_level,
5759         .get_asic_baco_capability = smu9_baco_get_capability,
5760         .get_asic_baco_state = smu9_baco_get_state,
5761         .set_asic_baco_state = vega10_baco_set_state,
5762         .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
5763         .get_ppfeature_status = vega10_get_ppfeature_status,
5764         .set_ppfeature_status = vega10_set_ppfeature_status,
5765         .set_mp1_state = vega10_set_mp1_state,
5766         .disable_power_features_for_compute_performance =
5767                         vega10_disable_power_features_for_compute_performance,
5768 };
5769
5770 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
5771 {
5772         struct amdgpu_device *adev = hwmgr->adev;
5773
5774         hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
5775         hwmgr->pptable_func = &vega10_pptable_funcs;
5776         if (amdgpu_passthrough(adev))
5777                 return vega10_baco_set_cap(hwmgr);
5778
5779         return 0;
5780 }