drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

   1 /* SPDX-License-Identifier: MIT */
   2 /* Copyright 2024 Advanced Micro Devices, Inc. */
   3
   4
   5 #include "dm_services.h"
   6 #include "dc.h"
   7
   8 #include "dcn31/dcn31_init.h"
   9 #include "dcn351/dcn351_init.h"
  10
  11 #include "resource.h"
  12 #include "include/irq_service_interface.h"
  13 #include "dcn351_resource.h"
  14
  15 #include "dcn20/dcn20_resource.h"
  16 #include "dcn30/dcn30_resource.h"
  17 #include "dcn31/dcn31_resource.h"
  18 #include "dcn32/dcn32_resource.h"
  19 #include "dcn35/dcn35_resource.h"
  20
  21 #include "dcn10/dcn10_ipp.h"
  22 #include "dcn30/dcn30_hubbub.h"
  23 #include "dcn31/dcn31_hubbub.h"
  24 #include "dcn35/dcn35_hubbub.h"
  25 #include "dcn32/dcn32_mpc.h"
  26 #include "dcn35/dcn35_hubp.h"
  27 #include "irq/dcn351/irq_service_dcn351.h"
  28 #include "dcn35/dcn35_dpp.h"
  29 #include "dcn35/dcn35_optc.h"
  30 #include "dcn20/dcn20_hwseq.h"
  31 #include "dcn30/dcn30_hwseq.h"
  32 #include "dce110/dce110_hwseq.h"
  33 #include "dcn35/dcn35_opp.h"
  34 #include "dcn35/dcn35_dsc.h"
  35 #include "dcn30/dcn30_vpg.h"
  36 #include "dcn30/dcn30_afmt.h"
  37
  38 #include "dcn31/dcn31_dio_link_encoder.h"
  39 #include "dcn35/dcn35_dio_stream_encoder.h"
  40 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  41 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  42 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
  43 #include "link.h"
  44 #include "dcn31/dcn31_apg.h"
  45 #include "dcn32/dcn32_dio_link_encoder.h"
  46 #include "dcn31/dcn31_vpg.h"
  47 #include "dcn31/dcn31_afmt.h"
  48 #include "dce/dce_clock_source.h"
  49 #include "dce/dce_audio.h"
  50 #include "dce/dce_hwseq.h"
  51 #include "clk_mgr.h"
  52 #include "virtual/virtual_stream_encoder.h"
  53 #include "dce110/dce110_resource.h"
  54 #include "dml/display_mode_vba.h"
  55 #include "dcn35/dcn35_dccg.h"
  56 #include "dcn35/dcn35_pg_cntl.h"
  57 #include "dcn10/dcn10_resource.h"
  58 #include "dcn31/dcn31_panel_cntl.h"
  59 #include "dcn35/dcn35_hwseq.h"
  60 #include "dcn35/dcn35_dio_link_encoder.h"
  61 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
  62 #include "dml/dcn35/dcn35_fpu.h"
  63 #include "dml/dcn351/dcn351_fpu.h"
  64 #include "dcn35/dcn35_dwb.h"
  65 #include "dcn35/dcn35_mmhubbub.h"
  66
  67 #include "dcn/dcn_3_5_1_offset.h"
  68 #include "dcn/dcn_3_5_1_sh_mask.h"
  69 #include "nbio/nbio_7_11_0_offset.h"
  70 #include "mmhub/mmhub_3_3_0_offset.h"
  71 #include "mmhub/mmhub_3_3_0_sh_mask.h"
  72
  73 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
  74 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
  75
  76 #include "reg_helper.h"
  77 #include "dce/dmub_abm.h"
  78 #include "dce/dmub_psr.h"
  79 #include "dce/dmub_replay.h"
  80 #include "dce/dce_aux.h"
  81 #include "dce/dce_i2c.h"
  82 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
  83 #include "vm_helper.h"
  84 #include "dcn20/dcn20_vmid.h"
  85
  86 #include "dml2/dml2_wrapper.h"
  87
  88 #include "link_enc_cfg.h"
  89 #define DC_LOGGER_INIT(logger)
  90
  91 enum dcn351_clk_src_array_id {
  92         DCN351_CLK_SRC_PLL0,
  93         DCN351_CLK_SRC_PLL1,
  94         DCN351_CLK_SRC_PLL2,
  95         DCN351_CLK_SRC_PLL3,
  96         DCN351_CLK_SRC_PLL4,
  97         DCN351_CLK_SRC_TOTAL
  98 };
  99
 100 /* begin *********************
 101  * macros to expend register list macro defined in HW object header file
 102  */
 103
 104 /* DCN */
 105 /* TODO awful hack. fixup dcn20_dwb.h */
 106 #undef BASE_INNER
 107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 108
 109 #define BASE(seg) BASE_INNER(seg)
 110
 111 #define SR(reg_name)\
 112                 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 113                                         reg ## reg_name
 114
 115 #define SR_ARR(reg_name, id) \
 116         REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 117
 118 #define SR_ARR_INIT(reg_name, id, value) \
 119         REG_STRUCT[id].reg_name = value
 120
 121 #define SRI(reg_name, block, id)\
 122         REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 123                                         reg ## block ## id ## _ ## reg_name
 124
 125 #define SRI_ARR(reg_name, block, id)\
 126         REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 127                 reg ## block ## id ## _ ## reg_name
 128
 129 #define SR_ARR_I2C(reg_name, id) \
 130         REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 131
 132 #define SRI_ARR_I2C(reg_name, block, id)\
 133         REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 134                 reg ## block ## id ## _ ## reg_name
 135
 136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 137         REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 138                 reg ## block ## id ## _ ## reg_name
 139
 140 #define SRI2(reg_name, block, id)\
 141         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 142                                         reg ## reg_name
 143
 144 #define SRI2_ARR(reg_name, block, id)\
 145         REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 146                 reg ## reg_name
 147
 148 #define SRIR(var_name, reg_name, block, id)\
 149         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 150                                         reg ## block ## id ## _ ## reg_name
 151
 152 #define SRII(reg_name, block, id)\
 153         REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 154                                         reg ## block ## id ## _ ## reg_name
 155
 156 #define SRII_ARR_2(reg_name, block, id, inst)\
 157         REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 158                 reg ## block ## id ## _ ## reg_name
 159
 160 #define SRII_MPC_RMU(reg_name, block, id)\
 161         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 162                                         reg ## block ## id ## _ ## reg_name
 163
 164 #define SRII_DWB(reg_name, temp_name, block, id)\
 165         REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 166                 reg ## block ## id ## _ ## temp_name
 167
 168 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 169         .field_name = reg_name ## __ ## field_name ## post_fix
 170
 171 #define DCCG_SRII(reg_name, block, id)\
 172         REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 173                 reg ## block ## id ## _ ## reg_name
 174
 175 #define VUPDATE_SRII(reg_name, block, id)\
 176         REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 177                 reg ## reg_name ## _ ## block ## id
 178
 179 /* NBIO */
 180 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 181
 182 #define NBIO_BASE(seg) \
 183         NBIO_BASE_INNER(seg)
 184
 185 #define NBIO_SR(reg_name)\
 186         REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 187                                 regBIF_BX2_ ## reg_name
 188
 189 #define NBIO_SR_ARR(reg_name, id)\
 190         REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 191                 regBIF_BX2_ ## reg_name
 192
 193 #define bios_regs_init() \
 194                 ( \
 195                 NBIO_SR(BIOS_SCRATCH_3),\
 196                 NBIO_SR(BIOS_SCRATCH_6)\
 197                 )
 198
 199 static struct bios_registers bios_regs;
 200
 201 #define clk_src_regs_init(index, pllid)\
 202         CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 203
 204 static struct dce110_clk_src_regs clk_src_regs[5];
 205
 206 static const struct dce110_clk_src_shift cs_shift = {
 207                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 208 };
 209
 210 static const struct dce110_clk_src_mask cs_mask = {
 211                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 212 };
 213
 214 #define abm_regs_init(id)\
 215                 ABM_DCN32_REG_LIST_RI(id)
 216
 217 static struct dce_abm_registers abm_regs[4];
 218
 219 static const struct dce_abm_shift abm_shift = {
 220                 ABM_MASK_SH_LIST_DCN35(__SHIFT)
 221 };
 222
 223 static const struct dce_abm_mask abm_mask = {
 224                 ABM_MASK_SH_LIST_DCN35(_MASK)
 225 };
 226
 227 #define audio_regs_init(id)\
 228                 AUD_COMMON_REG_LIST_RI(id)
 229
 230 static struct dce_audio_registers audio_regs[7];
 231
 232
 233 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 234                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 235                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 236                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 237
 238 static const struct dce_audio_shift audio_shift = {
 239                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 240 };
 241
 242 static const struct dce_audio_mask audio_mask = {
 243                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 244 };
 245
 246 #define vpg_regs_init(id)\
 247         VPG_DCN31_REG_LIST_RI(id)
 248
 249 static struct dcn31_vpg_registers vpg_regs[10];
 250
 251 static const struct dcn31_vpg_shift vpg_shift = {
 252         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 253 };
 254
 255 static const struct dcn31_vpg_mask vpg_mask = {
 256         DCN31_VPG_MASK_SH_LIST(_MASK)
 257 };
 258
 259 #define afmt_regs_init(id)\
 260         AFMT_DCN31_REG_LIST_RI(id)
 261
 262 static struct dcn31_afmt_registers afmt_regs[6];
 263
 264 static const struct dcn31_afmt_shift afmt_shift = {
 265         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 266 };
 267
 268 static const struct dcn31_afmt_mask afmt_mask = {
 269         DCN31_AFMT_MASK_SH_LIST(_MASK)
 270 };
 271
 272 #define apg_regs_init(id)\
 273         APG_DCN31_REG_LIST_RI(id)
 274
 275 static struct dcn31_apg_registers apg_regs[4];
 276
 277 static const struct dcn31_apg_shift apg_shift = {
 278         DCN31_APG_MASK_SH_LIST(__SHIFT)
 279 };
 280
 281 static const struct dcn31_apg_mask apg_mask = {
 282         DCN31_APG_MASK_SH_LIST(_MASK)
 283 };
 284
 285 #define stream_enc_regs_init(id)\
 286         SE_DCN35_REG_LIST_RI(id)
 287
 288 static struct dcn10_stream_enc_registers stream_enc_regs[5];
 289
 290 static const struct dcn10_stream_encoder_shift se_shift = {
 291                 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 292 };
 293
 294 static const struct dcn10_stream_encoder_mask se_mask = {
 295                 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
 296 };
 297
 298 #define aux_regs_init(id)\
 299         DCN2_AUX_REG_LIST_RI(id)
 300
 301 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 302
 303 #define hpd_regs_init(id)\
 304         HPD_REG_LIST_RI(id)
 305
 306 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 307
 308
 309 static const struct dce110_aux_registers_shift aux_shift = {
 310         DCN_AUX_MASK_SH_LIST(__SHIFT)
 311 };
 312
 313 static const struct dce110_aux_registers_mask aux_mask = {
 314         DCN_AUX_MASK_SH_LIST(_MASK)
 315 };
 316
 317 #define link_regs_init(id, phyid)\
 318         ( \
 319         LE_DCN35_REG_LIST_RI(id), \
 320         UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
 321         )
 322
 323 static struct dcn10_link_enc_registers link_enc_regs[5];
 324
 325 static const struct dcn10_link_enc_shift le_shift = {
 326         LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
 327         //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 328 };
 329
 330 static const struct dcn10_link_enc_mask le_mask = {
 331         LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
 332         //DPCS_DCN31_MASK_SH_LIST(_MASK)
 333 };
 334
 335 #define hpo_dp_stream_encoder_reg_init(id)\
 336         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 337
 338 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 339
 340 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 341         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 342 };
 343
 344 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 345         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 346 };
 347
 348 #define hpo_dp_link_encoder_reg_init(id)\
 349         DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 350         /*DCN3_1_RDPCSTX_REG_LIST(0),*/
 351         /*DCN3_1_RDPCSTX_REG_LIST(1),*/
 352         /*DCN3_1_RDPCSTX_REG_LIST(2),*/
 353         /*DCN3_1_RDPCSTX_REG_LIST(3),*/
 354
 355 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
 356
 357 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 358         DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
 359 };
 360
 361 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 362         DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
 363 };
 364
 365 #define dpp_regs_init(id)\
 366         DPP_REG_LIST_DCN35_RI(id)
 367
 368 static struct dcn3_dpp_registers dpp_regs[4];
 369
 370 static const struct dcn35_dpp_shift tf_shift = {
 371                 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
 372 };
 373
 374 static const struct dcn35_dpp_mask tf_mask = {
 375                 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
 376 };
 377
 378 #define opp_regs_init(id)\
 379         OPP_REG_LIST_DCN35_RI(id)
 380
 381 static struct dcn35_opp_registers opp_regs[4];
 382
 383 static const struct dcn35_opp_shift opp_shift = {
 384         OPP_MASK_SH_LIST_DCN35(__SHIFT)
 385 };
 386
 387 static const struct dcn35_opp_mask opp_mask = {
 388         OPP_MASK_SH_LIST_DCN35(_MASK)
 389 };
 390
 391 #define aux_engine_regs_init(id)\
 392         ( \
 393         AUX_COMMON_REG_LIST0_RI(id), \
 394         SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 395         SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 396         SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
 397         )
 398
 399 static struct dce110_aux_registers aux_engine_regs[5];
 400
 401 #define dwbc_regs_dcn3_init(id)\
 402         DWBC_COMMON_REG_LIST_DCN30_RI(id)
 403
 404 static struct dcn30_dwbc_registers dwbc35_regs[1];
 405
 406 static const struct dcn35_dwbc_shift dwbc35_shift = {
 407         DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 408 };
 409
 410 static const struct dcn35_dwbc_mask dwbc35_mask = {
 411         DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
 412 };
 413
 414 #define mcif_wb_regs_dcn3_init(id)\
 415         MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
 416
 417 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
 418
 419 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
 420         MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 421 };
 422
 423 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
 424         MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 425 };
 426
 427 #define dsc_regsDCN35_init(id)\
 428         DSC_REG_LIST_DCN20_RI(id)
 429
 430 static struct dcn20_dsc_registers dsc_regs[4];
 431
 432 static const struct dcn35_dsc_shift dsc_shift = {
 433         DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
 434 };
 435
 436 static const struct dcn35_dsc_mask dsc_mask = {
 437         DSC_REG_LIST_SH_MASK_DCN35(_MASK)
 438 };
 439
 440 static struct dcn30_mpc_registers mpc_regs;
 441
 442 #define dcn_mpc_regs_init() \
 443         MPC_REG_LIST_DCN3_2_RI(0),\
 444         MPC_REG_LIST_DCN3_2_RI(1),\
 445         MPC_REG_LIST_DCN3_2_RI(2),\
 446         MPC_REG_LIST_DCN3_2_RI(3),\
 447         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 448         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 449         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 450         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 451         MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 452
 453 static const struct dcn30_mpc_shift mpc_shift = {
 454         MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 455 };
 456
 457 static const struct dcn30_mpc_mask mpc_mask = {
 458         MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 459 };
 460
 461 #define optc_regs_init(id)\
 462         OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
 463
 464 static struct dcn_optc_registers optc_regs[4];
 465
 466 static const struct dcn_optc_shift optc_shift = {
 467         OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 468 };
 469
 470 static const struct dcn_optc_mask optc_mask = {
 471         OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 472 };
 473
 474 #define hubp_regs_init(id)\
 475         HUBP_REG_LIST_DCN30_RI(id)
 476
 477 static struct dcn_hubp2_registers hubp_regs[4];
 478
 479
 480 static const struct dcn35_hubp2_shift hubp_shift = {
 481                 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
 482 };
 483
 484 static const struct dcn35_hubp2_mask hubp_mask = {
 485                 HUBP_MASK_SH_LIST_DCN35(_MASK)
 486 };
 487
 488 static struct dcn_hubbub_registers hubbub_reg;
 489
 490 #define hubbub_reg_init()\
 491                 HUBBUB_REG_LIST_DCN35(0)
 492
 493 static const struct dcn_hubbub_shift hubbub_shift = {
 494                 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
 495 };
 496
 497 static const struct dcn_hubbub_mask hubbub_mask = {
 498                 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
 499 };
 500
 501 static struct dccg_registers dccg_regs;
 502
 503 #define dccg_regs_init()\
 504         DCCG_REG_LIST_DCN35()
 505
 506 static const struct dccg_shift dccg_shift = {
 507                 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
 508 };
 509
 510 static const struct dccg_mask dccg_mask = {
 511                 DCCG_MASK_SH_LIST_DCN35(_MASK)
 512 };
 513
 514 static struct pg_cntl_registers pg_cntl_regs;
 515
 516 #define pg_cntl_dcn35_regs_init() \
 517         PG_CNTL_REG_LIST_DCN35()
 518
 519 static const struct pg_cntl_shift pg_cntl_shift = {
 520                 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
 521 };
 522
 523 static const struct pg_cntl_mask pg_cntl_mask = {
 524                 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
 525 };
 526
 527 #define SRII2(reg_name_pre, reg_name_post, id)\
 528         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 529                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 530                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 531
 532 static struct dce_hwseq_registers hwseq_reg;
 533
 534 #define hwseq_reg_init()\
 535         HWSEQ_DCN35_REG_LIST()
 536
 537 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
 538         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 539         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 540         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 541         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 542         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 543         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 544         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 545         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 546         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 547         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 548         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 549         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 550         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 551         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 552         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 553         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 554         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 555         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 556         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 557         HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 558         HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 559         HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 560         HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 561         HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 562         HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 563         HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 564         HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 565         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 566         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 567         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 568         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 569         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 570         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 571         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 572         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 573         HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 574         HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 575         HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 576         HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 577         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 578         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 579         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 580         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 581         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 582         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 583         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
 584         HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
 585         HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
 586         HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
 587         HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 588         HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 589         HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 590         HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 591         HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 592         HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
 593         HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
 594         HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
 595         HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
 596         HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
 597         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
 598         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
 599         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
 600         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
 601         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
 602         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
 603         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
 604         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
 605         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
 606         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
 607         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
 608         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 609         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 610         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 611         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 612         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
 613         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
 614         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
 615         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
 616         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
 617         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
 618         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
 619         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
 620         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
 621         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
 622         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
 623         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
 624         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
 625
 626 static const struct dce_hwseq_shift hwseq_shift = {
 627                 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
 628 };
 629
 630 static const struct dce_hwseq_mask hwseq_mask = {
 631                 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
 632 };
 633
 634 #define vmid_regs_init(id)\
 635                 DCN20_VMID_REG_LIST_RI(id)
 636
 637 static struct dcn_vmid_registers vmid_regs[16];
 638
 639 static const struct dcn20_vmid_shift vmid_shifts = {
 640                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 641 };
 642
 643 static const struct dcn20_vmid_mask vmid_masks = {
 644                 DCN20_VMID_MASK_SH_LIST(_MASK)
 645 };
 646
 647 static const struct resource_caps res_cap_dcn351 = {
 648         .num_timing_generator = 4,
 649         .num_opp = 4,
 650         .num_video_plane = 4,
 651         .num_audio = 5,
 652         .num_stream_encoder = 5,
 653         .num_dig_link_enc = 5,
 654         .num_hpo_dp_stream_encoder = 4,
 655         .num_hpo_dp_link_encoder = 2,
 656         .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
 657         .num_dwb = 1,
 658         .num_ddc = 5,
 659         .num_vmid = 16,
 660         .num_mpc_3dlut = 2,
 661         .num_dsc = 4,
 662 };
 663
 664 static const struct dc_plane_cap plane_cap = {
 665         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 666         .per_pixel_alpha = true,
 667
 668         .pixel_format_support = {
 669                         .argb8888 = true,
 670                         .nv12 = true,
 671                         .fp16 = true,
 672                         .p010 = true,
 673                         .ayuv = false,
 674         },
 675
 676         .max_upscale_factor = {
 677                         .argb8888 = 16000,
 678                         .nv12 = 16000,
 679                         .fp16 = 16000
 680         },
 681
 682         // 6:1 downscaling ratio: 1000/6 = 166.666
 683         .max_downscale_factor = {
 684                         .argb8888 = 250,
 685                         .nv12 = 167,
 686                         .fp16 = 167
 687         },
 688         64,
 689         64
 690 };
 691
 692 static const struct dc_debug_options debug_defaults_drv = {
 693         .disable_dmcu = true,
 694         .force_abm_enable = false,
 695         .timing_trace = false,
 696         .clock_trace = true,
 697         .disable_pplib_clock_request = false,
 698         .pipe_split_policy = MPC_SPLIT_AVOID,
 699         .force_single_disp_pipe_split = false,
 700         .disable_dcc = DCC_ENABLE,
 701         .disable_dpp_power_gate = true,
 702         .disable_hubp_power_gate = true,
 703         .disable_optc_power_gate = true, /*should the same as above two*/
 704         .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
 705         .disable_clock_gate = false,
 706         .disable_dsc_power_gate = true,
 707         .vsr_support = true,
 708         .performance_trace = false,
 709         .max_downscale_src_width = 4096,/*upto true 4k*/
 710         .disable_pplib_wm_range = false,
 711         .scl_reset_length10 = true,
 712         .sanity_checks = false,
 713         .underflow_assert_delay_us = 0xFFFFFFFF,
 714         .dwb_fi_phase = -1, // -1 = disable,
 715         .dmub_command_table = true,
 716         .pstate_enabled = true,
 717         .use_max_lb = true,
 718         .enable_mem_low_power = {
 719                 .bits = {
 720                         .vga = false,
 721                         .i2c = true,
 722                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 723                         .dscl = true,
 724                         .cm = true,
 725                         .mpc = true,
 726                         .optc = true,
 727                         .vpg = true,
 728                         .afmt = true,
 729                 }
 730         },
 731         .root_clock_optimization = {
 732                 .bits = {
 733                         .dpp = true,
 734                         .dsc = true,/*dscclk and dsc pg*/
 735                         .hdmistream = true,
 736                         .hdmichar = true,
 737                         .dpstream = true,
 738                         .symclk32_se = true,
 739                         .symclk32_le = true,
 740                         .symclk_fe = true,
 741                         .physymclk = true,
 742                         .dpiasymclk = true,
 743                 }
 744         },
 745         .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
 746         .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 747         .minimum_z8_residency_time = 2100,
 748         .using_dml2 = true,
 749         .support_eDP1_5 = true,
 750         .enable_hpo_pg_support = false,
 751         .enable_legacy_fast_update = true,
 752         .enable_single_display_2to1_odm_policy = true,
 753         .disable_idle_power_optimizations = false,
 754         .dmcub_emulation = false,
 755         .disable_boot_optimizations = false,
 756         .disable_unbounded_requesting = false,
 757         .disable_mem_low_power = false,
 758         //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
 759         .enable_double_buffered_dsc_pg_support = true,
 760         .enable_dp_dig_pixel_rate_div_policy = 1,
 761         .disable_z10 = true,
 762         .ignore_pg = true,
 763         .psp_disabled_wa = true,
 764         .ips2_eval_delay_us = 2000,
 765         .ips2_entry_delay_us = 800,
 766         .disable_dmub_reallow_idle = true,
 767         .static_screen_wait_frames = 2,
 768 };
 769
 770 static const struct dc_panel_config panel_config_defaults = {
 771         .psr = {
 772                 .disable_psr = false,
 773                 .disallow_psrsu = false,
 774                 .disallow_replay = false,
 775         },
 776         .ilr = {
 777                 .optimize_edp_link_rate = true,
 778         },
 779 };
 780
 781 static void dcn35_dpp_destroy(struct dpp **dpp)
 782 {
 783         kfree(TO_DCN20_DPP(*dpp));
 784         *dpp = NULL;
 785 }
 786
 787 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
 788 {
 789         struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 790         bool success = (dpp != NULL);
 791
 792         if (!success)
 793                 return NULL;
 794
 795 #undef REG_STRUCT
 796 #define REG_STRUCT dpp_regs
 797         dpp_regs_init(0),
 798         dpp_regs_init(1),
 799         dpp_regs_init(2),
 800         dpp_regs_init(3);
 801
 802         success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
 803                                   &tf_mask);
 804         if (success) {
 805                 dpp35_set_fgcg(
 806                         dpp,
 807                         ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
 808                 return &dpp->base;
 809         }
 810
 811         BREAK_TO_DEBUGGER();
 812         kfree(dpp);
 813         return NULL;
 814 }
 815
 816 static struct output_pixel_processor *dcn35_opp_create(
 817         struct dc_context *ctx, uint32_t inst)
 818 {
 819         struct dcn20_opp *opp =
 820                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 821
 822         if (!opp) {
 823                 BREAK_TO_DEBUGGER();
 824                 return NULL;
 825         }
 826
 827 #undef REG_STRUCT
 828 #define REG_STRUCT opp_regs
 829         opp_regs_init(0),
 830         opp_regs_init(1),
 831         opp_regs_init(2),
 832         opp_regs_init(3);
 833
 834         dcn35_opp_construct(opp, ctx, inst,
 835                         &opp_regs[inst], &opp_shift, &opp_mask);
 836
 837         dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
 838
 839         return &opp->base;
 840 }
 841
 842 static struct dce_aux *dcn31_aux_engine_create(
 843         struct dc_context *ctx,
 844         uint32_t inst)
 845 {
 846         struct aux_engine_dce110 *aux_engine =
 847                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 848
 849         if (!aux_engine)
 850                 return NULL;
 851
 852 #undef REG_STRUCT
 853 #define REG_STRUCT aux_engine_regs
 854         aux_engine_regs_init(0),
 855         aux_engine_regs_init(1),
 856         aux_engine_regs_init(2),
 857         aux_engine_regs_init(3),
 858         aux_engine_regs_init(4);
 859
 860         dce110_aux_engine_construct(aux_engine, ctx, inst,
 861                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 862                                     &aux_engine_regs[inst],
 863                                         &aux_mask,
 864                                         &aux_shift,
 865                                         ctx->dc->caps.extended_aux_timeout_support);
 866
 867         return &aux_engine->base;
 868 }
 869
 870 #define i2c_inst_regs_init(id)\
 871         I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 872
 873 static struct dce_i2c_registers i2c_hw_regs[5];
 874
 875 static const struct dce_i2c_shift i2c_shifts = {
 876                 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 877 };
 878
 879 static const struct dce_i2c_mask i2c_masks = {
 880                 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
 881 };
 882
 883 /* ========================================================== */
 884
 885 /*
 886  * DPIA index | Preferred Encoder     |    Host Router
 887  *   0        |      C                |       0
 888  *   1        |      First Available  |       0
 889  *   2        |      D                |       1
 890  *   3        |      First Available  |       1
 891  */
 892 /* ========================================================== */
 893 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
 894                 ENGINE_ID_DIGC,
 895                 ENGINE_ID_DIGC,
 896                 ENGINE_ID_DIGD,
 897                 ENGINE_ID_DIGD
 898 };
 899
 900 static enum engine_id dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)
 901 {
 902         return dpia_to_preferred_enc_id_table[dpia_index];
 903 }
 904
 905 static struct dce_i2c_hw *dcn31_i2c_hw_create(
 906         struct dc_context *ctx,
 907         uint32_t inst)
 908 {
 909         struct dce_i2c_hw *dce_i2c_hw =
 910                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 911
 912         if (!dce_i2c_hw)
 913                 return NULL;
 914
 915 #undef REG_STRUCT
 916 #define REG_STRUCT i2c_hw_regs
 917         i2c_inst_regs_init(1),
 918         i2c_inst_regs_init(2),
 919         i2c_inst_regs_init(3),
 920         i2c_inst_regs_init(4),
 921         i2c_inst_regs_init(5);
 922
 923         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 924                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 925
 926         return dce_i2c_hw;
 927 }
 928 static struct mpc *dcn35_mpc_create(
 929                 struct dc_context *ctx,
 930                 int num_mpcc,
 931                 int num_rmu)
 932 {
 933         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 934
 935         if (!mpc30)
 936                 return NULL;
 937
 938 #undef REG_STRUCT
 939 #define REG_STRUCT mpc_regs
 940         dcn_mpc_regs_init();
 941
 942         dcn32_mpc_construct(mpc30, ctx,
 943                         &mpc_regs,
 944                         &mpc_shift,
 945                         &mpc_mask,
 946                         num_mpcc,
 947                         num_rmu);
 948
 949         return &mpc30->base;
 950 }
 951
 952 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
 953 {
 954         int i;
 955
 956         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 957                                           GFP_KERNEL);
 958
 959         if (!hubbub3)
 960                 return NULL;
 961
 962 #undef REG_STRUCT
 963 #define REG_STRUCT hubbub_reg
 964         hubbub_reg_init();
 965
 966 #undef REG_STRUCT
 967 #define REG_STRUCT vmid_regs
 968         vmid_regs_init(0),
 969         vmid_regs_init(1),
 970         vmid_regs_init(2),
 971         vmid_regs_init(3),
 972         vmid_regs_init(4),
 973         vmid_regs_init(5),
 974         vmid_regs_init(6),
 975         vmid_regs_init(7),
 976         vmid_regs_init(8),
 977         vmid_regs_init(9),
 978         vmid_regs_init(10),
 979         vmid_regs_init(11),
 980         vmid_regs_init(12),
 981         vmid_regs_init(13),
 982         vmid_regs_init(14),
 983         vmid_regs_init(15);
 984
 985         hubbub35_construct(hubbub3, ctx,
 986                         &hubbub_reg,
 987                         &hubbub_shift,
 988                         &hubbub_mask,
 989                         384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
 990                         8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
 991                         1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
 992
 993
 994         for (i = 0; i < res_cap_dcn351.num_vmid; i++) {
 995                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 996
 997                 vmid->ctx = ctx;
 998
 999                 vmid->regs = &vmid_regs[i];
1000                 vmid->shifts = &vmid_shifts;
1001                 vmid->masks = &vmid_masks;
1002         }
1003
1004         return &hubbub3->base;
1005 }
1006
1007 static struct timing_generator *dcn35_timing_generator_create(
1008                 struct dc_context *ctx,
1009                 uint32_t instance)
1010 {
1011         struct optc *tgn10 =
1012                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1013
1014         if (!tgn10)
1015                 return NULL;
1016
1017 #undef REG_STRUCT
1018 #define REG_STRUCT optc_regs
1019         optc_regs_init(0),
1020         optc_regs_init(1),
1021         optc_regs_init(2),
1022         optc_regs_init(3);
1023
1024         tgn10->base.inst = instance;
1025         tgn10->base.ctx = ctx;
1026
1027         tgn10->tg_regs = &optc_regs[instance];
1028         tgn10->tg_shift = &optc_shift;
1029         tgn10->tg_mask = &optc_mask;
1030
1031         dcn35_timing_generator_init(tgn10);
1032
1033         return &tgn10->base;
1034 }
1035
1036 static const struct encoder_feature_support link_enc_feature = {
1037                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1038                 .max_hdmi_pixel_clock = 600000,
1039                 .hdmi_ycbcr420_supported = true,
1040                 .dp_ycbcr420_supported = true,
1041                 .fec_supported = true,
1042                 .flags.bits.IS_HBR2_CAPABLE = true,
1043                 .flags.bits.IS_HBR3_CAPABLE = true,
1044                 .flags.bits.IS_TPS3_CAPABLE = true,
1045                 .flags.bits.IS_TPS4_CAPABLE = true
1046 };
1047
1048 static struct link_encoder *dcn35_link_encoder_create(
1049         struct dc_context *ctx,
1050         const struct encoder_init_data *enc_init_data)
1051 {
1052         struct dcn20_link_encoder *enc20 =
1053                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1054
1055         if (!enc20)
1056                 return NULL;
1057
1058 #undef REG_STRUCT
1059 #define REG_STRUCT link_enc_aux_regs
1060         aux_regs_init(0),
1061         aux_regs_init(1),
1062         aux_regs_init(2),
1063         aux_regs_init(3),
1064         aux_regs_init(4);
1065
1066 #undef REG_STRUCT
1067 #define REG_STRUCT link_enc_hpd_regs
1068         hpd_regs_init(0),
1069         hpd_regs_init(1),
1070         hpd_regs_init(2),
1071         hpd_regs_init(3),
1072         hpd_regs_init(4);
1073
1074 #undef REG_STRUCT
1075 #define REG_STRUCT link_enc_regs
1076         link_regs_init(0, A),
1077         link_regs_init(1, B),
1078         link_regs_init(2, C),
1079         link_regs_init(3, D),
1080         link_regs_init(4, E);
1081
1082         dcn35_link_encoder_construct(enc20,
1083                         enc_init_data,
1084                         &link_enc_feature,
1085                         &link_enc_regs[enc_init_data->transmitter],
1086                         &link_enc_aux_regs[enc_init_data->channel - 1],
1087                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1088                         &le_shift,
1089                         &le_mask);
1090
1091         return &enc20->enc10.base;
1092 }
1093
1094 /* Create a minimal link encoder object not associated with a particular
1095  * physical connector.
1096  * resource_funcs.link_enc_create_minimal
1097  */
1098 static struct link_encoder *dcn31_link_enc_create_minimal(
1099                 struct dc_context *ctx, enum engine_id eng_id)
1100 {
1101         struct dcn20_link_encoder *enc20;
1102
1103         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1104                 return NULL;
1105
1106         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1107         if (!enc20)
1108                 return NULL;
1109
1110         dcn31_link_encoder_construct_minimal(
1111                         enc20,
1112                         ctx,
1113                         &link_enc_feature,
1114                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1115                         eng_id);
1116
1117         return &enc20->enc10.base;
1118 }
1119
1120 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1121 {
1122         struct dcn31_panel_cntl *panel_cntl =
1123                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1124
1125         if (!panel_cntl)
1126                 return NULL;
1127
1128         dcn31_panel_cntl_construct(panel_cntl, init_data);
1129
1130         return &panel_cntl->base;
1131 }
1132
1133 static void read_dce_straps(
1134         struct dc_context *ctx,
1135         struct resource_straps *straps)
1136 {
1137         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1138                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1139
1140 }
1141
1142 static struct audio *dcn31_create_audio(
1143                 struct dc_context *ctx, unsigned int inst)
1144 {
1145
1146 #undef REG_STRUCT
1147 #define REG_STRUCT audio_regs
1148         audio_regs_init(0),
1149         audio_regs_init(1),
1150         audio_regs_init(2),
1151         audio_regs_init(3),
1152         audio_regs_init(4);
1153         audio_regs_init(5);
1154         audio_regs_init(6);
1155
1156         return dce_audio_create(ctx, inst,
1157                         &audio_regs[inst], &audio_shift, &audio_mask);
1158 }
1159
1160 static struct vpg *dcn31_vpg_create(
1161         struct dc_context *ctx,
1162         uint32_t inst)
1163 {
1164         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1165
1166         if (!vpg31)
1167                 return NULL;
1168
1169 #undef REG_STRUCT
1170 #define REG_STRUCT vpg_regs
1171         vpg_regs_init(0),
1172         vpg_regs_init(1),
1173         vpg_regs_init(2),
1174         vpg_regs_init(3),
1175         vpg_regs_init(4),
1176         vpg_regs_init(5),
1177         vpg_regs_init(6),
1178         vpg_regs_init(7),
1179         vpg_regs_init(8),
1180         vpg_regs_init(9);
1181
1182         vpg31_construct(vpg31, ctx, inst,
1183                         &vpg_regs[inst],
1184                         &vpg_shift,
1185                         &vpg_mask);
1186
1187         return &vpg31->base;
1188 }
1189
1190 static struct afmt *dcn31_afmt_create(
1191         struct dc_context *ctx,
1192         uint32_t inst)
1193 {
1194         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1195
1196         if (!afmt31)
1197                 return NULL;
1198
1199 #undef REG_STRUCT
1200 #define REG_STRUCT afmt_regs
1201         afmt_regs_init(0),
1202         afmt_regs_init(1),
1203         afmt_regs_init(2),
1204         afmt_regs_init(3),
1205         afmt_regs_init(4),
1206         afmt_regs_init(5);
1207
1208         afmt31_construct(afmt31, ctx, inst,
1209                         &afmt_regs[inst],
1210                         &afmt_shift,
1211                         &afmt_mask);
1212
1213         // Light sleep by default, no need to power down here
1214
1215         return &afmt31->base;
1216 }
1217
1218 static struct apg *dcn31_apg_create(
1219         struct dc_context *ctx,
1220         uint32_t inst)
1221 {
1222         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1223
1224         if (!apg31)
1225                 return NULL;
1226
1227 #undef REG_STRUCT
1228 #define REG_STRUCT apg_regs
1229         apg_regs_init(0),
1230         apg_regs_init(1),
1231         apg_regs_init(2),
1232         apg_regs_init(3);
1233
1234         apg31_construct(apg31, ctx, inst,
1235                         &apg_regs[inst],
1236                         &apg_shift,
1237                         &apg_mask);
1238
1239         return &apg31->base;
1240 }
1241
1242 static struct stream_encoder *dcn35_stream_encoder_create(
1243         enum engine_id eng_id,
1244         struct dc_context *ctx)
1245 {
1246         struct dcn10_stream_encoder *enc1;
1247         struct vpg *vpg;
1248         struct afmt *afmt;
1249         int vpg_inst;
1250         int afmt_inst;
1251
1252         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1253         if (eng_id <= ENGINE_ID_DIGF) {
1254                 vpg_inst = eng_id;
1255                 afmt_inst = eng_id;
1256         } else
1257                 return NULL;
1258
1259         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1260         vpg = dcn31_vpg_create(ctx, vpg_inst);
1261         afmt = dcn31_afmt_create(ctx, afmt_inst);
1262
1263         if (!enc1 || !vpg || !afmt) {
1264                 kfree(enc1);
1265                 kfree(vpg);
1266                 kfree(afmt);
1267                 return NULL;
1268         }
1269
1270 #undef REG_STRUCT
1271 #define REG_STRUCT stream_enc_regs
1272         stream_enc_regs_init(0),
1273         stream_enc_regs_init(1),
1274         stream_enc_regs_init(2),
1275         stream_enc_regs_init(3),
1276         stream_enc_regs_init(4);
1277
1278         dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1279                                         eng_id, vpg, afmt,
1280                                         &stream_enc_regs[eng_id],
1281                                         &se_shift, &se_mask);
1282
1283         return &enc1->base;
1284 }
1285
1286 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1287         enum engine_id eng_id,
1288         struct dc_context *ctx)
1289 {
1290         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1291         struct vpg *vpg;
1292         struct apg *apg;
1293         uint32_t hpo_dp_inst;
1294         uint32_t vpg_inst;
1295         uint32_t apg_inst;
1296
1297         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1298         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1299
1300         /* Mapping of VPG register blocks to HPO DP block instance:
1301          * VPG[6] -> HPO_DP[0]
1302          * VPG[7] -> HPO_DP[1]
1303          * VPG[8] -> HPO_DP[2]
1304          * VPG[9] -> HPO_DP[3]
1305          */
1306         vpg_inst = hpo_dp_inst + 6;
1307
1308         /* Mapping of APG register blocks to HPO DP block instance:
1309          * APG[0] -> HPO_DP[0]
1310          * APG[1] -> HPO_DP[1]
1311          * APG[2] -> HPO_DP[2]
1312          * APG[3] -> HPO_DP[3]
1313          */
1314         apg_inst = hpo_dp_inst;
1315
1316         /* allocate HPO stream encoder and create VPG sub-block */
1317         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1318         vpg = dcn31_vpg_create(ctx, vpg_inst);
1319         apg = dcn31_apg_create(ctx, apg_inst);
1320
1321         if (!hpo_dp_enc31 || !vpg || !apg) {
1322                 kfree(hpo_dp_enc31);
1323                 kfree(vpg);
1324                 kfree(apg);
1325                 return NULL;
1326         }
1327
1328 #undef REG_STRUCT
1329 #define REG_STRUCT hpo_dp_stream_enc_regs
1330         hpo_dp_stream_encoder_reg_init(0),
1331         hpo_dp_stream_encoder_reg_init(1),
1332         hpo_dp_stream_encoder_reg_init(2),
1333         hpo_dp_stream_encoder_reg_init(3);
1334
1335         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1336                                         hpo_dp_inst, eng_id, vpg, apg,
1337                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1338                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1339
1340         return &hpo_dp_enc31->base;
1341 }
1342
1343 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1344         uint8_t inst,
1345         struct dc_context *ctx)
1346 {
1347         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1348
1349         /* allocate HPO link encoder */
1350         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1351
1352 #undef REG_STRUCT
1353 #define REG_STRUCT hpo_dp_link_enc_regs
1354         hpo_dp_link_encoder_reg_init(0),
1355         hpo_dp_link_encoder_reg_init(1);
1356
1357         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1358                                         &hpo_dp_link_enc_regs[inst],
1359                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1360
1361         return &hpo_dp_enc31->base;
1362 }
1363
1364 static struct dce_hwseq *dcn351_hwseq_create(
1365         struct dc_context *ctx)
1366 {
1367         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1368
1369 #undef REG_STRUCT
1370 #define REG_STRUCT hwseq_reg
1371         hwseq_reg_init();
1372
1373         if (hws) {
1374                 hws->ctx = ctx;
1375                 hws->regs = &hwseq_reg;
1376                 hws->shifts = &hwseq_shift;
1377                 hws->masks = &hwseq_mask;
1378         }
1379         return hws;
1380 }
1381 static const struct resource_create_funcs res_create_funcs = {
1382         .read_dce_straps = read_dce_straps,
1383         .create_audio = dcn31_create_audio,
1384         .create_stream_encoder = dcn35_stream_encoder_create,
1385         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1386         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1387         .create_hwseq = dcn351_hwseq_create,
1388 };
1389
1390 static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
1391 {
1392         unsigned int i;
1393
1394         for (i = 0; i < pool->base.stream_enc_count; i++) {
1395                 if (pool->base.stream_enc[i] != NULL) {
1396                         if (pool->base.stream_enc[i]->vpg != NULL) {
1397                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1398                                 pool->base.stream_enc[i]->vpg = NULL;
1399                         }
1400                         if (pool->base.stream_enc[i]->afmt != NULL) {
1401                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1402                                 pool->base.stream_enc[i]->afmt = NULL;
1403                         }
1404                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1405                         pool->base.stream_enc[i] = NULL;
1406                 }
1407         }
1408
1409         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1410                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1411                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1412                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1413                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1414                         }
1415                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1416                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1417                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1418                         }
1419                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1420                         pool->base.hpo_dp_stream_enc[i] = NULL;
1421                 }
1422         }
1423
1424         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1425                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1426                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1427                         pool->base.hpo_dp_link_enc[i] = NULL;
1428                 }
1429         }
1430
1431         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1432                 if (pool->base.dscs[i] != NULL)
1433                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1434         }
1435
1436         if (pool->base.mpc != NULL) {
1437                 kfree(TO_DCN20_MPC(pool->base.mpc));
1438                 pool->base.mpc = NULL;
1439         }
1440         if (pool->base.hubbub != NULL) {
1441                 kfree(pool->base.hubbub);
1442                 pool->base.hubbub = NULL;
1443         }
1444         for (i = 0; i < pool->base.pipe_count; i++) {
1445                 if (pool->base.dpps[i] != NULL)
1446                         dcn35_dpp_destroy(&pool->base.dpps[i]);
1447
1448                 if (pool->base.ipps[i] != NULL)
1449                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1450
1451                 if (pool->base.hubps[i] != NULL) {
1452                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1453                         pool->base.hubps[i] = NULL;
1454                 }
1455
1456                 if (pool->base.irqs != NULL) {
1457                         dal_irq_service_destroy(&pool->base.irqs);
1458                 }
1459         }
1460
1461         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1462                 if (pool->base.engines[i] != NULL)
1463                         dce110_engine_destroy(&pool->base.engines[i]);
1464                 if (pool->base.hw_i2cs[i] != NULL) {
1465                         kfree(pool->base.hw_i2cs[i]);
1466                         pool->base.hw_i2cs[i] = NULL;
1467                 }
1468                 if (pool->base.sw_i2cs[i] != NULL) {
1469                         kfree(pool->base.sw_i2cs[i]);
1470                         pool->base.sw_i2cs[i] = NULL;
1471                 }
1472         }
1473
1474         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1475                 if (pool->base.opps[i] != NULL)
1476                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1477         }
1478
1479         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1480                 if (pool->base.timing_generators[i] != NULL)    {
1481                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1482                         pool->base.timing_generators[i] = NULL;
1483                 }
1484         }
1485
1486         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1487                 if (pool->base.dwbc[i] != NULL) {
1488                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1489                         pool->base.dwbc[i] = NULL;
1490                 }
1491                 if (pool->base.mcif_wb[i] != NULL) {
1492                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1493                         pool->base.mcif_wb[i] = NULL;
1494                 }
1495         }
1496
1497         for (i = 0; i < pool->base.audio_count; i++) {
1498                 if (pool->base.audios[i])
1499                         dce_aud_destroy(&pool->base.audios[i]);
1500         }
1501
1502         for (i = 0; i < pool->base.clk_src_count; i++) {
1503                 if (pool->base.clock_sources[i] != NULL) {
1504                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1505                         pool->base.clock_sources[i] = NULL;
1506                 }
1507         }
1508
1509         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1510                 if (pool->base.mpc_lut[i] != NULL) {
1511                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1512                         pool->base.mpc_lut[i] = NULL;
1513                 }
1514                 if (pool->base.mpc_shaper[i] != NULL) {
1515                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1516                         pool->base.mpc_shaper[i] = NULL;
1517                 }
1518         }
1519
1520         if (pool->base.dp_clock_source != NULL) {
1521                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1522                 pool->base.dp_clock_source = NULL;
1523         }
1524
1525         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1526                 if (pool->base.multiple_abms[i] != NULL)
1527                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1528         }
1529
1530         if (pool->base.psr != NULL)
1531                 dmub_psr_destroy(&pool->base.psr);
1532
1533         if (pool->base.replay != NULL)
1534                 dmub_replay_destroy(&pool->base.replay);
1535
1536         if (pool->base.pg_cntl != NULL)
1537                 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1538
1539         if (pool->base.dccg != NULL)
1540                 dcn_dccg_destroy(&pool->base.dccg);
1541 }
1542
1543 static struct hubp *dcn35_hubp_create(
1544         struct dc_context *ctx,
1545         uint32_t inst)
1546 {
1547         struct dcn20_hubp *hubp2 =
1548                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1549
1550         if (!hubp2)
1551                 return NULL;
1552
1553 #undef REG_STRUCT
1554 #define REG_STRUCT hubp_regs
1555         hubp_regs_init(0),
1556         hubp_regs_init(1),
1557         hubp_regs_init(2),
1558         hubp_regs_init(3);
1559
1560         if (hubp35_construct(hubp2, ctx, inst,
1561                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1562                 return &hubp2->base;
1563
1564         BREAK_TO_DEBUGGER();
1565         kfree(hubp2);
1566         return NULL;
1567 }
1568
1569 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1570 {
1571         dcn35_dwbc_set_fgcg(
1572                 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1573 }
1574
1575 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1576 {
1577         int i;
1578         uint32_t pipe_count = pool->res_cap->num_dwb;
1579
1580         for (i = 0; i < pipe_count; i++) {
1581                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1582                                                     GFP_KERNEL);
1583
1584                 if (!dwbc30) {
1585                         dm_error("DC: failed to create dwbc30!\n");
1586                         return false;
1587                 }
1588
1589 #undef REG_STRUCT
1590 #define REG_STRUCT dwbc35_regs
1591                 dwbc_regs_dcn3_init(0);
1592
1593                 dcn35_dwbc_construct(dwbc30, ctx,
1594                                 &dwbc35_regs[i],
1595                                 &dwbc35_shift,
1596                                 &dwbc35_mask,
1597                                 i);
1598
1599                 pool->dwbc[i] = &dwbc30->base;
1600
1601                 dcn35_dwbc_init(dwbc30, ctx);
1602         }
1603         return true;
1604 }
1605
1606 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1607                                 struct dc_context *ctx)
1608 {
1609         dcn35_mmhubbub_set_fgcg(
1610                 mcif_wb30,
1611                 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1612 }
1613
1614 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1615 {
1616         int i;
1617         uint32_t pipe_count = pool->res_cap->num_dwb;
1618
1619         for (i = 0; i < pipe_count; i++) {
1620                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1621                                                     GFP_KERNEL);
1622
1623                 if (!mcif_wb30) {
1624                         dm_error("DC: failed to create mcif_wb30!\n");
1625                         return false;
1626                 }
1627
1628 #undef REG_STRUCT
1629 #define REG_STRUCT mcif_wb35_regs
1630                 mcif_wb_regs_dcn3_init(0);
1631
1632                 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1633                                 &mcif_wb35_regs[i],
1634                                 &mcif_wb35_shift,
1635                                 &mcif_wb35_mask,
1636                                 i);
1637
1638                 dcn35_mmhubbub_init(mcif_wb30, ctx);
1639
1640                 pool->mcif_wb[i] = &mcif_wb30->base;
1641         }
1642         return true;
1643 }
1644
1645 static struct display_stream_compressor *dcn35_dsc_create(
1646         struct dc_context *ctx, uint32_t inst)
1647 {
1648         struct dcn20_dsc *dsc =
1649                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1650
1651         if (!dsc) {
1652                 BREAK_TO_DEBUGGER();
1653                 return NULL;
1654         }
1655
1656 #undef REG_STRUCT
1657 #define REG_STRUCT dsc_regs
1658         dsc_regsDCN35_init(0),
1659         dsc_regsDCN35_init(1),
1660         dsc_regsDCN35_init(2),
1661         dsc_regsDCN35_init(3);
1662
1663         dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1664         dsc35_set_fgcg(dsc,
1665                        ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1666         return &dsc->base;
1667 }
1668
1669 static void dcn351_destroy_resource_pool(struct resource_pool **pool)
1670 {
1671         struct dcn351_resource_pool *dcn351_pool = TO_DCN351_RES_POOL(*pool);
1672
1673         dcn351_resource_destruct(dcn351_pool);
1674         kfree(dcn351_pool);
1675         *pool = NULL;
1676 }
1677
1678 static struct clock_source *dcn35_clock_source_create(
1679                 struct dc_context *ctx,
1680                 struct dc_bios *bios,
1681                 enum clock_source_id id,
1682                 const struct dce110_clk_src_regs *regs,
1683                 bool dp_clk_src)
1684 {
1685         struct dce110_clk_src *clk_src =
1686                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1687
1688         if (!clk_src)
1689                 return NULL;
1690
1691         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1692                         regs, &cs_shift, &cs_mask)) {
1693                 clk_src->base.dp_clk_src = dp_clk_src;
1694                 return &clk_src->base;
1695         }
1696
1697         BREAK_TO_DEBUGGER();
1698         return NULL;
1699 }
1700
1701 static struct dc_cap_funcs cap_funcs = {
1702         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1703 };
1704
1705 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1706 {
1707         *panel_config = panel_config_defaults;
1708 }
1709
1710
1711 static bool dcn351_validate_bandwidth(struct dc *dc,
1712                 struct dc_state *context,
1713                 bool fast_validate)
1714 {
1715         bool out = false;
1716
1717         out = dml2_validate(dc, context, fast_validate);
1718
1719         if (fast_validate)
1720                 return out;
1721
1722         DC_FP_START();
1723         dcn351_decide_zstate_support(dc, context);
1724         DC_FP_END();
1725
1726         return out;
1727 }
1728
1729
1730 static struct resource_funcs dcn351_res_pool_funcs = {
1731         .destroy = dcn351_destroy_resource_pool,
1732         .link_enc_create = dcn35_link_encoder_create,
1733         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1734         .link_encs_assign = link_enc_cfg_link_encs_assign,
1735         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1736         .panel_cntl_create = dcn31_panel_cntl_create,
1737         .validate_bandwidth = dcn351_validate_bandwidth,
1738         .calculate_wm_and_dlg = NULL,
1739         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1740         .populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,
1741         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1742         .release_pipe = dcn20_release_pipe,
1743         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1744         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1745         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1746         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1747         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1748         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1749         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1750         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1751         .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,
1752         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1753         .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1754         .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
1755 };
1756
1757 static bool dcn351_resource_construct(
1758         uint8_t num_virtual_links,
1759         struct dc *dc,
1760         struct dcn351_resource_pool *pool)
1761 {
1762         int i;
1763         struct dc_context *ctx = dc->ctx;
1764         struct irq_service_init_data init_data;
1765
1766 #undef REG_STRUCT
1767 #define REG_STRUCT bios_regs
1768         bios_regs_init();
1769
1770 #undef REG_STRUCT
1771 #define REG_STRUCT clk_src_regs
1772         clk_src_regs_init(0, A),
1773         clk_src_regs_init(1, B),
1774         clk_src_regs_init(2, C),
1775         clk_src_regs_init(3, D),
1776         clk_src_regs_init(4, E);
1777
1778 #undef REG_STRUCT
1779 #define REG_STRUCT abm_regs
1780         abm_regs_init(0),
1781         abm_regs_init(1),
1782         abm_regs_init(2),
1783         abm_regs_init(3);
1784
1785 #undef REG_STRUCT
1786 #define REG_STRUCT dccg_regs
1787         dccg_regs_init();
1788
1789         ctx->dc_bios->regs = &bios_regs;
1790
1791         pool->base.res_cap = &res_cap_dcn351;
1792
1793         pool->base.funcs = &dcn351_res_pool_funcs;
1794
1795         /*************************************************
1796          *  Resource + asic cap harcoding                *
1797          *************************************************/
1798         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1799         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1800         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1801         dc->caps.max_downscale_ratio = 600;
1802         dc->caps.i2c_speed_in_khz = 100;
1803         dc->caps.i2c_speed_in_khz_hdcp = 100;
1804         dc->caps.max_cursor_size = 256;
1805         dc->caps.min_horizontal_blanking_period = 80;
1806         dc->caps.dmdata_alloc_size = 2048;
1807         dc->caps.max_slave_planes = 2;
1808         dc->caps.max_slave_yuv_planes = 2;
1809         dc->caps.max_slave_rgb_planes = 2;
1810         dc->caps.post_blend_color_processing = true;
1811         dc->caps.force_dp_tps4_for_cp2520 = true;
1812         if (dc->config.forceHBR2CP2520)
1813                 dc->caps.force_dp_tps4_for_cp2520 = false;
1814         dc->caps.dp_hpo = true;
1815         dc->caps.dp_hdmi21_pcon_support = true;
1816
1817         dc->caps.edp_dsc_support = true;
1818         dc->caps.extended_aux_timeout_support = true;
1819         dc->caps.dmcub_support = true;
1820         dc->caps.is_apu = true;
1821         dc->caps.seamless_odm = true;
1822
1823         dc->caps.zstate_support = true;
1824         dc->caps.ips_support = true;
1825         dc->caps.max_v_total = (1 << 15) - 1;
1826
1827         /* Color pipeline capabilities */
1828         dc->caps.color.dpp.dcn_arch = 1;
1829         dc->caps.color.dpp.input_lut_shared = 0;
1830         dc->caps.color.dpp.icsc = 1;
1831         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1832         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1833         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1834         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1835         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1836         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1837         dc->caps.color.dpp.post_csc = 1;
1838         dc->caps.color.dpp.gamma_corr = 1;
1839         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1840
1841         dc->caps.color.dpp.hw_3d_lut = 1;
1842         dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1
1843         // no OGAM ROM on DCN301
1844         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1845         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1846         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1847         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1848         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1849         dc->caps.color.dpp.ocsc = 0;
1850
1851         dc->caps.color.mpc.gamut_remap = 1;
1852         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1853         dc->caps.color.mpc.ogam_ram = 1;
1854         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1855         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1856         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1857         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1858         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1859         dc->caps.color.mpc.ocsc = 1;
1860
1861         /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1862          * to provide some margin.
1863          * It's expected for furture ASIC to have equal or higher value, in order to
1864          * have determinstic power improvement from generate to genration.
1865          * (i.e., we should not expect new ASIC generation with lower vmin rate)
1866          */
1867         dc->caps.max_disp_clock_khz_at_vmin = 650000;
1868
1869         /* Use pipe context based otg sync logic */
1870         dc->config.use_pipe_ctx_sync_logic = true;
1871
1872         /* read VBIOS LTTPR caps */
1873         {
1874                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1875                         enum bp_result bp_query_result;
1876                         uint8_t is_vbios_lttpr_enable = 0;
1877
1878                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1879                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1880                 }
1881
1882                 /* interop bit is implicit */
1883                 {
1884                         dc->caps.vbios_lttpr_aware = true;
1885                 }
1886         }
1887
1888         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1889                 dc->debug = debug_defaults_drv;
1890
1891         // Init the vm_helper
1892         if (dc->vm_helper)
1893                 vm_helper_init(dc->vm_helper, 16);
1894
1895         /*************************************************
1896          *  Create resources                             *
1897          *************************************************/
1898
1899         /* Clock Sources for Pixel Clock*/
1900         pool->base.clock_sources[DCN351_CLK_SRC_PLL0] =
1901                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1902                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1903                                 &clk_src_regs[0], false);
1904         pool->base.clock_sources[DCN351_CLK_SRC_PLL1] =
1905                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1906                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1907                                 &clk_src_regs[1], false);
1908         pool->base.clock_sources[DCN351_CLK_SRC_PLL2] =
1909                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1910                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1911                                 &clk_src_regs[2], false);
1912         pool->base.clock_sources[DCN351_CLK_SRC_PLL3] =
1913                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1914                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1915                                 &clk_src_regs[3], false);
1916         pool->base.clock_sources[DCN351_CLK_SRC_PLL4] =
1917                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1918                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1919                                 &clk_src_regs[4], false);
1920
1921         pool->base.clk_src_count = DCN351_CLK_SRC_TOTAL;
1922
1923         /* todo: not reuse phy_pll registers */
1924         pool->base.dp_clock_source =
1925                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1926                                 CLOCK_SOURCE_ID_DP_DTO,
1927                                 &clk_src_regs[0], true);
1928
1929         for (i = 0; i < pool->base.clk_src_count; i++) {
1930                 if (pool->base.clock_sources[i] == NULL) {
1931                         dm_error("DC: failed to create clock sources!\n");
1932                         BREAK_TO_DEBUGGER();
1933                         goto create_fail;
1934                 }
1935         }
1936         /*temp till dml2 fully work without dml1*/
1937         dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1938
1939         /* TODO: DCCG */
1940         pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1941         if (pool->base.dccg == NULL) {
1942                 dm_error("DC: failed to create dccg!\n");
1943                 BREAK_TO_DEBUGGER();
1944                 goto create_fail;
1945         }
1946
1947 #undef REG_STRUCT
1948 #define REG_STRUCT pg_cntl_regs
1949         pg_cntl_dcn35_regs_init();
1950
1951         pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1952         if (pool->base.pg_cntl == NULL) {
1953                 dm_error("DC: failed to create power gate control!\n");
1954                 BREAK_TO_DEBUGGER();
1955                 goto create_fail;
1956         }
1957
1958         /* TODO: IRQ */
1959         init_data.ctx = dc->ctx;
1960         pool->base.irqs = dal_irq_service_dcn351_create(&init_data);
1961         if (!pool->base.irqs)
1962                 goto create_fail;
1963
1964         /* HUBBUB */
1965         pool->base.hubbub = dcn35_hubbub_create(ctx);
1966         if (pool->base.hubbub == NULL) {
1967                 BREAK_TO_DEBUGGER();
1968                 dm_error("DC: failed to create hubbub!\n");
1969                 goto create_fail;
1970         }
1971
1972         /* HUBPs, DPPs, OPPs and TGs */
1973         for (i = 0; i < pool->base.pipe_count; i++) {
1974                 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
1975                 if (pool->base.hubps[i] == NULL) {
1976                         BREAK_TO_DEBUGGER();
1977                         dm_error(
1978                                 "DC: failed to create hubps!\n");
1979                         goto create_fail;
1980                 }
1981
1982                 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
1983                 if (pool->base.dpps[i] == NULL) {
1984                         BREAK_TO_DEBUGGER();
1985                         dm_error(
1986                                 "DC: failed to create dpps!\n");
1987                         goto create_fail;
1988                 }
1989         }
1990
1991         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1992                 pool->base.opps[i] = dcn35_opp_create(ctx, i);
1993                 if (pool->base.opps[i] == NULL) {
1994                         BREAK_TO_DEBUGGER();
1995                         dm_error(
1996                                 "DC: failed to create output pixel processor!\n");
1997                         goto create_fail;
1998                 }
1999         }
2000
2001         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2002                 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2003                                 ctx, i);
2004                 if (pool->base.timing_generators[i] == NULL) {
2005                         BREAK_TO_DEBUGGER();
2006                         dm_error("DC: failed to create tg!\n");
2007                         goto create_fail;
2008                 }
2009         }
2010         pool->base.timing_generator_count = i;
2011
2012         /* PSR */
2013         pool->base.psr = dmub_psr_create(ctx);
2014         if (pool->base.psr == NULL) {
2015                 dm_error("DC: failed to create psr obj!\n");
2016                 BREAK_TO_DEBUGGER();
2017                 goto create_fail;
2018         }
2019
2020         /* Replay */
2021         pool->base.replay = dmub_replay_create(ctx);
2022         if (pool->base.replay == NULL) {
2023                 dm_error("DC: failed to create replay obj!\n");
2024                 BREAK_TO_DEBUGGER();
2025                 goto create_fail;
2026         }
2027
2028         /* ABM */
2029         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2030                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2031                                 &abm_regs[i],
2032                                 &abm_shift,
2033                                 &abm_mask);
2034                 if (pool->base.multiple_abms[i] == NULL) {
2035                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2036                         BREAK_TO_DEBUGGER();
2037                         goto create_fail;
2038                 }
2039         }
2040
2041         /* MPC and DSC */
2042         pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2043         if (pool->base.mpc == NULL) {
2044                 BREAK_TO_DEBUGGER();
2045                 dm_error("DC: failed to create mpc!\n");
2046                 goto create_fail;
2047         }
2048
2049         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2050                 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2051                 if (pool->base.dscs[i] == NULL) {
2052                         BREAK_TO_DEBUGGER();
2053                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2054                         goto create_fail;
2055                 }
2056         }
2057
2058         /* DWB and MMHUBBUB */
2059         if (!dcn35_dwbc_create(ctx, &pool->base)) {
2060                 BREAK_TO_DEBUGGER();
2061                 dm_error("DC: failed to create dwbc!\n");
2062                 goto create_fail;
2063         }
2064
2065         if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2066                 BREAK_TO_DEBUGGER();
2067                 dm_error("DC: failed to create mcif_wb!\n");
2068                 goto create_fail;
2069         }
2070
2071         /* AUX and I2C */
2072         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2073                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2074                 if (pool->base.engines[i] == NULL) {
2075                         BREAK_TO_DEBUGGER();
2076                         dm_error(
2077                                 "DC:failed to create aux engine!!\n");
2078                         goto create_fail;
2079                 }
2080                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2081                 if (pool->base.hw_i2cs[i] == NULL) {
2082                         BREAK_TO_DEBUGGER();
2083                         dm_error(
2084                                 "DC:failed to create hw i2c!!\n");
2085                         goto create_fail;
2086                 }
2087                 pool->base.sw_i2cs[i] = NULL;
2088         }
2089
2090         /* DCN3.5 has 6 DPIA */
2091         pool->base.usb4_dpia_count = 4;
2092         if (dc->debug.dpia_debug.bits.disable_dpia)
2093                 pool->base.usb4_dpia_count = 0;
2094
2095         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2096         if (!resource_construct(num_virtual_links, dc, &pool->base,
2097                         &res_create_funcs))
2098                 goto create_fail;
2099
2100         /* HW Sequencer and Plane caps */
2101         dcn351_hw_sequencer_construct(dc);
2102
2103         dc->caps.max_planes =  pool->base.pipe_count;
2104
2105         for (i = 0; i < dc->caps.max_planes; ++i)
2106                 dc->caps.planes[i] = plane_cap;
2107
2108         dc->cap_funcs = cap_funcs;
2109
2110
2111         dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2112
2113         dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2114         dc->dml2_options.use_native_pstate_optimization = true;
2115         dc->dml2_options.use_native_soc_bb_construction = true;
2116         dc->dml2_options.minimize_dispclk_using_odm = false;
2117         if (dc->config.EnableMinDispClkODM)
2118                 dc->dml2_options.minimize_dispclk_using_odm = true;
2119         dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2120
2121         dc->dml2_options.callbacks.dc = dc;
2122         dc->dml2_options.callbacks.build_scaling_params = &resource_build_scaling_params;
2123         dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2124         dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
2125         dc->dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count;
2126         dc->dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count;
2127         dc->dml2_options.callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index;
2128         dc->dml2_options.callbacks.get_odm_slice_index = &resource_get_odm_slice_index;
2129         dc->dml2_options.callbacks.get_opp_head = &resource_get_opp_head;
2130         dc->dml2_options.max_segments_per_hubp = 24;
2131         dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2132
2133         if (dc->config.sdpif_request_limit_words_per_umc == 0)
2134                 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2135
2136         return true;
2137
2138 create_fail:
2139
2140         dcn351_resource_destruct(pool);
2141
2142         return false;
2143 }
2144
2145 struct resource_pool *dcn351_create_resource_pool(
2146                 const struct dc_init_data *init_data,
2147                 struct dc *dc)
2148 {
2149         struct dcn351_resource_pool *pool =
2150                 kzalloc(sizeof(struct dcn351_resource_pool), GFP_KERNEL);
2151
2152         if (!pool)
2153                 return NULL;
2154
2155         if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))
2156                 return &pool->base;
2157
2158         BREAK_TO_DEBUGGER();
2159         kfree(pool);
2160         return NULL;
2161 }