drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright 2023 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31 #include "dcn35/dcn35_init.h"
  32
  33 #include "resource.h"
  34 #include "include/irq_service_interface.h"
  35 #include "dcn35_resource.h"
  36 #include "dml2/dml2_wrapper.h"
  37
  38 #include "dcn20/dcn20_resource.h"
  39 #include "dcn30/dcn30_resource.h"
  40 #include "dcn31/dcn31_resource.h"
  41 #include "dcn32/dcn32_resource.h"
  42
  43 #include "dcn10/dcn10_ipp.h"
  44 #include "dcn30/dcn30_hubbub.h"
  45 #include "dcn31/dcn31_hubbub.h"
  46 #include "dcn35/dcn35_hubbub.h"
  47 #include "dcn32/dcn32_mpc.h"
  48 #include "dcn35/dcn35_hubp.h"
  49 #include "irq/dcn35/irq_service_dcn35.h"
  50 #include "dcn35/dcn35_dpp.h"
  51 #include "dcn35/dcn35_optc.h"
  52 #include "dcn20/dcn20_hwseq.h"
  53 #include "dcn30/dcn30_hwseq.h"
  54 #include "dce110/dce110_hwseq.h"
  55 #include "dcn35/dcn35_opp.h"
  56 #include "dcn35/dcn35_dsc.h"
  57 #include "dcn30/dcn30_vpg.h"
  58 #include "dcn30/dcn30_afmt.h"
  59 #include "dcn31/dcn31_dio_link_encoder.h"
  60 #include "dcn35/dcn35_dio_stream_encoder.h"
  61 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  62 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  63 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
  64 #include "link.h"
  65 #include "dcn31/dcn31_apg.h"
  66 #include "dcn32/dcn32_dio_link_encoder.h"
  67 #include "dcn31/dcn31_vpg.h"
  68 #include "dcn31/dcn31_afmt.h"
  69 #include "dce/dce_clock_source.h"
  70 #include "dce/dce_audio.h"
  71 #include "dce/dce_hwseq.h"
  72 #include "clk_mgr.h"
  73 #include "virtual/virtual_stream_encoder.h"
  74 #include "dce110/dce110_resource.h"
  75 #include "dml/display_mode_vba.h"
  76 #include "dcn35/dcn35_dccg.h"
  77 #include "dcn35/dcn35_pg_cntl.h"
  78 #include "dcn10/dcn10_resource.h"
  79 #include "dcn31/dcn31_panel_cntl.h"
  80 #include "dcn35/dcn35_hwseq.h"
  81 #include "dcn35/dcn35_dio_link_encoder.h"
  82 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
  83 #include "dml/dcn35/dcn35_fpu.h"
  84 #include "dcn35/dcn35_dwb.h"
  85 #include "dcn35/dcn35_mmhubbub.h"
  86
  87 #include "dcn/dcn_3_5_0_offset.h"
  88 #include "dcn/dcn_3_5_0_sh_mask.h"
  89 #include "nbio/nbio_7_11_0_offset.h"
  90 #include "mmhub/mmhub_3_3_0_offset.h"
  91 #include "mmhub/mmhub_3_3_0_sh_mask.h"
  92
  93 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
  94 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
  95
  96 #include "reg_helper.h"
  97 #include "dce/dmub_abm.h"
  98 #include "dce/dmub_psr.h"
  99 #include "dce/dmub_replay.h"
 100 #include "dce/dce_aux.h"
 101 #include "dce/dce_i2c.h"
 102 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
 103 #include "vm_helper.h"
 104 #include "dcn20/dcn20_vmid.h"
 105
 106 #include "dc_state_priv.h"
 107
 108 #include "link_enc_cfg.h"
 109 #define DC_LOGGER_INIT(logger)
 110
 111 enum dcn35_clk_src_array_id {
 112         DCN35_CLK_SRC_PLL0,
 113         DCN35_CLK_SRC_PLL1,
 114         DCN35_CLK_SRC_PLL2,
 115         DCN35_CLK_SRC_PLL3,
 116         DCN35_CLK_SRC_PLL4,
 117         DCN35_CLK_SRC_TOTAL
 118 };
 119
 120 /* begin *********************
 121  * macros to expend register list macro defined in HW object header file
 122  */
 123
 124 /* DCN */
 125 /* TODO awful hack. fixup dcn20_dwb.h */
 126 #undef BASE_INNER
 127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 128
 129 #define BASE(seg) BASE_INNER(seg)
 130
 131 #define SR(reg_name)\
 132                 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 133                                         reg ## reg_name
 134
 135 #define SR_ARR(reg_name, id) \
 136         REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 137
 138 #define SR_ARR_INIT(reg_name, id, value) \
 139         REG_STRUCT[id].reg_name = value
 140
 141 #define SRI(reg_name, block, id)\
 142         REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 143                                         reg ## block ## id ## _ ## reg_name
 144
 145 #define SRI_ARR(reg_name, block, id)\
 146         REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 147                 reg ## block ## id ## _ ## reg_name
 148
 149 #define SR_ARR_I2C(reg_name, id) \
 150         REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 151
 152 #define SRI_ARR_I2C(reg_name, block, id)\
 153         REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 154                 reg ## block ## id ## _ ## reg_name
 155
 156 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 157         REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 158                 reg ## block ## id ## _ ## reg_name
 159
 160 #define SRI2(reg_name, block, id)\
 161         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 162                                         reg ## reg_name
 163
 164 #define SRI2_ARR(reg_name, block, id)\
 165         REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 166                 reg ## reg_name
 167
 168 #define SRIR(var_name, reg_name, block, id)\
 169         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 170                                         reg ## block ## id ## _ ## reg_name
 171
 172 #define SRII(reg_name, block, id)\
 173         REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 174                                         reg ## block ## id ## _ ## reg_name
 175
 176 #define SRII_ARR_2(reg_name, block, id, inst)\
 177         REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 178                 reg ## block ## id ## _ ## reg_name
 179
 180 #define SRII_MPC_RMU(reg_name, block, id)\
 181         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 182                                         reg ## block ## id ## _ ## reg_name
 183
 184 #define SRII_DWB(reg_name, temp_name, block, id)\
 185         REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 186                 reg ## block ## id ## _ ## temp_name
 187
 188 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 189         .field_name = reg_name ## __ ## field_name ## post_fix
 190
 191 #define DCCG_SRII(reg_name, block, id)\
 192         REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 193                 reg ## block ## id ## _ ## reg_name
 194
 195 #define VUPDATE_SRII(reg_name, block, id)\
 196         REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 197                 reg ## reg_name ## _ ## block ## id
 198
 199 /* NBIO */
 200 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 201
 202 #define NBIO_BASE(seg) \
 203         NBIO_BASE_INNER(seg)
 204
 205 #define NBIO_SR(reg_name)\
 206         REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 207                                 regBIF_BX2_ ## reg_name
 208
 209 #define NBIO_SR_ARR(reg_name, id)\
 210         REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 211                 regBIF_BX2_ ## reg_name
 212
 213 #define bios_regs_init() \
 214                 ( \
 215                 NBIO_SR(BIOS_SCRATCH_3),\
 216                 NBIO_SR(BIOS_SCRATCH_6)\
 217                 )
 218
 219 static struct bios_registers bios_regs;
 220
 221 #define clk_src_regs_init(index, pllid)\
 222         CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 223
 224 static struct dce110_clk_src_regs clk_src_regs[5];
 225
 226 static const struct dce110_clk_src_shift cs_shift = {
 227                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 228 };
 229
 230 static const struct dce110_clk_src_mask cs_mask = {
 231                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 232 };
 233
 234 #define abm_regs_init(id)\
 235                 ABM_DCN32_REG_LIST_RI(id)
 236
 237 static struct dce_abm_registers abm_regs[4];
 238
 239 static const struct dce_abm_shift abm_shift = {
 240                 ABM_MASK_SH_LIST_DCN35(__SHIFT)
 241 };
 242
 243 static const struct dce_abm_mask abm_mask = {
 244                 ABM_MASK_SH_LIST_DCN35(_MASK)
 245 };
 246
 247 #define audio_regs_init(id)\
 248                 AUD_COMMON_REG_LIST_RI(id)
 249
 250 static struct dce_audio_registers audio_regs[7];
 251
 252
 253 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 254                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 255                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 256                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 257
 258 static const struct dce_audio_shift audio_shift = {
 259                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 260 };
 261
 262 static const struct dce_audio_mask audio_mask = {
 263                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 264 };
 265
 266 #define vpg_regs_init(id)\
 267         VPG_DCN31_REG_LIST_RI(id)
 268
 269 static struct dcn31_vpg_registers vpg_regs[10];
 270
 271 static const struct dcn31_vpg_shift vpg_shift = {
 272         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 273 };
 274
 275 static const struct dcn31_vpg_mask vpg_mask = {
 276         DCN31_VPG_MASK_SH_LIST(_MASK)
 277 };
 278
 279 #define afmt_regs_init(id)\
 280         AFMT_DCN31_REG_LIST_RI(id)
 281
 282 static struct dcn31_afmt_registers afmt_regs[6];
 283
 284 static const struct dcn31_afmt_shift afmt_shift = {
 285         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 286 };
 287
 288 static const struct dcn31_afmt_mask afmt_mask = {
 289         DCN31_AFMT_MASK_SH_LIST(_MASK)
 290 };
 291
 292 #define apg_regs_init(id)\
 293         APG_DCN31_REG_LIST_RI(id)
 294
 295 static struct dcn31_apg_registers apg_regs[4];
 296
 297 static const struct dcn31_apg_shift apg_shift = {
 298         DCN31_APG_MASK_SH_LIST(__SHIFT)
 299 };
 300
 301 static const struct dcn31_apg_mask apg_mask = {
 302         DCN31_APG_MASK_SH_LIST(_MASK)
 303 };
 304
 305 #define stream_enc_regs_init(id)\
 306         SE_DCN35_REG_LIST_RI(id)
 307
 308 static struct dcn10_stream_enc_registers stream_enc_regs[5];
 309
 310 static const struct dcn10_stream_encoder_shift se_shift = {
 311                 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 312 };
 313
 314 static const struct dcn10_stream_encoder_mask se_mask = {
 315                 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
 316 };
 317
 318 #define aux_regs_init(id)\
 319         DCN2_AUX_REG_LIST_RI(id)
 320
 321 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 322
 323 #define hpd_regs_init(id)\
 324         HPD_REG_LIST_RI(id)
 325
 326 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 327
 328
 329 static const struct dce110_aux_registers_shift aux_shift = {
 330         DCN_AUX_MASK_SH_LIST(__SHIFT)
 331 };
 332
 333 static const struct dce110_aux_registers_mask aux_mask = {
 334         DCN_AUX_MASK_SH_LIST(_MASK)
 335 };
 336
 337 #define link_regs_init(id, phyid)\
 338         ( \
 339         LE_DCN35_REG_LIST_RI(id), \
 340         UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
 341         )
 342
 343 static struct dcn10_link_enc_registers link_enc_regs[5];
 344
 345 static const struct dcn10_link_enc_shift le_shift = {
 346         LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
 347         //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 348 };
 349
 350 static const struct dcn10_link_enc_mask le_mask = {
 351         LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
 352         //DPCS_DCN31_MASK_SH_LIST(_MASK)
 353 };
 354
 355 #define hpo_dp_stream_encoder_reg_init(id)\
 356         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 357
 358 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 359
 360 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 361         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 362 };
 363
 364 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 365         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 366 };
 367
 368 #define hpo_dp_link_encoder_reg_init(id)\
 369         DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 370         /*DCN3_1_RDPCSTX_REG_LIST(0),*/
 371         /*DCN3_1_RDPCSTX_REG_LIST(1),*/
 372         /*DCN3_1_RDPCSTX_REG_LIST(2),*/
 373         /*DCN3_1_RDPCSTX_REG_LIST(3),*/
 374
 375 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
 376
 377 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 378         DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
 379 };
 380
 381 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 382         DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
 383 };
 384
 385 #define dpp_regs_init(id)\
 386         DPP_REG_LIST_DCN35_RI(id)
 387
 388 static struct dcn3_dpp_registers dpp_regs[4];
 389
 390 static const struct dcn35_dpp_shift tf_shift = {
 391                 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
 392 };
 393
 394 static const struct dcn35_dpp_mask tf_mask = {
 395                 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
 396 };
 397
 398 #define opp_regs_init(id)\
 399         OPP_REG_LIST_DCN35_RI(id)
 400
 401 static struct dcn35_opp_registers opp_regs[4];
 402
 403 static const struct dcn35_opp_shift opp_shift = {
 404         OPP_MASK_SH_LIST_DCN35(__SHIFT)
 405 };
 406
 407 static const struct dcn35_opp_mask opp_mask = {
 408         OPP_MASK_SH_LIST_DCN35(_MASK)
 409 };
 410
 411 #define aux_engine_regs_init(id)\
 412         ( \
 413         AUX_COMMON_REG_LIST0_RI(id), \
 414         SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 415         SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 416         SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
 417         )
 418
 419 static struct dce110_aux_registers aux_engine_regs[5];
 420
 421 #define dwbc_regs_dcn3_init(id)\
 422         DWBC_COMMON_REG_LIST_DCN30_RI(id)
 423
 424 static struct dcn30_dwbc_registers dwbc35_regs[1];
 425
 426 static const struct dcn35_dwbc_shift dwbc35_shift = {
 427         DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 428 };
 429
 430 static const struct dcn35_dwbc_mask dwbc35_mask = {
 431         DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
 432 };
 433
 434 #define mcif_wb_regs_dcn3_init(id)\
 435         MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
 436
 437 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
 438
 439 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
 440         MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 441 };
 442
 443 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
 444         MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 445 };
 446
 447 #define dsc_regsDCN35_init(id)\
 448         DSC_REG_LIST_DCN20_RI(id)
 449
 450 static struct dcn20_dsc_registers dsc_regs[4];
 451
 452 static const struct dcn35_dsc_shift dsc_shift = {
 453         DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
 454 };
 455
 456 static const struct dcn35_dsc_mask dsc_mask = {
 457         DSC_REG_LIST_SH_MASK_DCN35(_MASK)
 458 };
 459
 460 static struct dcn30_mpc_registers mpc_regs;
 461
 462 #define dcn_mpc_regs_init() \
 463         MPC_REG_LIST_DCN3_2_RI(0),\
 464         MPC_REG_LIST_DCN3_2_RI(1),\
 465         MPC_REG_LIST_DCN3_2_RI(2),\
 466         MPC_REG_LIST_DCN3_2_RI(3),\
 467         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 468         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 469         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 470         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 471         MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 472
 473 static const struct dcn30_mpc_shift mpc_shift = {
 474         MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 475 };
 476
 477 static const struct dcn30_mpc_mask mpc_mask = {
 478         MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 479 };
 480
 481 #define optc_regs_init(id)\
 482         OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
 483
 484 static struct dcn_optc_registers optc_regs[4];
 485
 486 static const struct dcn_optc_shift optc_shift = {
 487         OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 488 };
 489
 490 static const struct dcn_optc_mask optc_mask = {
 491         OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 492 };
 493
 494 #define hubp_regs_init(id)\
 495         HUBP_REG_LIST_DCN30_RI(id)
 496
 497 static struct dcn_hubp2_registers hubp_regs[4];
 498
 499
 500 static const struct dcn35_hubp2_shift hubp_shift = {
 501                 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
 502 };
 503
 504 static const struct dcn35_hubp2_mask hubp_mask = {
 505                 HUBP_MASK_SH_LIST_DCN35(_MASK)
 506 };
 507
 508 static struct dcn_hubbub_registers hubbub_reg;
 509
 510 #define hubbub_reg_init()\
 511                 HUBBUB_REG_LIST_DCN35(0)
 512
 513 static const struct dcn_hubbub_shift hubbub_shift = {
 514                 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
 515 };
 516
 517 static const struct dcn_hubbub_mask hubbub_mask = {
 518                 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
 519 };
 520
 521 static struct dccg_registers dccg_regs;
 522
 523 #define dccg_regs_init()\
 524         DCCG_REG_LIST_DCN35()
 525
 526 static const struct dccg_shift dccg_shift = {
 527                 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
 528 };
 529
 530 static const struct dccg_mask dccg_mask = {
 531                 DCCG_MASK_SH_LIST_DCN35(_MASK)
 532 };
 533
 534 static struct pg_cntl_registers pg_cntl_regs;
 535
 536 #define pg_cntl_dcn35_regs_init() \
 537         PG_CNTL_REG_LIST_DCN35()
 538
 539 static const struct pg_cntl_shift pg_cntl_shift = {
 540                 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
 541 };
 542
 543 static const struct pg_cntl_mask pg_cntl_mask = {
 544                 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
 545 };
 546
 547 #define SRII2(reg_name_pre, reg_name_post, id)\
 548         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 549                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 550                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 551
 552 static struct dce_hwseq_registers hwseq_reg;
 553
 554 #define hwseq_reg_init()\
 555         HWSEQ_DCN35_REG_LIST()
 556
 557 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
 558         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 559         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 560         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 561         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 562         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 563         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 564         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 565         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 566         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 567         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 568         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 569         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 570         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 571         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 572         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 573         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 574         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 575         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 576         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 577         HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 578         HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 579         HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 580         HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 581         HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 582         HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 583         HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 584         HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 585         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 586         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 587         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 588         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 589         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 590         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 591         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 592         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 593         HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 594         HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 595         HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 596         HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 597         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 598         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 599         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 600         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 601         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 602         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 603         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
 604         HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
 605         HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
 606         HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
 607         HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 608         HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 609         HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 610         HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 611         HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 612         HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
 613         HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
 614         HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
 615         HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
 616         HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
 617         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
 618         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
 619         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
 620         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
 621         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
 622         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
 623         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
 624         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
 625         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
 626         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
 627         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
 628         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 629         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 630         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 631         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 632         HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
 633         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
 634         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
 635         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
 636         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
 637         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
 638         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
 639         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
 640         HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
 641         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
 642         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
 643         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
 644         HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
 645
 646 static const struct dce_hwseq_shift hwseq_shift = {
 647                 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
 648 };
 649
 650 static const struct dce_hwseq_mask hwseq_mask = {
 651                 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
 652 };
 653
 654 #define vmid_regs_init(id)\
 655                 DCN20_VMID_REG_LIST_RI(id)
 656
 657 static struct dcn_vmid_registers vmid_regs[16];
 658
 659 static const struct dcn20_vmid_shift vmid_shifts = {
 660                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 661 };
 662
 663 static const struct dcn20_vmid_mask vmid_masks = {
 664                 DCN20_VMID_MASK_SH_LIST(_MASK)
 665 };
 666
 667 static const struct resource_caps res_cap_dcn35 = {
 668         .num_timing_generator = 4,
 669         .num_opp = 4,
 670         .num_video_plane = 4,
 671         .num_audio = 5,
 672         .num_stream_encoder = 5,
 673         .num_dig_link_enc = 5,
 674         .num_hpo_dp_stream_encoder = 4,
 675         .num_hpo_dp_link_encoder = 2,
 676         .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
 677         .num_dwb = 1,
 678         .num_ddc = 5,
 679         .num_vmid = 16,
 680         .num_mpc_3dlut = 2,
 681         .num_dsc = 4,
 682 };
 683
 684 static const struct dc_plane_cap plane_cap = {
 685         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 686         .per_pixel_alpha = true,
 687
 688         .pixel_format_support = {
 689                         .argb8888 = true,
 690                         .nv12 = true,
 691                         .fp16 = true,
 692                         .p010 = true,
 693                         .ayuv = false,
 694         },
 695
 696         .max_upscale_factor = {
 697                         .argb8888 = 16000,
 698                         .nv12 = 16000,
 699                         .fp16 = 16000
 700         },
 701
 702         // 6:1 downscaling ratio: 1000/6 = 166.666
 703         .max_downscale_factor = {
 704                         .argb8888 = 167,
 705                         .nv12 = 167,
 706                         .fp16 = 167
 707         },
 708         64,
 709         64
 710 };
 711
 712 static const struct dc_debug_options debug_defaults_drv = {
 713         .disable_dmcu = true,
 714         .force_abm_enable = false,
 715         .timing_trace = false,
 716         .clock_trace = true,
 717         .disable_pplib_clock_request = false,
 718         .pipe_split_policy = MPC_SPLIT_AVOID,
 719         .force_single_disp_pipe_split = false,
 720         .disable_dcc = DCC_ENABLE,
 721         .disable_dpp_power_gate = true,
 722         .disable_hubp_power_gate = true,
 723         .disable_optc_power_gate = true, /*should the same as above two*/
 724         .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
 725         .disable_clock_gate = false,
 726         .disable_dsc_power_gate = true,
 727         .vsr_support = true,
 728         .performance_trace = false,
 729         .max_downscale_src_width = 4096,/*upto true 4k*/
 730         .disable_pplib_wm_range = false,
 731         .scl_reset_length10 = true,
 732         .sanity_checks = false,
 733         .underflow_assert_delay_us = 0xFFFFFFFF,
 734         .dwb_fi_phase = -1, // -1 = disable,
 735         .dmub_command_table = true,
 736         .pstate_enabled = true,
 737         .use_max_lb = true,
 738         .enable_mem_low_power = {
 739                 .bits = {
 740                         .vga = false,
 741                         .i2c = true,
 742                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 743                         .dscl = true,
 744                         .cm = true,
 745                         .mpc = true,
 746                         .optc = true,
 747                         .vpg = true,
 748                         .afmt = true,
 749                 }
 750         },
 751         .root_clock_optimization = {
 752                 .bits = {
 753                         .dpp = true,
 754                         .dsc = true,/*dscclk and dsc pg*/
 755                         .hdmistream = true,
 756                         .hdmichar = true,
 757                         .dpstream = true,
 758                         .symclk32_se = true,
 759                         .symclk32_le = true,
 760                         .symclk_fe = true,
 761                         .physymclk = true,
 762                         .dpiasymclk = true,
 763                 }
 764         },
 765         .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
 766         .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 767         .using_dml2 = true,
 768         .support_eDP1_5 = true,
 769         .enable_hpo_pg_support = false,
 770         .enable_legacy_fast_update = true,
 771         .enable_single_display_2to1_odm_policy = false,
 772         .disable_idle_power_optimizations = false,
 773         .dmcub_emulation = false,
 774         .disable_boot_optimizations = false,
 775         .disable_unbounded_requesting = false,
 776         .disable_mem_low_power = false,
 777         //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
 778         .enable_double_buffered_dsc_pg_support = true,
 779         .enable_dp_dig_pixel_rate_div_policy = 1,
 780         .disable_z10 = false,
 781         .ignore_pg = true,
 782         .psp_disabled_wa = true,
 783         .ips2_eval_delay_us = 2000,
 784         .ips2_entry_delay_us = 800,
 785         .static_screen_wait_frames = 2,
 786 };
 787
 788 static const struct dc_panel_config panel_config_defaults = {
 789         .psr = {
 790                 .disable_psr = false,
 791                 .disallow_psrsu = false,
 792                 .disallow_replay = false,
 793         },
 794         .ilr = {
 795                 .optimize_edp_link_rate = true,
 796         },
 797 };
 798
 799 static void dcn35_dpp_destroy(struct dpp **dpp)
 800 {
 801         kfree(TO_DCN20_DPP(*dpp));
 802         *dpp = NULL;
 803 }
 804
 805 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
 806 {
 807         struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 808         bool success = (dpp != NULL);
 809
 810         if (!success)
 811                 return NULL;
 812
 813 #undef REG_STRUCT
 814 #define REG_STRUCT dpp_regs
 815         dpp_regs_init(0),
 816         dpp_regs_init(1),
 817         dpp_regs_init(2),
 818         dpp_regs_init(3);
 819
 820         success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
 821                                   &tf_mask);
 822         if (success) {
 823                 dpp35_set_fgcg(
 824                         dpp,
 825                         ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
 826                 return &dpp->base;
 827         }
 828
 829         BREAK_TO_DEBUGGER();
 830         kfree(dpp);
 831         return NULL;
 832 }
 833
 834 static struct output_pixel_processor *dcn35_opp_create(
 835         struct dc_context *ctx, uint32_t inst)
 836 {
 837         struct dcn20_opp *opp =
 838                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 839
 840         if (!opp) {
 841                 BREAK_TO_DEBUGGER();
 842                 return NULL;
 843         }
 844
 845 #undef REG_STRUCT
 846 #define REG_STRUCT opp_regs
 847         opp_regs_init(0),
 848         opp_regs_init(1),
 849         opp_regs_init(2),
 850         opp_regs_init(3);
 851
 852         dcn35_opp_construct(opp, ctx, inst,
 853                         &opp_regs[inst], &opp_shift, &opp_mask);
 854
 855         dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
 856
 857         return &opp->base;
 858 }
 859
 860 static struct dce_aux *dcn31_aux_engine_create(
 861         struct dc_context *ctx,
 862         uint32_t inst)
 863 {
 864         struct aux_engine_dce110 *aux_engine =
 865                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 866
 867         if (!aux_engine)
 868                 return NULL;
 869
 870 #undef REG_STRUCT
 871 #define REG_STRUCT aux_engine_regs
 872         aux_engine_regs_init(0),
 873         aux_engine_regs_init(1),
 874         aux_engine_regs_init(2),
 875         aux_engine_regs_init(3),
 876         aux_engine_regs_init(4);
 877
 878         dce110_aux_engine_construct(aux_engine, ctx, inst,
 879                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 880                                     &aux_engine_regs[inst],
 881                                         &aux_mask,
 882                                         &aux_shift,
 883                                         ctx->dc->caps.extended_aux_timeout_support);
 884
 885         return &aux_engine->base;
 886 }
 887
 888 #define i2c_inst_regs_init(id)\
 889         I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 890
 891 static struct dce_i2c_registers i2c_hw_regs[5];
 892
 893 static const struct dce_i2c_shift i2c_shifts = {
 894                 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 895 };
 896
 897 static const struct dce_i2c_mask i2c_masks = {
 898                 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
 899 };
 900
 901 /* ========================================================== */
 902
 903 /*
 904  * DPIA index | Preferred Encoder     |    Host Router
 905  *   0        |      C                |       0
 906  *   1        |      First Available  |       0
 907  *   2        |      D                |       1
 908  *   3        |      First Available  |       1
 909  */
 910 /* ========================================================== */
 911 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
 912                 ENGINE_ID_DIGC,
 913                 ENGINE_ID_DIGC,
 914                 ENGINE_ID_DIGD,
 915                 ENGINE_ID_DIGD
 916 };
 917
 918 static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)
 919 {
 920         return dpia_to_preferred_enc_id_table[dpia_index];
 921 }
 922
 923 static struct dce_i2c_hw *dcn31_i2c_hw_create(
 924         struct dc_context *ctx,
 925         uint32_t inst)
 926 {
 927         struct dce_i2c_hw *dce_i2c_hw =
 928                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 929
 930         if (!dce_i2c_hw)
 931                 return NULL;
 932
 933 #undef REG_STRUCT
 934 #define REG_STRUCT i2c_hw_regs
 935         i2c_inst_regs_init(1),
 936         i2c_inst_regs_init(2),
 937         i2c_inst_regs_init(3),
 938         i2c_inst_regs_init(4),
 939         i2c_inst_regs_init(5);
 940
 941         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 942                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 943
 944         return dce_i2c_hw;
 945 }
 946 static struct mpc *dcn35_mpc_create(
 947                 struct dc_context *ctx,
 948                 int num_mpcc,
 949                 int num_rmu)
 950 {
 951         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 952
 953         if (!mpc30)
 954                 return NULL;
 955
 956 #undef REG_STRUCT
 957 #define REG_STRUCT mpc_regs
 958         dcn_mpc_regs_init();
 959
 960         dcn32_mpc_construct(mpc30, ctx,
 961                         &mpc_regs,
 962                         &mpc_shift,
 963                         &mpc_mask,
 964                         num_mpcc,
 965                         num_rmu);
 966
 967         return &mpc30->base;
 968 }
 969
 970 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
 971 {
 972         int i;
 973
 974         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 975                                           GFP_KERNEL);
 976
 977         if (!hubbub3)
 978                 return NULL;
 979
 980 #undef REG_STRUCT
 981 #define REG_STRUCT hubbub_reg
 982         hubbub_reg_init();
 983
 984 #undef REG_STRUCT
 985 #define REG_STRUCT vmid_regs
 986         vmid_regs_init(0),
 987         vmid_regs_init(1),
 988         vmid_regs_init(2),
 989         vmid_regs_init(3),
 990         vmid_regs_init(4),
 991         vmid_regs_init(5),
 992         vmid_regs_init(6),
 993         vmid_regs_init(7),
 994         vmid_regs_init(8),
 995         vmid_regs_init(9),
 996         vmid_regs_init(10),
 997         vmid_regs_init(11),
 998         vmid_regs_init(12),
 999         vmid_regs_init(13),
1000         vmid_regs_init(14),
1001         vmid_regs_init(15);
1002
1003         hubbub35_construct(hubbub3, ctx,
1004                         &hubbub_reg,
1005                         &hubbub_shift,
1006                         &hubbub_mask,
1007                         384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1008                         8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1009                         1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1010
1011
1012         for (i = 0; i < res_cap_dcn35.num_vmid; i++) {
1013                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1014
1015                 vmid->ctx = ctx;
1016
1017                 vmid->regs = &vmid_regs[i];
1018                 vmid->shifts = &vmid_shifts;
1019                 vmid->masks = &vmid_masks;
1020         }
1021
1022         return &hubbub3->base;
1023 }
1024
1025 static struct timing_generator *dcn35_timing_generator_create(
1026                 struct dc_context *ctx,
1027                 uint32_t instance)
1028 {
1029         struct optc *tgn10 =
1030                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1031
1032         if (!tgn10)
1033                 return NULL;
1034
1035 #undef REG_STRUCT
1036 #define REG_STRUCT optc_regs
1037         optc_regs_init(0),
1038         optc_regs_init(1),
1039         optc_regs_init(2),
1040         optc_regs_init(3);
1041
1042         tgn10->base.inst = instance;
1043         tgn10->base.ctx = ctx;
1044
1045         tgn10->tg_regs = &optc_regs[instance];
1046         tgn10->tg_shift = &optc_shift;
1047         tgn10->tg_mask = &optc_mask;
1048
1049         dcn35_timing_generator_init(tgn10);
1050
1051         return &tgn10->base;
1052 }
1053
1054 static const struct encoder_feature_support link_enc_feature = {
1055                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1056                 .max_hdmi_pixel_clock = 600000,
1057                 .hdmi_ycbcr420_supported = true,
1058                 .dp_ycbcr420_supported = true,
1059                 .fec_supported = true,
1060                 .flags.bits.IS_HBR2_CAPABLE = true,
1061                 .flags.bits.IS_HBR3_CAPABLE = true,
1062                 .flags.bits.IS_TPS3_CAPABLE = true,
1063                 .flags.bits.IS_TPS4_CAPABLE = true
1064 };
1065
1066 static struct link_encoder *dcn35_link_encoder_create(
1067         struct dc_context *ctx,
1068         const struct encoder_init_data *enc_init_data)
1069 {
1070         struct dcn20_link_encoder *enc20 =
1071                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1072
1073         if (!enc20)
1074                 return NULL;
1075
1076 #undef REG_STRUCT
1077 #define REG_STRUCT link_enc_aux_regs
1078         aux_regs_init(0),
1079         aux_regs_init(1),
1080         aux_regs_init(2),
1081         aux_regs_init(3),
1082         aux_regs_init(4);
1083
1084 #undef REG_STRUCT
1085 #define REG_STRUCT link_enc_hpd_regs
1086         hpd_regs_init(0),
1087         hpd_regs_init(1),
1088         hpd_regs_init(2),
1089         hpd_regs_init(3),
1090         hpd_regs_init(4);
1091
1092 #undef REG_STRUCT
1093 #define REG_STRUCT link_enc_regs
1094         link_regs_init(0, A),
1095         link_regs_init(1, B),
1096         link_regs_init(2, C),
1097         link_regs_init(3, D),
1098         link_regs_init(4, E);
1099
1100         dcn35_link_encoder_construct(enc20,
1101                         enc_init_data,
1102                         &link_enc_feature,
1103                         &link_enc_regs[enc_init_data->transmitter],
1104                         &link_enc_aux_regs[enc_init_data->channel - 1],
1105                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1106                         &le_shift,
1107                         &le_mask);
1108
1109         return &enc20->enc10.base;
1110 }
1111
1112 /* Create a minimal link encoder object not associated with a particular
1113  * physical connector.
1114  * resource_funcs.link_enc_create_minimal
1115  */
1116 static struct link_encoder *dcn31_link_enc_create_minimal(
1117                 struct dc_context *ctx, enum engine_id eng_id)
1118 {
1119         struct dcn20_link_encoder *enc20;
1120
1121         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1122                 return NULL;
1123
1124         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1125         if (!enc20)
1126                 return NULL;
1127
1128         dcn31_link_encoder_construct_minimal(
1129                         enc20,
1130                         ctx,
1131                         &link_enc_feature,
1132                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1133                         eng_id);
1134
1135         return &enc20->enc10.base;
1136 }
1137
1138 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1139 {
1140         struct dcn31_panel_cntl *panel_cntl =
1141                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1142
1143         if (!panel_cntl)
1144                 return NULL;
1145
1146         dcn31_panel_cntl_construct(panel_cntl, init_data);
1147
1148         return &panel_cntl->base;
1149 }
1150
1151 static void read_dce_straps(
1152         struct dc_context *ctx,
1153         struct resource_straps *straps)
1154 {
1155         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1156                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1157
1158 }
1159
1160 static struct audio *dcn31_create_audio(
1161                 struct dc_context *ctx, unsigned int inst)
1162 {
1163
1164 #undef REG_STRUCT
1165 #define REG_STRUCT audio_regs
1166         audio_regs_init(0),
1167         audio_regs_init(1),
1168         audio_regs_init(2),
1169         audio_regs_init(3),
1170         audio_regs_init(4);
1171         audio_regs_init(5);
1172         audio_regs_init(6);
1173
1174         return dce_audio_create(ctx, inst,
1175                         &audio_regs[inst], &audio_shift, &audio_mask);
1176 }
1177
1178 static struct vpg *dcn31_vpg_create(
1179         struct dc_context *ctx,
1180         uint32_t inst)
1181 {
1182         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1183
1184         if (!vpg31)
1185                 return NULL;
1186
1187 #undef REG_STRUCT
1188 #define REG_STRUCT vpg_regs
1189         vpg_regs_init(0),
1190         vpg_regs_init(1),
1191         vpg_regs_init(2),
1192         vpg_regs_init(3),
1193         vpg_regs_init(4),
1194         vpg_regs_init(5),
1195         vpg_regs_init(6),
1196         vpg_regs_init(7),
1197         vpg_regs_init(8),
1198         vpg_regs_init(9);
1199
1200         vpg31_construct(vpg31, ctx, inst,
1201                         &vpg_regs[inst],
1202                         &vpg_shift,
1203                         &vpg_mask);
1204
1205         return &vpg31->base;
1206 }
1207
1208 static struct afmt *dcn31_afmt_create(
1209         struct dc_context *ctx,
1210         uint32_t inst)
1211 {
1212         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1213
1214         if (!afmt31)
1215                 return NULL;
1216
1217 #undef REG_STRUCT
1218 #define REG_STRUCT afmt_regs
1219         afmt_regs_init(0),
1220         afmt_regs_init(1),
1221         afmt_regs_init(2),
1222         afmt_regs_init(3),
1223         afmt_regs_init(4),
1224         afmt_regs_init(5);
1225
1226         afmt31_construct(afmt31, ctx, inst,
1227                         &afmt_regs[inst],
1228                         &afmt_shift,
1229                         &afmt_mask);
1230
1231         // Light sleep by default, no need to power down here
1232
1233         return &afmt31->base;
1234 }
1235
1236 static struct apg *dcn31_apg_create(
1237         struct dc_context *ctx,
1238         uint32_t inst)
1239 {
1240         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1241
1242         if (!apg31)
1243                 return NULL;
1244
1245 #undef REG_STRUCT
1246 #define REG_STRUCT apg_regs
1247         apg_regs_init(0),
1248         apg_regs_init(1),
1249         apg_regs_init(2),
1250         apg_regs_init(3);
1251
1252         apg31_construct(apg31, ctx, inst,
1253                         &apg_regs[inst],
1254                         &apg_shift,
1255                         &apg_mask);
1256
1257         return &apg31->base;
1258 }
1259
1260 static struct stream_encoder *dcn35_stream_encoder_create(
1261         enum engine_id eng_id,
1262         struct dc_context *ctx)
1263 {
1264         struct dcn10_stream_encoder *enc1;
1265         struct vpg *vpg;
1266         struct afmt *afmt;
1267         int vpg_inst;
1268         int afmt_inst;
1269
1270         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1271         if (eng_id <= ENGINE_ID_DIGF) {
1272                 vpg_inst = eng_id;
1273                 afmt_inst = eng_id;
1274         } else
1275                 return NULL;
1276
1277         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1278         vpg = dcn31_vpg_create(ctx, vpg_inst);
1279         afmt = dcn31_afmt_create(ctx, afmt_inst);
1280
1281         if (!enc1 || !vpg || !afmt) {
1282                 kfree(enc1);
1283                 kfree(vpg);
1284                 kfree(afmt);
1285                 return NULL;
1286         }
1287
1288 #undef REG_STRUCT
1289 #define REG_STRUCT stream_enc_regs
1290         stream_enc_regs_init(0),
1291         stream_enc_regs_init(1),
1292         stream_enc_regs_init(2),
1293         stream_enc_regs_init(3),
1294         stream_enc_regs_init(4);
1295
1296         dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1297                                         eng_id, vpg, afmt,
1298                                         &stream_enc_regs[eng_id],
1299                                         &se_shift, &se_mask);
1300
1301         return &enc1->base;
1302 }
1303
1304 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1305         enum engine_id eng_id,
1306         struct dc_context *ctx)
1307 {
1308         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1309         struct vpg *vpg;
1310         struct apg *apg;
1311         uint32_t hpo_dp_inst;
1312         uint32_t vpg_inst;
1313         uint32_t apg_inst;
1314
1315         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1316         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1317
1318         /* Mapping of VPG register blocks to HPO DP block instance:
1319          * VPG[6] -> HPO_DP[0]
1320          * VPG[7] -> HPO_DP[1]
1321          * VPG[8] -> HPO_DP[2]
1322          * VPG[9] -> HPO_DP[3]
1323          */
1324         vpg_inst = hpo_dp_inst + 6;
1325
1326         /* Mapping of APG register blocks to HPO DP block instance:
1327          * APG[0] -> HPO_DP[0]
1328          * APG[1] -> HPO_DP[1]
1329          * APG[2] -> HPO_DP[2]
1330          * APG[3] -> HPO_DP[3]
1331          */
1332         apg_inst = hpo_dp_inst;
1333
1334         /* allocate HPO stream encoder and create VPG sub-block */
1335         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1336         vpg = dcn31_vpg_create(ctx, vpg_inst);
1337         apg = dcn31_apg_create(ctx, apg_inst);
1338
1339         if (!hpo_dp_enc31 || !vpg || !apg) {
1340                 kfree(hpo_dp_enc31);
1341                 kfree(vpg);
1342                 kfree(apg);
1343                 return NULL;
1344         }
1345
1346 #undef REG_STRUCT
1347 #define REG_STRUCT hpo_dp_stream_enc_regs
1348         hpo_dp_stream_encoder_reg_init(0),
1349         hpo_dp_stream_encoder_reg_init(1),
1350         hpo_dp_stream_encoder_reg_init(2),
1351         hpo_dp_stream_encoder_reg_init(3);
1352
1353         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1354                                         hpo_dp_inst, eng_id, vpg, apg,
1355                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1356                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1357
1358         return &hpo_dp_enc31->base;
1359 }
1360
1361 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1362         uint8_t inst,
1363         struct dc_context *ctx)
1364 {
1365         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1366
1367         /* allocate HPO link encoder */
1368         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1369
1370 #undef REG_STRUCT
1371 #define REG_STRUCT hpo_dp_link_enc_regs
1372         hpo_dp_link_encoder_reg_init(0),
1373         hpo_dp_link_encoder_reg_init(1);
1374
1375         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1376                                         &hpo_dp_link_enc_regs[inst],
1377                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1378
1379         return &hpo_dp_enc31->base;
1380 }
1381
1382 static struct dce_hwseq *dcn35_hwseq_create(
1383         struct dc_context *ctx)
1384 {
1385         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1386
1387 #undef REG_STRUCT
1388 #define REG_STRUCT hwseq_reg
1389         hwseq_reg_init();
1390
1391         if (hws) {
1392                 hws->ctx = ctx;
1393                 hws->regs = &hwseq_reg;
1394                 hws->shifts = &hwseq_shift;
1395                 hws->masks = &hwseq_mask;
1396         }
1397         return hws;
1398 }
1399 static const struct resource_create_funcs res_create_funcs = {
1400         .read_dce_straps = read_dce_straps,
1401         .create_audio = dcn31_create_audio,
1402         .create_stream_encoder = dcn35_stream_encoder_create,
1403         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1404         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1405         .create_hwseq = dcn35_hwseq_create,
1406 };
1407
1408 static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
1409 {
1410         unsigned int i;
1411
1412         for (i = 0; i < pool->base.stream_enc_count; i++) {
1413                 if (pool->base.stream_enc[i] != NULL) {
1414                         if (pool->base.stream_enc[i]->vpg != NULL) {
1415                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1416                                 pool->base.stream_enc[i]->vpg = NULL;
1417                         }
1418                         if (pool->base.stream_enc[i]->afmt != NULL) {
1419                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1420                                 pool->base.stream_enc[i]->afmt = NULL;
1421                         }
1422                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1423                         pool->base.stream_enc[i] = NULL;
1424                 }
1425         }
1426
1427         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1428                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1429                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1430                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1431                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1432                         }
1433                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1434                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1435                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1436                         }
1437                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1438                         pool->base.hpo_dp_stream_enc[i] = NULL;
1439                 }
1440         }
1441
1442         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1443                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1444                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1445                         pool->base.hpo_dp_link_enc[i] = NULL;
1446                 }
1447         }
1448
1449         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1450                 if (pool->base.dscs[i] != NULL)
1451                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1452         }
1453
1454         if (pool->base.mpc != NULL) {
1455                 kfree(TO_DCN20_MPC(pool->base.mpc));
1456                 pool->base.mpc = NULL;
1457         }
1458         if (pool->base.hubbub != NULL) {
1459                 kfree(pool->base.hubbub);
1460                 pool->base.hubbub = NULL;
1461         }
1462         for (i = 0; i < pool->base.pipe_count; i++) {
1463                 if (pool->base.dpps[i] != NULL)
1464                         dcn35_dpp_destroy(&pool->base.dpps[i]);
1465
1466                 if (pool->base.ipps[i] != NULL)
1467                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1468
1469                 if (pool->base.hubps[i] != NULL) {
1470                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1471                         pool->base.hubps[i] = NULL;
1472                 }
1473
1474                 if (pool->base.irqs != NULL) {
1475                         dal_irq_service_destroy(&pool->base.irqs);
1476                 }
1477         }
1478
1479         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1480                 if (pool->base.engines[i] != NULL)
1481                         dce110_engine_destroy(&pool->base.engines[i]);
1482                 if (pool->base.hw_i2cs[i] != NULL) {
1483                         kfree(pool->base.hw_i2cs[i]);
1484                         pool->base.hw_i2cs[i] = NULL;
1485                 }
1486                 if (pool->base.sw_i2cs[i] != NULL) {
1487                         kfree(pool->base.sw_i2cs[i]);
1488                         pool->base.sw_i2cs[i] = NULL;
1489                 }
1490         }
1491
1492         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1493                 if (pool->base.opps[i] != NULL)
1494                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1495         }
1496
1497         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1498                 if (pool->base.timing_generators[i] != NULL)    {
1499                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1500                         pool->base.timing_generators[i] = NULL;
1501                 }
1502         }
1503
1504         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1505                 if (pool->base.dwbc[i] != NULL) {
1506                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1507                         pool->base.dwbc[i] = NULL;
1508                 }
1509                 if (pool->base.mcif_wb[i] != NULL) {
1510                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1511                         pool->base.mcif_wb[i] = NULL;
1512                 }
1513         }
1514
1515         for (i = 0; i < pool->base.audio_count; i++) {
1516                 if (pool->base.audios[i])
1517                         dce_aud_destroy(&pool->base.audios[i]);
1518         }
1519
1520         for (i = 0; i < pool->base.clk_src_count; i++) {
1521                 if (pool->base.clock_sources[i] != NULL) {
1522                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1523                         pool->base.clock_sources[i] = NULL;
1524                 }
1525         }
1526
1527         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1528                 if (pool->base.mpc_lut[i] != NULL) {
1529                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1530                         pool->base.mpc_lut[i] = NULL;
1531                 }
1532                 if (pool->base.mpc_shaper[i] != NULL) {
1533                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1534                         pool->base.mpc_shaper[i] = NULL;
1535                 }
1536         }
1537
1538         if (pool->base.dp_clock_source != NULL) {
1539                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1540                 pool->base.dp_clock_source = NULL;
1541         }
1542
1543         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1544                 if (pool->base.multiple_abms[i] != NULL)
1545                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1546         }
1547
1548         if (pool->base.psr != NULL)
1549                 dmub_psr_destroy(&pool->base.psr);
1550
1551         if (pool->base.replay != NULL)
1552                 dmub_replay_destroy(&pool->base.replay);
1553
1554         if (pool->base.pg_cntl != NULL)
1555                 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1556
1557         if (pool->base.dccg != NULL)
1558                 dcn_dccg_destroy(&pool->base.dccg);
1559 }
1560
1561 static struct hubp *dcn35_hubp_create(
1562         struct dc_context *ctx,
1563         uint32_t inst)
1564 {
1565         struct dcn20_hubp *hubp2 =
1566                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1567
1568         if (!hubp2)
1569                 return NULL;
1570
1571 #undef REG_STRUCT
1572 #define REG_STRUCT hubp_regs
1573         hubp_regs_init(0),
1574         hubp_regs_init(1),
1575         hubp_regs_init(2),
1576         hubp_regs_init(3);
1577
1578         if (hubp35_construct(hubp2, ctx, inst,
1579                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1580                 return &hubp2->base;
1581
1582         BREAK_TO_DEBUGGER();
1583         kfree(hubp2);
1584         return NULL;
1585 }
1586
1587 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1588 {
1589         dcn35_dwbc_set_fgcg(
1590                 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1591 }
1592
1593 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1594 {
1595         int i;
1596         uint32_t pipe_count = pool->res_cap->num_dwb;
1597
1598         for (i = 0; i < pipe_count; i++) {
1599                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1600                                                     GFP_KERNEL);
1601
1602                 if (!dwbc30) {
1603                         dm_error("DC: failed to create dwbc30!\n");
1604                         return false;
1605                 }
1606
1607 #undef REG_STRUCT
1608 #define REG_STRUCT dwbc35_regs
1609                 dwbc_regs_dcn3_init(0);
1610
1611                 dcn35_dwbc_construct(dwbc30, ctx,
1612                                 &dwbc35_regs[i],
1613                                 &dwbc35_shift,
1614                                 &dwbc35_mask,
1615                                 i);
1616
1617                 pool->dwbc[i] = &dwbc30->base;
1618
1619                 dcn35_dwbc_init(dwbc30, ctx);
1620         }
1621         return true;
1622 }
1623
1624 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1625                                 struct dc_context *ctx)
1626 {
1627         dcn35_mmhubbub_set_fgcg(
1628                 mcif_wb30,
1629                 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1630 }
1631
1632 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1633 {
1634         int i;
1635         uint32_t pipe_count = pool->res_cap->num_dwb;
1636
1637         for (i = 0; i < pipe_count; i++) {
1638                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1639                                                     GFP_KERNEL);
1640
1641                 if (!mcif_wb30) {
1642                         dm_error("DC: failed to create mcif_wb30!\n");
1643                         return false;
1644                 }
1645
1646 #undef REG_STRUCT
1647 #define REG_STRUCT mcif_wb35_regs
1648                 mcif_wb_regs_dcn3_init(0);
1649
1650                 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1651                                 &mcif_wb35_regs[i],
1652                                 &mcif_wb35_shift,
1653                                 &mcif_wb35_mask,
1654                                 i);
1655
1656                 dcn35_mmhubbub_init(mcif_wb30, ctx);
1657
1658                 pool->mcif_wb[i] = &mcif_wb30->base;
1659         }
1660         return true;
1661 }
1662
1663 static struct display_stream_compressor *dcn35_dsc_create(
1664         struct dc_context *ctx, uint32_t inst)
1665 {
1666         struct dcn20_dsc *dsc =
1667                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1668
1669         if (!dsc) {
1670                 BREAK_TO_DEBUGGER();
1671                 return NULL;
1672         }
1673
1674 #undef REG_STRUCT
1675 #define REG_STRUCT dsc_regs
1676         dsc_regsDCN35_init(0),
1677         dsc_regsDCN35_init(1),
1678         dsc_regsDCN35_init(2),
1679         dsc_regsDCN35_init(3);
1680
1681         dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1682         dsc35_set_fgcg(dsc,
1683                        ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1684         return &dsc->base;
1685 }
1686
1687 static void dcn35_destroy_resource_pool(struct resource_pool **pool)
1688 {
1689         struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);
1690
1691         dcn35_resource_destruct(dcn35_pool);
1692         kfree(dcn35_pool);
1693         *pool = NULL;
1694 }
1695
1696 static struct clock_source *dcn35_clock_source_create(
1697                 struct dc_context *ctx,
1698                 struct dc_bios *bios,
1699                 enum clock_source_id id,
1700                 const struct dce110_clk_src_regs *regs,
1701                 bool dp_clk_src)
1702 {
1703         struct dce110_clk_src *clk_src =
1704                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1705
1706         if (!clk_src)
1707                 return NULL;
1708
1709         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1710                         regs, &cs_shift, &cs_mask)) {
1711                 clk_src->base.dp_clk_src = dp_clk_src;
1712                 return &clk_src->base;
1713         }
1714
1715         BREAK_TO_DEBUGGER();
1716         return NULL;
1717 }
1718
1719 static struct dc_cap_funcs cap_funcs = {
1720         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1721 };
1722
1723 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1724 {
1725         *panel_config = panel_config_defaults;
1726 }
1727
1728
1729 static bool dcn35_validate_bandwidth(struct dc *dc,
1730                 struct dc_state *context,
1731                 bool fast_validate)
1732 {
1733         bool out = false;
1734
1735         out = dml2_validate(dc, context, fast_validate);
1736
1737         if (fast_validate)
1738                 return out;
1739
1740         DC_FP_START();
1741         dcn35_decide_zstate_support(dc, context);
1742         DC_FP_END();
1743
1744         return out;
1745 }
1746
1747
1748 static struct resource_funcs dcn35_res_pool_funcs = {
1749         .destroy = dcn35_destroy_resource_pool,
1750         .link_enc_create = dcn35_link_encoder_create,
1751         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1752         .link_encs_assign = link_enc_cfg_link_encs_assign,
1753         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1754         .panel_cntl_create = dcn31_panel_cntl_create,
1755         .validate_bandwidth = dcn35_validate_bandwidth,
1756         .calculate_wm_and_dlg = NULL,
1757         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1758         .populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu,
1759         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1760         .release_pipe = dcn20_release_pipe,
1761         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1762         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1763         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1764         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1765         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1766         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1767         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1768         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1769         .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1770         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1771         .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1772         .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
1773 };
1774
1775 static bool dcn35_resource_construct(
1776         uint8_t num_virtual_links,
1777         struct dc *dc,
1778         struct dcn35_resource_pool *pool)
1779 {
1780         int i;
1781         struct dc_context *ctx = dc->ctx;
1782         struct irq_service_init_data init_data;
1783
1784 #undef REG_STRUCT
1785 #define REG_STRUCT bios_regs
1786         bios_regs_init();
1787
1788 #undef REG_STRUCT
1789 #define REG_STRUCT clk_src_regs
1790         clk_src_regs_init(0, A),
1791         clk_src_regs_init(1, B),
1792         clk_src_regs_init(2, C),
1793         clk_src_regs_init(3, D),
1794         clk_src_regs_init(4, E);
1795
1796 #undef REG_STRUCT
1797 #define REG_STRUCT abm_regs
1798         abm_regs_init(0),
1799         abm_regs_init(1),
1800         abm_regs_init(2),
1801         abm_regs_init(3);
1802
1803 #undef REG_STRUCT
1804 #define REG_STRUCT dccg_regs
1805         dccg_regs_init();
1806
1807         ctx->dc_bios->regs = &bios_regs;
1808
1809         pool->base.res_cap = &res_cap_dcn35;
1810
1811         pool->base.funcs = &dcn35_res_pool_funcs;
1812
1813         /*************************************************
1814          *  Resource + asic cap harcoding                *
1815          *************************************************/
1816         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1817         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1818         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1819         dc->caps.max_downscale_ratio = 600;
1820         dc->caps.i2c_speed_in_khz = 100;
1821         dc->caps.i2c_speed_in_khz_hdcp = 100;
1822         dc->caps.max_cursor_size = 256;
1823         dc->caps.min_horizontal_blanking_period = 80;
1824         dc->caps.dmdata_alloc_size = 2048;
1825         dc->caps.max_slave_planes = 2;
1826         dc->caps.max_slave_yuv_planes = 2;
1827         dc->caps.max_slave_rgb_planes = 2;
1828         dc->caps.post_blend_color_processing = true;
1829         dc->caps.force_dp_tps4_for_cp2520 = true;
1830         if (dc->config.forceHBR2CP2520)
1831                 dc->caps.force_dp_tps4_for_cp2520 = false;
1832         dc->caps.dp_hpo = true;
1833         dc->caps.dp_hdmi21_pcon_support = true;
1834
1835         dc->caps.edp_dsc_support = true;
1836         dc->caps.extended_aux_timeout_support = true;
1837         dc->caps.dmcub_support = true;
1838         dc->caps.is_apu = true;
1839         dc->caps.seamless_odm = true;
1840
1841         dc->caps.zstate_support = true;
1842         dc->caps.ips_support = true;
1843         dc->caps.max_v_total = (1 << 15) - 1;
1844
1845         /* Color pipeline capabilities */
1846         dc->caps.color.dpp.dcn_arch = 1;
1847         dc->caps.color.dpp.input_lut_shared = 0;
1848         dc->caps.color.dpp.icsc = 1;
1849         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1850         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1851         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1852         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1853         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1854         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1855         dc->caps.color.dpp.post_csc = 1;
1856         dc->caps.color.dpp.gamma_corr = 1;
1857         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1858
1859         dc->caps.color.dpp.hw_3d_lut = 1;
1860         dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1
1861         // no OGAM ROM on DCN301
1862         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1863         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1864         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1865         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1866         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1867         dc->caps.color.dpp.ocsc = 0;
1868
1869         dc->caps.color.mpc.gamut_remap = 1;
1870         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1871         dc->caps.color.mpc.ogam_ram = 1;
1872         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1873         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1874         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1875         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1876         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1877         dc->caps.color.mpc.ocsc = 1;
1878
1879         /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1880          * to provide some margin.
1881          * It's expected for furture ASIC to have equal or higher value, in order to
1882          * have determinstic power improvement from generate to genration.
1883          * (i.e., we should not expect new ASIC generation with lower vmin rate)
1884          */
1885         dc->caps.max_disp_clock_khz_at_vmin = 650000;
1886
1887         /* Use pipe context based otg sync logic */
1888         dc->config.use_pipe_ctx_sync_logic = true;
1889
1890         /* read VBIOS LTTPR caps */
1891         {
1892                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1893                         enum bp_result bp_query_result;
1894                         uint8_t is_vbios_lttpr_enable = 0;
1895
1896                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1897                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1898                 }
1899
1900                 /* interop bit is implicit */
1901                 {
1902                         dc->caps.vbios_lttpr_aware = true;
1903                 }
1904         }
1905
1906         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1907                 dc->debug = debug_defaults_drv;
1908
1909         // Init the vm_helper
1910         if (dc->vm_helper)
1911                 vm_helper_init(dc->vm_helper, 16);
1912
1913         /*************************************************
1914          *  Create resources                             *
1915          *************************************************/
1916
1917         /* Clock Sources for Pixel Clock*/
1918         pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =
1919                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1920                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1921                                 &clk_src_regs[0], false);
1922         pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =
1923                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1924                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1925                                 &clk_src_regs[1], false);
1926         pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =
1927                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1928                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1929                                 &clk_src_regs[2], false);
1930         pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =
1931                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1932                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1933                                 &clk_src_regs[3], false);
1934         pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =
1935                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1936                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1937                                 &clk_src_regs[4], false);
1938
1939         pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;
1940
1941         /* todo: not reuse phy_pll registers */
1942         pool->base.dp_clock_source =
1943                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1944                                 CLOCK_SOURCE_ID_DP_DTO,
1945                                 &clk_src_regs[0], true);
1946
1947         for (i = 0; i < pool->base.clk_src_count; i++) {
1948                 if (pool->base.clock_sources[i] == NULL) {
1949                         dm_error("DC: failed to create clock sources!\n");
1950                         BREAK_TO_DEBUGGER();
1951                         goto create_fail;
1952                 }
1953         }
1954         /*temp till dml2 fully work without dml1*/
1955         dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1956
1957         /* TODO: DCCG */
1958         pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1959         if (pool->base.dccg == NULL) {
1960                 dm_error("DC: failed to create dccg!\n");
1961                 BREAK_TO_DEBUGGER();
1962                 goto create_fail;
1963         }
1964
1965 #undef REG_STRUCT
1966 #define REG_STRUCT pg_cntl_regs
1967         pg_cntl_dcn35_regs_init();
1968
1969         pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1970         if (pool->base.pg_cntl == NULL) {
1971                 dm_error("DC: failed to create power gate control!\n");
1972                 BREAK_TO_DEBUGGER();
1973                 goto create_fail;
1974         }
1975
1976         /* TODO: IRQ */
1977         init_data.ctx = dc->ctx;
1978         pool->base.irqs = dal_irq_service_dcn35_create(&init_data);
1979         if (!pool->base.irqs)
1980                 goto create_fail;
1981
1982         /* HUBBUB */
1983         pool->base.hubbub = dcn35_hubbub_create(ctx);
1984         if (pool->base.hubbub == NULL) {
1985                 BREAK_TO_DEBUGGER();
1986                 dm_error("DC: failed to create hubbub!\n");
1987                 goto create_fail;
1988         }
1989
1990         /* HUBPs, DPPs, OPPs and TGs */
1991         for (i = 0; i < pool->base.pipe_count; i++) {
1992                 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
1993                 if (pool->base.hubps[i] == NULL) {
1994                         BREAK_TO_DEBUGGER();
1995                         dm_error(
1996                                 "DC: failed to create hubps!\n");
1997                         goto create_fail;
1998                 }
1999
2000                 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2001                 if (pool->base.dpps[i] == NULL) {
2002                         BREAK_TO_DEBUGGER();
2003                         dm_error(
2004                                 "DC: failed to create dpps!\n");
2005                         goto create_fail;
2006                 }
2007         }
2008
2009         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2010                 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2011                 if (pool->base.opps[i] == NULL) {
2012                         BREAK_TO_DEBUGGER();
2013                         dm_error(
2014                                 "DC: failed to create output pixel processor!\n");
2015                         goto create_fail;
2016                 }
2017         }
2018
2019         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2020                 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2021                                 ctx, i);
2022                 if (pool->base.timing_generators[i] == NULL) {
2023                         BREAK_TO_DEBUGGER();
2024                         dm_error("DC: failed to create tg!\n");
2025                         goto create_fail;
2026                 }
2027         }
2028         pool->base.timing_generator_count = i;
2029
2030         /* PSR */
2031         pool->base.psr = dmub_psr_create(ctx);
2032         if (pool->base.psr == NULL) {
2033                 dm_error("DC: failed to create psr obj!\n");
2034                 BREAK_TO_DEBUGGER();
2035                 goto create_fail;
2036         }
2037
2038         /* Replay */
2039         pool->base.replay = dmub_replay_create(ctx);
2040         if (pool->base.replay == NULL) {
2041                 dm_error("DC: failed to create replay obj!\n");
2042                 BREAK_TO_DEBUGGER();
2043                 goto create_fail;
2044         }
2045
2046         /* ABM */
2047         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2048                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2049                                 &abm_regs[i],
2050                                 &abm_shift,
2051                                 &abm_mask);
2052                 if (pool->base.multiple_abms[i] == NULL) {
2053                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2054                         BREAK_TO_DEBUGGER();
2055                         goto create_fail;
2056                 }
2057         }
2058
2059         /* MPC and DSC */
2060         pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2061         if (pool->base.mpc == NULL) {
2062                 BREAK_TO_DEBUGGER();
2063                 dm_error("DC: failed to create mpc!\n");
2064                 goto create_fail;
2065         }
2066
2067         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2068                 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2069                 if (pool->base.dscs[i] == NULL) {
2070                         BREAK_TO_DEBUGGER();
2071                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2072                         goto create_fail;
2073                 }
2074         }
2075
2076         /* DWB and MMHUBBUB */
2077         if (!dcn35_dwbc_create(ctx, &pool->base)) {
2078                 BREAK_TO_DEBUGGER();
2079                 dm_error("DC: failed to create dwbc!\n");
2080                 goto create_fail;
2081         }
2082
2083         if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2084                 BREAK_TO_DEBUGGER();
2085                 dm_error("DC: failed to create mcif_wb!\n");
2086                 goto create_fail;
2087         }
2088
2089         /* AUX and I2C */
2090         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2091                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2092                 if (pool->base.engines[i] == NULL) {
2093                         BREAK_TO_DEBUGGER();
2094                         dm_error(
2095                                 "DC:failed to create aux engine!!\n");
2096                         goto create_fail;
2097                 }
2098                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2099                 if (pool->base.hw_i2cs[i] == NULL) {
2100                         BREAK_TO_DEBUGGER();
2101                         dm_error(
2102                                 "DC:failed to create hw i2c!!\n");
2103                         goto create_fail;
2104                 }
2105                 pool->base.sw_i2cs[i] = NULL;
2106         }
2107
2108         /* DCN3.5 has 6 DPIA */
2109         pool->base.usb4_dpia_count = 4;
2110         if (dc->debug.dpia_debug.bits.disable_dpia)
2111                 pool->base.usb4_dpia_count = 0;
2112
2113         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2114         if (!resource_construct(num_virtual_links, dc, &pool->base,
2115                         &res_create_funcs))
2116                 goto create_fail;
2117
2118         /* HW Sequencer and Plane caps */
2119         dcn35_hw_sequencer_construct(dc);
2120
2121         dc->caps.max_planes =  pool->base.pipe_count;
2122
2123         for (i = 0; i < dc->caps.max_planes; ++i)
2124                 dc->caps.planes[i] = plane_cap;
2125
2126         dc->cap_funcs = cap_funcs;
2127
2128         dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2129
2130         dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2131         dc->dml2_options.use_native_pstate_optimization = true;
2132         dc->dml2_options.use_native_soc_bb_construction = true;
2133         dc->dml2_options.minimize_dispclk_using_odm = false;
2134         if (dc->config.EnableMinDispClkODM)
2135                 dc->dml2_options.minimize_dispclk_using_odm = true;
2136         dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2137
2138         dc->dml2_options.callbacks.dc = dc;
2139         dc->dml2_options.callbacks.build_scaling_params = &resource_build_scaling_params;
2140         dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2141         dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
2142         dc->dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count;
2143         dc->dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count;
2144         dc->dml2_options.callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index;
2145         dc->dml2_options.callbacks.get_odm_slice_index = &resource_get_odm_slice_index;
2146         dc->dml2_options.callbacks.get_opp_head = &resource_get_opp_head;
2147         dc->dml2_options.max_segments_per_hubp = 24;
2148
2149         dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2150
2151         if (dc->config.sdpif_request_limit_words_per_umc == 0)
2152                 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2153
2154         return true;
2155
2156 create_fail:
2157
2158         dcn35_resource_destruct(pool);
2159
2160         return false;
2161 }
2162
2163 struct resource_pool *dcn35_create_resource_pool(
2164                 const struct dc_init_data *init_data,
2165                 struct dc *dc)
2166 {
2167         struct dcn35_resource_pool *pool =
2168                 kzalloc(sizeof(struct dcn35_resource_pool), GFP_KERNEL);
2169
2170         if (!pool)
2171                 return NULL;
2172
2173         if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))
2174                 return &pool->base;
2175
2176         BREAK_TO_DEBUGGER();
2177         kfree(pool);
2178         return NULL;
2179 }