drivers/gpu/drm/amd/display/dc/link/link_ddc.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* FILE POLICY AND INTENDED USAGE:
  27  *
  28  * This file implements generic display communication protocols such as i2c, aux
  29  * and scdc. The file should not contain any specific applications of these
  30  * protocols such as display capability query, detection, or handshaking such as
  31  * link training.
  32  */
  33 #include "link_ddc.h"
  34 #include "vector.h"
  35 #include "dce/dce_aux.h"
  36 #include "dal_asic_id.h"
  37 #include "link_dpcd.h"
  38 #include "dm_helpers.h"
  39 #include "atomfirmware.h"
  40
  41 #define DC_LOGGER_INIT(logger)
  42
  43 static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";
  44 /* DP to Dual link DVI converter */
  45 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
  46 static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
  47
  48 struct i2c_payloads {
  49         struct vector payloads;
  50 };
  51
  52 struct aux_payloads {
  53         struct vector payloads;
  54 };
  55
  56 static bool dal_ddc_i2c_payloads_create(
  57                 struct dc_context *ctx,
  58                 struct i2c_payloads *payloads,
  59                 uint32_t count)
  60 {
  61         if (dal_vector_construct(
  62                 &payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
  63                 return true;
  64
  65         return false;
  66 }
  67
  68 static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
  69 {
  70         return (struct i2c_payload *)p->payloads.container;
  71 }
  72
  73 static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
  74 {
  75         return p->payloads.count;
  76 }
  77
  78 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
  79
  80 static void i2c_payloads_add(
  81         struct i2c_payloads *payloads,
  82         uint32_t address,
  83         uint32_t len,
  84         uint8_t *data,
  85         bool write)
  86 {
  87         uint32_t payload_size = EDID_SEGMENT_SIZE;
  88         uint32_t pos;
  89
  90         for (pos = 0; pos < len; pos += payload_size) {
  91                 struct i2c_payload payload = {
  92                         .write = write,
  93                         .address = address,
  94                         .length = DDC_MIN(payload_size, len - pos),
  95                         .data = data + pos };
  96                 dal_vector_append(&payloads->payloads, &payload);
  97         }
  98
  99 }
 100
 101 static void ddc_service_construct(
 102         struct ddc_service *ddc_service,
 103         struct ddc_service_init_data *init_data)
 104 {
 105         enum connector_id connector_id =
 106                 dal_graphics_object_id_get_connector_id(init_data->id);
 107
 108         struct gpio_service *gpio_service = init_data->ctx->gpio_service;
 109         struct graphics_object_i2c_info i2c_info;
 110         struct gpio_ddc_hw_info hw_info;
 111         struct dc_bios *dcb = init_data->ctx->dc_bios;
 112
 113         ddc_service->link = init_data->link;
 114         ddc_service->ctx = init_data->ctx;
 115
 116         if (init_data->is_dpia_link ||
 117             dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {
 118                 ddc_service->ddc_pin = NULL;
 119         } else {
 120                 DC_LOGGER_INIT(ddc_service->ctx->logger);
 121                 DC_LOG_DC("BIOS object table - i2c_line: %d", i2c_info.i2c_line);
 122                 DC_LOG_DC("BIOS object table - i2c_engine_id: %d", i2c_info.i2c_engine_id);
 123
 124                 hw_info.ddc_channel = i2c_info.i2c_line;
 125                 if (ddc_service->link != NULL)
 126                         hw_info.hw_supported = i2c_info.i2c_hw_assist;
 127                 else
 128                         hw_info.hw_supported = false;
 129
 130                 ddc_service->ddc_pin = dal_gpio_create_ddc(
 131                         gpio_service,
 132                         i2c_info.gpio_info.clk_a_register_index,
 133                         1 << i2c_info.gpio_info.clk_a_shift,
 134                         &hw_info);
 135         }
 136
 137         ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
 138         ddc_service->flags.FORCE_READ_REPEATED_START = false;
 139         ddc_service->flags.EDID_STRESS_READ = false;
 140
 141         ddc_service->flags.IS_INTERNAL_DISPLAY =
 142                 connector_id == CONNECTOR_ID_EDP ||
 143                 connector_id == CONNECTOR_ID_LVDS;
 144
 145         ddc_service->wa.raw = 0;
 146 }
 147
 148 struct ddc_service *link_create_ddc_service(
 149         struct ddc_service_init_data *init_data)
 150 {
 151         struct ddc_service *ddc_service;
 152
 153         ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
 154
 155         if (!ddc_service)
 156                 return NULL;
 157
 158         ddc_service_construct(ddc_service, init_data);
 159         return ddc_service;
 160 }
 161
 162 static void ddc_service_destruct(struct ddc_service *ddc)
 163 {
 164         if (ddc->ddc_pin)
 165                 dal_gpio_destroy_ddc(&ddc->ddc_pin);
 166 }
 167
 168 void link_destroy_ddc_service(struct ddc_service **ddc)
 169 {
 170         if (!ddc || !*ddc) {
 171                 BREAK_TO_DEBUGGER();
 172                 return;
 173         }
 174         ddc_service_destruct(*ddc);
 175         kfree(*ddc);
 176         *ddc = NULL;
 177 }
 178
 179 void set_ddc_transaction_type(
 180         struct ddc_service *ddc,
 181         enum ddc_transaction_type type)
 182 {
 183         ddc->transaction_type = type;
 184 }
 185
 186 bool link_is_in_aux_transaction_mode(struct ddc_service *ddc)
 187 {
 188         switch (ddc->transaction_type) {
 189         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
 190         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
 191         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
 192                 return true;
 193         default:
 194                 break;
 195         }
 196         return false;
 197 }
 198
 199 void set_dongle_type(struct ddc_service *ddc,
 200                 enum display_dongle_type dongle_type)
 201 {
 202         ddc->dongle_type = dongle_type;
 203 }
 204
 205 static uint32_t defer_delay_converter_wa(
 206         struct ddc_service *ddc,
 207         uint32_t defer_delay)
 208 {
 209         struct dc_link *link = ddc->link;
 210
 211         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
 212                 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
 213                 (link->dpcd_caps.branch_fw_revision[0] < 0x01 ||
 214                                 (link->dpcd_caps.branch_fw_revision[0] == 0x01 &&
 215                                 link->dpcd_caps.branch_fw_revision[1] < 0x40)) &&
 216                 !memcmp(link->dpcd_caps.branch_dev_name,
 217                     DP_VGA_DONGLE_BRANCH_DEV_NAME,
 218                         sizeof(link->dpcd_caps.branch_dev_name)))
 219
 220                 return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?
 221                         defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;
 222
 223         if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
 224             !memcmp(link->dpcd_caps.branch_dev_name,
 225                     DP_DVI_CONVERTER_ID_4,
 226                     sizeof(link->dpcd_caps.branch_dev_name)))
 227                 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
 228                         defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
 229         if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&
 230             !memcmp(link->dpcd_caps.branch_dev_name,
 231                     DP_DVI_CONVERTER_ID_5,
 232                     sizeof(link->dpcd_caps.branch_dev_name)))
 233                 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?
 234                         I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;
 235
 236         return defer_delay;
 237 }
 238
 239 #define DP_TRANSLATOR_DELAY 5
 240
 241 uint32_t link_get_aux_defer_delay(struct ddc_service *ddc)
 242 {
 243         uint32_t defer_delay = 0;
 244
 245         switch (ddc->transaction_type) {
 246         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
 247                 if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
 248                         (DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
 249                         (DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
 250                                 ddc->dongle_type)) {
 251
 252                         defer_delay = DP_TRANSLATOR_DELAY;
 253
 254                         defer_delay =
 255                                 defer_delay_converter_wa(ddc, defer_delay);
 256
 257                 } else /*sink has a delay different from an Active Converter*/
 258                         defer_delay = 0;
 259                 break;
 260         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
 261                 defer_delay = DP_TRANSLATOR_DELAY;
 262                 break;
 263         default:
 264                 break;
 265         }
 266         return defer_delay;
 267 }
 268
 269 static bool submit_aux_command(struct ddc_service *ddc,
 270                 struct aux_payload *payload)
 271 {
 272         uint32_t retrieved = 0;
 273         bool ret = false;
 274
 275         if (!ddc)
 276                 return false;
 277
 278         if (!payload)
 279                 return false;
 280
 281         do {
 282                 struct aux_payload current_payload;
 283                 bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=
 284                                 payload->length;
 285                 uint32_t payload_length = is_end_of_payload ?
 286                                 payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
 287
 288                 current_payload.address = payload->address;
 289                 current_payload.data = &payload->data[retrieved];
 290                 current_payload.defer_delay = payload->defer_delay;
 291                 current_payload.i2c_over_aux = payload->i2c_over_aux;
 292                 current_payload.length = payload_length;
 293                 /* set mot (middle of transaction) to false if it is the last payload */
 294                 current_payload.mot = is_end_of_payload ? payload->mot:true;
 295                 current_payload.write_status_update = false;
 296                 current_payload.reply = payload->reply;
 297                 current_payload.write = payload->write;
 298
 299                 ret = link_aux_transfer_with_retries_no_mutex(ddc, &current_payload);
 300
 301                 retrieved += payload_length;
 302         } while (retrieved < payload->length && ret == true);
 303
 304         return ret;
 305 }
 306
 307 bool link_query_ddc_data(
 308         struct ddc_service *ddc,
 309         uint32_t address,
 310         uint8_t *write_buf,
 311         uint32_t write_size,
 312         uint8_t *read_buf,
 313         uint32_t read_size)
 314 {
 315         bool success = true;
 316         uint32_t payload_size =
 317                 link_is_in_aux_transaction_mode(ddc) ?
 318                         DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
 319
 320         uint32_t write_payloads =
 321                 (write_size + payload_size - 1) / payload_size;
 322
 323         uint32_t read_payloads =
 324                 (read_size + payload_size - 1) / payload_size;
 325
 326         uint32_t payloads_num = write_payloads + read_payloads;
 327
 328         if (!payloads_num)
 329                 return false;
 330
 331         if (link_is_in_aux_transaction_mode(ddc)) {
 332                 struct aux_payload payload;
 333
 334                 payload.i2c_over_aux = true;
 335                 payload.address = address;
 336                 payload.reply = NULL;
 337                 payload.defer_delay = link_get_aux_defer_delay(ddc);
 338                 payload.write_status_update = false;
 339
 340                 if (write_size != 0) {
 341                         payload.write = true;
 342                         /* should not set mot (middle of transaction) to 0
 343                          * if there are pending read payloads
 344                          */
 345                         payload.mot = !(read_size == 0);
 346                         payload.length = write_size;
 347                         payload.data = write_buf;
 348
 349                         success = submit_aux_command(ddc, &payload);
 350                 }
 351
 352                 if (read_size != 0 && success) {
 353                         payload.write = false;
 354                         /* should set mot (middle of transaction) to 0
 355                          * since it is the last payload to send
 356                          */
 357                         payload.mot = false;
 358                         payload.length = read_size;
 359                         payload.data = read_buf;
 360
 361                         success = submit_aux_command(ddc, &payload);
 362                 }
 363         } else {
 364                 struct i2c_command command = {0};
 365                 struct i2c_payloads payloads;
 366
 367                 if (!dal_ddc_i2c_payloads_create(ddc->ctx, &payloads, payloads_num))
 368                         return false;
 369
 370                 command.payloads = dal_ddc_i2c_payloads_get(&payloads);
 371                 command.number_of_payloads = 0;
 372                 command.engine = DDC_I2C_COMMAND_ENGINE;
 373                 command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
 374
 375                 i2c_payloads_add(
 376                         &payloads, address, write_size, write_buf, true);
 377
 378                 i2c_payloads_add(
 379                         &payloads, address, read_size, read_buf, false);
 380
 381                 command.number_of_payloads =
 382                         dal_ddc_i2c_payloads_get_count(&payloads);
 383
 384                 success = dm_helpers_submit_i2c(
 385                                 ddc->ctx,
 386                                 ddc->link,
 387                                 &command);
 388
 389                 dal_vector_destruct(&payloads.payloads);
 390         }
 391
 392         return success;
 393 }
 394
 395 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
 396                 struct aux_payload *payload,
 397                 enum aux_return_code_type *operation_result)
 398 {
 399         if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
 400             !ddc->ddc_pin) {
 401                 return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
 402         } else {
 403                 return dce_aux_transfer_raw(ddc, payload, operation_result);
 404         }
 405 }
 406
 407 bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,
 408                 struct aux_payload *payload)
 409 {
 410         return dce_aux_transfer_with_retries(ddc, payload);
 411 }
 412
 413
 414 bool try_to_configure_aux_timeout(struct ddc_service *ddc,
 415                 uint32_t timeout)
 416 {
 417         bool result = false;
 418         struct ddc *ddc_pin = ddc->ddc_pin;
 419
 420         if ((ddc->link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
 421                         !ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&
 422                         ASICREV_IS_YELLOW_CARP(ddc->ctx->asic_id.hw_internal_rev)) {
 423                 /* Fixed VS workaround for AUX timeout */
 424                 const uint32_t fixed_vs_address = 0xF004F;
 425                 const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};
 426
 427                 core_link_write_dpcd(ddc->link,
 428                                 fixed_vs_address,
 429                                 fixed_vs_data,
 430                                 sizeof(fixed_vs_data));
 431
 432                 timeout = 3072;
 433         }
 434
 435         /* Do not try to access nonexistent DDC pin. */
 436         if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
 437                 return true;
 438
 439         if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {
 440                 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
 441                 result = true;
 442         }
 443
 444         return result;
 445 }
 446
 447 struct ddc *get_ddc_pin(struct ddc_service *ddc_service)
 448 {
 449         return ddc_service->ddc_pin;
 450 }
 451
 452 void write_scdc_data(struct ddc_service *ddc_service,
 453                 uint32_t pix_clk,
 454                 bool lte_340_scramble)
 455 {
 456         bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
 457         uint8_t slave_address = HDMI_SCDC_ADDRESS;
 458         uint8_t offset = HDMI_SCDC_SINK_VERSION;
 459         uint8_t sink_version = 0;
 460         uint8_t write_buffer[2] = {0};
 461         /*Lower than 340 Scramble bit from SCDC caps*/
 462
 463         if (ddc_service->link->local_sink &&
 464                 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
 465                 return;
 466
 467         link_query_ddc_data(ddc_service, slave_address, &offset,
 468                         sizeof(offset), &sink_version, sizeof(sink_version));
 469         if (sink_version == 1) {
 470                 /*Source Version = 1*/
 471                 write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
 472                 write_buffer[1] = 1;
 473                 link_query_ddc_data(ddc_service, slave_address,
 474                                 write_buffer, sizeof(write_buffer), NULL, 0);
 475                 /*Read Request from SCDC caps*/
 476         }
 477         write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
 478
 479         if (over_340_mhz) {
 480                 write_buffer[1] = 3;
 481         } else if (lte_340_scramble) {
 482                 write_buffer[1] = 1;
 483         } else {
 484                 write_buffer[1] = 0;
 485         }
 486         link_query_ddc_data(ddc_service, slave_address, write_buffer,
 487                         sizeof(write_buffer), NULL, 0);
 488 }
 489
 490 void read_scdc_data(struct ddc_service *ddc_service)
 491 {
 492         uint8_t slave_address = HDMI_SCDC_ADDRESS;
 493         uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
 494         uint8_t tmds_config = 0;
 495
 496         if (ddc_service->link->local_sink &&
 497                 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
 498                 return;
 499
 500         link_query_ddc_data(ddc_service, slave_address, &offset,
 501                         sizeof(offset), &tmds_config, sizeof(tmds_config));
 502         if (tmds_config & 0x1) {
 503                 union hdmi_scdc_status_flags_data status_data = {0};
 504                 uint8_t scramble_status = 0;
 505
 506                 offset = HDMI_SCDC_SCRAMBLER_STATUS;
 507                 link_query_ddc_data(ddc_service, slave_address,
 508                                 &offset, sizeof(offset), &scramble_status,
 509                                 sizeof(scramble_status));
 510                 offset = HDMI_SCDC_STATUS_FLAGS;
 511                 link_query_ddc_data(ddc_service, slave_address,
 512                                 &offset, sizeof(offset), &status_data.byte,
 513                                 sizeof(status_data.byte));
 514         }
 515 }