2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef _CORE_TYPES_H_
27 #define _CORE_TYPES_H_
30 #include "dce_calcs.h"
31 #include "dcn_calcs.h"
32 #include "ddc_service_types.h"
33 #include "dc_bios_types.h"
34 #include "mem_input.h"
39 #include "panel_cntl.h"
41 #define MAX_CLOCK_SOURCES 7
43 void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
44 uint32_t controller_id);
46 #include "grph_object_id.h"
47 #include "link_encoder.h"
48 #include "stream_encoder.h"
49 #include "clock_source.h"
51 #include "dm_pp_smu.h"
52 #ifdef CONFIG_DRM_AMD_DC_HDCP
53 #include "dm_cp_psp.h"
55 #include "link_hwss.h"
57 /************ link *****************/
58 struct link_init_data {
60 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
61 uint32_t connector_index; /* this will be mapped to the HPD pins */
62 uint32_t link_index; /* this is mapped to DAL display_index
63 TODO: remove it when DC is complete. */
67 struct dc_link *link_create(const struct link_init_data *init_params);
68 void link_destroy(struct dc_link **link);
70 enum dc_status dc_link_validate_mode_timing(
71 const struct dc_stream_state *stream,
73 const struct dc_crtc_timing *timing);
75 void core_link_resume(struct dc_link *link);
77 void core_link_enable_stream(
78 struct dc_state *state,
79 struct pipe_ctx *pipe_ctx);
81 void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
83 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
84 /********** DAL Core*********************/
85 #include "transform.h"
90 struct resource_context;
93 struct resource_funcs {
94 void (*destroy)(struct resource_pool **pool);
95 void (*link_init)(struct dc_link *link);
96 struct panel_cntl*(*panel_cntl_create)(
97 const struct panel_cntl_init_data *panel_cntl_init_data);
98 struct link_encoder *(*link_enc_create)(
99 struct dc_context *ctx,
100 const struct encoder_init_data *init);
101 /* Create a minimal link encoder object with no dc_link object
102 * associated with it. */
103 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id);
105 bool (*validate_bandwidth)(
107 struct dc_state *context,
109 void (*calculate_wm_and_dlg)(
110 struct dc *dc, struct dc_state *context,
111 display_e2e_pipe_params_st *pipes,
114 void (*update_soc_for_wm_a)(
115 struct dc *dc, struct dc_state *context);
116 int (*populate_dml_pipes)(
118 struct dc_state *context,
119 display_e2e_pipe_params_st *pipes,
123 * Algorithm for assigning available link encoders to links.
125 * Update link_enc_assignments table and link_enc_avail list accordingly in
126 * struct resource_context.
128 void (*link_encs_assign)(
130 struct dc_state *state,
131 struct dc_stream_state *streams[],
132 uint8_t stream_count);
134 * Unassign a link encoder from a stream.
136 * Update link_enc_assignments table and link_enc_avail list accordingly in
137 * struct resource_context.
139 void (*link_enc_unassign)(
140 struct dc_state *state,
141 struct dc_stream_state *stream);
143 enum dc_status (*validate_global)(
145 struct dc_state *context);
148 * Acquires a free pipe for the head pipe.
149 * The head pipe is first pipe in the current context that matches the stream
150 * and does not have a top pipe or prev_odm_pipe.
152 struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
153 struct dc_state *context,
154 const struct resource_pool *pool,
155 struct dc_stream_state *stream);
158 * Acquires a free pipe for the head pipe with some additional checks for odm.
159 * The head pipe is passed in as an argument unlike acquire_idle_pipe_for_layer
160 * where it is read from the context. So this allows us look for different
161 * idle_pipe if the head_pipes are different ( ex. in odm 2:1 when we have
162 * a left and right pipe ).
164 * It also checks the old context to see if:
166 * 1. a pipe has already been allocated for the head pipe. If so, it will
167 * try to select that pipe as the idle pipe if it is available in the current
169 * 2. if the head_pipe is on the left, it will check if the right pipe has
170 * a pipe already allocated. If so, it will not use that pipe if it is
171 * selected as the idle pipe.
173 struct pipe_ctx *(*acquire_idle_pipe_for_head_pipe_in_layer)(
174 struct dc_state *context,
175 const struct resource_pool *pool,
176 struct dc_stream_state *stream,
177 struct pipe_ctx *head_pipe);
179 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
181 enum dc_status (*add_stream_to_ctx)(
183 struct dc_state *new_ctx,
184 struct dc_stream_state *dc_stream);
186 enum dc_status (*remove_stream_from_ctx)(
188 struct dc_state *new_ctx,
189 struct dc_stream_state *stream);
190 enum dc_status (*patch_unknown_plane_state)(
191 struct dc_plane_state *plane_state);
193 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)(
194 struct resource_context *res_ctx,
195 const struct resource_pool *pool,
196 struct dc_stream_state *stream);
197 void (*populate_dml_writeback_from_context)(
199 struct resource_context *res_ctx,
200 display_e2e_pipe_params_st *pipes);
202 void (*set_mcif_arb_params)(
204 struct dc_state *context,
205 display_e2e_pipe_params_st *pipes,
207 void (*update_bw_bounding_box)(
209 struct clk_bw_params *bw_params);
210 bool (*acquire_post_bldn_3dlut)(
211 struct resource_context *res_ctx,
212 const struct resource_pool *pool,
214 struct dc_3dlut **lut,
215 struct dc_transfer_func **shaper);
217 bool (*release_post_bldn_3dlut)(
218 struct resource_context *res_ctx,
219 const struct resource_pool *pool,
220 struct dc_3dlut **lut,
221 struct dc_transfer_func **shaper);
223 enum dc_status (*add_dsc_to_stream_resource)(
224 struct dc *dc, struct dc_state *state,
225 struct dc_stream_state *stream);
227 void (*add_phantom_pipes)(
229 struct dc_state *context,
230 display_e2e_pipe_params_st *pipes,
231 unsigned int pipe_cnt,
234 bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context);
237 struct audio_support{
239 bool hdmi_audio_on_dongle;
240 bool hdmi_audio_native;
243 #define NO_UNDERLAY_PIPE -1
245 struct resource_pool {
246 struct mem_input *mis[MAX_PIPES];
247 struct hubp *hubps[MAX_PIPES];
248 struct input_pixel_processor *ipps[MAX_PIPES];
249 struct transform *transforms[MAX_PIPES];
250 struct dpp *dpps[MAX_PIPES];
251 struct output_pixel_processor *opps[MAX_PIPES];
252 struct timing_generator *timing_generators[MAX_PIPES];
253 struct stream_encoder *stream_enc[MAX_PIPES * 2];
254 struct hubbub *hubbub;
256 struct pp_smu_funcs *pp_smu;
257 struct dce_aux *engines[MAX_PIPES];
258 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
259 struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
260 bool i2c_hw_buffer_in_use;
262 struct dwbc *dwbc[MAX_DWB_PIPES];
263 struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
265 unsigned int gsl_0:1;
266 unsigned int gsl_1:1;
267 unsigned int gsl_2:1;
270 struct display_stream_compressor *dscs[MAX_PIPES];
272 unsigned int pipe_count;
273 unsigned int underlay_pipe_index;
274 unsigned int stream_enc_count;
276 /* An array for accessing the link encoder objects that have been created.
277 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA
279 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS];
280 /* Number of DIG link encoder objects created - i.e. number of valid
281 * entries in link_encoders array.
283 unsigned int dig_link_enc_count;
284 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/
285 unsigned int usb4_dpia_count;
287 unsigned int hpo_dp_stream_enc_count;
288 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
289 unsigned int hpo_dp_link_enc_count;
290 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
291 struct dc_3dlut *mpc_lut[MAX_PIPES];
292 struct dc_transfer_func *mpc_shaper[MAX_PIPES];
295 unsigned int xtalin_clock_inKhz;
296 unsigned int dccg_ref_clock_inKhz;
297 unsigned int dchub_ref_clock_inKhz;
299 unsigned int timing_generator_count;
300 unsigned int mpcc_count;
302 unsigned int writeback_pipe_count;
304 * reserved clock source for DP
306 struct clock_source *dp_clock_source;
308 struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
309 unsigned int clk_src_count;
311 struct audio *audios[MAX_AUDIOS];
312 unsigned int audio_count;
313 struct audio_support audio_support;
316 struct irq_service *irqs;
320 struct dmub_psr *psr;
322 struct abm *multiple_abms[MAX_PIPES];
324 const struct resource_funcs *funcs;
325 const struct resource_caps *res_cap;
327 struct ddc_service *oem_device;
330 struct dcn_fe_bandwidth {
335 struct stream_resource {
336 struct output_pixel_processor *opp;
337 struct display_stream_compressor *dsc;
338 struct timing_generator *tg;
339 struct stream_encoder *stream_enc;
340 struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
343 struct pixel_clk_params pix_clk_params;
344 struct encoder_info_frame encoder_info_frame;
347 /* There are only (num_pipes+1)/2 groups. 0 means unassigned,
348 * otherwise it's using group number 'gsl_group-1'
353 struct plane_resource {
354 struct scaler_data scl_data;
356 struct mem_input *mi;
357 struct input_pixel_processor *ipp;
358 struct transform *xfm;
362 struct dcn_fe_bandwidth bw;
365 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF
366 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0
368 /* all mappable hardware resources used to enable a link */
369 struct link_resource {
370 struct hpo_dp_link_encoder *hpo_dp_link_enc;
374 struct dc_link_settings dp_link_settings;
376 union pipe_update_flags {
379 uint32_t disable : 1;
381 uint32_t global_sync : 1;
382 uint32_t opp_changed : 1;
383 uint32_t tg_changed : 1;
386 uint32_t hubp_interdependent : 1;
387 uint32_t hubp_rq_dlg_ttu : 1;
388 uint32_t gamut_remap : 1;
390 uint32_t viewport : 1;
391 uint32_t plane_changed : 1;
392 uint32_t det_size : 1;
398 struct dc_plane_state *plane_state;
399 struct dc_stream_state *stream;
401 struct plane_resource plane_res;
404 * @stream_res: Reference to DCN resource components such OPP and DSC.
406 struct stream_resource stream_res;
407 struct link_resource link_res;
409 struct clock_source *clock_source;
411 struct pll_settings pll_settings;
413 /* link config records software decision for what link config should be
414 * enabled given current link capability and stream during hw resource
415 * mapping. This is to decouple the dependency on link capability during
416 * dc commit or update.
418 struct link_config link_config;
421 uint8_t pipe_idx_syncd;
423 struct pipe_ctx *top_pipe;
424 struct pipe_ctx *bottom_pipe;
425 struct pipe_ctx *next_odm_pipe;
426 struct pipe_ctx *prev_odm_pipe;
428 struct _vcs_dpi_display_dlg_regs_st dlg_regs;
429 struct _vcs_dpi_display_ttu_regs_st ttu_regs;
430 struct _vcs_dpi_display_rq_regs_st rq_regs;
431 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
432 struct _vcs_dpi_display_rq_params_st dml_rq_param;
433 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param;
434 struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
435 int det_buffer_size_kb;
438 union pipe_update_flags update_flags;
440 struct mcif_wb *mcif_wb;
444 /* Data used for dynamic link encoder assignment.
445 * Tracks current and future assignments; available link encoders;
446 * and mode of operation (whether to use current or future assignments).
448 struct link_enc_cfg_context {
449 enum link_enc_cfg_mode mode;
450 struct link_enc_assignment link_enc_assignments[MAX_PIPES];
451 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];
452 struct link_enc_assignment transient_assignments[MAX_PIPES];
455 struct resource_context {
456 struct pipe_ctx pipe_ctx[MAX_PIPES];
457 bool is_stream_enc_acquired[MAX_PIPES * 2];
458 bool is_audio_acquired[MAX_PIPES];
459 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
460 uint8_t dp_clock_source_ref_count;
461 bool is_dsc_acquired[MAX_PIPES];
462 struct link_enc_cfg_context link_enc_cfg_ctx;
463 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
464 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
465 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
466 bool is_mpc_3dlut_acquired[MAX_PIPES];
469 struct dce_bw_output {
470 bool cpuc_state_change_enable;
471 bool cpup_state_change_enable;
472 bool stutter_mode_enable;
473 bool nbp_state_change_enable;
474 bool all_displays_in_sync;
475 struct dce_watermarks urgent_wm_ns[MAX_PIPES];
476 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
477 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
478 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
480 int sclk_deep_sleep_khz;
483 int blackout_recovery_time_us;
486 struct dcn_bw_writeback {
487 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
490 struct dcn_bw_output {
491 struct dc_clocks clk;
492 struct dcn_watermark_set watermarks;
493 struct dcn_bw_writeback bw_writeback;
498 struct dcn_bw_output dcn;
499 struct dce_bw_output dce;
504 struct display_mode_lib dml;
507 * struct dc_state - The full description of a state requested by a user
509 * @streams: Stream properties
510 * @stream_status: The planes on a given stream
511 * @res_ctx: Persistent state of resources
512 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
513 * @pp_display_cfg: PowerPlay clocks and settings
514 * @dcn_bw_vars: non-stack memory to support bandwidth calculations
518 struct dc_stream_state *streams[MAX_PIPES];
519 struct dc_stream_status stream_status[MAX_PIPES];
520 uint8_t stream_count;
523 struct resource_context res_ctx;
525 struct bw_context bw_ctx;
527 /* Note: these are big structures, do *not* put on stack! */
528 struct dm_pp_display_configuration pp_display_cfg;
529 struct dcn_bw_internal_vars dcn_bw_vars;
531 struct clk_mgr *clk_mgr;
533 struct kref refcount;
536 unsigned int stutter_period_us;
540 struct dc_bounding_box_max_clk {
547 #endif /* _CORE_TYPES_H_ */