2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
32 #include "dce/dce_hwseq.h"
33 #include "dcn30/dcn30_cm_common.h"
34 #include "reg_helper.h"
38 #include "timing_generator.h"
43 #include "dc_dmub_srv.h"
44 #include "link_hwss.h"
45 #include "dpcd_defs.h"
46 #include "dcn32_hwseq.h"
49 #include "dcn20/dcn20_optc.h"
50 #include "dce/dmub_hw_lock_mgr.h"
51 #include "dcn32/dcn32_resource.h"
53 #include "../dcn20/dcn20_hwseq.h"
54 #include "dc_state_priv.h"
56 #define DC_LOGGER_INIT(logger)
67 #define FN(reg_name, field_name) \
68 hws->shifts->field_name, hws->masks->field_name
70 void dcn32_dsc_pg_control(
71 struct dce_hwseq *hws,
72 unsigned int dsc_inst,
75 uint32_t power_gate = power_on ? 0 : 1;
76 uint32_t pwr_status = power_on ? 0 : 2;
77 uint32_t org_ip_request_cntl = 0;
79 if (hws->ctx->dc->debug.disable_dsc_power_gate)
82 if (!hws->ctx->dc->debug.enable_double_buffered_dsc_pg_support)
85 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
86 if (org_ip_request_cntl == 0)
87 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
91 REG_UPDATE(DOMAIN16_PG_CONFIG,
92 DOMAIN_POWER_GATE, power_gate);
94 REG_WAIT(DOMAIN16_PG_STATUS,
95 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
99 REG_UPDATE(DOMAIN17_PG_CONFIG,
100 DOMAIN_POWER_GATE, power_gate);
102 REG_WAIT(DOMAIN17_PG_STATUS,
103 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
107 REG_UPDATE(DOMAIN18_PG_CONFIG,
108 DOMAIN_POWER_GATE, power_gate);
110 REG_WAIT(DOMAIN18_PG_STATUS,
111 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
115 REG_UPDATE(DOMAIN19_PG_CONFIG,
116 DOMAIN_POWER_GATE, power_gate);
118 REG_WAIT(DOMAIN19_PG_STATUS,
119 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
127 if (org_ip_request_cntl == 0)
128 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
132 void dcn32_enable_power_gating_plane(
133 struct dce_hwseq *hws,
136 bool force_on = true; /* disable power gating */
137 uint32_t org_ip_request_cntl = 0;
142 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
143 if (org_ip_request_cntl == 0)
144 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
147 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
148 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
149 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
150 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
153 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
154 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
155 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
156 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
158 if (org_ip_request_cntl == 0)
159 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
162 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
164 uint32_t power_gate = power_on ? 0 : 1;
165 uint32_t pwr_status = power_on ? 0 : 2;
167 if (hws->ctx->dc->debug.disable_hubp_power_gate)
170 if (REG(DOMAIN0_PG_CONFIG) == 0)
175 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
176 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
179 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
180 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
183 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
184 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
187 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
188 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
196 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
200 /* First, check no-memory-request case */
201 for (i = 0; i < dc->current_state->stream_count; i++) {
202 if ((dc->current_state->stream_status[i].plane_count) &&
203 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))
204 /* Fail eligibility on a visible stream */
208 if (i == dc->current_state->stream_count)
215 /* This function loops through every surface that needs to be cached in CAB for SS,
216 * and calculates the total number of ways required to store all surfaces (primary,
219 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
222 uint32_t num_ways = 0;
223 uint32_t mall_ss_size_bytes = 0;
225 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
226 // TODO add additional logic for PSR active stream exclusion optimization
227 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;
229 // Include cursor size for CAB allocation
230 for (i = 0; i < dc->res_pool->pipe_count; i++) {
231 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];
233 if (!pipe->stream || !pipe->plane_state)
236 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
239 // Convert number of cache lines required to number of ways
240 if (dc->debug.force_mall_ss_num_ways > 0) {
241 num_ways = dc->debug.force_mall_ss_num_ways;
243 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes);
249 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
251 union dmub_rb_cmd cmd;
255 bool mall_ss_unsupported = false;
256 struct dc_plane_state *plane = NULL;
258 if (!dc->ctx->dmub_srv)
261 for (i = 0; i < dc->current_state->stream_count; i++) {
262 /* MALL SS messaging is not supported with PSR at this time */
263 if (dc->current_state->streams[i] != NULL &&
264 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
269 if (dc->current_state) {
271 /* 1. Check no memory request case for CAB.
272 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
274 if (dcn32_check_no_memory_request_for_cab(dc)) {
275 /* Enable no-memory-requests case */
276 memset(&cmd, 0, sizeof(cmd));
277 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
278 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
279 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
281 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
286 /* 2. Check if all surfaces can fit in CAB.
287 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
288 * and configure HUBP's to fetch from MALL
290 ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
292 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
293 * or TMZ surface, don't try to enter MALL.
295 for (i = 0; i < dc->current_state->stream_count; i++) {
296 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
297 plane = dc->current_state->stream_status[i].plane_states[j];
299 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
300 plane->address.tmz_surface) {
301 mall_ss_unsupported = true;
305 if (mall_ss_unsupported)
308 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
309 memset(&cmd, 0, sizeof(cmd));
310 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
311 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
312 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
313 cmd.cab.cab_alloc_ways = (uint8_t)ways;
315 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
325 memset(&cmd, 0, sizeof(cmd));
326 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
327 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
328 cmd.cab.header.payload_bytes =
329 sizeof(cmd.cab) - sizeof(cmd.cab.header);
331 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
336 /* Send DMCUB message with SubVP pipe info
337 * - For each pipe in context, populate payload with required SubVP information
338 * if the pipe is using SubVP for MCLK switch
339 * - This function must be called while the DMUB HW lock is acquired by driver
341 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
344 bool enable_subvp = false;
346 if (!dc->ctx || !dc->ctx->dmub_srv)
349 for (i = 0; i < dc->res_pool->pipe_count; i++) {
350 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
352 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {
353 // There is at least 1 SubVP pipe, so enable SubVP
358 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
361 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
362 * 1. Any full update for any SubVP main pipe
363 * 2. Any immediate flip for any SubVP pipe
364 * 3. Any flip for DRR pipe
365 * 4. If SubVP was previously in use (i.e. in old context)
367 void dcn32_subvp_pipe_control_lock(struct dc *dc,
368 struct dc_state *context,
370 bool should_lock_all_pipes,
371 struct pipe_ctx *top_pipe_to_program,
375 bool subvp_immediate_flip = false;
376 bool subvp_in_use = false;
377 struct pipe_ctx *pipe;
378 enum mall_stream_type pipe_mall_type = SUBVP_NONE;
380 for (i = 0; i < dc->res_pool->pipe_count; i++) {
381 pipe = &context->res_ctx.pipe_ctx[i];
382 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
384 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {
390 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
391 if (dc_state_get_pipe_subvp_type(context, top_pipe_to_program) == SUBVP_MAIN &&
392 top_pipe_to_program->plane_state->flip_immediate)
393 subvp_immediate_flip = true;
396 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
397 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
398 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
401 for (i = 0; i < dc->res_pool->pipe_count; i++) {
402 pipe = &context->res_ctx.pipe_ctx[i];
403 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&
404 should_lock_all_pipes)
405 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
409 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
410 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
411 hw_lock_cmd.bits.lock = lock;
412 hw_lock_cmd.bits.should_release = !lock;
413 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
417 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)
419 struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;
420 bool lock = params->subvp_pipe_control_lock_fast_params.lock;
421 bool subvp_immediate_flip = params->subvp_pipe_control_lock_fast_params.subvp_immediate_flip;
423 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
424 if (subvp_immediate_flip) {
425 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
427 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
428 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
429 hw_lock_cmd.bits.lock = lock;
430 hw_lock_cmd.bits.should_release = !lock;
431 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
435 bool dcn32_set_mpc_shaper_3dlut(
436 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
438 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
439 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
440 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
443 const struct pwl_params *shaper_lut = NULL;
444 //get the shaper lut params
445 if (stream->func_shaper) {
446 if (stream->func_shaper->type == TF_TYPE_HWPWL)
447 shaper_lut = &stream->func_shaper->pwl;
448 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
449 cm_helper_translate_curve_to_hw_format(stream->ctx,
451 &dpp_base->shaper_params, true);
452 shaper_lut = &dpp_base->shaper_params;
456 if (stream->lut3d_func &&
457 stream->lut3d_func->state.bits.initialized == 1) {
459 result = mpc->funcs->program_3dlut(mpc,
460 &stream->lut3d_func->lut_3d,
463 result = mpc->funcs->program_shaper(mpc,
471 bool dcn32_set_mcm_luts(
472 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
474 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
475 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
476 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
478 struct pwl_params *lut_params = NULL;
481 if (plane_state->blend_tf) {
482 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
483 lut_params = &plane_state->blend_tf->pwl;
484 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
485 cm3_helper_translate_curve_to_hw_format(plane_state->blend_tf,
486 &dpp_base->regamma_params, false);
487 lut_params = &dpp_base->regamma_params;
490 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
494 if (plane_state->in_shaper_func) {
495 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
496 lut_params = &plane_state->in_shaper_func->pwl;
497 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
498 // TODO: dpp_base replace
500 cm3_helper_translate_curve_to_hw_format(plane_state->in_shaper_func,
501 &dpp_base->shaper_params, true);
502 lut_params = &dpp_base->shaper_params;
506 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
509 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
510 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
512 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
517 bool dcn32_set_input_transfer_func(struct dc *dc,
518 struct pipe_ctx *pipe_ctx,
519 const struct dc_plane_state *plane_state)
521 struct dce_hwseq *hws = dc->hwseq;
522 struct mpc *mpc = dc->res_pool->mpc;
523 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
525 enum dc_transfer_func_predefined tf;
527 struct pwl_params *params = NULL;
529 if (mpc == NULL || plane_state == NULL)
532 tf = TRANSFER_FUNCTION_UNITY;
534 if (plane_state->in_transfer_func &&
535 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
536 tf = plane_state->in_transfer_func->tf;
538 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
540 if (plane_state->in_transfer_func) {
541 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
542 params = &plane_state->in_transfer_func->pwl;
543 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
544 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
545 &dpp_base->degamma_params, false))
546 params = &dpp_base->degamma_params;
549 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
551 if (pipe_ctx->stream_res.opp &&
552 pipe_ctx->stream_res.opp->ctx &&
553 hws->funcs.set_mcm_luts)
554 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
559 bool dcn32_set_output_transfer_func(struct dc *dc,
560 struct pipe_ctx *pipe_ctx,
561 const struct dc_stream_state *stream)
563 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
564 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
565 struct pwl_params *params = NULL;
568 /* program OGAM or 3DLUT only for the top pipe*/
569 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {
570 /*program shaper and 3dlut in MPC*/
571 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
572 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
573 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
574 params = &stream->out_transfer_func->pwl;
575 else if (pipe_ctx->stream->out_transfer_func->type ==
576 TF_TYPE_DISTRIBUTED_POINTS &&
577 cm3_helper_translate_curve_to_hw_format(
578 stream->out_transfer_func,
579 &mpc->blender_params, false))
580 params = &mpc->blender_params;
581 /* there are no ROM LUTs in OUTGAM */
582 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
587 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
591 /* Program P-State force value according to if pipe is using SubVP / FPO or not:
592 * 1. Reset P-State force on all pipes first
593 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
595 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)
599 /* Unforce p-state for each pipe if it is not FPO or SubVP.
600 * For FPO and SubVP, if it's already forced disallow, leave
603 for (i = 0; i < dc->res_pool->pipe_count; i++) {
604 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
605 struct hubp *hubp = pipe->plane_res.hubp;
607 if (!pipe->stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
608 pipe->stream->fpo_in_use)) {
609 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
610 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
611 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
612 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);
616 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
618 for (i = 0; i < dc->res_pool->pipe_count; i++) {
619 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
620 struct hubp *hubp = pipe->plane_res.hubp;
622 if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
623 pipe->stream->fpo_in_use)) {
624 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
625 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
626 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
627 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);
632 /* Update MALL_SEL register based on if pipe / plane
633 * is a phantom pipe, main pipe, and if using MALL
636 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
639 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
640 bool cache_cursor = false;
642 for (i = 0; i < dc->res_pool->pipe_count; i++) {
643 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
644 struct hubp *hubp = pipe->plane_res.hubp;
646 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
647 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
649 switch (hubp->curs_attr.color_format) {
650 case CURSOR_MODE_MONO:
653 case CURSOR_MODE_COLOR_1BIT_AND:
654 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
655 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
659 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
660 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
666 if (cursor_size > 16384)
669 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
670 hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
672 // MALL not supported with Stereo3D
673 hubp->funcs->hubp_update_mall_sel(hubp,
674 num_ways <= dc->caps.cache_num_ways &&
675 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
676 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&
677 !pipe->plane_state->address.tmz_surface ? 2 : 0,
684 /* Program the sub-viewport pipe configuration after the main / phantom pipes
685 * have been programmed in hardware.
686 * 1. Update force P-State for all the main pipes (disallow P-state)
687 * 2. Update MALL_SEL register
688 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
690 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
693 struct dce_hwseq *hws = dc->hwseq;
695 // Don't force p-state disallow -- can't block dummy p-state
697 // Update MALL_SEL register for each pipe
698 if (hws && hws->funcs.update_mall_sel)
699 hws->funcs.update_mall_sel(dc, context);
701 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
702 for (i = 0; i < dc->res_pool->pipe_count; i++) {
703 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
704 struct hubp *hubp = pipe->plane_res.hubp;
706 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
707 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
708 * - need to investigate single pipe MPO + SubVP case to
709 * see if CURSOR_REQ_MODE will be back to 1 for SubVP
710 * when it should be 0 for MPO
712 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
713 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
718 static void dcn32_initialize_min_clocks(struct dc *dc)
720 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;
722 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;
723 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;
724 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
725 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
726 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
727 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
728 clocks->fclk_p_state_change_support = true;
729 clocks->p_state_change_support = true;
730 if (dc->debug.disable_boot_optimizations) {
731 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
733 /* Even though DPG_EN = 1 for the connected display, it still requires the
734 * correct timing so we cannot set DISPCLK to min freq or it could cause
735 * audio corruption. Read current DISPCLK from DENTIST and request the same
736 * freq to ensure that the timing is valid and unchanged.
738 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
741 dc->clk_mgr->funcs->update_clocks(
747 void dcn32_init_hw(struct dc *dc)
749 struct abm **abms = dc->res_pool->multiple_abms;
750 struct dce_hwseq *hws = dc->hwseq;
751 struct dc_bios *dcb = dc->ctx->dc_bios;
752 struct resource_pool *res_pool = dc->res_pool;
755 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
756 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
758 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
759 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
761 // Initialize the dccg
762 if (res_pool->dccg->funcs->dccg_init)
763 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
765 if (!dcb->funcs->is_accelerated_mode(dcb)) {
766 hws->funcs.bios_golden_init(dc);
767 hws->funcs.disable_vga(dc->hwseq);
770 // Set default OPTC memory power states
771 if (dc->debug.enable_mem_low_power.bits.optc) {
772 // Shutdown when unassigned and light sleep in VBLANK
773 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
776 if (dc->debug.enable_mem_low_power.bits.vga) {
777 // Power down VGA memory
778 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
781 if (dc->ctx->dc_bios->fw_info_valid) {
782 res_pool->ref_clocks.xtalin_clock_inKhz =
783 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
785 if (res_pool->dccg && res_pool->hubbub) {
786 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
787 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
788 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
790 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
791 res_pool->ref_clocks.dccg_ref_clock_inKhz,
792 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
794 // Not all ASICs have DCCG sw component
795 res_pool->ref_clocks.dccg_ref_clock_inKhz =
796 res_pool->ref_clocks.xtalin_clock_inKhz;
797 res_pool->ref_clocks.dchub_ref_clock_inKhz =
798 res_pool->ref_clocks.xtalin_clock_inKhz;
801 ASSERT_CRITICAL(false);
803 for (i = 0; i < dc->link_count; i++) {
804 /* Power up AND update implementation according to the
805 * required signal (which may be different from the
806 * default signal on connector).
808 struct dc_link *link = dc->links[i];
810 link->link_enc->funcs->hw_init(link->link_enc);
812 /* Check for enabled DIG to identify enabled display */
813 if (link->link_enc->funcs->is_dig_enabled &&
814 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
815 link->link_status.link_active = true;
816 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
817 if (link->link_enc->funcs->fec_is_active &&
818 link->link_enc->funcs->fec_is_active(link->link_enc))
819 link->fec_state = dc_link_fec_enabled;
823 /* enable_power_gating_plane before dsc_pg_control because
824 * FORCEON = 1 with hw default value on bootup, resume from s3
826 if (hws->funcs.enable_power_gating_plane)
827 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
829 /* we want to turn off all dp displays before doing detection */
830 dc->link_srv->blank_all_dp_displays(dc);
832 /* If taking control over from VBIOS, we may want to optimize our first
833 * mode set, so we need to skip powering down pipes until we know which
834 * pipes we want to use.
835 * Otherwise, if taking control is not possible, we need to power
838 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
839 /* Disable boot optimizations means power down everything including PHY, DIG,
840 * and OTG (i.e. the boot is not optimized because we do a full power down).
842 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)
843 dc->hwss.enable_accelerated_mode(dc, dc->current_state);
845 hws->funcs.init_pipes(dc, dc->current_state);
847 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
848 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
849 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
851 dcn32_initialize_min_clocks(dc);
853 /* On HW init, allow idle optimizations after pipes have been turned off.
855 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state
856 * is reset (i.e. not in idle at the time hw init is called), but software state
857 * still has idle_optimizations = true, so we must disable idle optimizations first
858 * (i.e. set false), then re-enable (set true).
860 dc_allow_idle_optimizations(dc, false);
861 dc_allow_idle_optimizations(dc, true);
864 /* In headless boot cases, DIG may be turned
865 * on which causes HW/SW discrepancies.
866 * To avoid this, power down hardware on boot
867 * if DIG is turned on and seamless boot not enabled
869 if (!dc->config.seamless_boot_edp_requested) {
870 struct dc_link *edp_links[MAX_NUM_EDP];
871 struct dc_link *edp_link;
873 dc_get_edp_links(dc, edp_links, &edp_num);
875 for (i = 0; i < edp_num; i++) {
876 edp_link = edp_links[i];
877 if (edp_link->link_enc->funcs->is_dig_enabled &&
878 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
879 dc->hwss.edp_backlight_control &&
880 dc->hwss.power_down &&
881 dc->hwss.edp_power_control) {
882 dc->hwss.edp_backlight_control(edp_link, false);
883 dc->hwss.power_down(dc);
884 dc->hwss.edp_power_control(edp_link, false);
888 for (i = 0; i < dc->link_count; i++) {
889 struct dc_link *link = dc->links[i];
891 if (link->link_enc->funcs->is_dig_enabled &&
892 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
893 dc->hwss.power_down) {
894 dc->hwss.power_down(dc);
902 for (i = 0; i < res_pool->audio_count; i++) {
903 struct audio *audio = res_pool->audios[i];
905 audio->funcs->hw_init(audio);
908 for (i = 0; i < dc->link_count; i++) {
909 struct dc_link *link = dc->links[i];
911 if (link->panel_cntl) {
912 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
913 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
917 for (i = 0; i < dc->res_pool->pipe_count; i++) {
918 if (abms[i] != NULL && abms[i]->funcs != NULL)
919 abms[i]->funcs->abm_init(abms[i], backlight, user_level);
922 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
923 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
925 if (!dc->debug.disable_clock_gate) {
926 /* enable all DCN clock gating */
927 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
929 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
931 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
934 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
935 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
937 if (dc->clk_mgr->funcs->notify_wm_ranges)
938 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
940 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
941 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
943 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
944 dc->res_pool->hubbub->funcs->force_pstate_change_control(
945 dc->res_pool->hubbub, false, false);
947 if (dc->res_pool->hubbub->funcs->init_crb)
948 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
950 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
951 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
953 // Get DMCUB capabilities
954 if (dc->ctx->dmub_srv) {
955 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
956 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
957 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
958 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
959 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
961 if (dc->ctx->dmub_srv->dmub->fw_version <
962 DMUB_FW_VERSION(7, 0, 35)) {
963 dc->debug.force_disable_subvp = true;
964 dc->debug.disable_fpo_optimizations = true;
969 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
971 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
972 struct dc *dc = pipe_ctx->stream->ctx->dc;
973 struct dc_stream_state *stream = pipe_ctx->stream;
974 struct pipe_ctx *odm_pipe;
976 struct dccg *dccg = dc->res_pool->dccg;
977 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN
978 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a
979 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is
980 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings
981 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger
982 * this problem. We are implementing a workaround here to keep using dscclk
983 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e
984 * 48Mhz) pixel clock to avoid hitting this problem.
986 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&
987 stream->timing.pix_clk_100hz > 480000;
990 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
994 struct dsc_config dsc_cfg;
995 struct dsc_optc_config dsc_optc_cfg;
996 enum optc_dsc_mode optc_dsc_mode;
998 /* Enable DSC hw block */
999 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1000 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1001 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1002 dsc_cfg.color_depth = stream->timing.display_color_depth;
1003 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1004 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1005 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1006 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1008 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1009 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1010 if (should_use_dto_dscclk)
1011 dccg->funcs->set_dto_dscclk(dccg, dsc->inst);
1012 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1013 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1016 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1017 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1018 if (should_use_dto_dscclk)
1019 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst);
1021 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
1022 dsc_cfg.pic_width *= opp_cnt;
1024 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1026 /* Enable DSC in OPTC */
1027 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1028 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1030 dsc_optc_cfg.bytes_per_pixel,
1031 dsc_optc_cfg.slice_width);
1033 /* disable DSC in OPTC */
1034 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1035 pipe_ctx->stream_res.tg,
1036 OPTC_DSC_DISABLED, 0, 0);
1038 /* disable DSC block */
1039 if (dccg->funcs->set_ref_dscclk)
1040 dccg->funcs->set_ref_dscclk(dccg, pipe_ctx->stream_res.dsc->inst);
1041 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
1042 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1043 ASSERT(odm_pipe->stream_res.dsc);
1044 if (dccg->funcs->set_ref_dscclk)
1045 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);
1046 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
1052 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1053 * the OPPids which are used
1055 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1057 unsigned int opp_count = 1;
1058 struct pipe_ctx *odm_pipe;
1060 /* First get to the top pipe */
1061 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1064 /* First pipe is always used */
1066 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1068 /* Find and count odm pipes, if any */
1069 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1071 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1078 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1080 struct pipe_ctx *odm_pipe;
1082 int opp_inst[MAX_PIPES] = {0};
1084 opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1087 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1088 pipe_ctx->stream_res.tg,
1090 &pipe_ctx->stream->timing);
1092 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1093 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1095 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1096 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1097 odm_pipe->stream_res.opp,
1101 if (pipe_ctx->stream_res.dsc) {
1102 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1104 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1106 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
1107 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
1108 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
1109 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
1110 struct dccg *dccg = dc->res_pool->dccg;
1112 if (dccg->funcs->set_ref_dscclk)
1113 dccg->funcs->set_ref_dscclk(dccg, dsc->inst);
1114 /* disconnect DSC block from stream */
1115 dsc->funcs->dsc_disconnect(dsc);
1119 if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))
1121 * blank pattern is generated by OPP, reprogram blank pattern
1122 * due to OPP count change
1124 dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);
1127 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1129 struct dc_stream_state *stream = pipe_ctx->stream;
1130 unsigned int odm_combine_factor = 0;
1131 bool two_pix_per_container = false;
1133 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1134 odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1136 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1137 *k1_div = PIXEL_RATE_DIV_BY_1;
1138 *k2_div = PIXEL_RATE_DIV_BY_1;
1139 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) {
1140 *k1_div = PIXEL_RATE_DIV_BY_1;
1141 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1142 *k2_div = PIXEL_RATE_DIV_BY_2;
1144 *k2_div = PIXEL_RATE_DIV_BY_4;
1145 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {
1146 if (two_pix_per_container) {
1147 *k1_div = PIXEL_RATE_DIV_BY_1;
1148 *k2_div = PIXEL_RATE_DIV_BY_2;
1150 *k1_div = PIXEL_RATE_DIV_BY_1;
1151 *k2_div = PIXEL_RATE_DIV_BY_4;
1152 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1153 *k2_div = PIXEL_RATE_DIV_BY_2;
1157 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1160 return odm_combine_factor;
1163 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1165 uint32_t pix_per_cycle = 1;
1166 uint32_t odm_combine_factor = 1;
1168 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1171 odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1172 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1173 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1176 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1177 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1181 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
1184 struct pipe_ctx *pipe = NULL;
1185 bool otg_disabled[MAX_PIPES] = {false};
1187 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1188 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1190 if (!resource_is_pipe_type(pipe, OTG_MASTER))
1193 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
1194 && dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_PHANTOM) {
1195 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
1196 reset_sync_context_for_pipe(dc, context, i);
1197 otg_disabled[i] = true;
1201 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
1203 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1204 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1206 if (otg_disabled[i])
1207 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
1211 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1212 struct dc_link_settings *link_settings)
1214 struct encoder_unblank_param params = {0};
1215 struct dc_stream_state *stream = pipe_ctx->stream;
1216 struct dc_link *link = stream->link;
1217 struct dce_hwseq *hws = link->dc->hwseq;
1218 struct pipe_ctx *odm_pipe;
1219 uint32_t pix_per_cycle = 1;
1222 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1225 /* only 3 items below are used by unblank */
1226 params.timing = pipe_ctx->stream->timing;
1228 params.link_settings.link_rate = link_settings->link_rate;
1230 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1231 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1232 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1233 pipe_ctx->stream_res.hpo_dp_stream_enc,
1234 pipe_ctx->stream_res.tg->inst);
1235 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1236 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1237 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {
1238 params.timing.pix_clk_100hz /= 2;
1241 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1242 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1243 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
1246 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1247 hws->funcs.edp_backlight_control(link, true);
1250 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1252 struct dc *dc = pipe_ctx->stream->ctx->dc;
1254 if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
1257 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
1258 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1263 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
1265 /* There are use cases where SYMCLK is referenced by OTG. For instance
1266 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
1267 * However current link interface will power off PHY when disabling link
1268 * output. This will turn off SYMCLK generated by PHY. The workaround is
1269 * to identify such case where SYMCLK is still in use by OTG when we
1270 * power off PHY. When this is detected, we will temporarily power PHY
1271 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
1272 * program_pix_clk interface. When OTG is disabled, we will then power
1273 * off PHY by calling disable link output again.
1275 * In future dcn generations, we plan to rework transmitter control
1276 * interface so that we could have an option to set SYMCLK ON TX OFF
1277 * state in one step without this workaround
1280 struct dc *dc = link->ctx->dc;
1281 struct pipe_ctx *pipe_ctx = NULL;
1284 if (link->phy_state.symclk_ref_cnts.otg > 0) {
1285 for (i = 0; i < MAX_PIPES; i++) {
1286 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1287 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {
1288 pipe_ctx->clock_source->funcs->program_pix_clk(
1289 pipe_ctx->clock_source,
1290 &pipe_ctx->stream_res.pix_clk_params,
1291 dc->link_srv->dp_get_encoding_format(
1292 &pipe_ctx->link_config.dp_link_settings),
1293 &pipe_ctx->pll_settings);
1294 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1301 void dcn32_disable_link_output(struct dc_link *link,
1302 const struct link_resource *link_res,
1303 enum signal_type signal)
1305 struct dc *dc = link->ctx->dc;
1306 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1307 struct dmcu *dmcu = dc->res_pool->dmcu;
1309 if (signal == SIGNAL_TYPE_EDP &&
1310 link->dc->hwss.edp_backlight_control &&
1311 !link->skip_implict_edp_power_control)
1312 link->dc->hwss.edp_backlight_control(link, false);
1313 else if (dmcu != NULL && dmcu->funcs->lock_phy)
1314 dmcu->funcs->lock_phy(dmcu);
1316 link_hwss->disable_link_output(link, link_res, signal);
1317 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1319 if (signal == SIGNAL_TYPE_EDP &&
1320 link->dc->hwss.edp_backlight_control &&
1321 !link->skip_implict_edp_power_control)
1322 link->dc->hwss.edp_power_control(link, false);
1323 else if (dmcu != NULL && dmcu->funcs->lock_phy)
1324 dmcu->funcs->unlock_phy(dmcu);
1326 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
1328 apply_symclk_on_tx_off_wa(link);
1331 /* For SubVP the main pipe can have a viewport position change
1332 * without a full update. In this case we must also update the
1333 * viewport positions for the phantom pipe accordingly.
1335 void dcn32_update_phantom_vp_position(struct dc *dc,
1336 struct dc_state *context,
1337 struct pipe_ctx *phantom_pipe)
1340 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
1342 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1343 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1345 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &&
1346 dc_state_get_paired_subvp_stream(context, pipe->stream) == phantom_pipe->stream) {
1347 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
1349 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
1350 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
1351 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
1352 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
1353 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
1355 phantom_pipe->plane_state->update_flags.bits.position_change = 1;
1356 resource_build_scaling_params(phantom_pipe);
1363 /* Treat the phantom pipe as if it needs to be fully enabled.
1364 * If the pipe was previously in use but not phantom, it would
1365 * have been disabled earlier in the sequence so we need to run
1366 * the full enable sequence.
1368 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)
1370 phantom_pipe->update_flags.raw = 0;
1371 if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {
1372 phantom_pipe->update_flags.bits.enable = 1;
1373 phantom_pipe->update_flags.bits.mpcc = 1;
1374 phantom_pipe->update_flags.bits.dppclk = 1;
1375 phantom_pipe->update_flags.bits.hubp_interdependent = 1;
1376 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1377 phantom_pipe->update_flags.bits.gamut_remap = 1;
1378 phantom_pipe->update_flags.bits.scaler = 1;
1379 phantom_pipe->update_flags.bits.viewport = 1;
1380 phantom_pipe->update_flags.bits.det_size = 1;
1381 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {
1382 phantom_pipe->update_flags.bits.odm = 1;
1383 phantom_pipe->update_flags.bits.global_sync = 1;
1388 bool dcn32_dsc_pg_status(
1389 struct dce_hwseq *hws,
1390 unsigned int dsc_inst)
1392 uint32_t pwr_status = 0;
1396 REG_GET(DOMAIN16_PG_STATUS,
1397 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1401 REG_GET(DOMAIN17_PG_STATUS,
1402 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1405 REG_GET(DOMAIN18_PG_STATUS,
1406 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1409 REG_GET(DOMAIN19_PG_STATUS,
1410 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1413 BREAK_TO_DEBUGGER();
1417 return pwr_status == 0;
1420 void dcn32_update_dsc_pg(struct dc *dc,
1421 struct dc_state *context,
1422 bool safe_to_disable)
1424 struct dce_hwseq *hws = dc->hwseq;
1427 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1428 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1429 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
1431 if (context->res_ctx.is_dsc_acquired[i]) {
1432 if (!is_dsc_ungated) {
1433 hws->funcs.dsc_pg_control(hws, dsc->inst, true);
1435 } else if (safe_to_disable) {
1436 if (is_dsc_ungated) {
1437 hws->funcs.dsc_pg_control(hws, dsc->inst, false);
1443 void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)
1445 struct dce_hwseq *hws = dc->hwseq;
1448 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1449 struct pipe_ctx *pipe_ctx_old =
1450 &dc->current_state->res_ctx.pipe_ctx[i];
1451 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1453 if (!pipe_ctx_old->stream)
1456 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe_ctx_old) != SUBVP_PHANTOM)
1459 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
1462 if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||
1463 (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {
1464 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1466 if (hws->funcs.reset_back_end_for_pipe)
1467 hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1468 if (hws->funcs.enable_stream_gating)
1469 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
1471 old_clk->funcs->cs_power_down(old_clk);
1476 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)
1479 enum dc_status status = DC_OK;
1480 struct dce_hwseq *hws = dc->hwseq;
1482 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1483 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1484 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1486 /* If an active, non-phantom pipe is being transitioned into a phantom
1487 * pipe, wait for the double buffer update to complete first before we do
1488 * ANY phantom pipe programming.
1490 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &&
1491 old_pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_PHANTOM) {
1492 old_pipe->stream_res.tg->funcs->wait_for_state(
1493 old_pipe->stream_res.tg,
1495 old_pipe->stream_res.tg->funcs->wait_for_state(
1496 old_pipe->stream_res.tg,
1497 CRTC_STATE_VACTIVE);
1500 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1501 struct pipe_ctx *pipe_ctx_old =
1502 &dc->current_state->res_ctx.pipe_ctx[i];
1503 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1505 if (pipe_ctx->stream == NULL)
1508 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)
1511 if (pipe_ctx->stream == pipe_ctx_old->stream &&
1512 pipe_ctx->stream->link->link_state_valid) {
1516 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1519 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
1522 if (hws->funcs.apply_single_controller_ctx_to_hw)
1523 status = hws->funcs.apply_single_controller_ctx_to_hw(
1528 ASSERT(status == DC_OK);
1530 #ifdef CONFIG_DRM_AMD_DC_FP
1531 if (hws->funcs.resync_fifo_dccg_dio)
1532 hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
1537 /* Blank pixel data during initialization */
1538 void dcn32_init_blank(
1540 struct timing_generator *tg)
1542 struct dce_hwseq *hws = dc->hwseq;
1543 enum dc_color_space color_space;
1544 struct tg_color black_color = {0};
1545 struct output_pixel_processor *opp = NULL;
1546 struct output_pixel_processor *bottom_opp = NULL;
1547 uint32_t num_opps, opp_id_src0, opp_id_src1;
1548 uint32_t otg_active_width, otg_active_height;
1551 /* program opp dpg blank color */
1552 color_space = COLOR_SPACE_SRGB;
1553 color_space_to_black_color(dc, color_space, &black_color);
1555 /* get the OTG active size */
1556 tg->funcs->get_otg_active_size(tg,
1558 &otg_active_height);
1560 /* get the OPTC source */
1561 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1563 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
1568 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1569 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1570 opp = dc->res_pool->opps[i];
1575 if (num_opps == 2) {
1576 otg_active_width = otg_active_width / 2;
1578 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
1582 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1583 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {
1584 bottom_opp = dc->res_pool->opps[i];
1590 if (opp && opp->funcs->opp_set_disp_pattern_generator)
1591 opp->funcs->opp_set_disp_pattern_generator(
1593 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1594 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1595 COLOR_DEPTH_UNDEFINED,
1601 if (num_opps == 2) {
1602 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) {
1603 bottom_opp->funcs->opp_set_disp_pattern_generator(
1605 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1606 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1607 COLOR_DEPTH_UNDEFINED,
1612 hws->funcs.wait_for_blank_complete(bottom_opp);
1617 hws->funcs.wait_for_blank_complete(opp);
1620 void dcn32_blank_phantom(struct dc *dc,
1621 struct timing_generator *tg,
1625 struct dce_hwseq *hws = dc->hwseq;
1626 enum dc_color_space color_space;
1627 struct tg_color black_color = {0};
1628 struct output_pixel_processor *opp = NULL;
1629 uint32_t num_opps, opp_id_src0, opp_id_src1;
1630 uint32_t otg_active_width, otg_active_height;
1633 /* program opp dpg blank color */
1634 color_space = COLOR_SPACE_SRGB;
1635 color_space_to_black_color(dc, color_space, &black_color);
1637 otg_active_width = width;
1638 otg_active_height = height;
1640 /* get the OPTC source */
1641 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1642 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
1644 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1645 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1646 opp = dc->res_pool->opps[i];
1651 if (opp && opp->funcs->opp_set_disp_pattern_generator)
1652 opp->funcs->opp_set_disp_pattern_generator(
1654 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1655 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1656 COLOR_DEPTH_UNDEFINED,
1662 if (tg->funcs->is_tg_enabled(tg))
1663 hws->funcs.wait_for_blank_complete(opp);
1666 bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
1667 const struct dc_state *cur_ctx,
1668 const struct dc_state *new_ctx)
1671 const struct pipe_ctx *cur_pipe, *new_pipe;
1672 bool is_seamless = true;
1674 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1675 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];
1676 new_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1678 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) ||
1679 resource_is_pipe_type(new_pipe, FREE_PIPE))
1680 /* adding or removing free pipes is always seamless */
1682 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) {
1683 if (resource_is_pipe_type(new_pipe, OTG_MASTER))
1684 if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id)
1685 /* OTG master with the same stream is seamless */
1687 } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) {
1688 if (resource_is_pipe_type(new_pipe, OPP_HEAD)) {
1689 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg)
1691 * OPP heads sharing the same timing
1692 * generator is seamless
1696 } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) {
1697 if (resource_is_pipe_type(new_pipe, DPP_PIPE)) {
1698 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp)
1700 * DPP pipes sharing the same OPP head is
1708 * This pipe's transition doesn't fall under any seamless
1711 is_seamless = false;
1718 void dcn32_prepare_bandwidth(struct dc *dc,
1719 struct dc_state *context)
1721 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1722 /* Any transition into an FPO config should disable MCLK switching first to avoid
1723 * driver and FW P-State synchronization issues.
1725 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1726 dc->optimized_required = true;
1727 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1730 if (dc->clk_mgr->dc_mode_softmax_enabled)
1731 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1732 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1733 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1735 dcn20_prepare_bandwidth(dc, context);
1737 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1738 dc_dmub_srv_p_state_delegate(dc, false, context);
1740 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1741 /* After disabling P-State, restore the original value to ensure we get the correct P-State
1742 * on the next optimize.
1744 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
1748 void dcn32_interdependent_update_lock(struct dc *dc,
1749 struct dc_state *context, bool lock)
1752 struct pipe_ctx *pipe;
1753 struct timing_generator *tg;
1755 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1756 pipe = &context->res_ctx.pipe_ctx[i];
1757 tg = pipe->stream_res.tg;
1759 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
1760 !tg->funcs->is_tg_enabled(tg) ||
1761 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1765 dc->hwss.pipe_control_lock(dc, pipe, true);
1767 dc->hwss.pipe_control_lock(dc, pipe, false);