drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dm_helpers.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "dcn30_hwseq.h"
  32 #include "dccg.h"
  33 #include "dce/dce_hwseq.h"
  34 #include "dcn30/dcn30_mpc.h"
  35 #include "dcn30/dcn30_dpp.h"
  36 #include "dcn10/dcn10_cm_common.h"
  37 #include "dcn30/dcn30_cm_common.h"
  38 #include "reg_helper.h"
  39 #include "abm.h"
  40 #include "clk_mgr.h"
  41 #include "hubp.h"
  42 #include "dchubbub.h"
  43 #include "timing_generator.h"
  44 #include "opp.h"
  45 #include "ipp.h"
  46 #include "mpc.h"
  47 #include "mcif_wb.h"
  48 #include "dc_dmub_srv.h"
  49 #include "link_hwss.h"
  50 #include "dpcd_defs.h"
  51 #include "dcn20/dcn20_hwseq.h"
  52 #include "dcn30/dcn30_resource.h"
  53 #include "link.h"
  54
  55
  56
  57
  58 #define DC_LOGGER_INIT(logger)
  59
  60 #define CTX \
  61         hws->ctx
  62 #define REG(reg)\
  63         hws->regs->reg
  64 #define DC_LOGGER \
  65                 dc->ctx->logger
  66
  67
  68 #undef FN
  69 #define FN(reg_name, field_name) \
  70         hws->shifts->field_name, hws->masks->field_name
  71
  72 bool dcn30_set_blend_lut(
  73         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
  74 {
  75         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
  76         bool result = true;
  77         struct pwl_params *blend_lut = NULL;
  78
  79         if (plane_state->blend_tf) {
  80                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
  81                         blend_lut = &plane_state->blend_tf->pwl;
  82                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
  83                         cm3_helper_translate_curve_to_hw_format(
  84                                         plane_state->blend_tf, &dpp_base->regamma_params, false);
  85                         blend_lut = &dpp_base->regamma_params;
  86                 }
  87         }
  88         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
  89
  90         return result;
  91 }
  92
  93 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
  94                                        const struct dc_stream_state *stream)
  95 {
  96         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
  97         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
  98         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
  99         bool result = false;
 100         int acquired_rmu = 0;
 101         int mpcc_id_projected = 0;
 102
 103         const struct pwl_params *shaper_lut = NULL;
 104         //get the shaper lut params
 105         if (stream->func_shaper) {
 106                 if (stream->func_shaper->type == TF_TYPE_HWPWL) {
 107                         shaper_lut = &stream->func_shaper->pwl;
 108                 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
 109                         cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper,
 110                                                                &dpp_base->shaper_params, true);
 111                         shaper_lut = &dpp_base->shaper_params;
 112                 }
 113         }
 114
 115         if (stream->lut3d_func &&
 116             stream->lut3d_func->state.bits.initialized == 1 &&
 117             stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
 118                 if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
 119                         mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
 120                 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
 121                         mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
 122                 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
 123                         mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
 124                 if (mpcc_id_projected != mpcc_id)
 125                         BREAK_TO_DEBUGGER();
 126                 /* find the reason why logical layer assigned a different
 127                  * mpcc_id into acquire_post_bldn_3dlut
 128                  */
 129                 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
 130                                                        stream->lut3d_func->state.bits.rmu_mux_num);
 131                 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
 132                         BREAK_TO_DEBUGGER();
 133
 134                 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,
 135                                                    stream->lut3d_func->state.bits.rmu_mux_num);
 136                 result = mpc->funcs->program_shaper(mpc, shaper_lut,
 137                                                     stream->lut3d_func->state.bits.rmu_mux_num);
 138         } else {
 139                 // loop through the available mux and release the requested mpcc_id
 140                 mpc->funcs->release_rmu(mpc, mpcc_id);
 141         }
 142
 143         return result;
 144 }
 145
 146 bool dcn30_set_input_transfer_func(struct dc *dc,
 147                                 struct pipe_ctx *pipe_ctx,
 148                                 const struct dc_plane_state *plane_state)
 149 {
 150         struct dce_hwseq *hws = dc->hwseq;
 151         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 152         enum dc_transfer_func_predefined tf;
 153         bool result = true;
 154         struct pwl_params *params = NULL;
 155
 156         if (dpp_base == NULL || plane_state == NULL)
 157                 return false;
 158
 159         tf = TRANSFER_FUNCTION_UNITY;
 160
 161         if (plane_state->in_transfer_func &&
 162                 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
 163                 tf = plane_state->in_transfer_func->tf;
 164
 165         dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
 166
 167         if (plane_state->in_transfer_func) {
 168                 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
 169                         params = &plane_state->in_transfer_func->pwl;
 170                 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
 171                         cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
 172                                         &dpp_base->degamma_params, false))
 173                         params = &dpp_base->degamma_params;
 174         }
 175
 176         result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
 177
 178         if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
 179                 if (dpp_base->funcs->dpp_program_blnd_lut)
 180                         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 181                 if (dpp_base->funcs->dpp_program_shaper_lut &&
 182                                 dpp_base->funcs->dpp_program_3dlut)
 183                         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 184         }
 185
 186         return result;
 187 }
 188
 189 void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)
 190 {
 191         int i = 0;
 192         struct dpp_grph_csc_adjustment dpp_adjust;
 193         struct mpc_grph_gamut_adjustment mpc_adjust;
 194         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 195         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 196
 197         memset(&dpp_adjust, 0, sizeof(dpp_adjust));
 198         dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
 199
 200         if (pipe_ctx->plane_state &&
 201             pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
 202                 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
 203                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
 204                         dpp_adjust.temperature_matrix[i] =
 205                                 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
 206         }
 207
 208         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,
 209                                                             &dpp_adjust);
 210
 211         memset(&mpc_adjust, 0, sizeof(mpc_adjust));
 212         mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
 213
 214         if (pipe_ctx->top_pipe == NULL) {
 215                 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
 216                         mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
 217                         for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
 218                                 mpc_adjust.temperature_matrix[i] =
 219                                         pipe_ctx->stream->gamut_remap_matrix.matrix[i];
 220                 }
 221         }
 222
 223         mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
 224 }
 225
 226 bool dcn30_set_output_transfer_func(struct dc *dc,
 227                                 struct pipe_ctx *pipe_ctx,
 228                                 const struct dc_stream_state *stream)
 229 {
 230         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 231         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 232         struct pwl_params *params = NULL;
 233         bool ret = false;
 234
 235         /* program OGAM or 3DLUT only for the top pipe*/
 236         if (pipe_ctx->top_pipe == NULL) {
 237                 /*program rmu shaper and 3dlut in MPC*/
 238                 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
 239                 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 240                         if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 241                                 params = &stream->out_transfer_func->pwl;
 242                         else if (pipe_ctx->stream->out_transfer_func->type ==
 243                                         TF_TYPE_DISTRIBUTED_POINTS &&
 244                                         cm3_helper_translate_curve_to_hw_format(
 245                                         stream->out_transfer_func,
 246                                         &mpc->blender_params, false))
 247                                 params = &mpc->blender_params;
 248                          /* there are no ROM LUTs in OUTGAM */
 249                         if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 250                                 BREAK_TO_DEBUGGER();
 251                 }
 252         }
 253
 254         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 255         return ret;
 256 }
 257
 258 static void dcn30_set_writeback(
 259                 struct dc *dc,
 260                 struct dc_writeback_info *wb_info,
 261                 struct dc_state *context)
 262 {
 263         struct mcif_wb *mcif_wb;
 264         struct mcif_buf_params *mcif_buf_params;
 265
 266         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
 267         ASSERT(wb_info->wb_enabled);
 268         ASSERT(wb_info->mpcc_inst >= 0);
 269         ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
 270         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
 271         mcif_buf_params = &wb_info->mcif_buf_params;
 272
 273         /* set DWB MPC mux */
 274         dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
 275                         wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
 276         /* set MCIF_WB buffer and arbitration configuration */
 277         mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
 278         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
 279 }
 280
 281 void dcn30_update_writeback(
 282                 struct dc *dc,
 283                 struct dc_writeback_info *wb_info,
 284                 struct dc_state *context)
 285 {
 286         struct dwbc *dwb;
 287         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 288         DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
 289                 __func__, wb_info->dwb_pipe_inst,\
 290                 wb_info->mpcc_inst);
 291
 292         dcn30_set_writeback(dc, wb_info, context);
 293
 294         /* update DWB */
 295         dwb->funcs->update(dwb, &wb_info->dwb_params);
 296 }
 297
 298 bool dcn30_mmhubbub_warmup(
 299         struct dc *dc,
 300         unsigned int num_dwb,
 301         struct dc_writeback_info *wb_info)
 302 {
 303         struct dwbc *dwb;
 304         struct mcif_wb *mcif_wb;
 305         struct mcif_warmup_params warmup_params = {0};
 306         unsigned int  i, i_buf;
 307         /*make sure there is no active DWB eanbled */
 308         for (i = 0; i < num_dwb; i++) {
 309                 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
 310                 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
 311                         /*can not do warmup while any dwb enabled*/
 312                         return false;
 313                 }
 314         }
 315
 316         if (wb_info->mcif_warmup_params.p_vmid == 0)
 317                 return false;
 318
 319         /*check whether this is new interface: warmup big buffer once*/
 320         if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
 321                 wb_info->mcif_warmup_params.region_size != 0) {
 322                 /*mmhubbub is shared, so it does not matter which MCIF*/
 323                 mcif_wb = dc->res_pool->mcif_wb[0];
 324                 /*warmup a big chunk of VM buffer at once*/
 325                 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
 326                 warmup_params.address_increment =  wb_info->mcif_warmup_params.region_size;
 327                 warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
 328                 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
 329
 330                 if (warmup_params.address_increment == 0)
 331                         warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
 332
 333                 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
 334                 return true;
 335         }
 336         /*following is the original: warmup each DWB's mcif buffer*/
 337         for (i = 0; i < num_dwb; i++) {
 338                 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
 339                 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
 340                 /*warmup is for VM mode only*/
 341                 if (wb_info[i].mcif_buf_params.p_vmid == 0)
 342                         return false;
 343
 344                 /* Warmup MCIF_WB */
 345                 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
 346                         warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
 347                         warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
 348                         warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
 349                         warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
 350                         mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
 351                 }
 352         }
 353         return true;
 354 }
 355
 356 void dcn30_enable_writeback(
 357                 struct dc *dc,
 358                 struct dc_writeback_info *wb_info,
 359                 struct dc_state *context)
 360 {
 361         struct dwbc *dwb;
 362         struct mcif_wb *mcif_wb;
 363
 364         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 365         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
 366
 367         DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
 368                 __func__, wb_info->dwb_pipe_inst,\
 369                 wb_info->mpcc_inst);
 370
 371         /* Warmup interface */
 372         dcn30_mmhubbub_warmup(dc, 1, wb_info);
 373
 374         /* Update writeback pipe */
 375         dcn30_set_writeback(dc, wb_info, context);
 376
 377         /* Enable MCIF_WB */
 378         mcif_wb->funcs->enable_mcif(mcif_wb);
 379         /* Enable DWB */
 380         dwb->funcs->enable(dwb, &wb_info->dwb_params);
 381 }
 382
 383 void dcn30_disable_writeback(
 384                 struct dc *dc,
 385                 unsigned int dwb_pipe_inst)
 386 {
 387         struct dwbc *dwb;
 388         struct mcif_wb *mcif_wb;
 389
 390         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
 391         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
 392         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
 393         DC_LOG_DWB("%s dwb_pipe_inst = %d",\
 394                 __func__, dwb_pipe_inst);
 395
 396         /* disable DWB */
 397         dwb->funcs->disable(dwb);
 398         /* disable MCIF */
 399         mcif_wb->funcs->disable_mcif(mcif_wb);
 400         /* disable MPC DWB mux */
 401         dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
 402 }
 403
 404 void dcn30_program_all_writeback_pipes_in_tree(
 405                 struct dc *dc,
 406                 const struct dc_stream_state *stream,
 407                 struct dc_state *context)
 408 {
 409         struct dc_writeback_info wb_info;
 410         struct dwbc *dwb;
 411         struct dc_stream_status *stream_status = NULL;
 412         int i_wb, i_pipe, i_stream;
 413         DC_LOG_DWB("%s", __func__);
 414
 415         ASSERT(stream);
 416         for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
 417                 if (context->streams[i_stream] == stream) {
 418                         stream_status = &context->stream_status[i_stream];
 419                         break;
 420                 }
 421         }
 422         ASSERT(stream_status);
 423
 424         ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
 425         /* For each writeback pipe */
 426         for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
 427
 428                 /* copy writeback info to local non-const so mpcc_inst can be set */
 429                 wb_info = stream->writeback_info[i_wb];
 430                 if (wb_info.wb_enabled) {
 431
 432                         /* get the MPCC instance for writeback_source_plane */
 433                         wb_info.mpcc_inst = -1;
 434                         for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
 435                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
 436
 437                                 if (!pipe_ctx->plane_state)
 438                                         continue;
 439
 440                                 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
 441                                         wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
 442                                         break;
 443                                 }
 444                         }
 445
 446                         if (wb_info.mpcc_inst == -1) {
 447                                 /* Disable writeback pipe and disconnect from MPCC
 448                                  * if source plane has been removed
 449                                  */
 450                                 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
 451                                 continue;
 452                         }
 453
 454                         ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
 455                         dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
 456                         if (dwb->funcs->is_enabled(dwb)) {
 457                                 /* writeback pipe already enabled, only need to update */
 458                                 dc->hwss.update_writeback(dc, &wb_info, context);
 459                         } else {
 460                                 /* Enable writeback pipe and connect to MPCC */
 461                                 dc->hwss.enable_writeback(dc, &wb_info, context);
 462                         }
 463                 } else {
 464                         /* Disable writeback pipe and disconnect from MPCC */
 465                         dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
 466                 }
 467         }
 468 }
 469
 470 void dcn30_init_hw(struct dc *dc)
 471 {
 472         struct abm **abms = dc->res_pool->multiple_abms;
 473         struct dce_hwseq *hws = dc->hwseq;
 474         struct dc_bios *dcb = dc->ctx->dc_bios;
 475         struct resource_pool *res_pool = dc->res_pool;
 476         int i;
 477         int edp_num;
 478         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 479
 480         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 481                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 482
 483         // Initialize the dccg
 484         if (res_pool->dccg->funcs->dccg_init)
 485                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 486
 487         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 488                 hws->funcs.bios_golden_init(dc);
 489                 hws->funcs.disable_vga(dc->hwseq);
 490         }
 491
 492         if (dc->debug.enable_mem_low_power.bits.dmcu) {
 493                 // Force ERAM to shutdown if DMCU is not enabled
 494                 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
 495                         REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
 496                 }
 497         }
 498
 499         // Set default OPTC memory power states
 500         if (dc->debug.enable_mem_low_power.bits.optc) {
 501                 // Shutdown when unassigned and light sleep in VBLANK
 502                 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
 503         }
 504
 505         if (dc->debug.enable_mem_low_power.bits.vga) {
 506                 // Power down VGA memory
 507                 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
 508         }
 509
 510         if (dc->ctx->dc_bios->fw_info_valid) {
 511                 res_pool->ref_clocks.xtalin_clock_inKhz =
 512                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 513
 514                 if (res_pool->dccg && res_pool->hubbub) {
 515
 516                         (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
 517                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
 518                                         &res_pool->ref_clocks.dccg_ref_clock_inKhz);
 519
 520                         (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
 521                                         res_pool->ref_clocks.dccg_ref_clock_inKhz,
 522                                         &res_pool->ref_clocks.dchub_ref_clock_inKhz);
 523                 } else {
 524                         // Not all ASICs have DCCG sw component
 525                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 526                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 527                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 528                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 529                 }
 530         } else
 531                 ASSERT_CRITICAL(false);
 532
 533         for (i = 0; i < dc->link_count; i++) {
 534                 /* Power up AND update implementation according to the
 535                  * required signal (which may be different from the
 536                  * default signal on connector).
 537                  */
 538                 struct dc_link *link = dc->links[i];
 539
 540                 link->link_enc->funcs->hw_init(link->link_enc);
 541
 542                 /* Check for enabled DIG to identify enabled display */
 543                 if (link->link_enc->funcs->is_dig_enabled &&
 544                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 545                         link->link_status.link_active = true;
 546                         if (link->link_enc->funcs->fec_is_active &&
 547                                         link->link_enc->funcs->fec_is_active(link->link_enc))
 548                                 link->fec_state = dc_link_fec_enabled;
 549                 }
 550         }
 551
 552         /* we want to turn off all dp displays before doing detection */
 553         dc->link_srv->blank_all_dp_displays(dc);
 554
 555         if (hws->funcs.enable_power_gating_plane)
 556                 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 557
 558         /* If taking control over from VBIOS, we may want to optimize our first
 559          * mode set, so we need to skip powering down pipes until we know which
 560          * pipes we want to use.
 561          * Otherwise, if taking control is not possible, we need to power
 562          * everything down.
 563          */
 564         if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
 565                 hws->funcs.init_pipes(dc, dc->current_state);
 566                 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 567                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 568                                         !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 569         }
 570
 571         /* In headless boot cases, DIG may be turned
 572          * on which causes HW/SW discrepancies.
 573          * To avoid this, power down hardware on boot
 574          * if DIG is turned on and seamless boot not enabled
 575          */
 576         if (!dc->config.seamless_boot_edp_requested) {
 577                 struct dc_link *edp_links[MAX_NUM_EDP];
 578                 struct dc_link *edp_link = NULL;
 579
 580                 dc_get_edp_links(dc, edp_links, &edp_num);
 581                 if (edp_num)
 582                         edp_link = edp_links[0];
 583                 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
 584                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
 585                                 dc->hwss.edp_backlight_control &&
 586                                 dc->hwss.power_down &&
 587                                 dc->hwss.edp_power_control) {
 588                         dc->hwss.edp_backlight_control(edp_link, false);
 589                         dc->hwss.power_down(dc);
 590                         dc->hwss.edp_power_control(edp_link, false);
 591                 } else {
 592                         for (i = 0; i < dc->link_count; i++) {
 593                                 struct dc_link *link = dc->links[i];
 594
 595                                 if (link->link_enc->funcs->is_dig_enabled &&
 596                                                 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
 597                                                 dc->hwss.power_down) {
 598                                         dc->hwss.power_down(dc);
 599                                         break;
 600                                 }
 601
 602                         }
 603                 }
 604         }
 605
 606         for (i = 0; i < res_pool->audio_count; i++) {
 607                 struct audio *audio = res_pool->audios[i];
 608
 609                 audio->funcs->hw_init(audio);
 610         }
 611
 612         for (i = 0; i < dc->link_count; i++) {
 613                 struct dc_link *link = dc->links[i];
 614
 615                 if (link->panel_cntl)
 616                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
 617         }
 618
 619         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 620                 if (abms[i] != NULL)
 621                         abms[i]->funcs->abm_init(abms[i], backlight);
 622         }
 623
 624         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 625         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 626
 627         if (!dc->debug.disable_clock_gate) {
 628                 /* enable all DCN clock gating */
 629                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 630
 631                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 632
 633                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 634         }
 635
 636         if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
 637                 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 638
 639         if (dc->clk_mgr->funcs->notify_wm_ranges)
 640                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 641
 642         //if softmax is enabled then hardmax will be set by a different call
 643         if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
 644                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 645
 646         if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 647                 dc->res_pool->hubbub->funcs->force_pstate_change_control(
 648                                 dc->res_pool->hubbub, false, false);
 649         if (dc->res_pool->hubbub->funcs->init_crb)
 650                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 651
 652         // Get DMCUB capabilities
 653         dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
 654         dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
 655         dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
 656 }
 657
 658 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
 659 {
 660         if (pipe_ctx == NULL)
 661                 return;
 662
 663         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL)
 664                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
 665                                 pipe_ctx->stream_res.stream_enc,
 666                                 enable);
 667 }
 668
 669 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
 670 {
 671         bool is_hdmi_tmds;
 672         bool is_dp;
 673
 674         ASSERT(pipe_ctx->stream);
 675
 676         if (pipe_ctx->stream_res.stream_enc == NULL)
 677                 return;  /* this is not root pipe */
 678
 679         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 680         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 681
 682         if (!is_hdmi_tmds && !is_dp)
 683                 return;
 684
 685         if (is_hdmi_tmds)
 686                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 687                         pipe_ctx->stream_res.stream_enc,
 688                         &pipe_ctx->stream_res.encoder_info_frame);
 689         else {
 690                 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
 691                         pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
 692                                 pipe_ctx->stream_res.stream_enc,
 693                                 &pipe_ctx->stream_res.encoder_info_frame);
 694
 695                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 696                         pipe_ctx->stream_res.stream_enc,
 697                         &pipe_ctx->stream_res.encoder_info_frame);
 698         }
 699 }
 700
 701 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
 702 {
 703         struct dc_stream_state    *stream     = pipe_ctx->stream;
 704         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
 705         bool                       enable     = false;
 706         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
 707         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
 708                                                         ? dmdata_dp
 709                                                         : dmdata_hdmi;
 710
 711         /* if using dynamic meta, don't set up generic infopackets */
 712         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
 713                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
 714                 enable = true;
 715         }
 716
 717         if (!hubp)
 718                 return;
 719
 720         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
 721                 return;
 722
 723         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
 724                                                         hubp->inst, mode);
 725 }
 726
 727 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 728 {
 729         union dmub_rb_cmd cmd;
 730         uint32_t tmr_delay = 0, tmr_scale = 0;
 731         struct dc_cursor_attributes cursor_attr;
 732         bool cursor_cache_enable = false;
 733         struct dc_stream_state *stream = NULL;
 734         struct dc_plane_state *plane = NULL;
 735
 736         if (!dc->ctx->dmub_srv)
 737                 return false;
 738
 739         if (enable) {
 740                 if (dc->current_state) {
 741                         int i;
 742
 743                         /* First, check no-memory-requests case */
 744                         for (i = 0; i < dc->current_state->stream_count; i++) {
 745                                 if (dc->current_state->stream_status[i].plane_count)
 746                                         /* Fail eligibility on a visible stream */
 747                                         break;
 748                         }
 749
 750                         if (i == dc->current_state->stream_count) {
 751                                 /* Enable no-memory-requests case */
 752                                 memset(&cmd, 0, sizeof(cmd));
 753                                 cmd.mall.header.type = DMUB_CMD__MALL;
 754                                 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
 755                                 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
 756
 757                                 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 758
 759                                 return true;
 760                         }
 761
 762                         stream = dc->current_state->streams[0];
 763                         plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
 764
 765                         if (stream && plane) {
 766                                 cursor_cache_enable = stream->cursor_position.enable &&
 767                                                 plane->address.grph.cursor_cache_addr.quad_part;
 768                                 cursor_attr = stream->cursor_attributes;
 769                         }
 770
 771                         /*
 772                          * Second, check MALL eligibility
 773                          *
 774                          * single display only, single surface only, 8 and 16 bit formats only, no VM,
 775                          * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
 776                          *
 777                          * TODO: When we implement multi-display, PSR displays will be allowed if there is
 778                          * a non-PSR display present, since in that case we can't do D0i3.2
 779                          */
 780                         if (dc->current_state->stream_count == 1 &&
 781                                         stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
 782                                         dc->current_state->stream_status[0].plane_count == 1 &&
 783                                         plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
 784                                         plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
 785                                         plane->address.page_table_base.quad_part == 0 &&
 786                                         dc->hwss.does_plane_fit_in_mall &&
 787                                         dc->hwss.does_plane_fit_in_mall(dc, plane,
 788                                                         cursor_cache_enable ? &cursor_attr : NULL)) {
 789                                 unsigned int v_total = stream->adjust.v_total_max ?
 790                                                 stream->adjust.v_total_max : stream->timing.v_total;
 791                                 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
 792                                                 100LL, (v_total * stream->timing.h_total));
 793
 794                                 /*
 795                                  * one frame time in microsec:
 796                                  * Delay_Us = 1000000 / refresh
 797                                  * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
 798                                  *
 799                                  * one frame time modified by 'additional timer percent' (p):
 800                                  * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
 801                                  *                   = dynamic_delay_us * (1 + p / 100)
 802                                  *                   = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
 803                                  *                   = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
 804                                  *
 805                                  * formula for timer duration based on parameters, from regspec:
 806                                  * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
 807                                  *
 808                                  * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
 809                                  * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
 810                                  * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
 811                                  *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
 812                                  *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
 813                                  *
 814                                  * need to round up the result of the division before the subtraction
 815                                  */
 816                                 unsigned int denom = refresh_hz * 6528;
 817                                 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
 818
 819                                 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
 820                                                 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
 821                                                 denom) - 64LL;
 822
 823                                 /* In some cases the stutter period is really big (tiny modes) in these
 824                                  * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
 825                                  *
 826                                  * We can check if stutter_period is more than 1/10th the frame time to
 827                                  * consider if we can actually meet the range of hysteresis timer
 828                                  */
 829                                 if (stutter_period > 100000/refresh_hz)
 830                                         return false;
 831
 832                                 /* scale should be increased until it fits into 6 bits */
 833                                 while (tmr_delay & ~0x3F) {
 834                                         tmr_scale++;
 835
 836                                         if (tmr_scale > 3) {
 837                                                 /* Delay exceeds range of hysteresis timer */
 838                                                 ASSERT(false);
 839                                                 return false;
 840                                         }
 841
 842                                         denom *= 2;
 843                                         tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
 844                                                         (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
 845                                                         denom) - 64LL;
 846                                 }
 847
 848                                 /* Copy HW cursor */
 849                                 if (cursor_cache_enable) {
 850                                         memset(&cmd, 0, sizeof(cmd));
 851                                         cmd.mall.header.type = DMUB_CMD__MALL;
 852                                         cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
 853                                         cmd.mall.header.payload_bytes =
 854                                                         sizeof(cmd.mall) - sizeof(cmd.mall.header);
 855
 856                                         switch (cursor_attr.color_format) {
 857                                         case CURSOR_MODE_MONO:
 858                                                 cmd.mall.cursor_bpp = 2;
 859                                                 break;
 860                                         case CURSOR_MODE_COLOR_1BIT_AND:
 861                                         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
 862                                         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
 863                                                 cmd.mall.cursor_bpp = 32;
 864                                                 break;
 865
 866                                         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
 867                                         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
 868                                                 cmd.mall.cursor_bpp = 64;
 869                                                 break;
 870                                         }
 871
 872                                         cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
 873                                         cmd.mall.cursor_copy_dst.quad_part =
 874                                                         (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
 875                                         cmd.mall.cursor_width = cursor_attr.width;
 876                                         cmd.mall.cursor_height = cursor_attr.height;
 877                                         cmd.mall.cursor_pitch = cursor_attr.pitch;
 878
 879                                         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 880
 881                                         /* Use copied cursor, and it's okay to not switch back */
 882                                         cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
 883                                         dc_stream_set_cursor_attributes(stream, &cursor_attr);
 884                                 }
 885
 886                                 /* Enable MALL */
 887                                 memset(&cmd, 0, sizeof(cmd));
 888                                 cmd.mall.header.type = DMUB_CMD__MALL;
 889                                 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
 890                                 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
 891                                 cmd.mall.tmr_delay = tmr_delay;
 892                                 cmd.mall.tmr_scale = tmr_scale;
 893                                 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
 894
 895                                 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 896
 897                                 return true;
 898                         }
 899                 }
 900
 901                 /* No applicable optimizations */
 902                 return false;
 903         }
 904
 905         /* Disable MALL */
 906         memset(&cmd, 0, sizeof(cmd));
 907         cmd.mall.header.type = DMUB_CMD__MALL;
 908         cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
 909         cmd.mall.header.payload_bytes =
 910                 sizeof(cmd.mall) - sizeof(cmd.mall.header);
 911
 912         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 913
 914         return true;
 915 }
 916
 917 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
 918 {
 919         // add meta size?
 920         unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
 921                         (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
 922         unsigned int mall_size = dc->caps.mall_size_total;
 923         unsigned int cursor_size = 0;
 924
 925         if (dc->debug.mall_size_override)
 926                 mall_size = 1024 * 1024 * dc->debug.mall_size_override;
 927
 928         if (cursor_attr) {
 929                 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
 930
 931                 switch (cursor_attr->color_format) {
 932                 case CURSOR_MODE_MONO:
 933                         cursor_size /= 2;
 934                         break;
 935                 case CURSOR_MODE_COLOR_1BIT_AND:
 936                 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
 937                 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
 938                         cursor_size *= 4;
 939                         break;
 940
 941                 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
 942                 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
 943                         cursor_size *= 8;
 944                         break;
 945                 }
 946         }
 947
 948         return (surface_size + cursor_size) < mall_size;
 949 }
 950
 951 void dcn30_hardware_release(struct dc *dc)
 952 {
 953         bool subvp_in_use = false;
 954         uint32_t i;
 955
 956         dc_dmub_srv_p_state_delegate(dc, false, NULL);
 957         dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
 958
 959         /* SubVP treated the same way as FPO. If driver disable and
 960          * we are using a SubVP config, disable and force on DCN side
 961          * to prevent P-State hang on driver enable.
 962          */
 963         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 964                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 965
 966                 if (!pipe->stream)
 967                         continue;
 968
 969                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 970                         subvp_in_use = true;
 971                         break;
 972                 }
 973         }
 974         /* If pstate unsupported, or still supported
 975          * by firmware, force it supported by dcn
 976          */
 977         if (dc->current_state)
 978                 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
 979                                 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
 980                                 dc->res_pool->hubbub->funcs->force_pstate_change_control)
 981                         dc->res_pool->hubbub->funcs->force_pstate_change_control(
 982                                         dc->res_pool->hubbub, true, true);
 983 }
 984
 985 void dcn30_set_disp_pattern_generator(const struct dc *dc,
 986                 struct pipe_ctx *pipe_ctx,
 987                 enum controller_dp_test_pattern test_pattern,
 988                 enum controller_dp_color_space color_space,
 989                 enum dc_color_depth color_depth,
 990                 const struct tg_color *solid_color,
 991                 int width, int height, int offset)
 992 {
 993         pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
 994                         color_space, color_depth, solid_color, width, height, offset);
 995 }
 996
 997 void dcn30_prepare_bandwidth(struct dc *dc,
 998         struct dc_state *context)
 999 {
1000         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {
1001                 dc->optimized_required = true;
1002                 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1003         }
1004
1005         if (dc->clk_mgr->dc_mode_softmax_enabled)
1006                 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1007                                 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1008                         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1009
1010         dcn20_prepare_bandwidth(dc, context);
1011
1012         if (!dc->clk_mgr->clks.fw_based_mclk_switching)
1013                 dc_dmub_srv_p_state_delegate(dc, false, context);
1014 }
1015
1016 void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
1017                 int num_pipes, const struct dc_static_screen_params *params)
1018 {
1019         unsigned int i;
1020         unsigned int triggers = 0;
1021
1022         if (params->triggers.surface_update)
1023                 triggers |= 0x100;
1024         if (params->triggers.cursor_update)
1025                 triggers |= 0x8;
1026         if (params->triggers.force_trigger)
1027                 triggers |= 0x1;
1028
1029         for (i = 0; i < num_pipes; i++)
1030                 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1031                                         triggers, params->num_frames);
1032 }