drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include "dcn32_fpu.h"
  27 #include "dcn32/dcn32_resource.h"
  28 #include "dcn20/dcn20_resource.h"
  29 #include "display_mode_vba_util_32.h"
  30 #include "dml/dcn32/display_mode_vba_32.h"
  31 // We need this includes for WATERMARKS_* defines
  32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
  33 #include "dcn30/dcn30_resource.h"
  34 #include "link.h"
  35
  36 #define DC_LOGGER_INIT(logger)
  37
  38 static const struct subvp_high_refresh_list subvp_high_refresh_list = {
  39                         .min_refresh = 120,
  40                         .max_refresh = 175,
  41                         .res = {
  42                                 {.width = 3840, .height = 2160, },
  43                                 {.width = 3440, .height = 1440, },
  44                                 {.width = 2560, .height = 1440, }},
  45 };
  46
  47 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
  48         .gpuvm_enable = 0,
  49         .gpuvm_max_page_table_levels = 4,
  50         .hostvm_enable = 0,
  51         .rob_buffer_size_kbytes = 128,
  52         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
  53         .config_return_buffer_size_in_kbytes = 1280,
  54         .compressed_buffer_segment_size_in_kbytes = 64,
  55         .meta_fifo_size_in_kentries = 22,
  56         .zero_size_buffer_entries = 512,
  57         .compbuf_reserved_space_64b = 256,
  58         .compbuf_reserved_space_zs = 64,
  59         .dpp_output_buffer_pixels = 2560,
  60         .opp_output_buffer_lines = 1,
  61         .pixel_chunk_size_kbytes = 8,
  62         .alpha_pixel_chunk_size_kbytes = 4,
  63         .min_pixel_chunk_size_bytes = 1024,
  64         .dcc_meta_buffer_size_bytes = 6272,
  65         .meta_chunk_size_kbytes = 2,
  66         .min_meta_chunk_size_bytes = 256,
  67         .writeback_chunk_size_kbytes = 8,
  68         .ptoi_supported = false,
  69         .num_dsc = 4,
  70         .maximum_dsc_bits_per_component = 12,
  71         .maximum_pixels_per_line_per_dsc_unit = 6016,
  72         .dsc422_native_support = true,
  73         .is_line_buffer_bpp_fixed = true,
  74         .line_buffer_fixed_bpp = 57,
  75         .line_buffer_size_bits = 1171920,
  76         .max_line_buffer_lines = 32,
  77         .writeback_interface_buffer_size_kbytes = 90,
  78         .max_num_dpp = 4,
  79         .max_num_otg = 4,
  80         .max_num_hdmi_frl_outputs = 1,
  81         .max_num_wb = 1,
  82         .max_dchub_pscl_bw_pix_per_clk = 4,
  83         .max_pscl_lb_bw_pix_per_clk = 2,
  84         .max_lb_vscl_bw_pix_per_clk = 4,
  85         .max_vscl_hscl_bw_pix_per_clk = 4,
  86         .max_hscl_ratio = 6,
  87         .max_vscl_ratio = 6,
  88         .max_hscl_taps = 8,
  89         .max_vscl_taps = 8,
  90         .dpte_buffer_size_in_pte_reqs_luma = 64,
  91         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  92         .dispclk_ramp_margin_percent = 1,
  93         .max_inter_dcn_tile_repeaters = 8,
  94         .cursor_buffer_size = 16,
  95         .cursor_chunk_size = 2,
  96         .writeback_line_buffer_buffer_size = 0,
  97         .writeback_min_hscl_ratio = 1,
  98         .writeback_min_vscl_ratio = 1,
  99         .writeback_max_hscl_ratio = 1,
 100         .writeback_max_vscl_ratio = 1,
 101         .writeback_max_hscl_taps = 1,
 102         .writeback_max_vscl_taps = 1,
 103         .dppclk_delay_subtotal = 47,
 104         .dppclk_delay_scl = 50,
 105         .dppclk_delay_scl_lb_only = 16,
 106         .dppclk_delay_cnvc_formatter = 28,
 107         .dppclk_delay_cnvc_cursor = 6,
 108         .dispclk_delay_subtotal = 125,
 109         .dynamic_metadata_vm_enabled = false,
 110         .odm_combine_4to1_supported = false,
 111         .dcc_supported = true,
 112         .max_num_dp2p0_outputs = 2,
 113         .max_num_dp2p0_streams = 4,
 114 };
 115
 116 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 117         .clock_limits = {
 118                 {
 119                         .state = 0,
 120                         .dcfclk_mhz = 1564.0,
 121                         .fabricclk_mhz = 2500.0,
 122                         .dispclk_mhz = 2150.0,
 123                         .dppclk_mhz = 2150.0,
 124                         .phyclk_mhz = 810.0,
 125                         .phyclk_d18_mhz = 667.0,
 126                         .phyclk_d32_mhz = 625.0,
 127                         .socclk_mhz = 1200.0,
 128                         .dscclk_mhz = 716.667,
 129                         .dram_speed_mts = 18000.0,
 130                         .dtbclk_mhz = 1564.0,
 131                 },
 132         },
 133         .num_states = 1,
 134         .sr_exit_time_us = 42.97,
 135         .sr_enter_plus_exit_time_us = 49.94,
 136         .sr_exit_z8_time_us = 285.0,
 137         .sr_enter_plus_exit_z8_time_us = 320,
 138         .writeback_latency_us = 12.0,
 139         .round_trip_ping_latency_dcfclk_cycles = 263,
 140         .urgent_latency_pixel_data_only_us = 4.0,
 141         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 142         .urgent_latency_vm_data_only_us = 4.0,
 143         .fclk_change_latency_us = 25,
 144         .usr_retraining_latency_us = 2,
 145         .smn_latency_us = 2,
 146         .mall_allocated_for_dcn_mbytes = 64,
 147         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 148         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 149         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 150         .pct_ideal_sdp_bw_after_urgent = 90.0,
 151         .pct_ideal_fabric_bw_after_urgent = 67.0,
 152         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 153         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 154         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 155         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 156         .max_avg_sdp_bw_use_normal_percent = 80.0,
 157         .max_avg_fabric_bw_use_normal_percent = 60.0,
 158         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 159         .max_avg_dram_bw_use_normal_percent = 15.0,
 160         .num_chans = 24,
 161         .dram_channel_width_bytes = 2,
 162         .fabric_datapath_to_dcn_data_return_bytes = 64,
 163         .return_bus_width_bytes = 64,
 164         .downspread_percent = 0.38,
 165         .dcn_downspread_percent = 0.5,
 166         .dram_clock_change_latency_us = 400,
 167         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 168         .do_urgent_latency_adjustment = true,
 169         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 170         .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
 171 };
 172
 173 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
 174 {
 175         /* defaults */
 176         double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
 177         double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
 178         double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 179         double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 180         /* For min clocks use as reported by PM FW and report those as min */
 181         uint16_t min_uclk_mhz                   = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 182         uint16_t min_dcfclk_mhz                 = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 183         uint16_t setb_min_uclk_mhz              = min_uclk_mhz;
 184         uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
 185
 186         dc_assert_fp_enabled();
 187
 188         /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
 189         if (dcfclk_mhz_for_the_second_state)
 190                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
 191         else
 192                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 193
 194         if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
 195                 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 196
 197         /* Set A - Normal - default values */
 198         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
 199         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
 200         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 201         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
 202         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 203         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 204         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 205         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
 206         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
 207         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 208
 209         /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
 210         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
 211         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
 212         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 213         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 214         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 215         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 216         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 217         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
 218         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
 219
 220         /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 221         /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
 222         if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
 223                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
 224                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;
 225                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 226                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 227                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 228                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
 229                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 230                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 231                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 232                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 233                 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
 234                 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
 235                 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
 236                 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
 237                 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
 238                 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
 239                 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
 240                 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 241         }
 242         /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
 243         /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
 244         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 245         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
 246         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 247         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
 248         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
 249         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 250         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 251         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
 252         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
 253         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 254 }
 255
 256 /*
 257  * Finds dummy_latency_index when MCLK switching using firmware based
 258  * vblank stretch is enabled. This function will iterate through the
 259  * table of dummy pstate latencies until the lowest value that allows
 260  * dm_allow_self_refresh_and_mclk_switch to happen is found
 261  */
 262 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
 263                                                             struct dc_state *context,
 264                                                             display_e2e_pipe_params_st *pipes,
 265                                                             int pipe_cnt,
 266                                                             int vlevel)
 267 {
 268         const int max_latency_table_entries = 4;
 269         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 270         int dummy_latency_index = 0;
 271         enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 272
 273         dc_assert_fp_enabled();
 274
 275         while (dummy_latency_index < max_latency_table_entries) {
 276                 if (temp_clock_change_support != dm_dram_clock_change_unsupported)
 277                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 278                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
 279                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
 280                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
 281
 282                 /* for subvp + DRR case, if subvp pipes are still present we support pstate */
 283                 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported &&
 284                                 dcn32_subvp_in_use(dc, context))
 285                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 286
 287                 if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
 288                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
 289                         break;
 290
 291                 dummy_latency_index++;
 292         }
 293
 294         if (dummy_latency_index == max_latency_table_entries) {
 295                 ASSERT(dummy_latency_index != max_latency_table_entries);
 296                 /* If the execution gets here, it means dummy p_states are
 297                  * not possible. This should never happen and would mean
 298                  * something is severely wrong.
 299                  * Here we reset dummy_latency_index to 3, because it is
 300                  * better to have underflows than system crashes.
 301                  */
 302                 dummy_latency_index = max_latency_table_entries - 1;
 303         }
 304
 305         return dummy_latency_index;
 306 }
 307
 308 /**
 309  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
 310  * and populate pipe_ctx with those params.
 311  * @dc: [in] current dc state
 312  * @context: [in] new dc state
 313  * @pipes: [in] DML pipe params array
 314  * @pipe_cnt: [in] DML pipe count
 315  *
 316  * This function must be called AFTER the phantom pipes are added to context
 317  * and run through DML (so that the DLG params for the phantom pipes can be
 318  * populated), and BEFORE we program the timing for the phantom pipes.
 319  */
 320 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
 321                                               struct dc_state *context,
 322                                               display_e2e_pipe_params_st *pipes,
 323                                               int pipe_cnt)
 324 {
 325         uint32_t i, pipe_idx;
 326
 327         dc_assert_fp_enabled();
 328
 329         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 330                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 331
 332                 if (!pipe->stream)
 333                         continue;
 334
 335                 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 336                         pipes[pipe_idx].pipe.dest.vstartup_start =
 337                                 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 338                         pipes[pipe_idx].pipe.dest.vupdate_offset =
 339                                 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 340                         pipes[pipe_idx].pipe.dest.vupdate_width =
 341                                 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 342                         pipes[pipe_idx].pipe.dest.vready_offset =
 343                                 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 344                         pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 345                 }
 346                 pipe_idx++;
 347         }
 348 }
 349
 350 /**
 351  * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe
 352  * @context: [in] New DC state to be programmed
 353  * @pipe_e2e: [in] DML pipe end to end context
 354  *
 355  * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both
 356  * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is
 357  * determined by DPPClk requirements
 358  *
 359  * This function follows the same policy as DML:
 360  * - Check for ODM combine requirements / policy first
 361  * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and
 362  *   MPC is required
 363  *
 364  * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits).
 365  */
 366 uint8_t dcn32_predict_pipe_split(struct dc_state *context,
 367                                   display_e2e_pipe_params_st *pipe_e2e)
 368 {
 369         double pscl_throughput;
 370         double pscl_throughput_chroma;
 371         double dpp_clk_single_dpp, clock;
 372         double clk_frequency = 0.0;
 373         double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
 374         bool total_available_pipes_support = false;
 375         uint32_t number_of_dpp = 0;
 376         enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled;
 377         double req_dispclk_per_surface = 0;
 378         uint8_t num_splits = 0;
 379
 380         dc_assert_fp_enabled();
 381
 382         dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit,
 383                         pipe_e2e->pipe.dest.hactive,
 384                         pipe_e2e->dout.output_format,
 385                         pipe_e2e->dout.output_type,
 386                         pipe_e2e->pipe.dest.odm_combine_policy,
 387                         context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
 388                         context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
 389                         pipe_e2e->dout.dsc_enable != 0,
 390                         0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */
 391                         context->bw_ctx.dml.ip.max_num_dpp,
 392                         pipe_e2e->pipe.dest.pixel_rate_mhz,
 393                         context->bw_ctx.dml.soc.dcn_downspread_percent,
 394                         context->bw_ctx.dml.ip.dispclk_ramp_margin_percent,
 395                         context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz,
 396                         pipe_e2e->dout.dsc_slices,
 397                         /* Output */
 398                         &total_available_pipes_support,
 399                         &number_of_dpp,
 400                         &odm_mode,
 401                         &req_dispclk_per_surface);
 402
 403         dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio,
 404                         pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c,
 405                         pipe_e2e->pipe.scale_ratio_depth.vscl_ratio,
 406                         pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c,
 407                         context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
 408                         context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
 409                         pipe_e2e->pipe.dest.pixel_rate_mhz,
 410                         pipe_e2e->pipe.src.source_format,
 411                         pipe_e2e->pipe.scale_taps.htaps,
 412                         pipe_e2e->pipe.scale_taps.htaps_c,
 413                         pipe_e2e->pipe.scale_taps.vtaps,
 414                         pipe_e2e->pipe.scale_taps.vtaps_c,
 415                         /* Output */
 416                         &pscl_throughput, &pscl_throughput_chroma,
 417                         &dpp_clk_single_dpp);
 418
 419         clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);
 420
 421         if (clock > 0)
 422                 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock);
 423
 424         if (odm_mode == dm_odm_combine_mode_2to1)
 425                 num_splits = 1;
 426         else if (odm_mode == dm_odm_combine_mode_4to1)
 427                 num_splits = 3;
 428         else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz)
 429                 num_splits = 1;
 430
 431         return num_splits;
 432 }
 433
 434 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
 435 {
 436         float memory_bw_kbytes_sec;
 437         float fabric_bw_kbytes_sec;
 438         float sdp_bw_kbytes_sec;
 439         float limiting_bw_kbytes_sec;
 440
 441         memory_bw_kbytes_sec = entry->dram_speed_mts *
 442                                 dcn3_2_soc.num_chans *
 443                                 dcn3_2_soc.dram_channel_width_bytes *
 444                                 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 445
 446         fabric_bw_kbytes_sec = entry->fabricclk_mhz *
 447                                 dcn3_2_soc.return_bus_width_bytes *
 448                                 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 449
 450         sdp_bw_kbytes_sec = entry->dcfclk_mhz *
 451                                 dcn3_2_soc.return_bus_width_bytes *
 452                                 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 453
 454         limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
 455
 456         if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
 457                 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
 458
 459         if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
 460                 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
 461
 462         return limiting_bw_kbytes_sec;
 463 }
 464
 465 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
 466 {
 467         if (entry->dcfclk_mhz > 0) {
 468                 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 469
 470                 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 471                 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
 472                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 473         } else if (entry->fabricclk_mhz > 0) {
 474                 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 475
 476                 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 477                 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
 478                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 479         } else if (entry->dram_speed_mts > 0) {
 480                 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
 481                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 482
 483                 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 484                 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 485         }
 486 }
 487
 488 static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
 489                                     unsigned int *num_entries,
 490                                     struct _vcs_dpi_voltage_scaling_st *entry)
 491 {
 492         int i = 0;
 493         int index = 0;
 494
 495         dc_assert_fp_enabled();
 496
 497         if (*num_entries == 0) {
 498                 table[0] = *entry;
 499                 (*num_entries)++;
 500         } else {
 501                 while (entry->net_bw_in_kbytes_sec > table[index].net_bw_in_kbytes_sec) {
 502                         index++;
 503                         if (index >= *num_entries)
 504                                 break;
 505                 }
 506
 507                 for (i = *num_entries; i > index; i--)
 508                         table[i] = table[i - 1];
 509
 510                 table[index] = *entry;
 511                 (*num_entries)++;
 512         }
 513 }
 514
 515 /**
 516  * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream
 517  * @dc: current dc state
 518  * @context: new dc state
 519  * @ref_pipe: Main pipe for the phantom stream
 520  * @phantom_stream: target phantom stream state
 521  * @pipes: DML pipe params
 522  * @pipe_cnt: number of DML pipes
 523  * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
 524  *
 525  * Set timing params of the phantom stream based on calculated output from DML.
 526  * This function first gets the DML pipe index using the DC pipe index, then
 527  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
 528  * lines required for SubVP MCLK switching and assigns to the phantom stream
 529  * accordingly.
 530  *
 531  * - The number of SubVP lines calculated in DML does not take into account
 532  * FW processing delays and required pstate allow width, so we must include
 533  * that separately.
 534  *
 535  * - Set phantom backporch = vstartup of main pipe
 536  */
 537 void dcn32_set_phantom_stream_timing(struct dc *dc,
 538                                      struct dc_state *context,
 539                                      struct pipe_ctx *ref_pipe,
 540                                      struct dc_stream_state *phantom_stream,
 541                                      display_e2e_pipe_params_st *pipes,
 542                                      unsigned int pipe_cnt,
 543                                      unsigned int dc_pipe_idx)
 544 {
 545         unsigned int i, pipe_idx;
 546         struct pipe_ctx *pipe;
 547         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
 548         unsigned int num_dpp;
 549         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
 550         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 551         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
 552         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 553         struct dc_stream_state *main_stream = ref_pipe->stream;
 554
 555         dc_assert_fp_enabled();
 556
 557         // Find DML pipe index (pipe_idx) using dc_pipe_idx
 558         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 559                 pipe = &context->res_ctx.pipe_ctx[i];
 560
 561                 if (!pipe->stream)
 562                         continue;
 563
 564                 if (i == dc_pipe_idx)
 565                         break;
 566
 567                 pipe_idx++;
 568         }
 569
 570         // Calculate lines required for pstate allow width and FW processing delays
 571         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
 572                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
 573                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
 574                         (double)ref_pipe->stream->timing.h_total;
 575
 576         // Update clks_cfg for calling into recalculate
 577         pipes[0].clks_cfg.voltage = vlevel;
 578         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 579         pipes[0].clks_cfg.socclk_mhz = socclk;
 580
 581         // DML calculation for MALL region doesn't take into account FW delay
 582         // and required pstate allow width for multi-display cases
 583         /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned
 584          * to 2 swaths (i.e. 16 lines)
 585          */
 586         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
 587                                 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;
 588
 589         // W/A for DCC corruption with certain high resolution timings.
 590         // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive.
 591         num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]];
 592         phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0;
 593
 594         /* dc->debug.subvp_extra_lines 0 by default*/
 595         phantom_vactive += dc->debug.subvp_extra_lines;
 596
 597         // For backporch of phantom pipe, use vstartup of the main pipe
 598         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 599
 600         phantom_stream->dst.y = 0;
 601         phantom_stream->dst.height = phantom_vactive;
 602         /* When scaling, DML provides the end to end required number of lines for MALL.
 603          * dst.height is always correct for this case, but src.height is not which causes a
 604          * delta between main and phantom pipe scaling outputs. Need to adjust src.height on
 605          * phantom for this case.
 606          */
 607         phantom_stream->src.y = 0;
 608         phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height;
 609
 610         phantom_stream->timing.v_addressable = phantom_vactive;
 611         phantom_stream->timing.v_front_porch = 1;
 612         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
 613                                                 phantom_stream->timing.v_front_porch +
 614                                                 phantom_stream->timing.v_sync_width +
 615                                                 phantom_bp;
 616         phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
 617 }
 618
 619 /**
 620  * dcn32_get_num_free_pipes - Calculate number of free pipes
 621  * @dc: current dc state
 622  * @context: new dc state
 623  *
 624  * This function assumes that a "used" pipe is a pipe that has
 625  * both a stream and a plane assigned to it.
 626  *
 627  * Return: Number of free pipes available in the context
 628  */
 629 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
 630 {
 631         unsigned int i;
 632         unsigned int free_pipes = 0;
 633         unsigned int num_pipes = 0;
 634
 635         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 636                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 637
 638                 if (pipe->stream && !pipe->top_pipe) {
 639                         while (pipe) {
 640                                 num_pipes++;
 641                                 pipe = pipe->bottom_pipe;
 642                         }
 643                 }
 644         }
 645
 646         free_pipes = dc->res_pool->pipe_count - num_pipes;
 647         return free_pipes;
 648 }
 649
 650 /**
 651  * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP.
 652  * @dc: current dc state
 653  * @context: new dc state
 654  * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
 655  *
 656  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
 657  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
 658  * we are forcing SubVP P-State switching on the current config.
 659  *
 660  * The number of pipes used for the chosen surface must be less than or equal to the
 661  * number of free pipes available.
 662  *
 663  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
 664  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
 665  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
 666  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
 667  *
 668  * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
 669  */
 670 static bool dcn32_assign_subvp_pipe(struct dc *dc,
 671                                     struct dc_state *context,
 672                                     unsigned int *index)
 673 {
 674         unsigned int i, pipe_idx;
 675         unsigned int max_frame_time = 0;
 676         bool valid_assignment_found = false;
 677         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
 678         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 679
 680         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 681                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 682                 unsigned int num_pipes = 0;
 683                 unsigned int refresh_rate = 0;
 684
 685                 if (!pipe->stream)
 686                         continue;
 687
 688                 // Round up
 689                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 690                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 691                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
 692                 /* SubVP pipe candidate requirements:
 693                  * - Refresh rate < 120hz
 694                  * - Not able to switch in vactive naturally (switching in active means the
 695                  *   DET provides enough buffer to hide the P-State switch latency -- trying
 696                  *   to combine this with SubVP can cause issues with the scheduling).
 697                  * - Not TMZ surface
 698                  */
 699                 if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&
 700                                 !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &&
 701                                 (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&
 702                                 pipe->stream->mall_stream_config.type == SUBVP_NONE &&
 703                                 (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&
 704                                 !pipe->plane_state->address.tmz_surface &&
 705                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||
 706                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
 707                                                 dcn32_allow_subvp_with_active_margin(pipe)))) {
 708                         while (pipe) {
 709                                 num_pipes++;
 710                                 pipe = pipe->bottom_pipe;
 711                         }
 712
 713                         pipe = &context->res_ctx.pipe_ctx[i];
 714                         if (num_pipes <= free_pipes) {
 715                                 struct dc_stream_state *stream = pipe->stream;
 716                                 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
 717                                                 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
 718                                 if (frame_us > max_frame_time) {
 719                                         *index = i;
 720                                         max_frame_time = frame_us;
 721                                         valid_assignment_found = true;
 722                                 }
 723                         }
 724                 }
 725                 pipe_idx++;
 726         }
 727         return valid_assignment_found;
 728 }
 729
 730 /**
 731  * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP.
 732  * @dc: current dc state
 733  * @context: new dc state
 734  *
 735  * This function returns true if there are enough free pipes
 736  * to create the required phantom pipes for any given stream
 737  * (that does not already have phantom pipe assigned).
 738  *
 739  * e.g. For a 2 stream config where the first stream uses one
 740  * pipe and the second stream uses 2 pipes (i.e. pipe split),
 741  * this function will return true because there is 1 remaining
 742  * pipe which can be used as the phantom pipe for the non pipe
 743  * split pipe.
 744  *
 745  * Return:
 746  * True if there are enough free pipes to assign phantom pipes to at least one
 747  * stream that does not already have phantom pipes assigned. Otherwise false.
 748  */
 749 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
 750 {
 751         unsigned int i, split_cnt, free_pipes;
 752         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
 753         bool subvp_possible = false;
 754
 755         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 756                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 757
 758                 // Find the minimum pipe split count for non SubVP pipes
 759                 if (resource_is_pipe_type(pipe, OPP_HEAD) &&
 760                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 761                         split_cnt = 0;
 762                         while (pipe) {
 763                                 split_cnt++;
 764                                 pipe = pipe->bottom_pipe;
 765                         }
 766
 767                         if (split_cnt < min_pipe_split)
 768                                 min_pipe_split = split_cnt;
 769                 }
 770         }
 771
 772         free_pipes = dcn32_get_num_free_pipes(dc, context);
 773
 774         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
 775         // should not equal to the pipe_count)
 776         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
 777                 subvp_possible = true;
 778
 779         return subvp_possible;
 780 }
 781
 782 /**
 783  * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable
 784  * @dc: current dc state
 785  * @context: new dc state
 786  *
 787  * High level algorithm:
 788  * 1. Find longest microschedule length (in us) between the two SubVP pipes
 789  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
 790  * pipes still allows for the maximum microschedule to fit in the active
 791  * region for both pipes.
 792  *
 793  * Return: True if the SubVP + SubVP config is schedulable, false otherwise
 794  */
 795 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
 796 {
 797         struct pipe_ctx *subvp_pipes[2];
 798         struct dc_stream_state *phantom = NULL;
 799         uint32_t microschedule_lines = 0;
 800         uint32_t index = 0;
 801         uint32_t i;
 802         uint32_t max_microschedule_us = 0;
 803         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
 804
 805         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 806                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 807                 uint32_t time_us = 0;
 808
 809                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
 810                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
 811                  */
 812                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
 813                     pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 814                         phantom = pipe->stream->mall_stream_config.paired_stream;
 815                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
 816                                         phantom->timing.v_addressable;
 817
 818                         // Round up when calculating microschedule time (+ 1 at the end)
 819                         time_us = (microschedule_lines * phantom->timing.h_total) /
 820                                         (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
 821                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
 822                                                 dc->caps.subvp_fw_processing_delay_us + 1;
 823                         if (time_us > max_microschedule_us)
 824                                 max_microschedule_us = time_us;
 825
 826                         subvp_pipes[index] = pipe;
 827                         index++;
 828
 829                         // Maximum 2 SubVP pipes
 830                         if (index == 2)
 831                                 break;
 832                 }
 833         }
 834         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
 835                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 836         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
 837                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 838         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
 839                         subvp_pipes[0]->stream->timing.h_total) /
 840                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 841         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
 842                         subvp_pipes[1]->stream->timing.h_total) /
 843                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 844
 845         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
 846             (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
 847                 return true;
 848
 849         return false;
 850 }
 851
 852 /**
 853  * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable
 854  * @dc: current dc state
 855  * @context: new dc state
 856  *
 857  * High level algorithm:
 858  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 859  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
 860  * (the margin is equal to the MALL region + DRR margin (500us))
 861  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
 862  * then report the configuration as supported
 863  *
 864  * Return: True if the SubVP + DRR config is schedulable, false otherwise
 865  */
 866 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 867 {
 868         bool schedulable = false;
 869         uint32_t i;
 870         struct pipe_ctx *pipe = NULL;
 871         struct pipe_ctx *drr_pipe = NULL;
 872         struct dc_crtc_timing *main_timing = NULL;
 873         struct dc_crtc_timing *phantom_timing = NULL;
 874         struct dc_crtc_timing *drr_timing = NULL;
 875         int16_t prefetch_us = 0;
 876         int16_t mall_region_us = 0;
 877         int16_t drr_frame_us = 0;       // nominal frame time
 878         int16_t subvp_active_us = 0;
 879         int16_t stretched_drr_us = 0;
 880         int16_t drr_stretched_vblank_us = 0;
 881         int16_t max_vblank_mallregion = 0;
 882
 883         // Find SubVP pipe
 884         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 885                 pipe = &context->res_ctx.pipe_ctx[i];
 886
 887                 // We check for master pipe, but it shouldn't matter since we only need
 888                 // the pipe for timing info (stream should be same for any pipe splits)
 889                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 890                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 891                         continue;
 892
 893                 // Find the SubVP pipe
 894                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 895                         break;
 896         }
 897
 898         // Find the DRR pipe
 899         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 900                 drr_pipe = &context->res_ctx.pipe_ctx[i];
 901
 902                 // We check for master pipe only
 903                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 904                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 905                         continue;
 906
 907                 if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
 908                                 (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))
 909                         break;
 910         }
 911
 912         main_timing = &pipe->stream->timing;
 913         phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
 914         drr_timing = &drr_pipe->stream->timing;
 915         prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 916                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 917                         dc->caps.subvp_prefetch_end_to_mall_start_us;
 918         subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 919                         (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 920         drr_frame_us = drr_timing->v_total * drr_timing->h_total /
 921                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
 922         // P-State allow width and FW delays already included phantom_timing->v_addressable
 923         mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 924                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 925         stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 926         drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
 927                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
 928         max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
 929
 930         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
 931          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
 932          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 933          * and the max of (VBLANK blanking time, MALL region)).
 934          */
 935         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
 936                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
 937                 schedulable = true;
 938
 939         return schedulable;
 940 }
 941
 942
 943 /**
 944  * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable
 945  * @dc: current dc state
 946  * @context: new dc state
 947  *
 948  * High level algorithm:
 949  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
 950  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
 951  * then report the configuration as supported
 952  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
 953  *
 954  * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
 955  */
 956 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
 957 {
 958         struct pipe_ctx *pipe = NULL;
 959         struct pipe_ctx *subvp_pipe = NULL;
 960         bool found = false;
 961         bool schedulable = false;
 962         uint32_t i = 0;
 963         uint8_t vblank_index = 0;
 964         uint16_t prefetch_us = 0;
 965         uint16_t mall_region_us = 0;
 966         uint16_t vblank_frame_us = 0;
 967         uint16_t subvp_active_us = 0;
 968         uint16_t vblank_blank_us = 0;
 969         uint16_t max_vblank_mallregion = 0;
 970         struct dc_crtc_timing *main_timing = NULL;
 971         struct dc_crtc_timing *phantom_timing = NULL;
 972         struct dc_crtc_timing *vblank_timing = NULL;
 973
 974         /* For SubVP + VBLANK/DRR cases, we assume there can only be
 975          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
 976          * is supported, it is either a single VBLANK case or two VBLANK
 977          * displays which are synchronized (in which case they have identical
 978          * timings).
 979          */
 980         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 981                 pipe = &context->res_ctx.pipe_ctx[i];
 982
 983                 // We check for master pipe, but it shouldn't matter since we only need
 984                 // the pipe for timing info (stream should be same for any pipe splits)
 985                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 986                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 987                         continue;
 988
 989                 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 990                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
 991                         vblank_index = i;
 992                         found = true;
 993                 }
 994
 995                 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 996                         subvp_pipe = pipe;
 997         }
 998         if (found) {
 999                 main_timing = &subvp_pipe->stream->timing;
1000                 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
1001                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
1002                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
1003                 // Also include the prefetch end to mallstart delay time
1004                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
1005                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
1006                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
1007                 // P-State allow width and FW delays already included phantom_timing->v_addressable
1008                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
1009                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
1010                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
1011                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
1012                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
1013                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
1014                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
1015                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
1016                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
1017
1018                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
1019                 // and the max of (VBLANK blanking time, MALL region)
1020                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
1021                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
1022                         schedulable = true;
1023         }
1024         return schedulable;
1025 }
1026
1027 /**
1028  * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible
1029  *
1030  * @dc: Current DC state
1031  * @context: New DC state to be programmed
1032  *
1033  * SubVP + SubVP is admissible under the following conditions:
1034  * - All SubVP pipes are < 120Hz OR
1035  * - All SubVP pipes are >= 120hz
1036  *
1037  * Return: True if admissible, false otherwise
1038  */
1039 static bool subvp_subvp_admissable(struct dc *dc,
1040                                 struct dc_state *context)
1041 {
1042         bool result = false;
1043         uint32_t i;
1044         uint8_t subvp_count = 0;
1045         uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
1046         uint64_t refresh_rate = 0;
1047
1048         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1049                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1050
1051                 if (!pipe->stream)
1052                         continue;
1053
1054                 if (pipe->plane_state && !pipe->top_pipe &&
1055                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
1056                         refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
1057                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
1058                         refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
1059                         refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
1060
1061                         if ((uint32_t)refresh_rate < min_refresh)
1062                                 min_refresh = (uint32_t)refresh_rate;
1063                         if ((uint32_t)refresh_rate > max_refresh)
1064                                 max_refresh = (uint32_t)refresh_rate;
1065                         subvp_count++;
1066                 }
1067         }
1068
1069         if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
1070                 (min_refresh >= subvp_high_refresh_list.min_refresh &&
1071                                 max_refresh <= subvp_high_refresh_list.max_refresh)))
1072                 result = true;
1073
1074         return result;
1075 }
1076
1077 /**
1078  * subvp_validate_static_schedulability - Check which SubVP case is calculated
1079  * and handle static analysis based on the case.
1080  * @dc: current dc state
1081  * @context: new dc state
1082  * @vlevel: Voltage level calculated by DML
1083  *
1084  * Three cases:
1085  * 1. SubVP + SubVP
1086  * 2. SubVP + VBLANK (DRR checked internally)
1087  * 3. SubVP + VACTIVE (currently unsupported)
1088  *
1089  * Return: True if statically schedulable, false otherwise
1090  */
1091 static bool subvp_validate_static_schedulability(struct dc *dc,
1092                                 struct dc_state *context,
1093                                 int vlevel)
1094 {
1095         bool schedulable = false;
1096         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1097         uint32_t i, pipe_idx;
1098         uint8_t subvp_count = 0;
1099         uint8_t vactive_count = 0;
1100         uint8_t non_subvp_pipes = 0;
1101
1102         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1103                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1104
1105                 if (!pipe->stream)
1106                         continue;
1107
1108                 if (pipe->plane_state && !pipe->top_pipe) {
1109                         if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
1110                                 subvp_count++;
1111                         if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1112                                 non_subvp_pipes++;
1113                         }
1114                 }
1115
1116                 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE
1117                 // switching (SubVP + VACTIVE unsupported). In situations where we force
1118                 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
1119                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
1120                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1121                         vactive_count++;
1122                 }
1123                 pipe_idx++;
1124         }
1125
1126         if (subvp_count == 2) {
1127                 // Static schedulability check for SubVP + SubVP case
1128                 schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);
1129         } else if (subvp_count == 1 && non_subvp_pipes == 0) {
1130                 // Single SubVP configs will be supported by default as long as it's suppported by DML
1131                 schedulable = true;
1132         } else if (subvp_count == 1 && non_subvp_pipes == 1) {
1133                 if (dcn32_subvp_drr_admissable(dc, context))
1134                         schedulable = subvp_drr_schedulable(dc, context);
1135                 else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
1136                         schedulable = subvp_vblank_schedulable(dc, context);
1137         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
1138                         vactive_count > 0) {
1139                 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default.
1140                 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count.
1141                 // SubVP + VACTIVE currently unsupported
1142                 schedulable = false;
1143         }
1144         return schedulable;
1145 }
1146
1147 static void assign_subvp_index(struct dc *dc, struct dc_state *context)
1148 {
1149         int i;
1150         int index = 0;
1151
1152         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1153                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1154
1155                 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&
1156                                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
1157                         pipe_ctx->subvp_index = index++;
1158                 } else {
1159                         pipe_ctx->subvp_index = 0;
1160                 }
1161         }
1162 }
1163
1164 static void dcn32_full_validate_bw_helper(struct dc *dc,
1165                                    struct dc_state *context,
1166                                    display_e2e_pipe_params_st *pipes,
1167                                    int *vlevel,
1168                                    int *split,
1169                                    bool *merge,
1170                                    int *pipe_cnt)
1171 {
1172         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1173         unsigned int dc_pipe_idx = 0;
1174         int i = 0;
1175         bool found_supported_config = false;
1176
1177         dc_assert_fp_enabled();
1178
1179         /*
1180          * DML favors voltage over p-state, but we're more interested in
1181          * supporting p-state over voltage. We can't support p-state in
1182          * prefetch mode > 0 so try capping the prefetch mode to start.
1183          * Override present for testing.
1184          */
1185         if (dc->debug.dml_disallow_alternate_prefetch_modes)
1186                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1187                         dm_prefetch_support_uclk_fclk_and_stutter;
1188         else
1189                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1190                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1191
1192         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1193         /* This may adjust vlevel and maxMpcComb */
1194         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1195                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1196                 vba->VoltageLevel = *vlevel;
1197         }
1198
1199         /* Conditions for setting up phantom pipes for SubVP:
1200          * 1. Not force disable SubVP
1201          * 2. Full update (i.e. !fast_validate)
1202          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1203          * 4. Display configuration passes validation
1204          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
1205          */
1206         if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
1207             !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) &&
1208                 (*vlevel == context->bw_ctx.dml.soc.num_states ||
1209             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
1210             dc->debug.force_subvp_mclk_switch)) {
1211
1212                 dcn32_merge_pipes_for_subvp(dc, context);
1213                 memset(merge, 0, MAX_PIPES * sizeof(bool));
1214
1215                 /* to re-initialize viewport after the pipe merge */
1216                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1217                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1218
1219                         if (!pipe_ctx->plane_state || !pipe_ctx->stream)
1220                                 continue;
1221
1222                         resource_build_scaling_params(pipe_ctx);
1223                 }
1224
1225                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
1226                         dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
1227                         /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1228                          * Adding phantom pipes won't change the validation result, so change the DML input param
1229                          * for P-State support before adding phantom pipes and recalculating the DML result.
1230                          * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
1231                          * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
1232                          * enough to support MCLK switching.
1233                          */
1234                         if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1235                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==
1236                                         dm_prefetch_support_uclk_fclk_and_stutter) {
1237                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1238                                                                 dm_prefetch_support_fclk_and_stutter;
1239                                 /* There are params (such as FabricClock) that need to be recalculated
1240                                  * after validation fails (otherwise it will be 0). Calculation for
1241                                  * phantom vactive requires call into DML, so we must ensure all the
1242                                  * vba params are valid otherwise we'll get incorrect phantom vactive.
1243                                  */
1244                                 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1245                         }
1246
1247                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1248
1249                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1250                         // Populate dppclk to trigger a recalculate in dml_get_voltage_level
1251                         // so the phantom pipe DLG params can be assigned correctly.
1252                         pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1253                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1254
1255                         /* Check that vlevel requested supports pstate or not
1256                          * if not, select the lowest vlevel that supports it
1257                          */
1258                         for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
1259                                 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) {
1260                                         *vlevel = i;
1261                                         break;
1262                                 }
1263                         }
1264
1265                         if (*vlevel < context->bw_ctx.dml.soc.num_states
1266                             && subvp_validate_static_schedulability(dc, context, *vlevel))
1267                                 found_supported_config = true;
1268                         if (found_supported_config) {
1269                                 // For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
1270                                 if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {
1271                                         /* find lowest vlevel that supports the config */
1272                                         for (i = *vlevel; i >= 0; i--) {
1273                                                 if (vba->ModeSupport[i][vba->maxMpcComb]) {
1274                                                         *vlevel = i;
1275                                                 } else {
1276                                                         break;
1277                                                 }
1278                                         }
1279                                 }
1280                         }
1281                 }
1282
1283                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
1284                 // remove phantom pipes and repopulate dml pipes
1285                 if (!found_supported_config) {
1286                         dc->res_pool->funcs->remove_phantom_pipes(dc, context, false);
1287                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1288                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1289
1290                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1291                         /* This may adjust vlevel and maxMpcComb */
1292                         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1293                                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1294                                 vba->VoltageLevel = *vlevel;
1295                         }
1296                 } else {
1297                         // Most populate phantom DLG params before programming hardware / timing for phantom pipe
1298                         dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1299
1300                         /* Call validate_apply_pipe_split flags after calling DML getters for
1301                          * phantom dlg params, or some of the VBA params indicating pipe split
1302                          * can be overwritten by the getters.
1303                          *
1304                          * When setting up SubVP config, all pipes are merged before attempting to
1305                          * add phantom pipes. If pipe split (ODM / MPC) is required, both the main
1306                          * and phantom pipes will be split in the regular pipe splitting sequence.
1307                          */
1308                         memset(split, 0, MAX_PIPES * sizeof(int));
1309                         memset(merge, 0, MAX_PIPES * sizeof(bool));
1310                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1311                         vba->VoltageLevel = *vlevel;
1312                         // Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1313                         // until driver has acquired the DMCUB lock to do it safely.
1314                         assign_subvp_index(dc, context);
1315                 }
1316         }
1317 }
1318
1319 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
1320 {
1321         int i;
1322
1323         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1324                 if (!context->res_ctx.pipe_ctx[i].stream)
1325                         continue;
1326                 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1327                         return true;
1328         }
1329         return false;
1330 }
1331
1332 static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
1333 {
1334         struct dc_crtc_timing patched_crtc_timing;
1335         uint32_t asic_blank_end   = 0;
1336         uint32_t asic_blank_start = 0;
1337         uint32_t newVstartup      = 0;
1338
1339         patched_crtc_timing = *dc_crtc_timing;
1340
1341         if (patched_crtc_timing.flags.INTERLACE == 1) {
1342                 if (patched_crtc_timing.v_front_porch < 2)
1343                         patched_crtc_timing.v_front_porch = 2;
1344         } else {
1345                 if (patched_crtc_timing.v_front_porch < 1)
1346                         patched_crtc_timing.v_front_porch = 1;
1347         }
1348
1349         /* blank_start = frame end - front porch */
1350         asic_blank_start = patched_crtc_timing.v_total -
1351                                         patched_crtc_timing.v_front_porch;
1352
1353         /* blank_end = blank_start - active */
1354         asic_blank_end = asic_blank_start -
1355                                         patched_crtc_timing.v_border_bottom -
1356                                         patched_crtc_timing.v_addressable -
1357                                         patched_crtc_timing.v_border_top;
1358
1359         newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);
1360
1361         *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
1362 }
1363
1364 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
1365                                        display_e2e_pipe_params_st *pipes,
1366                                        int pipe_cnt, int vlevel)
1367 {
1368         int i, pipe_idx, active_hubp_count = 0;
1369         bool usr_retraining_support = false;
1370         bool unbounded_req_enabled = false;
1371         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1372
1373         dc_assert_fp_enabled();
1374
1375         /* Writeback MCIF_WB arbitration parameters */
1376         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1377
1378         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1379         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1380         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1381         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1382         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1383         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1384         context->bw_ctx.bw.dcn.clk.p_state_change_support =
1385                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1386                                         != dm_dram_clock_change_unsupported;
1387
1388         /* Pstate change might not be supported by hardware, but it might be
1389          * possible with firmware driven vertical blank stretching.
1390          */
1391         context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1392
1393         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1394         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1395         context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
1396         if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
1397                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
1398         else
1399                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1400
1401         usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1402         ASSERT(usr_retraining_support);
1403
1404         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1405                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1406
1407         unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
1408
1409         if (unbounded_req_enabled && pipe_cnt > 1) {
1410                 // Unbounded requesting should not ever be used when more than 1 pipe is enabled.
1411                 ASSERT(false);
1412                 unbounded_req_enabled = false;
1413         }
1414
1415         context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;
1416         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;
1417         context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;
1418
1419         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1420                 if (!context->res_ctx.pipe_ctx[i].stream)
1421                         continue;
1422                 if (context->res_ctx.pipe_ctx[i].plane_state)
1423                         active_hubp_count++;
1424                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
1425                                 pipe_idx);
1426                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1427                                 pipe_idx);
1428                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
1429                                 pipe_idx);
1430                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1431                                 pipe_idx);
1432
1433                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1434                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1435                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1436                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
1437                 } else {
1438                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,
1439                                                         pipe_idx);
1440                         context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;
1441                 }
1442
1443                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1444                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1445                 if (context->res_ctx.pipe_ctx[i].plane_state)
1446                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1447                 else
1448                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
1449                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1450
1451                 context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1452
1453                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0)
1454                         context->res_ctx.pipe_ctx[i].has_vactive_margin = true;
1455                 else
1456                         context->res_ctx.pipe_ctx[i].has_vactive_margin = false;
1457
1458                 /* MALL Allocation Sizes */
1459                 /* count from active, top pipes per plane only */
1460                 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&
1461                                 (context->res_ctx.pipe_ctx[i].top_pipe == NULL ||
1462                                 context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&
1463                                 context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1464                         /* SS: all active surfaces stored in MALL */
1465                         if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) {
1466                                 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1467
1468                                 if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {
1469                                         /* SS PSR On: all active surfaces part of streams not supporting PSR stored in MALL */
1470                                         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1471                                 }
1472                         } else {
1473                                 /* SUBVP: phantom surfaces only stored in MALL */
1474                                 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1475                         }
1476                 }
1477
1478                 if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
1479                         dcn20_adjust_freesync_v_startup(
1480                                 &context->res_ctx.pipe_ctx[i].stream->timing,
1481                                 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
1482
1483                 pipe_idx++;
1484         }
1485         /* If DCN isn't making memory requests we can allow pstate change and lower clocks */
1486         if (!active_hubp_count) {
1487                 context->bw_ctx.bw.dcn.clk.socclk_khz = 0;
1488                 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1489                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;
1490                 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;
1491                 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;
1492                 context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
1493                 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
1494                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1495         }
1496         /*save a original dppclock copy*/
1497         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1498         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1499         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
1500                         * 1000;
1501         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
1502                         * 1000;
1503
1504         context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);
1505
1506         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes;
1507
1508         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1509                 if (context->res_ctx.pipe_ctx[i].stream)
1510                         context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;
1511         }
1512
1513         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1514
1515                 if (!context->res_ctx.pipe_ctx[i].stream)
1516                         continue;
1517
1518                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
1519                                 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
1520                                 pipe_cnt, pipe_idx);
1521
1522                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
1523                                 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1524                 pipe_idx++;
1525         }
1526 }
1527
1528 static struct pipe_ctx *dcn32_find_split_pipe(
1529                 struct dc *dc,
1530                 struct dc_state *context,
1531                 int old_index)
1532 {
1533         struct pipe_ctx *pipe = NULL;
1534         int i;
1535
1536         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1537                 pipe = &context->res_ctx.pipe_ctx[old_index];
1538                 pipe->pipe_idx = old_index;
1539         }
1540
1541         if (!pipe)
1542                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1543                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1544                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1545                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1546                                         pipe = &context->res_ctx.pipe_ctx[i];
1547                                         pipe->pipe_idx = i;
1548                                         break;
1549                                 }
1550                         }
1551                 }
1552
1553         /*
1554          * May need to fix pipes getting tossed from 1 opp to another on flip
1555          * Add for debugging transient underflow during topology updates:
1556          * ASSERT(pipe);
1557          */
1558         if (!pipe)
1559                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1560                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1561                                 pipe = &context->res_ctx.pipe_ctx[i];
1562                                 pipe->pipe_idx = i;
1563                                 break;
1564                         }
1565                 }
1566
1567         return pipe;
1568 }
1569
1570 static bool dcn32_split_stream_for_mpc_or_odm(
1571                 const struct dc *dc,
1572                 struct resource_context *res_ctx,
1573                 struct pipe_ctx *pri_pipe,
1574                 struct pipe_ctx *sec_pipe,
1575                 bool odm)
1576 {
1577         int pipe_idx = sec_pipe->pipe_idx;
1578         const struct resource_pool *pool = dc->res_pool;
1579
1580         DC_LOGGER_INIT(dc->ctx->logger);
1581
1582         if (odm && pri_pipe->plane_state) {
1583                 /* ODM + window MPO, where MPO window is on left half only */
1584                 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
1585                                 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {
1586
1587                         DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n",
1588                                         __func__,
1589                                         pri_pipe->pipe_idx);
1590                         return true;
1591                 }
1592
1593                 /* ODM + window MPO, where MPO window is on right half only */
1594                 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x +  pri_pipe->stream->src.width/2) {
1595
1596                         DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n",
1597                                         __func__,
1598                                         pri_pipe->pipe_idx);
1599                         return true;
1600                 }
1601         }
1602
1603         *sec_pipe = *pri_pipe;
1604
1605         sec_pipe->pipe_idx = pipe_idx;
1606         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1607         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1608         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1609         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1610         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1611         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1612         sec_pipe->stream_res.dsc = NULL;
1613         if (odm) {
1614                 if (pri_pipe->next_odm_pipe) {
1615                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1616                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1617                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1618                 }
1619                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1620                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1621                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1622                 }
1623                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1624                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1625                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1626                 }
1627                 pri_pipe->next_odm_pipe = sec_pipe;
1628                 sec_pipe->prev_odm_pipe = pri_pipe;
1629                 ASSERT(sec_pipe->top_pipe == NULL);
1630
1631                 if (!sec_pipe->top_pipe)
1632                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1633                 else
1634                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1635                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1636                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1637                         ASSERT(sec_pipe->stream_res.dsc);
1638                         if (sec_pipe->stream_res.dsc == NULL)
1639                                 return false;
1640                 }
1641         } else {
1642                 if (pri_pipe->bottom_pipe) {
1643                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1644                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1645                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1646                 }
1647                 pri_pipe->bottom_pipe = sec_pipe;
1648                 sec_pipe->top_pipe = pri_pipe;
1649
1650                 ASSERT(pri_pipe->plane_state);
1651         }
1652
1653         return true;
1654 }
1655
1656 bool dcn32_internal_validate_bw(struct dc *dc,
1657                                 struct dc_state *context,
1658                                 display_e2e_pipe_params_st *pipes,
1659                                 int *pipe_cnt_out,
1660                                 int *vlevel_out,
1661                                 bool fast_validate)
1662 {
1663         bool out = false;
1664         bool repopulate_pipes = false;
1665         int split[MAX_PIPES] = { 0 };
1666         bool merge[MAX_PIPES] = { false };
1667         bool newly_split[MAX_PIPES] = { false };
1668         int pipe_cnt, i, pipe_idx;
1669         int vlevel = context->bw_ctx.dml.soc.num_states;
1670         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1671
1672         dc_assert_fp_enabled();
1673
1674         ASSERT(pipes);
1675         if (!pipes)
1676                 return false;
1677
1678         // For each full update, remove all existing phantom pipes first
1679         dc->res_pool->funcs->remove_phantom_pipes(dc, context, fast_validate);
1680
1681         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1682
1683         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1684
1685         if (!pipe_cnt) {
1686                 out = true;
1687                 goto validate_out;
1688         }
1689
1690         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1691         context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);
1692
1693         if (!fast_validate)
1694                 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
1695
1696         if (fast_validate ||
1697                         (dc->debug.dml_disallow_alternate_prefetch_modes &&
1698                         (vlevel == context->bw_ctx.dml.soc.num_states ||
1699                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
1700                 /*
1701                  * If dml_disallow_alternate_prefetch_modes is false, then we have already
1702                  * tried alternate prefetch modes during full validation.
1703                  *
1704                  * If mode is unsupported or there is no p-state support, then
1705                  * fall back to favouring voltage.
1706                  *
1707                  * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try
1708                  * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)
1709                  */
1710                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1711                         dm_prefetch_support_none;
1712
1713                 context->bw_ctx.dml.validate_max_state = fast_validate;
1714                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1715
1716                 context->bw_ctx.dml.validate_max_state = false;
1717
1718                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1719                         memset(split, 0, sizeof(split));
1720                         memset(merge, 0, sizeof(merge));
1721                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1722                         // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML
1723                         vba->VoltageLevel = vlevel;
1724                 }
1725         }
1726
1727         dml_log_mode_support_params(&context->bw_ctx.dml);
1728
1729         if (vlevel == context->bw_ctx.dml.soc.num_states)
1730                 goto validate_fail;
1731
1732         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1733                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1734                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1735
1736                 if (!pipe->stream)
1737                         continue;
1738
1739                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1740                                 && !dc->config.enable_windowed_mpo_odm
1741                                 && pipe->plane_state && mpo_pipe
1742                                 && memcmp(&mpo_pipe->plane_state->clip_rect,
1743                                                 &pipe->stream->src,
1744                                                 sizeof(struct rect)) != 0) {
1745                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1746                         goto validate_fail;
1747                 }
1748                 pipe_idx++;
1749         }
1750
1751         /* merge pipes if necessary */
1752         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1753                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1754
1755                 /*skip pipes that don't need merging*/
1756                 if (!merge[i])
1757                         continue;
1758
1759                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1760                 if (pipe->prev_odm_pipe) {
1761                         /*split off odm pipe*/
1762                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1763                         if (pipe->next_odm_pipe)
1764                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1765
1766                         /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/
1767                         if (pipe->bottom_pipe) {
1768                                 if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {
1769                                         /*MPC split rules will handle this case*/
1770                                         pipe->bottom_pipe->top_pipe = NULL;
1771                                 } else {
1772                                         /* when merging an ODM pipes, the bottom MPC pipe must now point to
1773                                          * the previous ODM pipe and its associated stream assets
1774                                          */
1775                                         if (pipe->prev_odm_pipe->bottom_pipe) {
1776                                                 /* 3 plane MPO*/
1777                                                 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;
1778                                                 pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;
1779                                         } else {
1780                                                 /* 2 plane MPO*/
1781                                                 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;
1782                                                 pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;
1783                                         }
1784
1785                                         memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));
1786                                 }
1787                         }
1788
1789                         if (pipe->top_pipe) {
1790                                 pipe->top_pipe->bottom_pipe = NULL;
1791                         }
1792
1793                         pipe->bottom_pipe = NULL;
1794                         pipe->next_odm_pipe = NULL;
1795                         pipe->plane_state = NULL;
1796                         pipe->stream = NULL;
1797                         pipe->top_pipe = NULL;
1798                         pipe->prev_odm_pipe = NULL;
1799                         if (pipe->stream_res.dsc)
1800                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1801                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1802                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1803                         memset(&pipe->link_res, 0, sizeof(pipe->link_res));
1804                         repopulate_pipes = true;
1805                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1806                         struct pipe_ctx *top_pipe = pipe->top_pipe;
1807                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1808
1809                         top_pipe->bottom_pipe = bottom_pipe;
1810                         if (bottom_pipe)
1811                                 bottom_pipe->top_pipe = top_pipe;
1812
1813                         pipe->top_pipe = NULL;
1814                         pipe->bottom_pipe = NULL;
1815                         pipe->plane_state = NULL;
1816                         pipe->stream = NULL;
1817                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1818                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1819                         memset(&pipe->link_res, 0, sizeof(pipe->link_res));
1820                         repopulate_pipes = true;
1821                 } else
1822                         ASSERT(0); /* Should never try to merge master pipe */
1823
1824         }
1825
1826         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1827                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1828                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1829                 struct pipe_ctx *hsplit_pipe = NULL;
1830                 bool odm;
1831                 int old_index = -1;
1832
1833                 if (!pipe->stream || newly_split[i])
1834                         continue;
1835
1836                 pipe_idx++;
1837                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1838
1839                 if (!pipe->plane_state && !odm)
1840                         continue;
1841
1842                 if (split[i]) {
1843                         if (odm) {
1844                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1845                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1846                                 else if (old_pipe->next_odm_pipe)
1847                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
1848                         } else {
1849                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1850                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1851                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1852                                 else if (old_pipe->bottom_pipe &&
1853                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1854                                         old_index = old_pipe->bottom_pipe->pipe_idx;
1855                         }
1856                         hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
1857                         ASSERT(hsplit_pipe);
1858                         if (!hsplit_pipe)
1859                                 goto validate_fail;
1860
1861                         if (!dcn32_split_stream_for_mpc_or_odm(
1862                                         dc, &context->res_ctx,
1863                                         pipe, hsplit_pipe, odm))
1864                                 goto validate_fail;
1865
1866                         newly_split[hsplit_pipe->pipe_idx] = true;
1867                         repopulate_pipes = true;
1868                 }
1869                 if (split[i] == 4) {
1870                         struct pipe_ctx *pipe_4to1;
1871
1872                         if (odm && old_pipe->next_odm_pipe)
1873                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
1874                         else if (!odm && old_pipe->bottom_pipe &&
1875                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1876                                 old_index = old_pipe->bottom_pipe->pipe_idx;
1877                         else
1878                                 old_index = -1;
1879                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1880                         ASSERT(pipe_4to1);
1881                         if (!pipe_4to1)
1882                                 goto validate_fail;
1883                         if (!dcn32_split_stream_for_mpc_or_odm(
1884                                         dc, &context->res_ctx,
1885                                         pipe, pipe_4to1, odm))
1886                                 goto validate_fail;
1887                         newly_split[pipe_4to1->pipe_idx] = true;
1888
1889                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1890                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1891                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1892                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1893                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1894                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1895                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1896                         else
1897                                 old_index = -1;
1898                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1899                         ASSERT(pipe_4to1);
1900                         if (!pipe_4to1)
1901                                 goto validate_fail;
1902                         if (!dcn32_split_stream_for_mpc_or_odm(
1903                                         dc, &context->res_ctx,
1904                                         hsplit_pipe, pipe_4to1, odm))
1905                                 goto validate_fail;
1906                         newly_split[pipe_4to1->pipe_idx] = true;
1907                 }
1908                 if (odm)
1909                         dcn20_build_mapped_resource(dc, context, pipe->stream);
1910         }
1911
1912         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1913                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1914
1915                 if (pipe->plane_state) {
1916                         if (!resource_build_scaling_params(pipe))
1917                                 goto validate_fail;
1918                 }
1919         }
1920
1921         /* Actual dsc count per stream dsc validation*/
1922         if (!dcn20_validate_dsc(dc, context)) {
1923                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1924                 goto validate_fail;
1925         }
1926
1927         if (repopulate_pipes) {
1928                 int flag_max_mpc_comb = vba->maxMpcComb;
1929                 int flag_vlevel = vlevel;
1930                 int i;
1931
1932                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1933
1934                 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case
1935                  * we have to re-calculate the DET allocation and run through DML once more to
1936                  * ensure all the params are calculated correctly. We do not need to run the
1937                  * pipe split check again after this call (pipes are already split / merged).
1938                  * */
1939                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1940                                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1941                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1942                 if (vlevel == context->bw_ctx.dml.soc.num_states) {
1943                         /* failed after DET size changes */
1944                         goto validate_fail;
1945                 } else if (flag_max_mpc_comb == 0 &&
1946                                 flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {
1947                         /* check the context constructed with pipe split flags is still valid*/
1948                         bool flags_valid = false;
1949                         for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
1950                                 if (vba->ModeSupport[i][flag_max_mpc_comb]) {
1951                                         vba->maxMpcComb = flag_max_mpc_comb;
1952                                         vba->VoltageLevel = i;
1953                                         vlevel = i;
1954                                         flags_valid = true;
1955                                 }
1956                         }
1957
1958                         /* this should never happen */
1959                         if (!flags_valid)
1960                                 goto validate_fail;
1961                 }
1962         }
1963         *vlevel_out = vlevel;
1964         *pipe_cnt_out = pipe_cnt;
1965
1966         out = true;
1967         goto validate_out;
1968
1969 validate_fail:
1970         out = false;
1971
1972 validate_out:
1973         return out;
1974 }
1975
1976
1977 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
1978                                 display_e2e_pipe_params_st *pipes,
1979                                 int pipe_cnt,
1980                                 int vlevel)
1981 {
1982         int i, pipe_idx, vlevel_temp = 0;
1983         double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
1984         double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1985         double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;
1986         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
1987                         dm_dram_clock_change_unsupported;
1988         unsigned int dummy_latency_index = 0;
1989         int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
1990         unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
1991         bool subvp_in_use = dcn32_subvp_in_use(dc, context);
1992         unsigned int min_dram_speed_mts_margin;
1993         bool need_fclk_lat_as_dummy = false;
1994         bool is_subvp_p_drr = false;
1995         struct dc_stream_state *fpo_candidate_stream = NULL;
1996
1997         dc_assert_fp_enabled();
1998
1999         /* need to find dummy latency index for subvp */
2000         if (subvp_in_use) {
2001                 /* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */
2002                 if (!pstate_en) {
2003                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2004                         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter;
2005                         pstate_en = true;
2006                         is_subvp_p_drr = true;
2007                 }
2008                 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2009                                                 context, pipes, pipe_cnt, vlevel);
2010
2011                 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so prefetch is
2012                  * scheduled correctly to account for dummy pstate.
2013                  */
2014                 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2015                         need_fclk_lat_as_dummy = true;
2016                         context->bw_ctx.dml.soc.fclk_change_latency_us =
2017                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2018                 }
2019                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2020                                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2021                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2022                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2023                 if (is_subvp_p_drr) {
2024                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2025                 }
2026         }
2027
2028         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2029         for (i = 0; i < context->stream_count; i++) {
2030                 if (context->streams[i])
2031                         context->streams[i]->fpo_in_use = false;
2032         }
2033
2034         if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&
2035                         pstate_en && vlevel != 0)) {
2036                 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */
2037                 fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
2038                 if (fpo_candidate_stream) {
2039                         fpo_candidate_stream->fpo_in_use = true;
2040                         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;
2041                 }
2042
2043                 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2044                         dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2045                                 context, pipes, pipe_cnt, vlevel);
2046
2047                         /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
2048                          * we reinstate the original dram_clock_change_latency_us on the context
2049                          * and all variables that may have changed up to this point, except the
2050                          * newly found dummy_latency_index
2051                          */
2052                         context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2053                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2054                         /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so
2055                          * prefetch is scheduled correctly to account for dummy pstate.
2056                          */
2057                         if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2058                                 need_fclk_lat_as_dummy = true;
2059                                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2060                                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2061                         }
2062                         dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false);
2063                         if (vlevel_temp < vlevel) {
2064                                 vlevel = vlevel_temp;
2065                                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2066                                 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2067                                 pstate_en = true;
2068                                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank;
2069                         } else {
2070                                 /* Restore FCLK latency and re-run validation to go back to original validation
2071                                  * output if we find that enabling FPO does not give us any benefit (i.e. lower
2072                                  * voltage level)
2073                                  */
2074                                 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2075                                 for (i = 0; i < context->stream_count; i++) {
2076                                         if (context->streams[i])
2077                                                 context->streams[i]->fpo_in_use = false;
2078                                 }
2079                                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2080                                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2081                         }
2082                 }
2083         }
2084
2085         /* Set B:
2086          * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
2087          * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
2088          * calculations to cover bootup clocks.
2089          * DCFCLK: soc.clock_limits[2] when available
2090          * UCLK: soc.clock_limits[2] when available
2091          */
2092         if (dcn3_2_soc.num_states > 2) {
2093                 vlevel_temp = 2;
2094                 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
2095         } else
2096                 dcfclk = 615; //DCFCLK Vmin_lv
2097
2098         pipes[0].clks_cfg.voltage = vlevel_temp;
2099         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2100         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2101
2102         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2103                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2104                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
2105                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2106                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2107         }
2108         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2109         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2110         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2111         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2112         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2113         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2114         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2115         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2116         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2117         context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2118
2119         /* Set D:
2120          * All clocks min.
2121          * DCFCLK: Min, as reported by PM FW when available
2122          * UCLK  : Min, as reported by PM FW when available
2123          * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
2124          */
2125
2126         /*
2127         if (dcn3_2_soc.num_states > 2) {
2128                 vlevel_temp = 0;
2129                 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
2130         } else
2131                 dcfclk = 615; //DCFCLK Vmin_lv
2132
2133         pipes[0].clks_cfg.voltage = vlevel_temp;
2134         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2135         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2136
2137         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2138                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2139                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
2140                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2141                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2142         }
2143         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2144         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2145         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2146         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2147         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2148         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2149         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2150         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2151         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2152         context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2153         */
2154
2155         /* Set C, for Dummy P-State:
2156          * All clocks min.
2157          * DCFCLK: Min, as reported by PM FW, when available
2158          * UCLK  : Min,  as reported by PM FW, when available
2159          * pstate latency as per UCLK state dummy pstate latency
2160          */
2161
2162         // For Set A and Set C use values from validation
2163         pipes[0].clks_cfg.voltage = vlevel;
2164         pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
2165         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2166
2167         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2168                 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;
2169         }
2170
2171         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2172                 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2173                 min_dram_speed_mts_margin = 160;
2174
2175                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2176                         dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
2177
2178                 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
2179                         dm_dram_clock_change_unsupported) {
2180                         int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;
2181
2182                         min_dram_speed_mts =
2183                                 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
2184                 }
2185
2186                 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) {
2187                         /* find largest table entry that is lower than dram speed,
2188                          * but lower than DPM0 still uses DPM0
2189                          */
2190                         for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)
2191                                 if (min_dram_speed_mts + min_dram_speed_mts_margin >
2192                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
2193                                         break;
2194                 }
2195
2196                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2197                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2198
2199                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
2200                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2201                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2202         }
2203
2204         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2205         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2206         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2207         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2208         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2209         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2210         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2211         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2212         /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state.
2213          * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM
2214          * value.
2215          */
2216         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2217         context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2218
2219         if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
2220                 /* The only difference between A and C is p-state latency, if p-state is not supported
2221                  * with full p-state latency we want to calculate DLG based on dummy p-state latency,
2222                  * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30.
2223                  */
2224                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2225                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2226                 /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case
2227                  * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported
2228                  */
2229                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2230         } else {
2231                 /* Set A:
2232                  * All clocks min.
2233                  * DCFCLK: Min, as reported by PM FW, when available
2234                  * UCLK: Min, as reported by PM FW, when available
2235                  */
2236
2237                 /* For set A set the correct latency values (i.e. non-dummy values) unconditionally
2238                  */
2239                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2240                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2241                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2242
2243                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2244                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2245                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2246                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2247                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2248                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2249                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2250                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2251                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2252                 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2253         }
2254
2255         /* Make set D = set A since we do not optimized watermarks for MALL */
2256         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2257
2258         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2259                 if (!context->res_ctx.pipe_ctx[i].stream)
2260                         continue;
2261
2262                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2263                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2264
2265                 if (dc->config.forced_clocks) {
2266                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2267                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2268                 }
2269                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2270                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2271                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2272                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2273
2274                 pipe_idx++;
2275         }
2276
2277         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2278
2279         /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */
2280         if (need_fclk_lat_as_dummy)
2281                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2282                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2283
2284         dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2285
2286         if (!pstate_en)
2287                 /* Restore full p-state latency */
2288                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2289                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2290
2291         /* revert fclk lat changes if required */
2292         if (need_fclk_lat_as_dummy)
2293                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2294                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2295 }
2296
2297 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2298                 unsigned int *optimal_dcfclk,
2299                 unsigned int *optimal_fclk)
2300 {
2301         double bw_from_dram, bw_from_dram1, bw_from_dram2;
2302
2303         bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
2304                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
2305         bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
2306                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
2307
2308         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2309
2310         if (optimal_fclk)
2311                 *optimal_fclk = bw_from_dram /
2312                 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2313
2314         if (optimal_dcfclk)
2315                 *optimal_dcfclk =  bw_from_dram /
2316                 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2317 }
2318
2319 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
2320                 unsigned int index)
2321 {
2322         int i;
2323
2324         if (*num_entries == 0)
2325                 return;
2326
2327         for (i = index; i < *num_entries - 1; i++) {
2328                 table[i] = table[i + 1];
2329         }
2330         memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
2331 }
2332
2333 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params)
2334 {
2335         int i;
2336         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
2337                         max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
2338
2339         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2340                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2341                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2342                 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
2343                         max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2344                 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
2345                         max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2346                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2347                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2348                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2349                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2350                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2351                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2352                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
2353                         max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2354         }
2355
2356         /* Scan through clock values we currently have and if they are 0,
2357          *  then populate it with dcn3_2_soc.clock_limits[] value.
2358          *
2359          * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being
2360          *  0, will cause it to skip building the clock table.
2361          */
2362         if (max_dcfclk_mhz == 0)
2363                 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2364         if (max_dispclk_mhz == 0)
2365                 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2366         if (max_dtbclk_mhz == 0)
2367                 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz;
2368         if (max_uclk_mhz == 0)
2369                 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16;
2370 }
2371
2372 static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry,
2373                 struct _vcs_dpi_voltage_scaling_st *second_entry)
2374 {
2375         struct _vcs_dpi_voltage_scaling_st temp_entry = *first_entry;
2376         *first_entry = *second_entry;
2377         *second_entry = temp_entry;
2378 }
2379
2380 /*
2381  * sort_entries_with_same_bw - Sort entries sharing the same bandwidth by DCFCLK
2382  */
2383 static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2384 {
2385         unsigned int start_index = 0;
2386         unsigned int end_index = 0;
2387         unsigned int current_bw = 0;
2388
2389         for (int i = 0; i < (*num_entries - 1); i++) {
2390                 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
2391                         current_bw = table[i].net_bw_in_kbytes_sec;
2392                         start_index = i;
2393                         end_index = ++i;
2394
2395                         while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw))
2396                                 end_index = ++i;
2397                 }
2398
2399                 if (start_index != end_index) {
2400                         for (int j = start_index; j < end_index; j++) {
2401                                 for (int k = start_index; k < end_index; k++) {
2402                                         if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
2403                                                 swap_table_entries(&table[k], &table[k+1]);
2404                                 }
2405                         }
2406                 }
2407
2408                 start_index = 0;
2409                 end_index = 0;
2410
2411         }
2412 }
2413
2414 /*
2415  * remove_inconsistent_entries - Ensure entries with the same bandwidth have MEMCLK and FCLK monotonically increasing
2416  *                               and remove entries that do not
2417  */
2418 static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2419 {
2420         for (int i = 0; i < (*num_entries - 1); i++) {
2421                 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
2422                         if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
2423                                 (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz))
2424                                 remove_entry_from_table_at_index(table, num_entries, i);
2425                 }
2426         }
2427 }
2428
2429 /*
2430  * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings
2431  * Input:
2432  *      max_clk_limit - struct containing the desired clock timings
2433  * Output:
2434  *      curr_clk_limit  - struct containing the timings that need to be overwritten
2435  * Return: 0 upon success, non-zero for failure
2436  */
2437 static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit,
2438                 struct clk_limit_table_entry *curr_clk_limit)
2439 {
2440         if (NULL == max_clk_limit || NULL == curr_clk_limit)
2441                 return -1; //invalid parameters
2442
2443         //only overwrite if desired max clock frequency is initialized
2444         if (max_clk_limit->dcfclk_mhz != 0)
2445                 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz;
2446
2447         if (max_clk_limit->fclk_mhz != 0)
2448                 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz;
2449
2450         if (max_clk_limit->memclk_mhz != 0)
2451                 curr_clk_limit->memclk_mhz = max_clk_limit->memclk_mhz;
2452
2453         if (max_clk_limit->socclk_mhz != 0)
2454                 curr_clk_limit->socclk_mhz = max_clk_limit->socclk_mhz;
2455
2456         if (max_clk_limit->dtbclk_mhz != 0)
2457                 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz;
2458
2459         if (max_clk_limit->dispclk_mhz != 0)
2460                 curr_clk_limit->dispclk_mhz = max_clk_limit->dispclk_mhz;
2461
2462         return 0;
2463 }
2464
2465 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
2466                 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2467 {
2468         int i, j;
2469         struct _vcs_dpi_voltage_scaling_st entry = {0};
2470         struct clk_limit_table_entry max_clk_data = {0};
2471
2472         unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
2473
2474         static const unsigned int num_dcfclk_stas = 5;
2475         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2476
2477         unsigned int num_uclk_dpms = 0;
2478         unsigned int num_fclk_dpms = 0;
2479         unsigned int num_dcfclk_dpms = 0;
2480
2481         unsigned int num_dc_uclk_dpms = 0;
2482         unsigned int num_dc_fclk_dpms = 0;
2483         unsigned int num_dc_dcfclk_dpms = 0;
2484
2485         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2486                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)
2487                         max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2488                 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz)
2489                         max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2490                 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz)
2491                         max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2492                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz)
2493                         max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2494                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz)
2495                         max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2496                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz)
2497                         max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2498                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz)
2499                         max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2500
2501                 if (bw_params->clk_table.entries[i].memclk_mhz > 0) {
2502                         num_uclk_dpms++;
2503                         if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz)
2504                                 num_dc_uclk_dpms++;
2505                 }
2506                 if (bw_params->clk_table.entries[i].fclk_mhz > 0) {
2507                         num_fclk_dpms++;
2508                         if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz)
2509                                 num_dc_fclk_dpms++;
2510                 }
2511                 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) {
2512                         num_dcfclk_dpms++;
2513                         if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz)
2514                                 num_dc_dcfclk_dpms++;
2515                 }
2516         }
2517
2518         if (!disable_dc_mode_overwrite) {
2519                 //Overwrite max frequencies with max DC mode frequencies for DC mode systems
2520                 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data);
2521                 num_uclk_dpms = num_dc_uclk_dpms;
2522                 num_fclk_dpms = num_dc_fclk_dpms;
2523                 num_dcfclk_dpms = num_dc_dcfclk_dpms;
2524                 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms;
2525                 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms;
2526         }
2527
2528         if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
2529                 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
2530
2531         if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz)
2532                 return -1;
2533
2534         if (max_clk_data.dppclk_mhz == 0)
2535                 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz;
2536
2537         if (max_clk_data.fclk_mhz == 0)
2538                 max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz *
2539                                 dcn3_2_soc.pct_ideal_sdp_bw_after_urgent /
2540                                 dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
2541
2542         if (max_clk_data.phyclk_mhz == 0)
2543                 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2544
2545         *num_entries = 0;
2546         entry.dispclk_mhz = max_clk_data.dispclk_mhz;
2547         entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3;
2548         entry.dppclk_mhz = max_clk_data.dppclk_mhz;
2549         entry.dtbclk_mhz = max_clk_data.dtbclk_mhz;
2550         entry.phyclk_mhz = max_clk_data.phyclk_mhz;
2551         entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2552         entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2553
2554         // Insert all the DCFCLK STAs
2555         for (i = 0; i < num_dcfclk_stas; i++) {
2556                 entry.dcfclk_mhz = dcfclk_sta_targets[i];
2557                 entry.fabricclk_mhz = 0;
2558                 entry.dram_speed_mts = 0;
2559
2560                 get_optimal_ntuple(&entry);
2561                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2562                 insert_entry_into_table_sorted(table, num_entries, &entry);
2563         }
2564
2565         // Insert the max DCFCLK
2566         entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2567         entry.fabricclk_mhz = 0;
2568         entry.dram_speed_mts = 0;
2569
2570         get_optimal_ntuple(&entry);
2571         entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2572         insert_entry_into_table_sorted(table, num_entries, &entry);
2573
2574         // Insert the UCLK DPMS
2575         for (i = 0; i < num_uclk_dpms; i++) {
2576                 entry.dcfclk_mhz = 0;
2577                 entry.fabricclk_mhz = 0;
2578                 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
2579
2580                 get_optimal_ntuple(&entry);
2581                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2582                 insert_entry_into_table_sorted(table, num_entries, &entry);
2583         }
2584
2585         // If FCLK is coarse grained, insert individual DPMs.
2586         if (num_fclk_dpms > 2) {
2587                 for (i = 0; i < num_fclk_dpms; i++) {
2588                         entry.dcfclk_mhz = 0;
2589                         entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2590                         entry.dram_speed_mts = 0;
2591
2592                         get_optimal_ntuple(&entry);
2593                         entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2594                         insert_entry_into_table_sorted(table, num_entries, &entry);
2595                 }
2596         }
2597         // If FCLK fine grained, only insert max
2598         else {
2599                 entry.dcfclk_mhz = 0;
2600                 entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2601                 entry.dram_speed_mts = 0;
2602
2603                 get_optimal_ntuple(&entry);
2604                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2605                 insert_entry_into_table_sorted(table, num_entries, &entry);
2606         }
2607
2608         // At this point, the table contains all "points of interest" based on
2609         // DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock
2610         // ratios (by derate, are exact).
2611
2612         // Remove states that require higher clocks than are supported
2613         for (i = *num_entries - 1; i >= 0 ; i--) {
2614                 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz ||
2615                                 table[i].fabricclk_mhz > max_clk_data.fclk_mhz ||
2616                                 table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16)
2617                         remove_entry_from_table_at_index(table, num_entries, i);
2618         }
2619
2620         // Insert entry with all max dc limits without bandwidth matching
2621         if (!disable_dc_mode_overwrite) {
2622                 struct _vcs_dpi_voltage_scaling_st max_dc_limits_entry = entry;
2623
2624                 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2625                 max_dc_limits_entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2626                 max_dc_limits_entry.dram_speed_mts = max_clk_data.memclk_mhz * 16;
2627
2628                 max_dc_limits_entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&max_dc_limits_entry);
2629                 insert_entry_into_table_sorted(table, num_entries, &max_dc_limits_entry);
2630
2631                 sort_entries_with_same_bw(table, num_entries);
2632                 remove_inconsistent_entries(table, num_entries);
2633         }
2634
2635         // At this point, the table only contains supported points of interest
2636         // it could be used as is, but some states may be redundant due to
2637         // coarse grained nature of some clocks, so we want to round up to
2638         // coarse grained DPMs and remove duplicates.
2639
2640         // Round up UCLKs
2641         for (i = *num_entries - 1; i >= 0 ; i--) {
2642                 for (j = 0; j < num_uclk_dpms; j++) {
2643                         if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
2644                                 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
2645                                 break;
2646                         }
2647                 }
2648         }
2649
2650         // If FCLK is coarse grained, round up to next DPMs
2651         if (num_fclk_dpms > 2) {
2652                 for (i = *num_entries - 1; i >= 0 ; i--) {
2653                         for (j = 0; j < num_fclk_dpms; j++) {
2654                                 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
2655                                         table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
2656                                         break;
2657                                 }
2658                         }
2659                 }
2660         }
2661         // Otherwise, round up to minimum.
2662         else {
2663                 for (i = *num_entries - 1; i >= 0 ; i--) {
2664                         if (table[i].fabricclk_mhz < min_fclk_mhz) {
2665                                 table[i].fabricclk_mhz = min_fclk_mhz;
2666                         }
2667                 }
2668         }
2669
2670         // Round DCFCLKs up to minimum
2671         for (i = *num_entries - 1; i >= 0 ; i--) {
2672                 if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
2673                         table[i].dcfclk_mhz = min_dcfclk_mhz;
2674                 }
2675         }
2676
2677         // Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
2678         i = 0;
2679         while (i < *num_entries - 1) {
2680                 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
2681                                 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
2682                                 table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
2683                         remove_entry_from_table_at_index(table, num_entries, i + 1);
2684                 else
2685                         i++;
2686         }
2687
2688         // Fix up the state indicies
2689         for (i = *num_entries - 1; i >= 0 ; i--) {
2690                 table[i].state = i;
2691         }
2692
2693         return 0;
2694 }
2695
2696 /*
2697  * dcn32_update_bw_bounding_box
2698  *
2699  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from
2700  * spreadsheet with actual values as per dGPU SKU:
2701  * - with passed few options from dc->config
2702  * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
2703  *   need to get it from PM FW)
2704  * - with passed latency values (passed in ns units) in dc-> bb override for
2705  *   debugging purposes
2706  * - with passed latencies from VBIOS (in 100_ns units) if available for
2707  *   certain dGPU SKU
2708  * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
2709  *   of the same ASIC)
2710  * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
2711  *   FW for different clocks (which might differ for certain dGPU SKU of the
2712  *   same ASIC)
2713  */
2714 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
2715 {
2716         dc_assert_fp_enabled();
2717
2718         /* Overrides from dc->config options */
2719         dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
2720
2721         /* Override from passed dc->bb_overrides if available*/
2722         if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2723                         && dc->bb_overrides.sr_exit_time_ns) {
2724                 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2725         }
2726
2727         if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
2728                         != dc->bb_overrides.sr_enter_plus_exit_time_ns
2729                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2730                 dcn3_2_soc.sr_enter_plus_exit_time_us =
2731                         dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2732         }
2733
2734         if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2735                 && dc->bb_overrides.urgent_latency_ns) {
2736                 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2737                 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2738         }
2739
2740         if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
2741                         != dc->bb_overrides.dram_clock_change_latency_ns
2742                         && dc->bb_overrides.dram_clock_change_latency_ns) {
2743                 dcn3_2_soc.dram_clock_change_latency_us =
2744                         dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2745         }
2746
2747         if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000)
2748                         != dc->bb_overrides.fclk_clock_change_latency_ns
2749                         && dc->bb_overrides.fclk_clock_change_latency_ns) {
2750                 dcn3_2_soc.fclk_change_latency_us =
2751                         dc->bb_overrides.fclk_clock_change_latency_ns / 1000;
2752         }
2753
2754         if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
2755                         != dc->bb_overrides.dummy_clock_change_latency_ns
2756                         && dc->bb_overrides.dummy_clock_change_latency_ns) {
2757                 dcn3_2_soc.dummy_pstate_latency_us =
2758                         dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
2759         }
2760
2761         /* Override from VBIOS if VBIOS bb_info available */
2762         if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
2763                 struct bp_soc_bb_info bb_info = {0};
2764
2765                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
2766                         if (bb_info.dram_clock_change_latency_100ns > 0)
2767                                 dcn3_2_soc.dram_clock_change_latency_us =
2768                                         bb_info.dram_clock_change_latency_100ns * 10;
2769
2770                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
2771                                 dcn3_2_soc.sr_enter_plus_exit_time_us =
2772                                         bb_info.dram_sr_enter_exit_latency_100ns * 10;
2773
2774                         if (bb_info.dram_sr_exit_latency_100ns > 0)
2775                                 dcn3_2_soc.sr_exit_time_us =
2776                                         bb_info.dram_sr_exit_latency_100ns * 10;
2777                 }
2778         }
2779
2780         /* Override from VBIOS for num_chan */
2781         if (dc->ctx->dc_bios->vram_info.num_chans) {
2782                 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2783                 dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,
2784                         dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);
2785         }
2786
2787         if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2788                 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2789
2790         /* DML DSC delay factor workaround */
2791         dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
2792
2793         dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
2794
2795         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
2796         dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2797         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2798
2799         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
2800         if (bw_params->clk_table.entries[0].memclk_mhz) {
2801                 if (dc->debug.use_legacy_soc_bb_mechanism) {
2802                         unsigned int i = 0, j = 0, num_states = 0;
2803
2804                         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2805                         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2806                         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2807                         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2808                         unsigned int min_dcfclk = UINT_MAX;
2809                         /* Set 199 as first value in STA target array to have a minimum DCFCLK value.
2810                          * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */
2811                         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2812                         unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
2813                         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
2814
2815                         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2816                                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2817                                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2818                                 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
2819                                                 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
2820                                         min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
2821                                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2822                                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2823                                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2824                                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2825                                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2826                                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2827                         }
2828                         if (min_dcfclk > dcfclk_sta_targets[0])
2829                                 dcfclk_sta_targets[0] = min_dcfclk;
2830                         if (!max_dcfclk_mhz)
2831                                 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2832                         if (!max_dispclk_mhz)
2833                                 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2834                         if (!max_dppclk_mhz)
2835                                 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
2836                         if (!max_phyclk_mhz)
2837                                 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2838
2839                         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2840                                 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2841                                 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2842                                 num_dcfclk_sta_targets++;
2843                         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2844                                 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2845                                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2846                                         if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2847                                                 dcfclk_sta_targets[i] = max_dcfclk_mhz;
2848                                                 break;
2849                                         }
2850                                 }
2851                                 // Update size of array since we "removed" duplicates
2852                                 num_dcfclk_sta_targets = i + 1;
2853                         }
2854
2855                         num_uclk_states = bw_params->clk_table.num_entries;
2856
2857                         // Calculate optimal dcfclk for each uclk
2858                         for (i = 0; i < num_uclk_states; i++) {
2859                                 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2860                                                 &optimal_dcfclk_for_uclk[i], NULL);
2861                                 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2862                                         optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2863                                 }
2864                         }
2865
2866                         // Calculate optimal uclk for each dcfclk sta target
2867                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
2868                                 for (j = 0; j < num_uclk_states; j++) {
2869                                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2870                                                 optimal_uclk_for_dcfclk_sta_targets[i] =
2871                                                                 bw_params->clk_table.entries[j].memclk_mhz * 16;
2872                                                 break;
2873                                         }
2874                                 }
2875                         }
2876
2877                         i = 0;
2878                         j = 0;
2879                         // create the final dcfclk and uclk table
2880                         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2881                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2882                                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2883                                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2884                                 } else {
2885                                         if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2886                                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2887                                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2888                                         } else {
2889                                                 j = num_uclk_states;
2890                                         }
2891                                 }
2892                         }
2893
2894                         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2895                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2896                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2897                         }
2898
2899                         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2900                                         optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2901                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2902                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2903                         }
2904
2905                         dcn3_2_soc.num_states = num_states;
2906                         for (i = 0; i < dcn3_2_soc.num_states; i++) {
2907                                 dcn3_2_soc.clock_limits[i].state = i;
2908                                 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2909                                 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2910
2911                                 /* Fill all states with max values of all these clocks */
2912                                 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
2913                                 dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
2914                                 dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
2915                                 dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
2916
2917                                 /* Populate from bw_params for DTBCLK, SOCCLK */
2918                                 if (i > 0) {
2919                                         if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
2920                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
2921                                         } else {
2922                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2923                                         }
2924                                 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
2925                                         dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2926                                 }
2927
2928                                 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
2929                                         dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
2930                                 else
2931                                         dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
2932
2933                                 if (!dram_speed_mts[i] && i > 0)
2934                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
2935                                 else
2936                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2937
2938                                 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
2939                                 /* PHYCLK_D18, PHYCLK_D32 */
2940                                 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2941                                 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2942                         }
2943                 } else {
2944                         build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,
2945                                         dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);
2946                 }
2947
2948                 /* Re-init DML with updated bb */
2949                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2950                 if (dc->current_state)
2951                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2952         }
2953 }
2954
2955 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
2956                                   int pipe_cnt)
2957 {
2958         dc_assert_fp_enabled();
2959
2960         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
2961         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
2962 }
2963
2964 bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
2965 {
2966         bool allow = false;
2967         uint32_t refresh_rate = 0;
2968
2969         /* Allow subvp on displays that have active margin for 2560x1440@60hz displays
2970          * only for now. There must be no scaling as well.
2971          *
2972          * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs
2973          * for p-state switching.
2974          */
2975         if (pipe->stream && pipe->plane_state) {
2976                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
2977                                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
2978                                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
2979                 if (pipe->stream->timing.v_addressable == 1440 &&
2980                                 pipe->stream->timing.h_addressable == 2560 &&
2981                                 refresh_rate >= 55 && refresh_rate <= 65 &&
2982                                 pipe->plane_state->src_rect.height == 1440 &&
2983                                 pipe->plane_state->src_rect.width == 2560 &&
2984                                 pipe->plane_state->dst_rect.height == 1440 &&
2985                                 pipe->plane_state->dst_rect.width == 2560)
2986                         allow = true;
2987         }
2988         return allow;
2989 }
2990
2991 /**
2992  * dcn32_allow_subvp_high_refresh_rate: Determine if the high refresh rate config will allow subvp
2993  *
2994  * @dc: Current DC state
2995  * @context: New DC state to be programmed
2996  * @pipe: Pipe to be considered for use in subvp
2997  *
2998  * On high refresh rate display configs, we will allow subvp under the following conditions:
2999  * 1. Resolution is 3840x2160, 3440x1440, or 2560x1440
3000  * 2. Refresh rate is between 120hz - 165hz
3001  * 3. No scaling
3002  * 4. Freesync is inactive
3003  * 5. For single display cases, freesync must be disabled
3004  *
3005  * Return: True if pipe can be used for subvp, false otherwise
3006  */
3007 bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)
3008 {
3009         bool allow = false;
3010         uint32_t refresh_rate = 0;
3011         uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;
3012         uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;
3013         uint32_t min_refresh = subvp_max_refresh;
3014         uint32_t i;
3015
3016         /* Only allow SubVP on high refresh displays if all connected displays
3017          * are considered "high refresh" (i.e. >= 120hz). We do not want to
3018          * allow combinations such as 120hz (SubVP) + 60hz (SubVP).
3019          */
3020         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3021                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
3022
3023                 if (!pipe_ctx->stream)
3024                         continue;
3025                 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +
3026                                 pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
3027                                                 / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);
3028
3029                 if (refresh_rate < min_refresh)
3030                         min_refresh = refresh_rate;
3031         }
3032
3033         if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&
3034                         pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
3035                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
3036                                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
3037                                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
3038                 if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) {
3039                         for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) {
3040                                 uint32_t width = subvp_high_refresh_list.res[i].width;
3041                                 uint32_t height = subvp_high_refresh_list.res[i].height;
3042
3043                                 if (dcn32_check_native_scaling_for_res(pipe, width, height)) {
3044                                         if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) {
3045                                                 allow = true;
3046                                                 break;
3047                                         }
3048                                 }
3049                         }
3050                 }
3051         }
3052         return allow;
3053 }
3054
3055 /**
3056  * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy
3057  *
3058  * @dc: Current DC state
3059  * @context: New DC state to be programmed
3060  *
3061  * Return: Max vratio for prefetch
3062  */
3063 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)
3064 {
3065         double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4
3066         int i;
3067
3068         /* For single display MPO configs, allow the max vratio to be 8
3069          * if any plane is YUV420 format
3070          */
3071         if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) {
3072                 for (i = 0; i < context->stream_status[0].plane_count; i++) {
3073                         if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr ||
3074                                         context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) {
3075                                 max_vratio_pre = __DML_MAX_VRATIO_PRE__;
3076                         }
3077                 }
3078         }
3079         return max_vratio_pre;
3080 }
3081
3082 /**
3083  * dcn32_assign_fpo_vactive_candidate - Assign the FPO stream candidate for FPO + VActive case
3084  *
3085  * This function chooses the FPO candidate stream for FPO + VActive cases (2 stream config).
3086  * For FPO + VAtive cases, the assumption is that one display has ActiveMargin > 0, and the
3087  * other display has ActiveMargin <= 0. This function will choose the pipe/stream that has
3088  * ActiveMargin <= 0 to be the FPO stream candidate if found.
3089  *
3090  *
3091  * @dc: current dc state
3092  * @context: new dc state
3093  * @fpo_candidate_stream: pointer to FPO stream candidate if one is found
3094  *
3095  * Return: void
3096  */
3097 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)
3098 {
3099         unsigned int i, pipe_idx;
3100         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
3101
3102         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3103                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3104
3105                 if (!pipe->stream)
3106                         continue;
3107
3108                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
3109                         *fpo_candidate_stream = pipe->stream;
3110                         break;
3111                 }
3112                 pipe_idx++;
3113         }
3114 }
3115
3116 /**
3117  * dcn32_find_vactive_pipe - Determines if the config has a pipe that can switch in VACTIVE
3118  *
3119  * @dc: current dc state
3120  * @context: new dc state
3121  * @vactive_margin_req_us: The vactive marign required for a vactive pipe to be considered "found"
3122  *
3123  * Return: True if VACTIVE display is found, false otherwise
3124  */
3125 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us)
3126 {
3127         unsigned int i, pipe_idx;
3128         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
3129         bool vactive_found = false;
3130         unsigned int blank_us = 0;
3131
3132         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3133                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3134
3135                 if (!pipe->stream)
3136                         continue;
3137
3138                 blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total /
3139                                 (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000;
3140                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] >= vactive_margin_req_us &&
3141                                 !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed) && blank_us < dc->debug.fpo_vactive_max_blank_us) {
3142                         vactive_found = true;
3143                         break;
3144                 }
3145                 pipe_idx++;
3146         }
3147         return vactive_found;
3148 }
3149
3150 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
3151 {
3152         dc_assert_fp_enabled();
3153         dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;
3154 }
3155
3156 void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)
3157 {
3158         // WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue)
3159         if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&
3160                         dc->dml.soc.num_chans <= 8) {
3161                 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3162
3163                 if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&
3164                                 num_mclk_levels > 1) {
3165                         context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;
3166                         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3167                 }
3168         }
3169 }