drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include "dcn32_fpu.h"
  27 #include "dc_link_dp.h"
  28 #include "dcn32/dcn32_resource.h"
  29 #include "dcn20/dcn20_resource.h"
  30 #include "display_mode_vba_util_32.h"
  31 // We need this includes for WATERMARKS_* defines
  32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
  33 #include "dcn30/dcn30_resource.h"
  34
  35 #define DC_LOGGER_INIT(logger)
  36
  37 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
  38         .gpuvm_enable = 0,
  39         .gpuvm_max_page_table_levels = 4,
  40         .hostvm_enable = 0,
  41         .rob_buffer_size_kbytes = 128,
  42         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
  43         .config_return_buffer_size_in_kbytes = 1280,
  44         .compressed_buffer_segment_size_in_kbytes = 64,
  45         .meta_fifo_size_in_kentries = 22,
  46         .zero_size_buffer_entries = 512,
  47         .compbuf_reserved_space_64b = 256,
  48         .compbuf_reserved_space_zs = 64,
  49         .dpp_output_buffer_pixels = 2560,
  50         .opp_output_buffer_lines = 1,
  51         .pixel_chunk_size_kbytes = 8,
  52         .alpha_pixel_chunk_size_kbytes = 4,
  53         .min_pixel_chunk_size_bytes = 1024,
  54         .dcc_meta_buffer_size_bytes = 6272,
  55         .meta_chunk_size_kbytes = 2,
  56         .min_meta_chunk_size_bytes = 256,
  57         .writeback_chunk_size_kbytes = 8,
  58         .ptoi_supported = false,
  59         .num_dsc = 4,
  60         .maximum_dsc_bits_per_component = 12,
  61         .maximum_pixels_per_line_per_dsc_unit = 6016,
  62         .dsc422_native_support = true,
  63         .is_line_buffer_bpp_fixed = true,
  64         .line_buffer_fixed_bpp = 57,
  65         .line_buffer_size_bits = 1171920,
  66         .max_line_buffer_lines = 32,
  67         .writeback_interface_buffer_size_kbytes = 90,
  68         .max_num_dpp = 4,
  69         .max_num_otg = 4,
  70         .max_num_hdmi_frl_outputs = 1,
  71         .max_num_wb = 1,
  72         .max_dchub_pscl_bw_pix_per_clk = 4,
  73         .max_pscl_lb_bw_pix_per_clk = 2,
  74         .max_lb_vscl_bw_pix_per_clk = 4,
  75         .max_vscl_hscl_bw_pix_per_clk = 4,
  76         .max_hscl_ratio = 6,
  77         .max_vscl_ratio = 6,
  78         .max_hscl_taps = 8,
  79         .max_vscl_taps = 8,
  80         .dpte_buffer_size_in_pte_reqs_luma = 64,
  81         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  82         .dispclk_ramp_margin_percent = 1,
  83         .max_inter_dcn_tile_repeaters = 8,
  84         .cursor_buffer_size = 16,
  85         .cursor_chunk_size = 2,
  86         .writeback_line_buffer_buffer_size = 0,
  87         .writeback_min_hscl_ratio = 1,
  88         .writeback_min_vscl_ratio = 1,
  89         .writeback_max_hscl_ratio = 1,
  90         .writeback_max_vscl_ratio = 1,
  91         .writeback_max_hscl_taps = 1,
  92         .writeback_max_vscl_taps = 1,
  93         .dppclk_delay_subtotal = 47,
  94         .dppclk_delay_scl = 50,
  95         .dppclk_delay_scl_lb_only = 16,
  96         .dppclk_delay_cnvc_formatter = 28,
  97         .dppclk_delay_cnvc_cursor = 6,
  98         .dispclk_delay_subtotal = 125,
  99         .dynamic_metadata_vm_enabled = false,
 100         .odm_combine_4to1_supported = false,
 101         .dcc_supported = true,
 102         .max_num_dp2p0_outputs = 2,
 103         .max_num_dp2p0_streams = 4,
 104 };
 105
 106 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 107         .clock_limits = {
 108                 {
 109                         .state = 0,
 110                         .dcfclk_mhz = 1564.0,
 111                         .fabricclk_mhz = 400.0,
 112                         .dispclk_mhz = 2150.0,
 113                         .dppclk_mhz = 2150.0,
 114                         .phyclk_mhz = 810.0,
 115                         .phyclk_d18_mhz = 667.0,
 116                         .phyclk_d32_mhz = 625.0,
 117                         .socclk_mhz = 1200.0,
 118                         .dscclk_mhz = 716.667,
 119                         .dram_speed_mts = 16000.0,
 120                         .dtbclk_mhz = 1564.0,
 121                 },
 122         },
 123         .num_states = 1,
 124         .sr_exit_time_us = 20.16,
 125         .sr_enter_plus_exit_time_us = 27.13,
 126         .sr_exit_z8_time_us = 285.0,
 127         .sr_enter_plus_exit_z8_time_us = 320,
 128         .writeback_latency_us = 12.0,
 129         .round_trip_ping_latency_dcfclk_cycles = 263,
 130         .urgent_latency_pixel_data_only_us = 4.0,
 131         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 132         .urgent_latency_vm_data_only_us = 4.0,
 133         .fclk_change_latency_us = 20,
 134         .usr_retraining_latency_us = 2,
 135         .smn_latency_us = 2,
 136         .mall_allocated_for_dcn_mbytes = 64,
 137         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 138         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 139         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 140         .pct_ideal_sdp_bw_after_urgent = 100.0,
 141         .pct_ideal_fabric_bw_after_urgent = 67.0,
 142         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 143         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 144         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 145         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 146         .max_avg_sdp_bw_use_normal_percent = 80.0,
 147         .max_avg_fabric_bw_use_normal_percent = 60.0,
 148         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 149         .max_avg_dram_bw_use_normal_percent = 15.0,
 150         .num_chans = 8,
 151         .dram_channel_width_bytes = 2,
 152         .fabric_datapath_to_dcn_data_return_bytes = 64,
 153         .return_bus_width_bytes = 64,
 154         .downspread_percent = 0.38,
 155         .dcn_downspread_percent = 0.5,
 156         .dram_clock_change_latency_us = 400,
 157         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 158         .do_urgent_latency_adjustment = true,
 159         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 160         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 161 };
 162
 163 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
 164 {
 165         /* defaults */
 166         double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
 167         double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
 168         double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 169         double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 170         /* For min clocks use as reported by PM FW and report those as min */
 171         uint16_t min_uclk_mhz                   = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 172         uint16_t min_dcfclk_mhz                 = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 173         uint16_t setb_min_uclk_mhz              = min_uclk_mhz;
 174         uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
 175
 176         dc_assert_fp_enabled();
 177
 178         /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
 179         if (dcfclk_mhz_for_the_second_state)
 180                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
 181         else
 182                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 183
 184         if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
 185                 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 186
 187         /* Set A - Normal - default values */
 188         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
 189         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
 190         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 191         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
 192         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 193         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 194         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 195         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
 196         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
 197         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 198
 199         /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
 200         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
 201         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
 202         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 203         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 204         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 205         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 206         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 207         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
 208         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
 209
 210         /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 211         /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
 212         if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
 213                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
 214                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38;
 215                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 216                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 217                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 218                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
 219                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 220                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 221                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 222                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 223                 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
 224                 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
 225                 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
 226                 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
 227                 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
 228                 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
 229                 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
 230                 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 231         }
 232         /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
 233         /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
 234         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 235         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
 236         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 237         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
 238         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
 239         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 240         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 241         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
 242         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
 243         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 244 }
 245
 246 /**
 247  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
 248  * and populate pipe_ctx with those params.
 249  *
 250  * This function must be called AFTER the phantom pipes are added to context
 251  * and run through DML (so that the DLG params for the phantom pipes can be
 252  * populated), and BEFORE we program the timing for the phantom pipes.
 253  *
 254  * @dc: [in] current dc state
 255  * @context: [in] new dc state
 256  * @pipes: [in] DML pipe params array
 257  * @pipe_cnt: [in] DML pipe count
 258  */
 259 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
 260                                               struct dc_state *context,
 261                                               display_e2e_pipe_params_st *pipes,
 262                                               int pipe_cnt)
 263 {
 264         uint32_t i, pipe_idx;
 265
 266         dc_assert_fp_enabled();
 267
 268         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 269                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 270
 271                 if (!pipe->stream)
 272                         continue;
 273
 274                 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 275                         pipes[pipe_idx].pipe.dest.vstartup_start =
 276                                 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 277                         pipes[pipe_idx].pipe.dest.vupdate_offset =
 278                                 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 279                         pipes[pipe_idx].pipe.dest.vupdate_width =
 280                                 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 281                         pipes[pipe_idx].pipe.dest.vready_offset =
 282                                 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 283                         pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 284                 }
 285                 pipe_idx++;
 286         }
 287 }
 288
 289 bool dcn32_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index)
 290 {
 291         double pscl_throughput;
 292         double pscl_throughput_chroma;
 293         double dpp_clk_single_dpp, clock;
 294         double clk_frequency = 0.0;
 295         double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
 296
 297         dc_assert_fp_enabled();
 298
 299         dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe.scale_ratio_depth.hscl_ratio,
 300                                                         pipe.scale_ratio_depth.hscl_ratio_c,
 301                                                         pipe.scale_ratio_depth.vscl_ratio,
 302                                                         pipe.scale_ratio_depth.vscl_ratio_c,
 303                                                         context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
 304                                                         context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
 305                                                         pipe.dest.pixel_rate_mhz,
 306                                                         pipe.src.source_format,
 307                                                         pipe.scale_taps.htaps,
 308                                                         pipe.scale_taps.htaps_c,
 309                                                         pipe.scale_taps.vtaps,
 310                                                         pipe.scale_taps.vtaps_c,
 311                                                         /* Output */
 312                                                         &pscl_throughput, &pscl_throughput_chroma,
 313                                                         &dpp_clk_single_dpp);
 314
 315         clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);
 316
 317         if (clock > 0)
 318                 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0));
 319
 320         if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[index].dppclk_mhz)
 321                 return true;
 322         else
 323                 return false;
 324 }
 325
 326 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
 327 {
 328         float memory_bw_kbytes_sec;
 329         float fabric_bw_kbytes_sec;
 330         float sdp_bw_kbytes_sec;
 331         float limiting_bw_kbytes_sec;
 332
 333         memory_bw_kbytes_sec = entry->dram_speed_mts *
 334                                 dcn3_2_soc.num_chans *
 335                                 dcn3_2_soc.dram_channel_width_bytes *
 336                                 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 337
 338         fabric_bw_kbytes_sec = entry->fabricclk_mhz *
 339                                 dcn3_2_soc.return_bus_width_bytes *
 340                                 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 341
 342         sdp_bw_kbytes_sec = entry->dcfclk_mhz *
 343                                 dcn3_2_soc.return_bus_width_bytes *
 344                                 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 345
 346         limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
 347
 348         if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
 349                 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
 350
 351         if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
 352                 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
 353
 354         return limiting_bw_kbytes_sec;
 355 }
 356
 357 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
 358 {
 359         if (entry->dcfclk_mhz > 0) {
 360                 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 361
 362                 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 363                 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
 364                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 365         } else if (entry->fabricclk_mhz > 0) {
 366                 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 367
 368                 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 369                 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
 370                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 371         } else if (entry->dram_speed_mts > 0) {
 372                 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
 373                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 374
 375                 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 376                 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 377         }
 378 }
 379
 380 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
 381                                     unsigned int *num_entries,
 382                                     struct _vcs_dpi_voltage_scaling_st *entry)
 383 {
 384         int i = 0;
 385         int index = 0;
 386         float net_bw_of_new_state = 0;
 387
 388         dc_assert_fp_enabled();
 389
 390         get_optimal_ntuple(entry);
 391
 392         if (*num_entries == 0) {
 393                 table[0] = *entry;
 394                 (*num_entries)++;
 395         } else {
 396                 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry);
 397                 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) {
 398                         index++;
 399                         if (index >= *num_entries)
 400                                 break;
 401                 }
 402
 403                 for (i = *num_entries; i > index; i--)
 404                         table[i] = table[i - 1];
 405
 406                 table[index] = *entry;
 407                 (*num_entries)++;
 408         }
 409 }
 410
 411 /**
 412  * dcn32_set_phantom_stream_timing: Set timing params for the phantom stream
 413  *
 414  * Set timing params of the phantom stream based on calculated output from DML.
 415  * This function first gets the DML pipe index using the DC pipe index, then
 416  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
 417  * lines required for SubVP MCLK switching and assigns to the phantom stream
 418  * accordingly.
 419  *
 420  * - The number of SubVP lines calculated in DML does not take into account
 421  * FW processing delays and required pstate allow width, so we must include
 422  * that separately.
 423  *
 424  * - Set phantom backporch = vstartup of main pipe
 425  *
 426  * @dc: current dc state
 427  * @context: new dc state
 428  * @ref_pipe: Main pipe for the phantom stream
 429  * @pipes: DML pipe params
 430  * @pipe_cnt: number of DML pipes
 431  * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
 432  */
 433 void dcn32_set_phantom_stream_timing(struct dc *dc,
 434                                      struct dc_state *context,
 435                                      struct pipe_ctx *ref_pipe,
 436                                      struct dc_stream_state *phantom_stream,
 437                                      display_e2e_pipe_params_st *pipes,
 438                                      unsigned int pipe_cnt,
 439                                      unsigned int dc_pipe_idx)
 440 {
 441         unsigned int i, pipe_idx;
 442         struct pipe_ctx *pipe;
 443         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
 444         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
 445         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 446         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
 447
 448         dc_assert_fp_enabled();
 449
 450         // Find DML pipe index (pipe_idx) using dc_pipe_idx
 451         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 452                 pipe = &context->res_ctx.pipe_ctx[i];
 453
 454                 if (!pipe->stream)
 455                         continue;
 456
 457                 if (i == dc_pipe_idx)
 458                         break;
 459
 460                 pipe_idx++;
 461         }
 462
 463         // Calculate lines required for pstate allow width and FW processing delays
 464         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
 465                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
 466                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
 467                         (double)ref_pipe->stream->timing.h_total;
 468
 469         // Update clks_cfg for calling into recalculate
 470         pipes[0].clks_cfg.voltage = vlevel;
 471         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 472         pipes[0].clks_cfg.socclk_mhz = socclk;
 473
 474         // DML calculation for MALL region doesn't take into account FW delay
 475         // and required pstate allow width for multi-display cases
 476         /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned
 477          * to 2 swaths (i.e. 16 lines)
 478          */
 479         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
 480                                 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;
 481
 482         // For backporch of phantom pipe, use vstartup of the main pipe
 483         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 484
 485         phantom_stream->dst.y = 0;
 486         phantom_stream->dst.height = phantom_vactive;
 487         phantom_stream->src.y = 0;
 488         phantom_stream->src.height = phantom_vactive;
 489
 490         phantom_stream->timing.v_addressable = phantom_vactive;
 491         phantom_stream->timing.v_front_porch = 1;
 492         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
 493                                                 phantom_stream->timing.v_front_porch +
 494                                                 phantom_stream->timing.v_sync_width +
 495                                                 phantom_bp;
 496         phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
 497 }
 498
 499 /**
 500  * dcn32_get_num_free_pipes: Calculate number of free pipes
 501  *
 502  * This function assumes that a "used" pipe is a pipe that has
 503  * both a stream and a plane assigned to it.
 504  *
 505  * @dc: current dc state
 506  * @context: new dc state
 507  *
 508  * Return:
 509  * Number of free pipes available in the context
 510  */
 511 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
 512 {
 513         unsigned int i;
 514         unsigned int free_pipes = 0;
 515         unsigned int num_pipes = 0;
 516
 517         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 518                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 519
 520                 if (pipe->stream && !pipe->top_pipe) {
 521                         while (pipe) {
 522                                 num_pipes++;
 523                                 pipe = pipe->bottom_pipe;
 524                         }
 525                 }
 526         }
 527
 528         free_pipes = dc->res_pool->pipe_count - num_pipes;
 529         return free_pipes;
 530 }
 531
 532 /**
 533  * dcn32_assign_subvp_pipe: Function to decide which pipe will use Sub-VP.
 534  *
 535  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
 536  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
 537  * we are forcing SubVP P-State switching on the current config.
 538  *
 539  * The number of pipes used for the chosen surface must be less than or equal to the
 540  * number of free pipes available.
 541  *
 542  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
 543  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
 544  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
 545  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
 546  *
 547  * @param dc: current dc state
 548  * @param context: new dc state
 549  * @param index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
 550  *
 551  * Return:
 552  * True if a valid pipe assignment was found for Sub-VP. Otherwise false.
 553  */
 554 static bool dcn32_assign_subvp_pipe(struct dc *dc,
 555                                     struct dc_state *context,
 556                                     unsigned int *index)
 557 {
 558         unsigned int i, pipe_idx;
 559         unsigned int max_frame_time = 0;
 560         bool valid_assignment_found = false;
 561         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
 562         bool current_assignment_freesync = false;
 563
 564         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 565                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 566                 unsigned int num_pipes = 0;
 567                 unsigned int refresh_rate = 0;
 568
 569                 if (!pipe->stream)
 570                         continue;
 571
 572                 // Round up
 573                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 574                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 575                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
 576                 if (pipe->plane_state && !pipe->top_pipe &&
 577                                 pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120) {
 578                         while (pipe) {
 579                                 num_pipes++;
 580                                 pipe = pipe->bottom_pipe;
 581                         }
 582
 583                         pipe = &context->res_ctx.pipe_ctx[i];
 584                         if (num_pipes <= free_pipes) {
 585                                 struct dc_stream_state *stream = pipe->stream;
 586                                 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
 587                                                 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
 588                                 if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
 589                                         *index = i;
 590                                         max_frame_time = frame_us;
 591                                         valid_assignment_found = true;
 592                                         current_assignment_freesync = false;
 593                                 /* For the 2-Freesync display case, still choose the one with the
 594                              * longest frame time
 595                              */
 596                                 } else if (stream->ignore_msa_timing_param && (!valid_assignment_found ||
 597                                                 (current_assignment_freesync && frame_us > max_frame_time))) {
 598                                         *index = i;
 599                                         valid_assignment_found = true;
 600                                         current_assignment_freesync = true;
 601                                 }
 602                         }
 603                 }
 604                 pipe_idx++;
 605         }
 606         return valid_assignment_found;
 607 }
 608
 609 /**
 610  * dcn32_enough_pipes_for_subvp: Function to check if there are "enough" pipes for SubVP.
 611  *
 612  * This function returns true if there are enough free pipes
 613  * to create the required phantom pipes for any given stream
 614  * (that does not already have phantom pipe assigned).
 615  *
 616  * e.g. For a 2 stream config where the first stream uses one
 617  * pipe and the second stream uses 2 pipes (i.e. pipe split),
 618  * this function will return true because there is 1 remaining
 619  * pipe which can be used as the phantom pipe for the non pipe
 620  * split pipe.
 621  *
 622  * @dc: current dc state
 623  * @context: new dc state
 624  *
 625  * Return:
 626  * True if there are enough free pipes to assign phantom pipes to at least one
 627  * stream that does not already have phantom pipes assigned. Otherwise false.
 628  */
 629 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
 630 {
 631         unsigned int i, split_cnt, free_pipes;
 632         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
 633         bool subvp_possible = false;
 634
 635         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 636                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 637
 638                 // Find the minimum pipe split count for non SubVP pipes
 639                 if (pipe->stream && !pipe->top_pipe &&
 640                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 641                         split_cnt = 0;
 642                         while (pipe) {
 643                                 split_cnt++;
 644                                 pipe = pipe->bottom_pipe;
 645                         }
 646
 647                         if (split_cnt < min_pipe_split)
 648                                 min_pipe_split = split_cnt;
 649                 }
 650         }
 651
 652         free_pipes = dcn32_get_num_free_pipes(dc, context);
 653
 654         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
 655         // should not equal to the pipe_count)
 656         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
 657                 subvp_possible = true;
 658
 659         return subvp_possible;
 660 }
 661
 662 /**
 663  * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable
 664  *
 665  * High level algorithm:
 666  * 1. Find longest microschedule length (in us) between the two SubVP pipes
 667  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
 668  * pipes still allows for the maximum microschedule to fit in the active
 669  * region for both pipes.
 670  *
 671  * @dc: current dc state
 672  * @context: new dc state
 673  *
 674  * Return:
 675  * bool - True if the SubVP + SubVP config is schedulable, false otherwise
 676  */
 677 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
 678 {
 679         struct pipe_ctx *subvp_pipes[2];
 680         struct dc_stream_state *phantom = NULL;
 681         uint32_t microschedule_lines = 0;
 682         uint32_t index = 0;
 683         uint32_t i;
 684         uint32_t max_microschedule_us = 0;
 685         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
 686
 687         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 688                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 689                 uint32_t time_us = 0;
 690
 691                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
 692                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
 693                  */
 694                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
 695                     pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 696                         phantom = pipe->stream->mall_stream_config.paired_stream;
 697                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
 698                                         phantom->timing.v_addressable;
 699
 700                         // Round up when calculating microschedule time (+ 1 at the end)
 701                         time_us = (microschedule_lines * phantom->timing.h_total) /
 702                                         (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
 703                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
 704                                                 dc->caps.subvp_fw_processing_delay_us + 1;
 705                         if (time_us > max_microschedule_us)
 706                                 max_microschedule_us = time_us;
 707
 708                         subvp_pipes[index] = pipe;
 709                         index++;
 710
 711                         // Maximum 2 SubVP pipes
 712                         if (index == 2)
 713                                 break;
 714                 }
 715         }
 716         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
 717                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 718         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
 719                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 720         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
 721                         subvp_pipes[0]->stream->timing.h_total) /
 722                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 723         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
 724                         subvp_pipes[1]->stream->timing.h_total) /
 725                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 726
 727         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
 728             (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
 729                 return true;
 730
 731         return false;
 732 }
 733
 734 /**
 735  * subvp_drr_schedulable: Determine if SubVP + DRR config is schedulable
 736  *
 737  * High level algorithm:
 738  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 739  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
 740  * (the margin is equal to the MALL region + DRR margin (500us))
 741  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
 742  * then report the configuration as supported
 743  *
 744  * @dc: current dc state
 745  * @context: new dc state
 746  * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config
 747  *
 748  * Return:
 749  * bool - True if the SubVP + DRR config is schedulable, false otherwise
 750  */
 751 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
 752 {
 753         bool schedulable = false;
 754         uint32_t i;
 755         struct pipe_ctx *pipe = NULL;
 756         struct dc_crtc_timing *main_timing = NULL;
 757         struct dc_crtc_timing *phantom_timing = NULL;
 758         struct dc_crtc_timing *drr_timing = NULL;
 759         int16_t prefetch_us = 0;
 760         int16_t mall_region_us = 0;
 761         int16_t drr_frame_us = 0;       // nominal frame time
 762         int16_t subvp_active_us = 0;
 763         int16_t stretched_drr_us = 0;
 764         int16_t drr_stretched_vblank_us = 0;
 765         int16_t max_vblank_mallregion = 0;
 766
 767         // Find SubVP pipe
 768         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 769                 pipe = &context->res_ctx.pipe_ctx[i];
 770
 771                 // We check for master pipe, but it shouldn't matter since we only need
 772                 // the pipe for timing info (stream should be same for any pipe splits)
 773                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
 774                         continue;
 775
 776                 // Find the SubVP pipe
 777                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 778                         break;
 779         }
 780
 781         main_timing = &pipe->stream->timing;
 782         phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
 783         drr_timing = &drr_pipe->stream->timing;
 784         prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 785                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 786                         dc->caps.subvp_prefetch_end_to_mall_start_us;
 787         subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 788                         (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 789         drr_frame_us = drr_timing->v_total * drr_timing->h_total /
 790                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
 791         // P-State allow width and FW delays already included phantom_timing->v_addressable
 792         mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 793                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 794         stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 795         drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
 796                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
 797         max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
 798
 799         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
 800          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
 801          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 802          * and the max of (VBLANK blanking time, MALL region)).
 803          */
 804         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
 805                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
 806                 schedulable = true;
 807
 808         return schedulable;
 809 }
 810
 811
 812 /**
 813  * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable
 814  *
 815  * High level algorithm:
 816  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
 817  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
 818  * then report the configuration as supported
 819  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
 820  *
 821  * @dc: current dc state
 822  * @context: new dc state
 823  *
 824  * Return:
 825  * bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
 826  */
 827 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
 828 {
 829         struct pipe_ctx *pipe = NULL;
 830         struct pipe_ctx *subvp_pipe = NULL;
 831         bool found = false;
 832         bool schedulable = false;
 833         uint32_t i = 0;
 834         uint8_t vblank_index = 0;
 835         uint16_t prefetch_us = 0;
 836         uint16_t mall_region_us = 0;
 837         uint16_t vblank_frame_us = 0;
 838         uint16_t subvp_active_us = 0;
 839         uint16_t vblank_blank_us = 0;
 840         uint16_t max_vblank_mallregion = 0;
 841         struct dc_crtc_timing *main_timing = NULL;
 842         struct dc_crtc_timing *phantom_timing = NULL;
 843         struct dc_crtc_timing *vblank_timing = NULL;
 844
 845         /* For SubVP + VBLANK/DRR cases, we assume there can only be
 846          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
 847          * is supported, it is either a single VBLANK case or two VBLANK
 848          * displays which are synchronized (in which case they have identical
 849          * timings).
 850          */
 851         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 852                 pipe = &context->res_ctx.pipe_ctx[i];
 853
 854                 // We check for master pipe, but it shouldn't matter since we only need
 855                 // the pipe for timing info (stream should be same for any pipe splits)
 856                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
 857                         continue;
 858
 859                 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 860                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
 861                         vblank_index = i;
 862                         found = true;
 863                 }
 864
 865                 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 866                         subvp_pipe = pipe;
 867         }
 868         // Use ignore_msa_timing_param flag to identify as DRR
 869         if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {
 870                 // SUBVP + DRR case
 871                 schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
 872         } else if (found) {
 873                 main_timing = &subvp_pipe->stream->timing;
 874                 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 875                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
 876                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
 877                 // Also include the prefetch end to mallstart delay time
 878                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 879                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 880                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
 881                 // P-State allow width and FW delays already included phantom_timing->v_addressable
 882                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 883                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 884                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
 885                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 886                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
 887                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 888                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 889                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 890                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
 891
 892                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 893                 // and the max of (VBLANK blanking time, MALL region)
 894                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
 895                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
 896                         schedulable = true;
 897         }
 898         return schedulable;
 899 }
 900
 901 /**
 902  * subvp_validate_static_schedulability: Check which SubVP case is calculated and handle
 903  * static analysis based on the case.
 904  *
 905  * Three cases:
 906  * 1. SubVP + SubVP
 907  * 2. SubVP + VBLANK (DRR checked internally)
 908  * 3. SubVP + VACTIVE (currently unsupported)
 909  *
 910  * @dc: current dc state
 911  * @context: new dc state
 912  * @vlevel: Voltage level calculated by DML
 913  *
 914  * Return:
 915  * bool - True if statically schedulable, false otherwise
 916  */
 917 static bool subvp_validate_static_schedulability(struct dc *dc,
 918                                 struct dc_state *context,
 919                                 int vlevel)
 920 {
 921         bool schedulable = true;        // true by default for single display case
 922         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 923         uint32_t i, pipe_idx;
 924         uint8_t subvp_count = 0;
 925         uint8_t vactive_count = 0;
 926
 927         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 928                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 929
 930                 if (!pipe->stream)
 931                         continue;
 932
 933                 if (pipe->plane_state && !pipe->top_pipe &&
 934                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 935                         subvp_count++;
 936
 937                 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE
 938                 // switching (SubVP + VACTIVE unsupported). In situations where we force
 939                 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
 940                 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
 941                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 942                         vactive_count++;
 943                 }
 944                 pipe_idx++;
 945         }
 946
 947         if (subvp_count == 2) {
 948                 // Static schedulability check for SubVP + SubVP case
 949                 schedulable = subvp_subvp_schedulable(dc, context);
 950         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
 951                 // Static schedulability check for SubVP + VBLANK case. Also handle the case where
 952                 // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
 953                 if (vactive_count > 0)
 954                         schedulable = false;
 955                 else
 956                         schedulable = subvp_vblank_schedulable(dc, context);
 957         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
 958                         vactive_count > 0) {
 959                 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default.
 960                 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count.
 961                 // SubVP + VACTIVE currently unsupported
 962                 schedulable = false;
 963         }
 964         return schedulable;
 965 }
 966
 967 static void dcn32_full_validate_bw_helper(struct dc *dc,
 968                                    struct dc_state *context,
 969                                    display_e2e_pipe_params_st *pipes,
 970                                    int *vlevel,
 971                                    int *split,
 972                                    bool *merge,
 973                                    int *pipe_cnt)
 974 {
 975         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 976         unsigned int dc_pipe_idx = 0;
 977         bool found_supported_config = false;
 978         struct pipe_ctx *pipe = NULL;
 979         uint32_t non_subvp_pipes = 0;
 980         bool drr_pipe_found = false;
 981         uint32_t drr_pipe_index = 0;
 982         uint32_t i = 0;
 983
 984         dc_assert_fp_enabled();
 985
 986         /*
 987          * DML favors voltage over p-state, but we're more interested in
 988          * supporting p-state over voltage. We can't support p-state in
 989          * prefetch mode > 0 so try capping the prefetch mode to start.
 990          * Override present for testing.
 991          */
 992         if (dc->debug.dml_disallow_alternate_prefetch_modes)
 993                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
 994                         dm_prefetch_support_uclk_fclk_and_stutter;
 995         else
 996                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
 997                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
 998
 999         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1000         /* This may adjust vlevel and maxMpcComb */
1001         if (*vlevel < context->bw_ctx.dml.soc.num_states)
1002                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1003
1004         /* Conditions for setting up phantom pipes for SubVP:
1005          * 1. Not force disable SubVP
1006          * 2. Full update (i.e. !fast_validate)
1007          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1008          * 4. Display configuration passes validation
1009          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
1010          */
1011         if (!dc->debug.force_disable_subvp && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
1012             !dcn32_mpo_in_use(context) && (*vlevel == context->bw_ctx.dml.soc.num_states ||
1013             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
1014             dc->debug.force_subvp_mclk_switch)) {
1015
1016                 dcn32_merge_pipes_for_subvp(dc, context);
1017
1018                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
1019                         dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
1020                         /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1021                          * Adding phantom pipes won't change the validation result, so change the DML input param
1022                          * for P-State support before adding phantom pipes and recalculating the DML result.
1023                          * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
1024                          * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
1025                          * enough to support MCLK switching.
1026                          */
1027                         if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1028                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==
1029                                         dm_prefetch_support_uclk_fclk_and_stutter) {
1030                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1031                                                                 dm_prefetch_support_stutter;
1032                                 /* There are params (such as FabricClock) that need to be recalculated
1033                                  * after validation fails (otherwise it will be 0). Calculation for
1034                                  * phantom vactive requires call into DML, so we must ensure all the
1035                                  * vba params are valid otherwise we'll get incorrect phantom vactive.
1036                                  */
1037                                 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1038                         }
1039
1040                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1041
1042                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1043                         // Populate dppclk to trigger a recalculate in dml_get_voltage_level
1044                         // so the phantom pipe DLG params can be assigned correctly.
1045                         pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1046                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1047
1048                         if (*vlevel < context->bw_ctx.dml.soc.num_states &&
1049                             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
1050                             && subvp_validate_static_schedulability(dc, context, *vlevel)) {
1051                                 found_supported_config = true;
1052                         } else if (*vlevel < context->bw_ctx.dml.soc.num_states &&
1053                                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1054                                 /* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles
1055                                  * the case for SubVP + DRR, where the DRR display does not support MCLK switch
1056                                  * at it's native refresh rate / timing.
1057                                  */
1058                                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1059                                         pipe = &context->res_ctx.pipe_ctx[i];
1060                                         if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
1061                                             pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1062                                                 non_subvp_pipes++;
1063                                                 // Use ignore_msa_timing_param flag to identify as DRR
1064                                                 if (pipe->stream->ignore_msa_timing_param) {
1065                                                         drr_pipe_found = true;
1066                                                         drr_pipe_index = i;
1067                                                 }
1068                                         }
1069                                 }
1070                                 // If there is only 1 remaining non SubVP pipe that is DRR, check static
1071                                 // schedulability for SubVP + DRR.
1072                                 if (non_subvp_pipes == 1 && drr_pipe_found) {
1073                                         found_supported_config = subvp_drr_schedulable(dc, context,
1074                                                                                        &context->res_ctx.pipe_ctx[drr_pipe_index]);
1075                                 }
1076                         }
1077                 }
1078
1079                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
1080                 // remove phantom pipes and repopulate dml pipes
1081                 if (!found_supported_config) {
1082                         dc->res_pool->funcs->remove_phantom_pipes(dc, context);
1083                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1084                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1085                 } else {
1086                         // only call dcn20_validate_apply_pipe_split_flags if we found a supported config
1087                         memset(split, 0, MAX_PIPES * sizeof(int));
1088                         memset(merge, 0, MAX_PIPES * sizeof(bool));
1089                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1090
1091                         // Most populate phantom DLG params before programming hardware / timing for phantom pipe
1092                         DC_FP_START();
1093                         dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1094                         DC_FP_END();
1095
1096                         // Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1097                         // until driver has acquired the DMCUB lock to do it safely.
1098                 }
1099         }
1100 }
1101
1102 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
1103 {
1104         int i;
1105
1106         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1107                 if (!context->res_ctx.pipe_ctx[i].stream)
1108                         continue;
1109                 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1110                         return true;
1111         }
1112         return false;
1113 }
1114
1115 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
1116                                        display_e2e_pipe_params_st *pipes,
1117                                        int pipe_cnt, int vlevel)
1118 {
1119         int i, pipe_idx;
1120         bool usr_retraining_support = false;
1121         bool unbounded_req_enabled = false;
1122
1123         dc_assert_fp_enabled();
1124
1125         /* Writeback MCIF_WB arbitration parameters */
1126         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1127
1128         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1129         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1130         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1131         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1132         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1133         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1134         context->bw_ctx.bw.dcn.clk.p_state_change_support =
1135                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1136                                         != dm_dram_clock_change_unsupported;
1137         context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);
1138
1139         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1140         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1141         context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
1142         if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
1143                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
1144         else
1145                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1146
1147         usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1148         ASSERT(usr_retraining_support);
1149
1150         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1151                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1152
1153         unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
1154
1155         if (unbounded_req_enabled && pipe_cnt > 1) {
1156                 // Unbounded requesting should not ever be used when more than 1 pipe is enabled.
1157                 ASSERT(false);
1158                 unbounded_req_enabled = false;
1159         }
1160
1161         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1162                 if (!context->res_ctx.pipe_ctx[i].stream)
1163                         continue;
1164                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
1165                                 pipe_idx);
1166                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1167                                 pipe_idx);
1168                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
1169                                 pipe_idx);
1170                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1171                                 pipe_idx);
1172
1173                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1174                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1175                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1176                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
1177                 } else {
1178                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,
1179                                                         pipe_idx);
1180                         context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;
1181                 }
1182
1183                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1184                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1185                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1186                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1187                 pipe_idx++;
1188         }
1189         /*save a original dppclock copy*/
1190         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1191         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1192         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
1193                         * 1000;
1194         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
1195                         * 1000;
1196
1197         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes;
1198
1199         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1200                 if (context->res_ctx.pipe_ctx[i].stream)
1201                         context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;
1202         }
1203
1204         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1205
1206                 if (!context->res_ctx.pipe_ctx[i].stream)
1207                         continue;
1208
1209                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
1210                                 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
1211                                 pipe_cnt, pipe_idx);
1212
1213                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
1214                                 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1215                 pipe_idx++;
1216         }
1217 }
1218
1219 static struct pipe_ctx *dcn32_find_split_pipe(
1220                 struct dc *dc,
1221                 struct dc_state *context,
1222                 int old_index)
1223 {
1224         struct pipe_ctx *pipe = NULL;
1225         int i;
1226
1227         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1228                 pipe = &context->res_ctx.pipe_ctx[old_index];
1229                 pipe->pipe_idx = old_index;
1230         }
1231
1232         if (!pipe)
1233                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1234                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1235                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1236                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1237                                         pipe = &context->res_ctx.pipe_ctx[i];
1238                                         pipe->pipe_idx = i;
1239                                         break;
1240                                 }
1241                         }
1242                 }
1243
1244         /*
1245          * May need to fix pipes getting tossed from 1 opp to another on flip
1246          * Add for debugging transient underflow during topology updates:
1247          * ASSERT(pipe);
1248          */
1249         if (!pipe)
1250                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1251                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1252                                 pipe = &context->res_ctx.pipe_ctx[i];
1253                                 pipe->pipe_idx = i;
1254                                 break;
1255                         }
1256                 }
1257
1258         return pipe;
1259 }
1260
1261 static bool dcn32_split_stream_for_mpc_or_odm(
1262                 const struct dc *dc,
1263                 struct resource_context *res_ctx,
1264                 struct pipe_ctx *pri_pipe,
1265                 struct pipe_ctx *sec_pipe,
1266                 bool odm)
1267 {
1268         int pipe_idx = sec_pipe->pipe_idx;
1269         const struct resource_pool *pool = dc->res_pool;
1270
1271         DC_LOGGER_INIT(dc->ctx->logger);
1272
1273         if (odm && pri_pipe->plane_state) {
1274                 /* ODM + window MPO, where MPO window is on left half only */
1275                 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
1276                                 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {
1277
1278                         DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n",
1279                                         __func__,
1280                                         pri_pipe->pipe_idx);
1281                         return true;
1282                 }
1283
1284                 /* ODM + window MPO, where MPO window is on right half only */
1285                 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x +  pri_pipe->stream->src.width/2) {
1286
1287                         DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n",
1288                                         __func__,
1289                                         pri_pipe->pipe_idx);
1290                         return true;
1291                 }
1292         }
1293
1294         *sec_pipe = *pri_pipe;
1295
1296         sec_pipe->pipe_idx = pipe_idx;
1297         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1298         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1299         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1300         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1301         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1302         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1303         sec_pipe->stream_res.dsc = NULL;
1304         if (odm) {
1305                 if (pri_pipe->next_odm_pipe) {
1306                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1307                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1308                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1309                 }
1310                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1311                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1312                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1313                 }
1314                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1315                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1316                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1317                 }
1318                 pri_pipe->next_odm_pipe = sec_pipe;
1319                 sec_pipe->prev_odm_pipe = pri_pipe;
1320                 ASSERT(sec_pipe->top_pipe == NULL);
1321
1322                 if (!sec_pipe->top_pipe)
1323                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1324                 else
1325                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1326                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1327                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1328                         ASSERT(sec_pipe->stream_res.dsc);
1329                         if (sec_pipe->stream_res.dsc == NULL)
1330                                 return false;
1331                 }
1332         } else {
1333                 if (pri_pipe->bottom_pipe) {
1334                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1335                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1336                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1337                 }
1338                 pri_pipe->bottom_pipe = sec_pipe;
1339                 sec_pipe->top_pipe = pri_pipe;
1340
1341                 ASSERT(pri_pipe->plane_state);
1342         }
1343
1344         return true;
1345 }
1346
1347 bool dcn32_internal_validate_bw(struct dc *dc,
1348                                 struct dc_state *context,
1349                                 display_e2e_pipe_params_st *pipes,
1350                                 int *pipe_cnt_out,
1351                                 int *vlevel_out,
1352                                 bool fast_validate)
1353 {
1354         bool out = false;
1355         bool repopulate_pipes = false;
1356         int split[MAX_PIPES] = { 0 };
1357         bool merge[MAX_PIPES] = { false };
1358         bool newly_split[MAX_PIPES] = { false };
1359         int pipe_cnt, i, pipe_idx;
1360         int vlevel = context->bw_ctx.dml.soc.num_states;
1361         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1362
1363         dc_assert_fp_enabled();
1364
1365         ASSERT(pipes);
1366         if (!pipes)
1367                 return false;
1368
1369         // For each full update, remove all existing phantom pipes first
1370         dc->res_pool->funcs->remove_phantom_pipes(dc, context);
1371
1372         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1373
1374         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1375
1376         if (!pipe_cnt) {
1377                 out = true;
1378                 goto validate_out;
1379         }
1380
1381         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1382
1383         if (!fast_validate) {
1384                 DC_FP_START();
1385                 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
1386                 DC_FP_END();
1387         }
1388
1389         if (fast_validate ||
1390                         (dc->debug.dml_disallow_alternate_prefetch_modes &&
1391                         (vlevel == context->bw_ctx.dml.soc.num_states ||
1392                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
1393                 /*
1394                  * If dml_disallow_alternate_prefetch_modes is false, then we have already
1395                  * tried alternate prefetch modes during full validation.
1396                  *
1397                  * If mode is unsupported or there is no p-state support, then
1398                  * fall back to favouring voltage.
1399                  *
1400                  * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try
1401                  * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)
1402                  */
1403                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1404                         dm_prefetch_support_fclk_and_stutter;
1405
1406                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1407
1408                 /* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */
1409                 if (vlevel == context->bw_ctx.dml.soc.num_states) {
1410                         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1411                                 dm_prefetch_support_stutter;
1412                         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1413                 }
1414
1415                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1416                         memset(split, 0, sizeof(split));
1417                         memset(merge, 0, sizeof(merge));
1418                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1419                 }
1420         }
1421
1422         dml_log_mode_support_params(&context->bw_ctx.dml);
1423
1424         if (vlevel == context->bw_ctx.dml.soc.num_states)
1425                 goto validate_fail;
1426
1427         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1428                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1429                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1430
1431                 if (!pipe->stream)
1432                         continue;
1433
1434                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1435                                 && !dc->config.enable_windowed_mpo_odm
1436                                 && pipe->plane_state && mpo_pipe
1437                                 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1438                                                 &pipe->plane_res.scl_data.recout,
1439                                                 sizeof(struct rect)) != 0) {
1440                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1441                         goto validate_fail;
1442                 }
1443                 pipe_idx++;
1444         }
1445
1446         /* merge pipes if necessary */
1447         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1448                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1449
1450                 /*skip pipes that don't need merging*/
1451                 if (!merge[i])
1452                         continue;
1453
1454                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1455                 if (pipe->prev_odm_pipe) {
1456                         /*split off odm pipe*/
1457                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1458                         if (pipe->next_odm_pipe)
1459                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1460
1461                         pipe->bottom_pipe = NULL;
1462                         pipe->next_odm_pipe = NULL;
1463                         pipe->plane_state = NULL;
1464                         pipe->stream = NULL;
1465                         pipe->top_pipe = NULL;
1466                         pipe->prev_odm_pipe = NULL;
1467                         if (pipe->stream_res.dsc)
1468                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1469                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1470                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1471                         repopulate_pipes = true;
1472                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1473                         struct pipe_ctx *top_pipe = pipe->top_pipe;
1474                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1475
1476                         top_pipe->bottom_pipe = bottom_pipe;
1477                         if (bottom_pipe)
1478                                 bottom_pipe->top_pipe = top_pipe;
1479
1480                         pipe->top_pipe = NULL;
1481                         pipe->bottom_pipe = NULL;
1482                         pipe->plane_state = NULL;
1483                         pipe->stream = NULL;
1484                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1485                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1486                         repopulate_pipes = true;
1487                 } else
1488                         ASSERT(0); /* Should never try to merge master pipe */
1489
1490         }
1491
1492         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1493                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1494                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1495                 struct pipe_ctx *hsplit_pipe = NULL;
1496                 bool odm;
1497                 int old_index = -1;
1498
1499                 if (!pipe->stream || newly_split[i])
1500                         continue;
1501
1502                 pipe_idx++;
1503                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1504
1505                 if (!pipe->plane_state && !odm)
1506                         continue;
1507
1508                 if (split[i]) {
1509                         if (odm) {
1510                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1511                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1512                                 else if (old_pipe->next_odm_pipe)
1513                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
1514                         } else {
1515                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1516                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1517                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1518                                 else if (old_pipe->bottom_pipe &&
1519                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1520                                         old_index = old_pipe->bottom_pipe->pipe_idx;
1521                         }
1522                         hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
1523                         ASSERT(hsplit_pipe);
1524                         if (!hsplit_pipe)
1525                                 goto validate_fail;
1526
1527                         if (!dcn32_split_stream_for_mpc_or_odm(
1528                                         dc, &context->res_ctx,
1529                                         pipe, hsplit_pipe, odm))
1530                                 goto validate_fail;
1531
1532                         newly_split[hsplit_pipe->pipe_idx] = true;
1533                         repopulate_pipes = true;
1534                 }
1535                 if (split[i] == 4) {
1536                         struct pipe_ctx *pipe_4to1;
1537
1538                         if (odm && old_pipe->next_odm_pipe)
1539                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
1540                         else if (!odm && old_pipe->bottom_pipe &&
1541                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1542                                 old_index = old_pipe->bottom_pipe->pipe_idx;
1543                         else
1544                                 old_index = -1;
1545                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1546                         ASSERT(pipe_4to1);
1547                         if (!pipe_4to1)
1548                                 goto validate_fail;
1549                         if (!dcn32_split_stream_for_mpc_or_odm(
1550                                         dc, &context->res_ctx,
1551                                         pipe, pipe_4to1, odm))
1552                                 goto validate_fail;
1553                         newly_split[pipe_4to1->pipe_idx] = true;
1554
1555                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1556                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1557                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1558                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1559                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1560                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1561                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1562                         else
1563                                 old_index = -1;
1564                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1565                         ASSERT(pipe_4to1);
1566                         if (!pipe_4to1)
1567                                 goto validate_fail;
1568                         if (!dcn32_split_stream_for_mpc_or_odm(
1569                                         dc, &context->res_ctx,
1570                                         hsplit_pipe, pipe_4to1, odm))
1571                                 goto validate_fail;
1572                         newly_split[pipe_4to1->pipe_idx] = true;
1573                 }
1574                 if (odm)
1575                         dcn20_build_mapped_resource(dc, context, pipe->stream);
1576         }
1577
1578         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1579                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1580
1581                 if (pipe->plane_state) {
1582                         if (!resource_build_scaling_params(pipe))
1583                                 goto validate_fail;
1584                 }
1585         }
1586
1587         /* Actual dsc count per stream dsc validation*/
1588         if (!dcn20_validate_dsc(dc, context)) {
1589                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1590                 goto validate_fail;
1591         }
1592
1593         if (repopulate_pipes)
1594                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1595         *vlevel_out = vlevel;
1596         *pipe_cnt_out = pipe_cnt;
1597
1598         out = true;
1599         goto validate_out;
1600
1601 validate_fail:
1602         out = false;
1603
1604 validate_out:
1605         return out;
1606 }
1607
1608
1609 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
1610                                 display_e2e_pipe_params_st *pipes,
1611                                 int pipe_cnt,
1612                                 int vlevel)
1613 {
1614         int i, pipe_idx, vlevel_temp = 0;
1615         double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
1616         double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1617         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
1618                         dm_dram_clock_change_unsupported;
1619         unsigned int dummy_latency_index = 0;
1620         int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
1621         unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
1622         unsigned int min_dram_speed_mts_margin;
1623
1624         dc_assert_fp_enabled();
1625
1626         // Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK
1627         if (!pstate_en && dcn32_subvp_in_use(dc, context)) {
1628                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
1629                 pstate_en = true;
1630         }
1631
1632         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
1633
1634         if (!pstate_en) {
1635                 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */
1636                 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =
1637                         dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
1638
1639                 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
1640                         dummy_latency_index = dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
1641                                 context, pipes, pipe_cnt, vlevel);
1642
1643                         /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
1644                          * we reinstate the original dram_clock_change_latency_us on the context
1645                          * and all variables that may have changed up to this point, except the
1646                          * newly found dummy_latency_index
1647                          */
1648                         context->bw_ctx.dml.soc.dram_clock_change_latency_us =
1649                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
1650                         dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
1651                         maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
1652                         dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1653                         pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
1654                                         dm_dram_clock_change_unsupported;
1655                 }
1656         }
1657
1658         /* Set B:
1659          * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
1660          * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
1661          * calculations to cover bootup clocks.
1662          * DCFCLK: soc.clock_limits[2] when available
1663          * UCLK: soc.clock_limits[2] when available
1664          */
1665         if (dcn3_2_soc.num_states > 2) {
1666                 vlevel_temp = 2;
1667                 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
1668         } else
1669                 dcfclk = 615; //DCFCLK Vmin_lv
1670
1671         pipes[0].clks_cfg.voltage = vlevel_temp;
1672         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1673         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
1674
1675         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1676                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1677                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
1678                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1679                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1680         }
1681         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1682         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1683         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1684         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1685         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1686         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1687         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1688         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1689         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1690         context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1691
1692         /* Set D:
1693          * All clocks min.
1694          * DCFCLK: Min, as reported by PM FW when available
1695          * UCLK  : Min, as reported by PM FW when available
1696          * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
1697          */
1698
1699         if (dcn3_2_soc.num_states > 2) {
1700                 vlevel_temp = 0;
1701                 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
1702         } else
1703                 dcfclk = 615; //DCFCLK Vmin_lv
1704
1705         pipes[0].clks_cfg.voltage = vlevel_temp;
1706         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1707         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
1708
1709         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1710                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1711                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
1712                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1713                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1714         }
1715         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1716         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1717         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1718         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1719         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1720         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1721         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1722         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1723         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1724         context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1725
1726         /* Set C, for Dummy P-State:
1727          * All clocks min.
1728          * DCFCLK: Min, as reported by PM FW, when available
1729          * UCLK  : Min,  as reported by PM FW, when available
1730          * pstate latency as per UCLK state dummy pstate latency
1731          */
1732
1733         // For Set A and Set C use values from validation
1734         pipes[0].clks_cfg.voltage = vlevel;
1735         pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
1736         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1737
1738         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1739                 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
1740                 min_dram_speed_mts_margin = 160;
1741
1742                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
1743                         dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
1744
1745                 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
1746                         dm_dram_clock_change_unsupported) {
1747                         int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries - 1;
1748
1749                         min_dram_speed_mts =
1750                                 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
1751                 }
1752
1753                 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
1754                         /* find largest table entry that is lower than dram speed,
1755                          * but lower than DPM0 still uses DPM0
1756                          */
1757                         for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)
1758                                 if (min_dram_speed_mts + min_dram_speed_mts_margin >
1759                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
1760                                         break;
1761                 }
1762
1763                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
1764                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
1765
1766                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
1767                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1768                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1769         }
1770
1771         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1772         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1773         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1774         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1775         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1776         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1777         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1778         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1779         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1780         context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1781
1782         if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
1783                 /* The only difference between A and C is p-state latency, if p-state is not supported
1784                  * with full p-state latency we want to calculate DLG based on dummy p-state latency,
1785                  * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30.
1786                  */
1787                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
1788                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
1789         } else {
1790                 /* Set A:
1791                  * All clocks min.
1792                  * DCFCLK: Min, as reported by PM FW, when available
1793                  * UCLK: Min, as reported by PM FW, when available
1794                  */
1795                 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1796                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1797                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1798                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1799                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1800                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1801                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1802                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1803                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1804                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1805                 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1806         }
1807
1808         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1809                 if (!context->res_ctx.pipe_ctx[i].stream)
1810                         continue;
1811
1812                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1813                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1814
1815                 if (dc->config.forced_clocks) {
1816                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1817                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1818                 }
1819                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1820                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1821                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1822                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1823
1824                 pipe_idx++;
1825         }
1826
1827         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
1828
1829         dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1830
1831         if (!pstate_en)
1832                 /* Restore full p-state latency */
1833                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
1834                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
1835
1836         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1837                 dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context);
1838 }
1839
1840 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
1841                 unsigned int *optimal_dcfclk,
1842                 unsigned int *optimal_fclk)
1843 {
1844         double bw_from_dram, bw_from_dram1, bw_from_dram2;
1845
1846         bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
1847                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
1848         bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
1849                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
1850
1851         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
1852
1853         if (optimal_fclk)
1854                 *optimal_fclk = bw_from_dram /
1855                 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
1856
1857         if (optimal_dcfclk)
1858                 *optimal_dcfclk =  bw_from_dram /
1859                 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
1860 }
1861
1862 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
1863                 unsigned int index)
1864 {
1865         int i;
1866
1867         if (*num_entries == 0)
1868                 return;
1869
1870         for (i = index; i < *num_entries - 1; i++) {
1871                 table[i] = table[i + 1];
1872         }
1873         memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
1874 }
1875
1876 static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
1877                 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
1878 {
1879         int i, j;
1880         struct _vcs_dpi_voltage_scaling_st entry = {0};
1881
1882         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
1883                         max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
1884
1885         unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
1886
1887         static const unsigned int num_dcfclk_stas = 5;
1888         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
1889
1890         unsigned int num_uclk_dpms = 0;
1891         unsigned int num_fclk_dpms = 0;
1892         unsigned int num_dcfclk_dpms = 0;
1893
1894         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
1895                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
1896                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
1897                 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
1898                         max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
1899                 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
1900                         max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
1901                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
1902                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
1903                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
1904                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
1905                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
1906                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
1907                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
1908                         max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
1909
1910                 if (bw_params->clk_table.entries[i].memclk_mhz > 0)
1911                         num_uclk_dpms++;
1912                 if (bw_params->clk_table.entries[i].fclk_mhz > 0)
1913                         num_fclk_dpms++;
1914                 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0)
1915                         num_dcfclk_dpms++;
1916         }
1917
1918         if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)
1919                 return -1;
1920
1921         if (max_dppclk_mhz == 0)
1922                 max_dppclk_mhz = max_dispclk_mhz;
1923
1924         if (max_fclk_mhz == 0)
1925                 max_fclk_mhz = max_dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
1926
1927         if (max_phyclk_mhz == 0)
1928                 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
1929
1930         *num_entries = 0;
1931         entry.dispclk_mhz = max_dispclk_mhz;
1932         entry.dscclk_mhz = max_dispclk_mhz / 3;
1933         entry.dppclk_mhz = max_dppclk_mhz;
1934         entry.dtbclk_mhz = max_dtbclk_mhz;
1935         entry.phyclk_mhz = max_phyclk_mhz;
1936         entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
1937         entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
1938
1939         // Insert all the DCFCLK STAs
1940         for (i = 0; i < num_dcfclk_stas; i++) {
1941                 entry.dcfclk_mhz = dcfclk_sta_targets[i];
1942                 entry.fabricclk_mhz = 0;
1943                 entry.dram_speed_mts = 0;
1944
1945                 DC_FP_START();
1946                 insert_entry_into_table_sorted(table, num_entries, &entry);
1947                 DC_FP_END();
1948         }
1949
1950         // Insert the max DCFCLK
1951         entry.dcfclk_mhz = max_dcfclk_mhz;
1952         entry.fabricclk_mhz = 0;
1953         entry.dram_speed_mts = 0;
1954
1955         DC_FP_START();
1956         insert_entry_into_table_sorted(table, num_entries, &entry);
1957         DC_FP_END();
1958
1959         // Insert the UCLK DPMS
1960         for (i = 0; i < num_uclk_dpms; i++) {
1961                 entry.dcfclk_mhz = 0;
1962                 entry.fabricclk_mhz = 0;
1963                 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
1964
1965                 DC_FP_START();
1966                 insert_entry_into_table_sorted(table, num_entries, &entry);
1967                 DC_FP_END();
1968         }
1969
1970         // If FCLK is coarse grained, insert individual DPMs.
1971         if (num_fclk_dpms > 2) {
1972                 for (i = 0; i < num_fclk_dpms; i++) {
1973                         entry.dcfclk_mhz = 0;
1974                         entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
1975                         entry.dram_speed_mts = 0;
1976
1977                         DC_FP_START();
1978                         insert_entry_into_table_sorted(table, num_entries, &entry);
1979                         DC_FP_END();
1980                 }
1981         }
1982         // If FCLK fine grained, only insert max
1983         else {
1984                 entry.dcfclk_mhz = 0;
1985                 entry.fabricclk_mhz = max_fclk_mhz;
1986                 entry.dram_speed_mts = 0;
1987
1988                 DC_FP_START();
1989                 insert_entry_into_table_sorted(table, num_entries, &entry);
1990                 DC_FP_END();
1991         }
1992
1993         // At this point, the table contains all "points of interest" based on
1994         // DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock
1995         // ratios (by derate, are exact).
1996
1997         // Remove states that require higher clocks than are supported
1998         for (i = *num_entries - 1; i >= 0 ; i--) {
1999                 if (table[i].dcfclk_mhz > max_dcfclk_mhz ||
2000                                 table[i].fabricclk_mhz > max_fclk_mhz ||
2001                                 table[i].dram_speed_mts > max_uclk_mhz * 16)
2002                         remove_entry_from_table_at_index(table, num_entries, i);
2003         }
2004
2005         // At this point, the table only contains supported points of interest
2006         // it could be used as is, but some states may be redundant due to
2007         // coarse grained nature of some clocks, so we want to round up to
2008         // coarse grained DPMs and remove duplicates.
2009
2010         // Round up UCLKs
2011         for (i = *num_entries - 1; i >= 0 ; i--) {
2012                 for (j = 0; j < num_uclk_dpms; j++) {
2013                         if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
2014                                 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
2015                                 break;
2016                         }
2017                 }
2018         }
2019
2020         // If FCLK is coarse grained, round up to next DPMs
2021         if (num_fclk_dpms > 2) {
2022                 for (i = *num_entries - 1; i >= 0 ; i--) {
2023                         for (j = 0; j < num_fclk_dpms; j++) {
2024                                 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
2025                                         table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
2026                                         break;
2027                                 }
2028                         }
2029                 }
2030         }
2031         // Otherwise, round up to minimum.
2032         else {
2033                 for (i = *num_entries - 1; i >= 0 ; i--) {
2034                         if (table[i].fabricclk_mhz < min_fclk_mhz) {
2035                                 table[i].fabricclk_mhz = min_fclk_mhz;
2036                                 break;
2037                         }
2038                 }
2039         }
2040
2041         // Round DCFCLKs up to minimum
2042         for (i = *num_entries - 1; i >= 0 ; i--) {
2043                 if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
2044                         table[i].dcfclk_mhz = min_dcfclk_mhz;
2045                         break;
2046                 }
2047         }
2048
2049         // Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
2050         i = 0;
2051         while (i < *num_entries - 1) {
2052                 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
2053                                 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
2054                                 table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
2055                         remove_entry_from_table_at_index(table, num_entries, i + 1);
2056                 else
2057                         i++;
2058         }
2059
2060         // Fix up the state indicies
2061         for (i = *num_entries - 1; i >= 0 ; i--) {
2062                 table[i].state = i;
2063         }
2064
2065         return 0;
2066 }
2067
2068 /**
2069  * dcn32_update_bw_bounding_box
2070  *
2071  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from
2072  * spreadsheet with actual values as per dGPU SKU:
2073  * - with passed few options from dc->config
2074  * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
2075  *   need to get it from PM FW)
2076  * - with passed latency values (passed in ns units) in dc-> bb override for
2077  *   debugging purposes
2078  * - with passed latencies from VBIOS (in 100_ns units) if available for
2079  *   certain dGPU SKU
2080  * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
2081  *   of the same ASIC)
2082  * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
2083  *   FW for different clocks (which might differ for certain dGPU SKU of the
2084  *   same ASIC)
2085  */
2086 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
2087 {
2088         dc_assert_fp_enabled();
2089
2090         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2091                 /* Overrides from dc->config options */
2092                 dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
2093
2094                 /* Override from passed dc->bb_overrides if available*/
2095                 if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2096                                 && dc->bb_overrides.sr_exit_time_ns) {
2097                         dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2098                 }
2099
2100                 if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
2101                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
2102                                 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2103                         dcn3_2_soc.sr_enter_plus_exit_time_us =
2104                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2105                 }
2106
2107                 if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2108                         && dc->bb_overrides.urgent_latency_ns) {
2109                         dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2110                 }
2111
2112                 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
2113                                 != dc->bb_overrides.dram_clock_change_latency_ns
2114                                 && dc->bb_overrides.dram_clock_change_latency_ns) {
2115                         dcn3_2_soc.dram_clock_change_latency_us =
2116                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2117                 }
2118
2119                 if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000)
2120                                 != dc->bb_overrides.fclk_clock_change_latency_ns
2121                                 && dc->bb_overrides.fclk_clock_change_latency_ns) {
2122                         dcn3_2_soc.fclk_change_latency_us =
2123                                 dc->bb_overrides.fclk_clock_change_latency_ns / 1000;
2124                 }
2125
2126                 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
2127                                 != dc->bb_overrides.dummy_clock_change_latency_ns
2128                                 && dc->bb_overrides.dummy_clock_change_latency_ns) {
2129                         dcn3_2_soc.dummy_pstate_latency_us =
2130                                 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
2131                 }
2132
2133                 /* Override from VBIOS if VBIOS bb_info available */
2134                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
2135                         struct bp_soc_bb_info bb_info = {0};
2136
2137                         if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
2138                                 if (bb_info.dram_clock_change_latency_100ns > 0)
2139                                         dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
2140
2141                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
2142                                 dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
2143
2144                         if (bb_info.dram_sr_exit_latency_100ns > 0)
2145                                 dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
2146                         }
2147                 }
2148
2149                 /* Override from VBIOS for num_chan */
2150                 if (dc->ctx->dc_bios->vram_info.num_chans)
2151                         dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2152
2153                 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2154                         dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2155
2156         }
2157
2158         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
2159         dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2160         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2161
2162         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
2163         if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
2164                 if (dc->debug.use_legacy_soc_bb_mechanism) {
2165                         unsigned int i = 0, j = 0, num_states = 0;
2166
2167                         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2168                         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2169                         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2170                         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2171                         unsigned int min_dcfclk = UINT_MAX;
2172                         /* Set 199 as first value in STA target array to have a minimum DCFCLK value.
2173                          * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */
2174                         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2175                         unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
2176                         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
2177
2178                         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2179                                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2180                                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2181                                 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
2182                                                 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
2183                                         min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
2184                                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2185                                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2186                                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2187                                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2188                                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2189                                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2190                         }
2191                         if (min_dcfclk > dcfclk_sta_targets[0])
2192                                 dcfclk_sta_targets[0] = min_dcfclk;
2193                         if (!max_dcfclk_mhz)
2194                                 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2195                         if (!max_dispclk_mhz)
2196                                 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2197                         if (!max_dppclk_mhz)
2198                                 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
2199                         if (!max_phyclk_mhz)
2200                                 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2201
2202                         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2203                                 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2204                                 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2205                                 num_dcfclk_sta_targets++;
2206                         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2207                                 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2208                                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2209                                         if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2210                                                 dcfclk_sta_targets[i] = max_dcfclk_mhz;
2211                                                 break;
2212                                         }
2213                                 }
2214                                 // Update size of array since we "removed" duplicates
2215                                 num_dcfclk_sta_targets = i + 1;
2216                         }
2217
2218                         num_uclk_states = bw_params->clk_table.num_entries;
2219
2220                         // Calculate optimal dcfclk for each uclk
2221                         for (i = 0; i < num_uclk_states; i++) {
2222                                 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2223                                                 &optimal_dcfclk_for_uclk[i], NULL);
2224                                 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2225                                         optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2226                                 }
2227                         }
2228
2229                         // Calculate optimal uclk for each dcfclk sta target
2230                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
2231                                 for (j = 0; j < num_uclk_states; j++) {
2232                                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2233                                                 optimal_uclk_for_dcfclk_sta_targets[i] =
2234                                                                 bw_params->clk_table.entries[j].memclk_mhz * 16;
2235                                                 break;
2236                                         }
2237                                 }
2238                         }
2239
2240                         i = 0;
2241                         j = 0;
2242                         // create the final dcfclk and uclk table
2243                         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2244                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2245                                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2246                                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2247                                 } else {
2248                                         if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2249                                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2250                                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2251                                         } else {
2252                                                 j = num_uclk_states;
2253                                         }
2254                                 }
2255                         }
2256
2257                         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2258                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2259                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2260                         }
2261
2262                         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2263                                         optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2264                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2265                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2266                         }
2267
2268                         dcn3_2_soc.num_states = num_states;
2269                         for (i = 0; i < dcn3_2_soc.num_states; i++) {
2270                                 dcn3_2_soc.clock_limits[i].state = i;
2271                                 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2272                                 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2273
2274                                 /* Fill all states with max values of all these clocks */
2275                                 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
2276                                 dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
2277                                 dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
2278                                 dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
2279
2280                                 /* Populate from bw_params for DTBCLK, SOCCLK */
2281                                 if (i > 0) {
2282                                         if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
2283                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
2284                                         } else {
2285                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2286                                         }
2287                                 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
2288                                         dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2289                                 }
2290
2291                                 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
2292                                         dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
2293                                 else
2294                                         dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
2295
2296                                 if (!dram_speed_mts[i] && i > 0)
2297                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
2298                                 else
2299                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2300
2301                                 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
2302                                 /* PHYCLK_D18, PHYCLK_D32 */
2303                                 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2304                                 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2305                         }
2306                 } else {
2307                         build_synthetic_soc_states(bw_params, dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);
2308                 }
2309
2310                 /* Re-init DML with updated bb */
2311                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2312                 if (dc->current_state)
2313                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2314         }
2315 }
2316