drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

   1 /*
   2  * Copyright 2019-2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "resource.h"
  27 #include "clk_mgr.h"
  28
  29 #include "dml/dcn20/dcn20_fpu.h"
  30 #include "dcn31_fpu.h"
  31
  32 /**
  33  * DOC: DCN31x FPU manipulation Overview
  34  *
  35  * The DCN architecture relies on FPU operations, which require special
  36  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
  37  * want to avoid spreading FPU access across multiple files. With this idea in
  38  * mind, this file aims to centralize all DCN3.1.x functions that require FPU
  39  * access in a single place. Code in this file follows the following code
  40  * pattern:
  41  *
  42  * 1. Functions that use FPU operations should be isolated in static functions.
  43  * 2. The FPU functions should have the noinline attribute to ensure anything
  44  *    that deals with FP register is contained within this call.
  45  * 3. All function that needs to be accessed outside this file requires a
  46  *    public interface that not uses any FPU reference.
  47  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
  48  *    to ensure that the caller invokes it before access any function available
  49  *    in this file. For this reason, public functions in this file must invoke
  50  *    dc_assert_fp_enabled();
  51  */
  52
  53 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
  54         .gpuvm_enable = 1,
  55         .gpuvm_max_page_table_levels = 1,
  56         .hostvm_enable = 1,
  57         .hostvm_max_page_table_levels = 2,
  58         .rob_buffer_size_kbytes = 64,
  59         .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
  60         .config_return_buffer_size_in_kbytes = 1792,
  61         .compressed_buffer_segment_size_in_kbytes = 64,
  62         .meta_fifo_size_in_kentries = 32,
  63         .zero_size_buffer_entries = 512,
  64         .compbuf_reserved_space_64b = 256,
  65         .compbuf_reserved_space_zs = 64,
  66         .dpp_output_buffer_pixels = 2560,
  67         .opp_output_buffer_lines = 1,
  68         .pixel_chunk_size_kbytes = 8,
  69         .meta_chunk_size_kbytes = 2,
  70         .min_meta_chunk_size_bytes = 256,
  71         .writeback_chunk_size_kbytes = 8,
  72         .ptoi_supported = false,
  73         .num_dsc = 3,
  74         .maximum_dsc_bits_per_component = 10,
  75         .dsc422_native_support = false,
  76         .is_line_buffer_bpp_fixed = true,
  77         .line_buffer_fixed_bpp = 48,
  78         .line_buffer_size_bits = 789504,
  79         .max_line_buffer_lines = 12,
  80         .writeback_interface_buffer_size_kbytes = 90,
  81         .max_num_dpp = 4,
  82         .max_num_otg = 4,
  83         .max_num_hdmi_frl_outputs = 1,
  84         .max_num_wb = 1,
  85         .max_dchub_pscl_bw_pix_per_clk = 4,
  86         .max_pscl_lb_bw_pix_per_clk = 2,
  87         .max_lb_vscl_bw_pix_per_clk = 4,
  88         .max_vscl_hscl_bw_pix_per_clk = 4,
  89         .max_hscl_ratio = 6,
  90         .max_vscl_ratio = 6,
  91         .max_hscl_taps = 8,
  92         .max_vscl_taps = 8,
  93         .dpte_buffer_size_in_pte_reqs_luma = 64,
  94         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  95         .dispclk_ramp_margin_percent = 1,
  96         .max_inter_dcn_tile_repeaters = 8,
  97         .cursor_buffer_size = 16,
  98         .cursor_chunk_size = 2,
  99         .writeback_line_buffer_buffer_size = 0,
 100         .writeback_min_hscl_ratio = 1,
 101         .writeback_min_vscl_ratio = 1,
 102         .writeback_max_hscl_ratio = 1,
 103         .writeback_max_vscl_ratio = 1,
 104         .writeback_max_hscl_taps = 1,
 105         .writeback_max_vscl_taps = 1,
 106         .dppclk_delay_subtotal = 46,
 107         .dppclk_delay_scl = 50,
 108         .dppclk_delay_scl_lb_only = 16,
 109         .dppclk_delay_cnvc_formatter = 27,
 110         .dppclk_delay_cnvc_cursor = 6,
 111         .dispclk_delay_subtotal = 119,
 112         .dynamic_metadata_vm_enabled = false,
 113         .odm_combine_4to1_supported = false,
 114         .dcc_supported = true,
 115 };
 116
 117 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
 118                 /*TODO: correct dispclk/dppclk voltage level determination*/
 119         .clock_limits = {
 120                 {
 121                         .state = 0,
 122                         .dispclk_mhz = 1200.0,
 123                         .dppclk_mhz = 1200.0,
 124                         .phyclk_mhz = 600.0,
 125                         .phyclk_d18_mhz = 667.0,
 126                         .dscclk_mhz = 186.0,
 127                         .dtbclk_mhz = 625.0,
 128                 },
 129                 {
 130                         .state = 1,
 131                         .dispclk_mhz = 1200.0,
 132                         .dppclk_mhz = 1200.0,
 133                         .phyclk_mhz = 810.0,
 134                         .phyclk_d18_mhz = 667.0,
 135                         .dscclk_mhz = 209.0,
 136                         .dtbclk_mhz = 625.0,
 137                 },
 138                 {
 139                         .state = 2,
 140                         .dispclk_mhz = 1200.0,
 141                         .dppclk_mhz = 1200.0,
 142                         .phyclk_mhz = 810.0,
 143                         .phyclk_d18_mhz = 667.0,
 144                         .dscclk_mhz = 209.0,
 145                         .dtbclk_mhz = 625.0,
 146                 },
 147                 {
 148                         .state = 3,
 149                         .dispclk_mhz = 1200.0,
 150                         .dppclk_mhz = 1200.0,
 151                         .phyclk_mhz = 810.0,
 152                         .phyclk_d18_mhz = 667.0,
 153                         .dscclk_mhz = 371.0,
 154                         .dtbclk_mhz = 625.0,
 155                 },
 156                 {
 157                         .state = 4,
 158                         .dispclk_mhz = 1200.0,
 159                         .dppclk_mhz = 1200.0,
 160                         .phyclk_mhz = 810.0,
 161                         .phyclk_d18_mhz = 667.0,
 162                         .dscclk_mhz = 417.0,
 163                         .dtbclk_mhz = 625.0,
 164                 },
 165         },
 166         .num_states = 5,
 167         .sr_exit_time_us = 9.0,
 168         .sr_enter_plus_exit_time_us = 11.0,
 169         .sr_exit_z8_time_us = 442.0,
 170         .sr_enter_plus_exit_z8_time_us = 560.0,
 171         .writeback_latency_us = 12.0,
 172         .dram_channel_width_bytes = 4,
 173         .round_trip_ping_latency_dcfclk_cycles = 106,
 174         .urgent_latency_pixel_data_only_us = 4.0,
 175         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 176         .urgent_latency_vm_data_only_us = 4.0,
 177         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 178         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 179         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 180         .pct_ideal_sdp_bw_after_urgent = 80.0,
 181         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 182         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 183         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 184         .max_avg_sdp_bw_use_normal_percent = 60.0,
 185         .max_avg_dram_bw_use_normal_percent = 60.0,
 186         .fabric_datapath_to_dcn_data_return_bytes = 32,
 187         .return_bus_width_bytes = 64,
 188         .downspread_percent = 0.38,
 189         .dcn_downspread_percent = 0.5,
 190         .gpuvm_min_page_size_bytes = 4096,
 191         .hostvm_min_page_size_bytes = 4096,
 192         .do_urgent_latency_adjustment = false,
 193         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 194         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 195 };
 196
 197 struct _vcs_dpi_ip_params_st dcn3_15_ip = {
 198         .gpuvm_enable = 1,
 199         .gpuvm_max_page_table_levels = 1,
 200         .hostvm_enable = 1,
 201         .hostvm_max_page_table_levels = 2,
 202         .rob_buffer_size_kbytes = 64,
 203         .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE,
 204         .min_comp_buffer_size_kbytes = DCN3_15_MIN_COMPBUF_SIZE_KB,
 205         .config_return_buffer_size_in_kbytes = 1024,
 206         .compressed_buffer_segment_size_in_kbytes = 64,
 207         .meta_fifo_size_in_kentries = 32,
 208         .zero_size_buffer_entries = 512,
 209         .compbuf_reserved_space_64b = 256,
 210         .compbuf_reserved_space_zs = 64,
 211         .dpp_output_buffer_pixels = 2560,
 212         .opp_output_buffer_lines = 1,
 213         .pixel_chunk_size_kbytes = 8,
 214         .meta_chunk_size_kbytes = 2,
 215         .min_meta_chunk_size_bytes = 256,
 216         .writeback_chunk_size_kbytes = 8,
 217         .ptoi_supported = false,
 218         .num_dsc = 3,
 219         .maximum_dsc_bits_per_component = 10,
 220         .dsc422_native_support = false,
 221         .is_line_buffer_bpp_fixed = true,
 222         .line_buffer_fixed_bpp = 49,
 223         .line_buffer_size_bits = 789504,
 224         .max_line_buffer_lines = 12,
 225         .writeback_interface_buffer_size_kbytes = 90,
 226         .max_num_dpp = 4,
 227         .max_num_otg = 4,
 228         .max_num_hdmi_frl_outputs = 1,
 229         .max_num_wb = 1,
 230         .max_dchub_pscl_bw_pix_per_clk = 4,
 231         .max_pscl_lb_bw_pix_per_clk = 2,
 232         .max_lb_vscl_bw_pix_per_clk = 4,
 233         .max_vscl_hscl_bw_pix_per_clk = 4,
 234         .max_hscl_ratio = 6,
 235         .max_vscl_ratio = 6,
 236         .max_hscl_taps = 8,
 237         .max_vscl_taps = 8,
 238         .dpte_buffer_size_in_pte_reqs_luma = 64,
 239         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 240         .dispclk_ramp_margin_percent = 1,
 241         .max_inter_dcn_tile_repeaters = 9,
 242         .cursor_buffer_size = 16,
 243         .cursor_chunk_size = 2,
 244         .writeback_line_buffer_buffer_size = 0,
 245         .writeback_min_hscl_ratio = 1,
 246         .writeback_min_vscl_ratio = 1,
 247         .writeback_max_hscl_ratio = 1,
 248         .writeback_max_vscl_ratio = 1,
 249         .writeback_max_hscl_taps = 1,
 250         .writeback_max_vscl_taps = 1,
 251         .dppclk_delay_subtotal = 46,
 252         .dppclk_delay_scl = 50,
 253         .dppclk_delay_scl_lb_only = 16,
 254         .dppclk_delay_cnvc_formatter = 27,
 255         .dppclk_delay_cnvc_cursor = 6,
 256         .dispclk_delay_subtotal = 119,
 257         .dynamic_metadata_vm_enabled = false,
 258         .odm_combine_4to1_supported = false,
 259         .dcc_supported = true,
 260 };
 261
 262 struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {
 263                 /*TODO: correct dispclk/dppclk voltage level determination*/
 264         .clock_limits = {
 265                 {
 266                         .state = 0,
 267                         .dispclk_mhz = 1372.0,
 268                         .dppclk_mhz = 1372.0,
 269                         .phyclk_mhz = 810.0,
 270                         .phyclk_d18_mhz = 667.0,
 271                         .dscclk_mhz = 417.0,
 272                         .dtbclk_mhz = 600.0,
 273                 },
 274                 {
 275                         .state = 1,
 276                         .dispclk_mhz = 1372.0,
 277                         .dppclk_mhz = 1372.0,
 278                         .phyclk_mhz = 810.0,
 279                         .phyclk_d18_mhz = 667.0,
 280                         .dscclk_mhz = 417.0,
 281                         .dtbclk_mhz = 600.0,
 282                 },
 283                 {
 284                         .state = 2,
 285                         .dispclk_mhz = 1372.0,
 286                         .dppclk_mhz = 1372.0,
 287                         .phyclk_mhz = 810.0,
 288                         .phyclk_d18_mhz = 667.0,
 289                         .dscclk_mhz = 417.0,
 290                         .dtbclk_mhz = 600.0,
 291                 },
 292                 {
 293                         .state = 3,
 294                         .dispclk_mhz = 1372.0,
 295                         .dppclk_mhz = 1372.0,
 296                         .phyclk_mhz = 810.0,
 297                         .phyclk_d18_mhz = 667.0,
 298                         .dscclk_mhz = 417.0,
 299                         .dtbclk_mhz = 600.0,
 300                 },
 301                 {
 302                         .state = 4,
 303                         .dispclk_mhz = 1372.0,
 304                         .dppclk_mhz = 1372.0,
 305                         .phyclk_mhz = 810.0,
 306                         .phyclk_d18_mhz = 667.0,
 307                         .dscclk_mhz = 417.0,
 308                         .dtbclk_mhz = 600.0,
 309                 },
 310         },
 311         .num_states = 5,
 312         .sr_exit_time_us = 9.0,
 313         .sr_enter_plus_exit_time_us = 11.0,
 314         .sr_exit_z8_time_us = 50.0,
 315         .sr_enter_plus_exit_z8_time_us = 50.0,
 316         .writeback_latency_us = 12.0,
 317         .dram_channel_width_bytes = 4,
 318         .round_trip_ping_latency_dcfclk_cycles = 106,
 319         .urgent_latency_pixel_data_only_us = 4.0,
 320         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 321         .urgent_latency_vm_data_only_us = 4.0,
 322         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 323         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 324         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 325         .pct_ideal_sdp_bw_after_urgent = 80.0,
 326         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 327         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 328         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 329         .max_avg_sdp_bw_use_normal_percent = 60.0,
 330         .max_avg_dram_bw_use_normal_percent = 60.0,
 331         .fabric_datapath_to_dcn_data_return_bytes = 32,
 332         .return_bus_width_bytes = 64,
 333         .downspread_percent = 0.38,
 334         .dcn_downspread_percent = 0.38,
 335         .gpuvm_min_page_size_bytes = 4096,
 336         .hostvm_min_page_size_bytes = 4096,
 337         .do_urgent_latency_adjustment = false,
 338         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 339         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 340 };
 341
 342 struct _vcs_dpi_ip_params_st dcn3_16_ip = {
 343         .gpuvm_enable = 1,
 344         .gpuvm_max_page_table_levels = 1,
 345         .hostvm_enable = 1,
 346         .hostvm_max_page_table_levels = 2,
 347         .rob_buffer_size_kbytes = 64,
 348         .det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE,
 349         .config_return_buffer_size_in_kbytes = 1024,
 350         .compressed_buffer_segment_size_in_kbytes = 64,
 351         .meta_fifo_size_in_kentries = 32,
 352         .zero_size_buffer_entries = 512,
 353         .compbuf_reserved_space_64b = 256,
 354         .compbuf_reserved_space_zs = 64,
 355         .dpp_output_buffer_pixels = 2560,
 356         .opp_output_buffer_lines = 1,
 357         .pixel_chunk_size_kbytes = 8,
 358         .meta_chunk_size_kbytes = 2,
 359         .min_meta_chunk_size_bytes = 256,
 360         .writeback_chunk_size_kbytes = 8,
 361         .ptoi_supported = false,
 362         .num_dsc = 3,
 363         .maximum_dsc_bits_per_component = 10,
 364         .dsc422_native_support = false,
 365         .is_line_buffer_bpp_fixed = true,
 366         .line_buffer_fixed_bpp = 48,
 367         .line_buffer_size_bits = 789504,
 368         .max_line_buffer_lines = 12,
 369         .writeback_interface_buffer_size_kbytes = 90,
 370         .max_num_dpp = 4,
 371         .max_num_otg = 4,
 372         .max_num_hdmi_frl_outputs = 1,
 373         .max_num_wb = 1,
 374         .max_dchub_pscl_bw_pix_per_clk = 4,
 375         .max_pscl_lb_bw_pix_per_clk = 2,
 376         .max_lb_vscl_bw_pix_per_clk = 4,
 377         .max_vscl_hscl_bw_pix_per_clk = 4,
 378         .max_hscl_ratio = 6,
 379         .max_vscl_ratio = 6,
 380         .max_hscl_taps = 8,
 381         .max_vscl_taps = 8,
 382         .dpte_buffer_size_in_pte_reqs_luma = 64,
 383         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 384         .dispclk_ramp_margin_percent = 1,
 385         .max_inter_dcn_tile_repeaters = 8,
 386         .cursor_buffer_size = 16,
 387         .cursor_chunk_size = 2,
 388         .writeback_line_buffer_buffer_size = 0,
 389         .writeback_min_hscl_ratio = 1,
 390         .writeback_min_vscl_ratio = 1,
 391         .writeback_max_hscl_ratio = 1,
 392         .writeback_max_vscl_ratio = 1,
 393         .writeback_max_hscl_taps = 1,
 394         .writeback_max_vscl_taps = 1,
 395         .dppclk_delay_subtotal = 46,
 396         .dppclk_delay_scl = 50,
 397         .dppclk_delay_scl_lb_only = 16,
 398         .dppclk_delay_cnvc_formatter = 27,
 399         .dppclk_delay_cnvc_cursor = 6,
 400         .dispclk_delay_subtotal = 119,
 401         .dynamic_metadata_vm_enabled = false,
 402         .odm_combine_4to1_supported = false,
 403         .dcc_supported = true,
 404 };
 405
 406 struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
 407                 /*TODO: correct dispclk/dppclk voltage level determination*/
 408         .clock_limits = {
 409                 {
 410                         .state = 0,
 411                         .dispclk_mhz = 556.0,
 412                         .dppclk_mhz = 556.0,
 413                         .phyclk_mhz = 600.0,
 414                         .phyclk_d18_mhz = 445.0,
 415                         .dscclk_mhz = 186.0,
 416                         .dtbclk_mhz = 625.0,
 417                 },
 418                 {
 419                         .state = 1,
 420                         .dispclk_mhz = 625.0,
 421                         .dppclk_mhz = 625.0,
 422                         .phyclk_mhz = 810.0,
 423                         .phyclk_d18_mhz = 667.0,
 424                         .dscclk_mhz = 209.0,
 425                         .dtbclk_mhz = 625.0,
 426                 },
 427                 {
 428                         .state = 2,
 429                         .dispclk_mhz = 625.0,
 430                         .dppclk_mhz = 625.0,
 431                         .phyclk_mhz = 810.0,
 432                         .phyclk_d18_mhz = 667.0,
 433                         .dscclk_mhz = 209.0,
 434                         .dtbclk_mhz = 625.0,
 435                 },
 436                 {
 437                         .state = 3,
 438                         .dispclk_mhz = 1112.0,
 439                         .dppclk_mhz = 1112.0,
 440                         .phyclk_mhz = 810.0,
 441                         .phyclk_d18_mhz = 667.0,
 442                         .dscclk_mhz = 371.0,
 443                         .dtbclk_mhz = 625.0,
 444                 },
 445                 {
 446                         .state = 4,
 447                         .dispclk_mhz = 1250.0,
 448                         .dppclk_mhz = 1250.0,
 449                         .phyclk_mhz = 810.0,
 450                         .phyclk_d18_mhz = 667.0,
 451                         .dscclk_mhz = 417.0,
 452                         .dtbclk_mhz = 625.0,
 453                 },
 454         },
 455         .num_states = 5,
 456         .sr_exit_time_us = 9.0,
 457         .sr_enter_plus_exit_time_us = 11.0,
 458         .sr_exit_z8_time_us = 442.0,
 459         .sr_enter_plus_exit_z8_time_us = 560.0,
 460         .writeback_latency_us = 12.0,
 461         .dram_channel_width_bytes = 4,
 462         .round_trip_ping_latency_dcfclk_cycles = 106,
 463         .urgent_latency_pixel_data_only_us = 4.0,
 464         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 465         .urgent_latency_vm_data_only_us = 4.0,
 466         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 467         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 468         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 469         .pct_ideal_sdp_bw_after_urgent = 80.0,
 470         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 471         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 472         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 473         .max_avg_sdp_bw_use_normal_percent = 60.0,
 474         .max_avg_dram_bw_use_normal_percent = 60.0,
 475         .fabric_datapath_to_dcn_data_return_bytes = 32,
 476         .return_bus_width_bytes = 64,
 477         .downspread_percent = 0.38,
 478         .dcn_downspread_percent = 0.5,
 479         .gpuvm_min_page_size_bytes = 4096,
 480         .hostvm_min_page_size_bytes = 4096,
 481         .do_urgent_latency_adjustment = false,
 482         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 483         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 484 };
 485
 486 void dcn31_calculate_wm_and_dlg_fp(
 487                 struct dc *dc, struct dc_state *context,
 488                 display_e2e_pipe_params_st *pipes,
 489                 int pipe_cnt,
 490                 int vlevel)
 491 {
 492         int i, pipe_idx;
 493         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 494
 495         dc_assert_fp_enabled();
 496
 497         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
 498                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
 499
 500         /* We don't recalculate clocks for 0 pipe configs, which can block
 501          * S0i3 as high clocks will block low power states
 502          * Override any clocks that can block S0i3 to min here
 503          */
 504         if (pipe_cnt == 0) {
 505                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
 506                 return;
 507         }
 508
 509         pipes[0].clks_cfg.voltage = vlevel;
 510         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 511         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
 512
 513 #if 0 // TODO
 514         /* Set B:
 515          * TODO
 516          */
 517         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
 518                 if (vlevel == 0) {
 519                         pipes[0].clks_cfg.voltage = 1;
 520                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
 521                 }
 522                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
 523                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
 524                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
 525         }
 526         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 527         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 528         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 529         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 530         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 531         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 532         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 533         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 534         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 535         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 536
 537         pipes[0].clks_cfg.voltage = vlevel;
 538         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 539
 540         /* Set C:
 541          * TODO
 542          */
 543         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
 544                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
 545                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
 546                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
 547         }
 548         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 549         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 550         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 551         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 552         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 553         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 554         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 555         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 556         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 557         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 558
 559         /* Set D:
 560          * TODO
 561          */
 562         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
 563                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
 564                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
 565                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
 566         }
 567         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 568         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 569         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 570         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 571         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 572         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 573         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 574         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 575         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 576         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 577 #endif
 578
 579         /* Set A:
 580          * All clocks min required
 581          *
 582          * Set A calculated last so that following calculations are based on Set A
 583          */
 584         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
 585         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 586         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 587         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 588         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 589         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 590         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 591         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 592         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 593         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 594         context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 595         /* TODO: remove: */
 596         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
 597         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
 598         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
 599         /* end remove*/
 600
 601         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 602                 if (!context->res_ctx.pipe_ctx[i].stream)
 603                         continue;
 604
 605                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
 606                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 607
 608                 if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
 609                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
 610                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
 611                 }
 612                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
 613                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
 614                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 615                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
 616
 617                 pipe_idx++;
 618         }
 619
 620         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 621 }
 622
 623 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 624 {
 625         struct clk_limit_table *clk_table = &bw_params->clk_table;
 626         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 627         unsigned int i, closest_clk_lvl;
 628         int j;
 629
 630         dc_assert_fp_enabled();
 631
 632         // Default clock levels are used for diags, which may lead to overclocking.
 633         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 634                 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 635
 636                 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 637                 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
 638                 dcn3_1_soc.num_chans = bw_params->num_channels;
 639
 640                 ASSERT(clk_table->num_entries);
 641
 642                 /* Prepass to find max clocks independent of voltage level. */
 643                 for (i = 0; i < clk_table->num_entries; ++i) {
 644                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
 645                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
 646                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
 647                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
 648                 }
 649
 650                 for (i = 0; i < clk_table->num_entries; i++) {
 651                         /* loop backwards*/
 652                         for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
 653                                 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
 654                                         closest_clk_lvl = j;
 655                                         break;
 656                                 }
 657                         }
 658
 659                         clock_limits[i].state = i;
 660
 661                         /* Clocks dependent on voltage level. */
 662                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 663                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
 664                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
 665                         clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 666
 667                         /* Clocks independent of voltage level. */
 668                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 669                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 670
 671                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 672                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 673
 674                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
 675                         clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
 676                         clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
 677                         clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
 678                         clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 679                 }
 680                 for (i = 0; i < clk_table->num_entries; i++)
 681                         dcn3_1_soc.clock_limits[i] = clock_limits[i];
 682                 if (clk_table->num_entries) {
 683                         dcn3_1_soc.num_states = clk_table->num_entries;
 684                 }
 685         }
 686
 687         dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 688         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 689
 690         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 691                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
 692         else
 693                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
 694 }
 695
 696 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 697 {
 698         struct clk_limit_table *clk_table = &bw_params->clk_table;
 699         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 700         unsigned int i, closest_clk_lvl;
 701         int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 702         int j;
 703
 704         dc_assert_fp_enabled();
 705
 706         // Default clock levels are used for diags, which may lead to overclocking.
 707         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 708
 709                 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 710                 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;
 711                 dcn3_15_soc.num_chans = bw_params->num_channels;
 712
 713                 ASSERT(clk_table->num_entries);
 714
 715                 /* Prepass to find max clocks independent of voltage level. */
 716                 for (i = 0; i < clk_table->num_entries; ++i) {
 717                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
 718                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
 719                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
 720                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
 721                 }
 722
 723                 for (i = 0; i < clk_table->num_entries; i++) {
 724                         /* loop backwards*/
 725                         for (closest_clk_lvl = 0, j = dcn3_15_soc.num_states - 1; j >= 0; j--) {
 726                                 if ((unsigned int) dcn3_15_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
 727                                         closest_clk_lvl = j;
 728                                         break;
 729                                 }
 730                         }
 731                         if (clk_table->num_entries == 1) {
 732                                 /*smu gives one DPM level, let's take the highest one*/
 733                                 closest_clk_lvl = dcn3_15_soc.num_states - 1;
 734                         }
 735
 736                         clock_limits[i].state = i;
 737
 738                         /* Clocks dependent on voltage level. */
 739                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 740                         if (clk_table->num_entries == 1 &&
 741                                 clock_limits[i].dcfclk_mhz < dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
 742                                 /*SMU fix not released yet*/
 743                                 clock_limits[i].dcfclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
 744                         }
 745                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
 746                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
 747                         clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 748
 749                         /* Clocks independent of voltage level. */
 750                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 751                                 dcn3_15_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 752
 753                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 754                                 dcn3_15_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 755
 756                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_15_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
 757                         clock_limits[i].dscclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
 758                         clock_limits[i].dtbclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
 759                         clock_limits[i].phyclk_d18_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
 760                         clock_limits[i].phyclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 761                 }
 762                 for (i = 0; i < clk_table->num_entries; i++)
 763                         dcn3_15_soc.clock_limits[i] = clock_limits[i];
 764                 if (clk_table->num_entries) {
 765                         dcn3_15_soc.num_states = clk_table->num_entries;
 766                 }
 767         }
 768
 769         if (max_dispclk_mhz) {
 770                 dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 771                 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 772         }
 773
 774         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 775                 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31);
 776         else
 777                 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31_FPGA);
 778 }
 779
 780 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 781 {
 782         struct clk_limit_table *clk_table = &bw_params->clk_table;
 783         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 784         unsigned int i, closest_clk_lvl;
 785         int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 786         int j;
 787
 788         dc_assert_fp_enabled();
 789
 790         // Default clock levels are used for diags, which may lead to overclocking.
 791         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 792
 793                 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 794                 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count;
 795                 dcn3_16_soc.num_chans = bw_params->num_channels;
 796
 797                 ASSERT(clk_table->num_entries);
 798
 799                 /* Prepass to find max clocks independent of voltage level. */
 800                 for (i = 0; i < clk_table->num_entries; ++i) {
 801                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
 802                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
 803                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
 804                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
 805                 }
 806
 807                 for (i = 0; i < clk_table->num_entries; i++) {
 808                         /* loop backwards*/
 809                         for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) {
 810                                 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
 811                                         closest_clk_lvl = j;
 812                                         break;
 813                                 }
 814                         }
 815                         // Ported from DCN315
 816                         if (clk_table->num_entries == 1) {
 817                                 /*smu gives one DPM level, let's take the highest one*/
 818                                 closest_clk_lvl = dcn3_16_soc.num_states - 1;
 819                         }
 820
 821                         clock_limits[i].state = i;
 822
 823                         /* Clocks dependent on voltage level. */
 824                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 825                         if (clk_table->num_entries == 1 &&
 826                                 clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
 827                                 /*SMU fix not released yet*/
 828                                 clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
 829                         }
 830                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
 831                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
 832                         clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 833
 834                         /* Clocks independent of voltage level. */
 835                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 836                                 dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 837
 838                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 839                                 dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 840
 841                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
 842                         clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
 843                         clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
 844                         clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
 845                         clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 846                 }
 847                 for (i = 0; i < clk_table->num_entries; i++)
 848                         dcn3_16_soc.clock_limits[i] = clock_limits[i];
 849                 if (clk_table->num_entries) {
 850                         dcn3_16_soc.num_states = clk_table->num_entries;
 851                 }
 852         }
 853
 854         if (max_dispclk_mhz) {
 855                 dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 856                 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 857         }
 858
 859         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 860                 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31);
 861         else
 862                 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA);
 863 }