drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn32/dcn32_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn32/dcn32_resource.h"
  35 #include "dcn321_resource.h"
  36
  37 #include "dcn20/dcn20_resource.h"
  38 #include "dcn30/dcn30_resource.h"
  39
  40 #include "dcn10/dcn10_ipp.h"
  41 #include "dcn30/dcn30_hubbub.h"
  42 #include "dcn31/dcn31_hubbub.h"
  43 #include "dcn32/dcn32_hubbub.h"
  44 #include "dcn32/dcn32_mpc.h"
  45 #include "dcn32/dcn32_hubp.h"
  46 #include "irq/dcn32/irq_service_dcn32.h"
  47 #include "dcn32/dcn32_dpp.h"
  48 #include "dcn32/dcn32_optc.h"
  49 #include "dcn20/dcn20_hwseq.h"
  50 #include "dcn30/dcn30_hwseq.h"
  51 #include "dce110/dce110_hw_sequencer.h"
  52 #include "dcn30/dcn30_opp.h"
  53 #include "dcn20/dcn20_dsc.h"
  54 #include "dcn30/dcn30_vpg.h"
  55 #include "dcn30/dcn30_afmt.h"
  56 #include "dcn30/dcn30_dio_stream_encoder.h"
  57 #include "dcn32/dcn32_dio_stream_encoder.h"
  58 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  59 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  60 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
  61 #include "dc_link_dp.h"
  62 #include "dcn31/dcn31_apg.h"
  63 #include "dcn31/dcn31_dio_link_encoder.h"
  64 #include "dcn32/dcn32_dio_link_encoder.h"
  65 #include "dce/dce_clock_source.h"
  66 #include "dce/dce_audio.h"
  67 #include "dce/dce_hwseq.h"
  68 #include "clk_mgr.h"
  69 #include "virtual/virtual_stream_encoder.h"
  70 #include "dml/display_mode_vba.h"
  71 #include "dcn32/dcn32_dccg.h"
  72 #include "dcn10/dcn10_resource.h"
  73 #include "dc_link_ddc.h"
  74 #include "dcn31/dcn31_panel_cntl.h"
  75
  76 #include "dcn30/dcn30_dwb.h"
  77 #include "dcn32/dcn32_mmhubbub.h"
  78
  79 #include "dcn/dcn_3_2_1_offset.h"
  80 #include "dcn/dcn_3_2_1_sh_mask.h"
  81 #include "nbio/nbio_4_3_0_offset.h"
  82
  83 #include "reg_helper.h"
  84 #include "dce/dmub_abm.h"
  85 #include "dce/dmub_psr.h"
  86 #include "dce/dce_aux.h"
  87 #include "dce/dce_i2c.h"
  88
  89 #include "dml/dcn30/display_mode_vba_30.h"
  90 #include "vm_helper.h"
  91 #include "dcn20/dcn20_vmid.h"
  92
  93 #define DCN_BASE__INST0_SEG1                       0x000000C0
  94 #define DCN_BASE__INST0_SEG2                       0x000034C0
  95 #define DCN_BASE__INST0_SEG3                       0x00009000
  96 #define NBIO_BASE__INST0_SEG1                      0x00000014
  97
  98 #define MAX_INSTANCE                                        8
  99 #define MAX_SEGMENT                                         6
 100
 101
 102 struct IP_BASE_INSTANCE
 103 {
 104     unsigned int segment[MAX_SEGMENT];
 105 };
 106
 107 struct IP_BASE
 108 {
 109     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
 110 };
 111
 112 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
 113                                         { { 0, 0, 0, 0, 0, 0 } },
 114                                         { { 0, 0, 0, 0, 0, 0 } },
 115                                         { { 0, 0, 0, 0, 0, 0 } },
 116                                         { { 0, 0, 0, 0, 0, 0 } },
 117                                         { { 0, 0, 0, 0, 0, 0 } },
 118                                         { { 0, 0, 0, 0, 0, 0 } },
 119                                         { { 0, 0, 0, 0, 0, 0 } } } };
 120
 121 #define DC_LOGGER_INIT(logger)
 122 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
 123 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
 124
 125 #define DCN3_2_DEFAULT_DET_SIZE 256
 126
 127 struct _vcs_dpi_ip_params_st dcn3_21_ip = {
 128         .gpuvm_enable = 1,
 129         .gpuvm_max_page_table_levels = 1,
 130         .hostvm_enable = 0,
 131         .rob_buffer_size_kbytes = 128,
 132         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
 133         .config_return_buffer_size_in_kbytes = 1280,
 134         .compressed_buffer_segment_size_in_kbytes = 64,
 135         .meta_fifo_size_in_kentries = 22,
 136         .zero_size_buffer_entries = 512,
 137         .compbuf_reserved_space_64b = 256,
 138         .compbuf_reserved_space_zs = 64,
 139         .dpp_output_buffer_pixels = 2560,
 140         .opp_output_buffer_lines = 1,
 141         .pixel_chunk_size_kbytes = 8,
 142         .alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team
 143         .min_pixel_chunk_size_bytes = 1024,
 144         .dcc_meta_buffer_size_bytes = 6272,
 145         .meta_chunk_size_kbytes = 2,
 146         .min_meta_chunk_size_bytes = 256,
 147         .writeback_chunk_size_kbytes = 8,
 148         .ptoi_supported = false,
 149         .num_dsc = 4,
 150         .maximum_dsc_bits_per_component = 12,
 151         .maximum_pixels_per_line_per_dsc_unit = 6016,
 152         .dsc422_native_support = true,
 153         .is_line_buffer_bpp_fixed = true,
 154         .line_buffer_fixed_bpp = 57,
 155         .line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp
 156         .max_line_buffer_lines = 32,
 157         .writeback_interface_buffer_size_kbytes = 90,
 158         .max_num_dpp = 4,
 159         .max_num_otg = 4,
 160         .max_num_hdmi_frl_outputs = 1,
 161         .max_num_wb = 1,
 162         .max_dchub_pscl_bw_pix_per_clk = 4,
 163         .max_pscl_lb_bw_pix_per_clk = 2,
 164         .max_lb_vscl_bw_pix_per_clk = 4,
 165         .max_vscl_hscl_bw_pix_per_clk = 4,
 166         .max_hscl_ratio = 6,
 167         .max_vscl_ratio = 6,
 168         .max_hscl_taps = 8,
 169         .max_vscl_taps = 8,
 170         .dpte_buffer_size_in_pte_reqs_luma = 64,
 171         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 172         .dispclk_ramp_margin_percent = 1,
 173         .max_inter_dcn_tile_repeaters = 8,
 174         .cursor_buffer_size = 16,
 175         .cursor_chunk_size = 2,
 176         .writeback_line_buffer_buffer_size = 0,
 177         .writeback_min_hscl_ratio = 1,
 178         .writeback_min_vscl_ratio = 1,
 179         .writeback_max_hscl_ratio = 1,
 180         .writeback_max_vscl_ratio = 1,
 181         .writeback_max_hscl_taps = 1,
 182         .writeback_max_vscl_taps = 1,
 183         .dppclk_delay_subtotal = 47,
 184         .dppclk_delay_scl = 50,
 185         .dppclk_delay_scl_lb_only = 16,
 186         .dppclk_delay_cnvc_formatter = 28,
 187         .dppclk_delay_cnvc_cursor = 6,
 188         .dispclk_delay_subtotal = 125,
 189         .dynamic_metadata_vm_enabled = false,
 190         .odm_combine_4to1_supported = false,
 191         .dcc_supported = true,
 192         .max_num_dp2p0_outputs = 2,
 193         .max_num_dp2p0_streams = 4,
 194 };
 195
 196 struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
 197         .clock_limits = {
 198                 {
 199                         .state = 0,
 200                         .dcfclk_mhz = 1564.0,
 201                         .fabricclk_mhz = 400.0,
 202                         .dispclk_mhz = 2150.0,
 203                         .dppclk_mhz = 2150.0,
 204                         .phyclk_mhz = 810.0,
 205                         .phyclk_d18_mhz = 667.0,
 206                         .phyclk_d32_mhz = 625.0,
 207                         .socclk_mhz = 1200.0,
 208                         .dscclk_mhz = 716.667,
 209                         .dram_speed_mts = 1600.0,
 210                         .dtbclk_mhz = 1564.0,
 211                 },
 212         },
 213         .num_states = 1,
 214         .sr_exit_time_us = 5.20,
 215         .sr_enter_plus_exit_time_us = 9.60,
 216         .sr_exit_z8_time_us = 285.0,
 217         .sr_enter_plus_exit_z8_time_us = 320,
 218         .writeback_latency_us = 12.0,
 219         .round_trip_ping_latency_dcfclk_cycles = 263,
 220         .urgent_latency_pixel_data_only_us = 4.0,
 221         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 222         .urgent_latency_vm_data_only_us = 4.0,
 223         .fclk_change_latency_us = 20,
 224         .usr_retraining_latency_us = 2,
 225         .smn_latency_us = 2,
 226         .mall_allocated_for_dcn_mbytes = 64,
 227         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 228         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 229         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 230         .pct_ideal_sdp_bw_after_urgent = 100.0,
 231         .pct_ideal_fabric_bw_after_urgent = 67.0,
 232         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 233         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 234         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 235         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 236         .max_avg_sdp_bw_use_normal_percent = 80.0,
 237         .max_avg_fabric_bw_use_normal_percent = 60.0,
 238         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 239         .max_avg_dram_bw_use_normal_percent = 15.0,
 240         .num_chans = 8,
 241         .dram_channel_width_bytes = 2,
 242         .fabric_datapath_to_dcn_data_return_bytes = 64,
 243         .return_bus_width_bytes = 64,
 244         .downspread_percent = 0.38,
 245         .dcn_downspread_percent = 0.5,
 246         .dram_clock_change_latency_us = 400,
 247         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 248         .do_urgent_latency_adjustment = true,
 249         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 250         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 251 };
 252
 253 enum dcn321_clk_src_array_id {
 254         DCN321_CLK_SRC_PLL0,
 255         DCN321_CLK_SRC_PLL1,
 256         DCN321_CLK_SRC_PLL2,
 257         DCN321_CLK_SRC_PLL3,
 258         DCN321_CLK_SRC_PLL4,
 259         DCN321_CLK_SRC_TOTAL
 260 };
 261
 262 /* begin *********************
 263  * macros to expend register list macro defined in HW object header file
 264  */
 265
 266 /* DCN */
 267 /* TODO awful hack. fixup dcn20_dwb.h */
 268 #undef BASE_INNER
 269 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 270
 271 #define BASE(seg) BASE_INNER(seg)
 272
 273 #define SR(reg_name)\
 274                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 275                                         reg ## reg_name
 276
 277 #define SRI(reg_name, block, id)\
 278         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 279                                         reg ## block ## id ## _ ## reg_name
 280
 281 #define SRI2(reg_name, block, id)\
 282         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 283                                         reg ## reg_name
 284
 285 #define SRIR(var_name, reg_name, block, id)\
 286         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 287                                         reg ## block ## id ## _ ## reg_name
 288
 289 #define SRII(reg_name, block, id)\
 290         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 291                                         reg ## block ## id ## _ ## reg_name
 292
 293 #define SRII_MPC_RMU(reg_name, block, id)\
 294         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 295                                         reg ## block ## id ## _ ## reg_name
 296
 297 #define SRII_DWB(reg_name, temp_name, block, id)\
 298         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 299                                         reg ## block ## id ## _ ## temp_name
 300
 301 #define DCCG_SRII(reg_name, block, id)\
 302         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 303                                         reg ## block ## id ## _ ## reg_name
 304
 305 #define VUPDATE_SRII(reg_name, block, id)\
 306         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 307                                         reg ## reg_name ## _ ## block ## id
 308
 309 /* NBIO */
 310 #define NBIO_BASE_INNER(seg) \
 311         NBIO_BASE__INST0_SEG ## seg
 312
 313 #define NBIO_BASE(seg) \
 314         NBIO_BASE_INNER(seg)
 315
 316 #define NBIO_SR(reg_name)\
 317                 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 318                                         regBIF_BX0_ ## reg_name
 319
 320 #define CTX ctx
 321 #define REG(reg_name) \
 322         (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 323
 324 static const struct bios_registers bios_regs = {
 325                 NBIO_SR(BIOS_SCRATCH_3),
 326                 NBIO_SR(BIOS_SCRATCH_6)
 327 };
 328
 329 #define clk_src_regs(index, pllid)\
 330 [index] = {\
 331         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 332 }
 333
 334 static const struct dce110_clk_src_regs clk_src_regs[] = {
 335         clk_src_regs(0, A),
 336         clk_src_regs(1, B),
 337         clk_src_regs(2, C),
 338         clk_src_regs(3, D)
 339 };
 340
 341 static const struct dce110_clk_src_shift cs_shift = {
 342                 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 343 };
 344
 345 static const struct dce110_clk_src_mask cs_mask = {
 346                 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 347 };
 348
 349 #define abm_regs(id)\
 350 [id] = {\
 351                 ABM_DCN32_REG_LIST(id)\
 352 }
 353
 354 static const struct dce_abm_registers abm_regs[] = {
 355                 abm_regs(0),
 356                 abm_regs(1),
 357                 abm_regs(2),
 358                 abm_regs(3),
 359 };
 360
 361 static const struct dce_abm_shift abm_shift = {
 362                 ABM_MASK_SH_LIST_DCN32(__SHIFT)
 363 };
 364
 365 static const struct dce_abm_mask abm_mask = {
 366                 ABM_MASK_SH_LIST_DCN32(_MASK)
 367 };
 368
 369 #define audio_regs(id)\
 370 [id] = {\
 371                 AUD_COMMON_REG_LIST(id)\
 372 }
 373
 374 static const struct dce_audio_registers audio_regs[] = {
 375         audio_regs(0),
 376         audio_regs(1),
 377         audio_regs(2),
 378         audio_regs(3),
 379         audio_regs(4)
 380 };
 381
 382 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 383                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 384                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 385                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 386
 387 static const struct dce_audio_shift audio_shift = {
 388                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 389 };
 390
 391 static const struct dce_audio_mask audio_mask = {
 392                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 393 };
 394
 395 #define vpg_regs(id)\
 396 [id] = {\
 397         VPG_DCN3_REG_LIST(id)\
 398 }
 399
 400 static const struct dcn30_vpg_registers vpg_regs[] = {
 401         vpg_regs(0),
 402         vpg_regs(1),
 403         vpg_regs(2),
 404         vpg_regs(3),
 405         vpg_regs(4),
 406         vpg_regs(5),
 407         vpg_regs(6),
 408         vpg_regs(7),
 409         vpg_regs(8),
 410         vpg_regs(9),
 411 };
 412
 413 static const struct dcn30_vpg_shift vpg_shift = {
 414         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 415 };
 416
 417 static const struct dcn30_vpg_mask vpg_mask = {
 418         DCN3_VPG_MASK_SH_LIST(_MASK)
 419 };
 420
 421 #define afmt_regs(id)\
 422 [id] = {\
 423         AFMT_DCN3_REG_LIST(id)\
 424 }
 425
 426 static const struct dcn30_afmt_registers afmt_regs[] = {
 427         afmt_regs(0),
 428         afmt_regs(1),
 429         afmt_regs(2),
 430         afmt_regs(3),
 431         afmt_regs(4),
 432         afmt_regs(5)
 433 };
 434
 435 static const struct dcn30_afmt_shift afmt_shift = {
 436         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 437 };
 438
 439 static const struct dcn30_afmt_mask afmt_mask = {
 440         DCN3_AFMT_MASK_SH_LIST(_MASK)
 441 };
 442
 443 #define apg_regs(id)\
 444 [id] = {\
 445         APG_DCN31_REG_LIST(id)\
 446 }
 447
 448 static const struct dcn31_apg_registers apg_regs[] = {
 449         apg_regs(0),
 450         apg_regs(1),
 451         apg_regs(2),
 452         apg_regs(3)
 453 };
 454
 455 static const struct dcn31_apg_shift apg_shift = {
 456         DCN31_APG_MASK_SH_LIST(__SHIFT)
 457 };
 458
 459 static const struct dcn31_apg_mask apg_mask = {
 460                 DCN31_APG_MASK_SH_LIST(_MASK)
 461 };
 462
 463 #define stream_enc_regs(id)\
 464 [id] = {\
 465         SE_DCN32_REG_LIST(id)\
 466 }
 467
 468 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 469         stream_enc_regs(0),
 470         stream_enc_regs(1),
 471         stream_enc_regs(2),
 472         stream_enc_regs(3),
 473         stream_enc_regs(4)
 474 };
 475
 476 static const struct dcn10_stream_encoder_shift se_shift = {
 477                 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 478 };
 479
 480 static const struct dcn10_stream_encoder_mask se_mask = {
 481                 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
 482 };
 483
 484
 485 #define aux_regs(id)\
 486 [id] = {\
 487         DCN2_AUX_REG_LIST(id)\
 488 }
 489
 490 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 491                 aux_regs(0),
 492                 aux_regs(1),
 493                 aux_regs(2),
 494                 aux_regs(3),
 495                 aux_regs(4)
 496 };
 497
 498 #define hpd_regs(id)\
 499 [id] = {\
 500         HPD_REG_LIST(id)\
 501 }
 502
 503 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 504                 hpd_regs(0),
 505                 hpd_regs(1),
 506                 hpd_regs(2),
 507                 hpd_regs(3),
 508                 hpd_regs(4)
 509 };
 510
 511 #define link_regs(id, phyid)\
 512 [id] = {\
 513         LE_DCN31_REG_LIST(id), \
 514         UNIPHY_DCN2_REG_LIST(phyid), \
 515         /*DPCS_DCN31_REG_LIST(id),*/ \
 516 }
 517
 518 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 519         link_regs(0, A),
 520         link_regs(1, B),
 521         link_regs(2, C),
 522         link_regs(3, D),
 523         link_regs(4, E)
 524 };
 525
 526 static const struct dcn10_link_enc_shift le_shift = {
 527         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 528 //      DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 529 };
 530
 531 static const struct dcn10_link_enc_mask le_mask = {
 532         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 533 //      DPCS_DCN31_MASK_SH_LIST(_MASK)
 534 };
 535
 536 #define hpo_dp_stream_encoder_reg_list(id)\
 537 [id] = {\
 538         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 539 }
 540
 541 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 542         hpo_dp_stream_encoder_reg_list(0),
 543         hpo_dp_stream_encoder_reg_list(1),
 544         hpo_dp_stream_encoder_reg_list(2),
 545         hpo_dp_stream_encoder_reg_list(3),
 546 };
 547
 548 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 549         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 550 };
 551
 552 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 553         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 554 };
 555
 556
 557 #define hpo_dp_link_encoder_reg_list(id)\
 558 [id] = {\
 559         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 560         /*DCN3_1_RDPCSTX_REG_LIST(0),*/\
 561         /*DCN3_1_RDPCSTX_REG_LIST(1),*/\
 562         /*DCN3_1_RDPCSTX_REG_LIST(2),*/\
 563         /*DCN3_1_RDPCSTX_REG_LIST(3),*/\
 564         /*DCN3_1_RDPCSTX_REG_LIST(4)*/\
 565 }
 566
 567 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 568         hpo_dp_link_encoder_reg_list(0),
 569         hpo_dp_link_encoder_reg_list(1),
 570 };
 571
 572 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 573         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 574 };
 575
 576 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 577         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 578 };
 579
 580 #define dpp_regs(id)\
 581 [id] = {\
 582         DPP_REG_LIST_DCN30_COMMON(id),\
 583 }
 584
 585 static const struct dcn3_dpp_registers dpp_regs[] = {
 586         dpp_regs(0),
 587         dpp_regs(1),
 588         dpp_regs(2),
 589         dpp_regs(3)
 590 };
 591
 592 static const struct dcn3_dpp_shift tf_shift = {
 593                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
 594 };
 595
 596 static const struct dcn3_dpp_mask tf_mask = {
 597                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
 598 };
 599
 600
 601 #define opp_regs(id)\
 602 [id] = {\
 603         OPP_REG_LIST_DCN30(id),\
 604 }
 605
 606 static const struct dcn20_opp_registers opp_regs[] = {
 607         opp_regs(0),
 608         opp_regs(1),
 609         opp_regs(2),
 610         opp_regs(3)
 611 };
 612
 613 static const struct dcn20_opp_shift opp_shift = {
 614         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 615 };
 616
 617 static const struct dcn20_opp_mask opp_mask = {
 618         OPP_MASK_SH_LIST_DCN20(_MASK)
 619 };
 620
 621 #define aux_engine_regs(id)\
 622 [id] = {\
 623         AUX_COMMON_REG_LIST0(id), \
 624         .AUXN_IMPCAL = 0, \
 625         .AUXP_IMPCAL = 0, \
 626         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 627 }
 628
 629 static const struct dce110_aux_registers aux_engine_regs[] = {
 630                 aux_engine_regs(0),
 631                 aux_engine_regs(1),
 632                 aux_engine_regs(2),
 633                 aux_engine_regs(3),
 634                 aux_engine_regs(4)
 635 };
 636
 637 static const struct dce110_aux_registers_shift aux_shift = {
 638         DCN_AUX_MASK_SH_LIST(__SHIFT)
 639 };
 640
 641 static const struct dce110_aux_registers_mask aux_mask = {
 642         DCN_AUX_MASK_SH_LIST(_MASK)
 643 };
 644
 645
 646 #define dwbc_regs_dcn3(id)\
 647 [id] = {\
 648         DWBC_COMMON_REG_LIST_DCN30(id),\
 649 }
 650
 651 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 652         dwbc_regs_dcn3(0),
 653 };
 654
 655 static const struct dcn30_dwbc_shift dwbc30_shift = {
 656         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 657 };
 658
 659 static const struct dcn30_dwbc_mask dwbc30_mask = {
 660         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 661 };
 662
 663 #define mcif_wb_regs_dcn3(id)\
 664 [id] = {\
 665         MCIF_WB_COMMON_REG_LIST_DCN32(id),\
 666 }
 667
 668 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 669         mcif_wb_regs_dcn3(0)
 670 };
 671
 672 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 673         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 674 };
 675
 676 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 677         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
 678 };
 679
 680 #define dsc_regsDCN20(id)\
 681 [id] = {\
 682         DSC_REG_LIST_DCN20(id)\
 683 }
 684
 685 static const struct dcn20_dsc_registers dsc_regs[] = {
 686         dsc_regsDCN20(0),
 687         dsc_regsDCN20(1),
 688         dsc_regsDCN20(2),
 689         dsc_regsDCN20(3)
 690 };
 691
 692 static const struct dcn20_dsc_shift dsc_shift = {
 693         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 694 };
 695
 696 static const struct dcn20_dsc_mask dsc_mask = {
 697         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 698 };
 699
 700 static const struct dcn30_mpc_registers mpc_regs = {
 701                 MPC_REG_LIST_DCN3_0(0),
 702                 MPC_REG_LIST_DCN3_0(1),
 703                 MPC_REG_LIST_DCN3_0(2),
 704                 MPC_REG_LIST_DCN3_0(3),
 705                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 706                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 707                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 708                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 709                 MPC_MCM_REG_LIST_DCN32(0),
 710                 MPC_MCM_REG_LIST_DCN32(1),
 711                 MPC_MCM_REG_LIST_DCN32(2),
 712                 MPC_MCM_REG_LIST_DCN32(3),
 713                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 714 };
 715
 716 static const struct dcn30_mpc_shift mpc_shift = {
 717         MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 718 };
 719
 720 static const struct dcn30_mpc_mask mpc_mask = {
 721         MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 722 };
 723
 724 #define optc_regs(id)\
 725 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
 726
 727 static const struct dcn_optc_registers optc_regs[] = {
 728         optc_regs(0),
 729         optc_regs(1),
 730         optc_regs(2),
 731         optc_regs(3)
 732 };
 733
 734 static const struct dcn_optc_shift optc_shift = {
 735         OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 736 };
 737
 738 static const struct dcn_optc_mask optc_mask = {
 739         OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 740 };
 741
 742 #define hubp_regs(id)\
 743 [id] = {\
 744         HUBP_REG_LIST_DCN32(id)\
 745 }
 746
 747 static const struct dcn_hubp2_registers hubp_regs[] = {
 748                 hubp_regs(0),
 749                 hubp_regs(1),
 750                 hubp_regs(2),
 751                 hubp_regs(3)
 752 };
 753
 754
 755 static const struct dcn_hubp2_shift hubp_shift = {
 756                 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
 757 };
 758
 759 static const struct dcn_hubp2_mask hubp_mask = {
 760                 HUBP_MASK_SH_LIST_DCN32(_MASK)
 761 };
 762 static const struct dcn_hubbub_registers hubbub_reg = {
 763                 HUBBUB_REG_LIST_DCN32(0)
 764 };
 765
 766 static const struct dcn_hubbub_shift hubbub_shift = {
 767                 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
 768 };
 769
 770 static const struct dcn_hubbub_mask hubbub_mask = {
 771                 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
 772 };
 773
 774 static const struct dccg_registers dccg_regs = {
 775                 DCCG_REG_LIST_DCN32()
 776 };
 777
 778 static const struct dccg_shift dccg_shift = {
 779                 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
 780 };
 781
 782 static const struct dccg_mask dccg_mask = {
 783                 DCCG_MASK_SH_LIST_DCN32(_MASK)
 784 };
 785
 786
 787 #define SRII2(reg_name_pre, reg_name_post, id)\
 788         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 789                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 790                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 791
 792
 793 #define HWSEQ_DCN32_REG_LIST()\
 794         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 795         SR(DIO_MEM_PWR_CTRL), \
 796         SR(ODM_MEM_PWR_CTRL3), \
 797         SR(MMHUBBUB_MEM_PWR_CNTL), \
 798         SR(DCCG_GATE_DISABLE_CNTL), \
 799         SR(DCCG_GATE_DISABLE_CNTL2), \
 800         SR(DCFCLK_CNTL),\
 801         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 802         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 803         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 804         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 805         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 806         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 807         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 808         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 809         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 810         SR(MICROSECOND_TIME_BASE_DIV), \
 811         SR(MILLISECOND_TIME_BASE_DIV), \
 812         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 813         SR(RBBMIF_TIMEOUT_DIS), \
 814         SR(RBBMIF_TIMEOUT_DIS_2), \
 815         SR(DCHUBBUB_CRC_CTRL), \
 816         SR(DPP_TOP0_DPP_CRC_CTRL), \
 817         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 818         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 819         SR(MPC_CRC_CTRL), \
 820         SR(MPC_CRC_RESULT_GB), \
 821         SR(MPC_CRC_RESULT_C), \
 822         SR(MPC_CRC_RESULT_AR), \
 823         SR(DOMAIN0_PG_CONFIG), \
 824         SR(DOMAIN1_PG_CONFIG), \
 825         SR(DOMAIN2_PG_CONFIG), \
 826         SR(DOMAIN3_PG_CONFIG), \
 827         SR(DOMAIN16_PG_CONFIG), \
 828         SR(DOMAIN17_PG_CONFIG), \
 829         SR(DOMAIN18_PG_CONFIG), \
 830         SR(DOMAIN19_PG_CONFIG), \
 831         SR(DOMAIN0_PG_STATUS), \
 832         SR(DOMAIN1_PG_STATUS), \
 833         SR(DOMAIN2_PG_STATUS), \
 834         SR(DOMAIN3_PG_STATUS), \
 835         SR(DOMAIN16_PG_STATUS), \
 836         SR(DOMAIN17_PG_STATUS), \
 837         SR(DOMAIN18_PG_STATUS), \
 838         SR(DOMAIN19_PG_STATUS), \
 839         SR(D1VGA_CONTROL), \
 840         SR(D2VGA_CONTROL), \
 841         SR(D3VGA_CONTROL), \
 842         SR(D4VGA_CONTROL), \
 843         SR(D5VGA_CONTROL), \
 844         SR(D6VGA_CONTROL), \
 845         SR(DC_IP_REQUEST_CNTL), \
 846         SR(AZALIA_AUDIO_DTO), \
 847         SR(AZALIA_CONTROLLER_CLOCK_GATING)
 848
 849 static const struct dce_hwseq_registers hwseq_reg = {
 850                 HWSEQ_DCN32_REG_LIST()
 851 };
 852
 853 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
 854         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 855         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 856         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 857         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 858         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 859         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 860         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 861         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 862         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 863         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 864         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 865         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 866         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 867         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 868         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 869         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 870         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 871         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 872         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 873         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 874         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 875         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 876         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 877         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 878         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 879         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 880         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 881         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 882         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 883         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 884         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 885         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 886
 887 static const struct dce_hwseq_shift hwseq_shift = {
 888                 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
 889 };
 890
 891 static const struct dce_hwseq_mask hwseq_mask = {
 892                 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
 893 };
 894 #define vmid_regs(id)\
 895 [id] = {\
 896                 DCN20_VMID_REG_LIST(id)\
 897 }
 898
 899 static const struct dcn_vmid_registers vmid_regs[] = {
 900         vmid_regs(0),
 901         vmid_regs(1),
 902         vmid_regs(2),
 903         vmid_regs(3),
 904         vmid_regs(4),
 905         vmid_regs(5),
 906         vmid_regs(6),
 907         vmid_regs(7),
 908         vmid_regs(8),
 909         vmid_regs(9),
 910         vmid_regs(10),
 911         vmid_regs(11),
 912         vmid_regs(12),
 913         vmid_regs(13),
 914         vmid_regs(14),
 915         vmid_regs(15)
 916 };
 917
 918 static const struct dcn20_vmid_shift vmid_shifts = {
 919                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 920 };
 921
 922 static const struct dcn20_vmid_mask vmid_masks = {
 923                 DCN20_VMID_MASK_SH_LIST(_MASK)
 924 };
 925
 926 static const struct resource_caps res_cap_dcn321 = {
 927         .num_timing_generator = 4,
 928         .num_opp = 4,
 929         .num_video_plane = 4,
 930         .num_audio = 5,
 931         .num_stream_encoder = 5,
 932         .num_hpo_dp_stream_encoder = 4,
 933         .num_hpo_dp_link_encoder = 2,
 934         .num_pll = 5,
 935         .num_dwb = 1,
 936         .num_ddc = 5,
 937         .num_vmid = 16,
 938         .num_mpc_3dlut = 4,
 939         .num_dsc = 4,
 940 };
 941
 942 static const struct dc_plane_cap plane_cap = {
 943         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 944         .blends_with_above = true,
 945         .blends_with_below = true,
 946         .per_pixel_alpha = true,
 947
 948         .pixel_format_support = {
 949                         .argb8888 = true,
 950                         .nv12 = true,
 951                         .fp16 = true,
 952                         .p010 = true,
 953                         .ayuv = false,
 954         },
 955
 956         .max_upscale_factor = {
 957                         .argb8888 = 16000,
 958                         .nv12 = 16000,
 959                         .fp16 = 16000
 960         },
 961
 962         // 6:1 downscaling ratio: 1000/6 = 166.666
 963         .max_downscale_factor = {
 964                         .argb8888 = 167,
 965                         .nv12 = 167,
 966                         .fp16 = 167
 967         },
 968         64,
 969         64
 970 };
 971
 972 static const struct dc_debug_options debug_defaults_drv = {
 973         .disable_dmcu = true,
 974         .force_abm_enable = false,
 975         .timing_trace = false,
 976         .clock_trace = true,
 977         .disable_pplib_clock_request = false,
 978         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 979         .force_single_disp_pipe_split = false,
 980         .disable_dcc = DCC_ENABLE,
 981         .vsr_support = true,
 982         .performance_trace = false,
 983         .max_downscale_src_width = 7680,/*upto 8K*/
 984         .disable_pplib_wm_range = false,
 985         .scl_reset_length10 = true,
 986         .sanity_checks = false,
 987         .underflow_assert_delay_us = 0xFFFFFFFF,
 988         .dwb_fi_phase = -1, // -1 = disable,
 989         .dmub_command_table = true,
 990         .enable_mem_low_power = {
 991                 .bits = {
 992                         .vga = false,
 993                         .i2c = false,
 994                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 995                         .dscl = false,
 996                         .cm = false,
 997                         .mpc = false,
 998                         .optc = false,
 999                 }
1000         },
1001         .use_max_lb = true,
1002         .force_disable_subvp = true
1003 };
1004
1005 static const struct dc_debug_options debug_defaults_diags = {
1006         .disable_dmcu = true,
1007         .force_abm_enable = false,
1008         .timing_trace = true,
1009         .clock_trace = true,
1010         .disable_dpp_power_gate = true,
1011         .disable_hubp_power_gate = true,
1012         .disable_dsc_power_gate = true,
1013         .disable_clock_gate = true,
1014         .disable_pplib_clock_request = true,
1015         .disable_pplib_wm_range = true,
1016         .disable_stutter = false,
1017         .scl_reset_length10 = true,
1018         .dwb_fi_phase = -1, // -1 = disable
1019         .dmub_command_table = true,
1020         .enable_tri_buf = true,
1021         .use_max_lb = true,
1022         .force_disable_subvp = true
1023 };
1024
1025
1026 static struct dce_aux *dcn321_aux_engine_create(
1027         struct dc_context *ctx,
1028         uint32_t inst)
1029 {
1030         struct aux_engine_dce110 *aux_engine =
1031                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1032
1033         if (!aux_engine)
1034                 return NULL;
1035
1036         dce110_aux_engine_construct(aux_engine, ctx, inst,
1037                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1038                                     &aux_engine_regs[inst],
1039                                         &aux_mask,
1040                                         &aux_shift,
1041                                         ctx->dc->caps.extended_aux_timeout_support);
1042
1043         return &aux_engine->base;
1044 }
1045 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1046
1047 static const struct dce_i2c_registers i2c_hw_regs[] = {
1048                 i2c_inst_regs(1),
1049                 i2c_inst_regs(2),
1050                 i2c_inst_regs(3),
1051                 i2c_inst_regs(4),
1052                 i2c_inst_regs(5),
1053 };
1054
1055 static const struct dce_i2c_shift i2c_shifts = {
1056                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1057 };
1058
1059 static const struct dce_i2c_mask i2c_masks = {
1060                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1061 };
1062
1063 static struct dce_i2c_hw *dcn321_i2c_hw_create(
1064         struct dc_context *ctx,
1065         uint32_t inst)
1066 {
1067         struct dce_i2c_hw *dce_i2c_hw =
1068                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1069
1070         if (!dce_i2c_hw)
1071                 return NULL;
1072
1073         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1074                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1075
1076         return dce_i2c_hw;
1077 }
1078
1079 static struct clock_source *dcn321_clock_source_create(
1080                 struct dc_context *ctx,
1081                 struct dc_bios *bios,
1082                 enum clock_source_id id,
1083                 const struct dce110_clk_src_regs *regs,
1084                 bool dp_clk_src)
1085 {
1086         struct dce110_clk_src *clk_src =
1087                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1088
1089         if (!clk_src)
1090                 return NULL;
1091
1092         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1093                         regs, &cs_shift, &cs_mask)) {
1094                 clk_src->base.dp_clk_src = dp_clk_src;
1095                 return &clk_src->base;
1096         }
1097
1098         BREAK_TO_DEBUGGER();
1099         return NULL;
1100 }
1101
1102 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
1103 {
1104         int i;
1105
1106         struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
1107                                           GFP_KERNEL);
1108
1109         if (!hubbub2)
1110                 return NULL;
1111
1112         hubbub32_construct(hubbub2, ctx,
1113                         &hubbub_reg,
1114                         &hubbub_shift,
1115                         &hubbub_mask,
1116                         ctx->dc->dml.ip.det_buffer_size_kbytes,
1117                         ctx->dc->dml.ip.pixel_chunk_size_kbytes,
1118                         ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
1119
1120
1121         for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
1122                 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
1123
1124                 vmid->ctx = ctx;
1125
1126                 vmid->regs = &vmid_regs[i];
1127                 vmid->shifts = &vmid_shifts;
1128                 vmid->masks = &vmid_masks;
1129         }
1130
1131         return &hubbub2->base;
1132 }
1133
1134 static struct hubp *dcn321_hubp_create(
1135         struct dc_context *ctx,
1136         uint32_t inst)
1137 {
1138         struct dcn20_hubp *hubp2 =
1139                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1140
1141         if (!hubp2)
1142                 return NULL;
1143
1144         if (hubp32_construct(hubp2, ctx, inst,
1145                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1146                 return &hubp2->base;
1147
1148         BREAK_TO_DEBUGGER();
1149         kfree(hubp2);
1150         return NULL;
1151 }
1152
1153 static void dcn321_dpp_destroy(struct dpp **dpp)
1154 {
1155         kfree(TO_DCN30_DPP(*dpp));
1156         *dpp = NULL;
1157 }
1158
1159 static struct dpp *dcn321_dpp_create(
1160         struct dc_context *ctx,
1161         uint32_t inst)
1162 {
1163         struct dcn3_dpp *dpp3 =
1164                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1165
1166         if (!dpp3)
1167                 return NULL;
1168
1169         if (dpp32_construct(dpp3, ctx, inst,
1170                         &dpp_regs[inst], &tf_shift, &tf_mask))
1171                 return &dpp3->base;
1172
1173         BREAK_TO_DEBUGGER();
1174         kfree(dpp3);
1175         return NULL;
1176 }
1177
1178 static struct mpc *dcn321_mpc_create(
1179                 struct dc_context *ctx,
1180                 int num_mpcc,
1181                 int num_rmu)
1182 {
1183         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1184                                           GFP_KERNEL);
1185
1186         if (!mpc30)
1187                 return NULL;
1188
1189         dcn32_mpc_construct(mpc30, ctx,
1190                         &mpc_regs,
1191                         &mpc_shift,
1192                         &mpc_mask,
1193                         num_mpcc,
1194                         num_rmu);
1195
1196         return &mpc30->base;
1197 }
1198
1199 static struct output_pixel_processor *dcn321_opp_create(
1200         struct dc_context *ctx, uint32_t inst)
1201 {
1202         struct dcn20_opp *opp2 =
1203                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1204
1205         if (!opp2) {
1206                 BREAK_TO_DEBUGGER();
1207                 return NULL;
1208         }
1209
1210         dcn20_opp_construct(opp2, ctx, inst,
1211                         &opp_regs[inst], &opp_shift, &opp_mask);
1212         return &opp2->base;
1213 }
1214
1215
1216 static struct timing_generator *dcn321_timing_generator_create(
1217                 struct dc_context *ctx,
1218                 uint32_t instance)
1219 {
1220         struct optc *tgn10 =
1221                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1222
1223         if (!tgn10)
1224                 return NULL;
1225
1226         tgn10->base.inst = instance;
1227         tgn10->base.ctx = ctx;
1228
1229         tgn10->tg_regs = &optc_regs[instance];
1230         tgn10->tg_shift = &optc_shift;
1231         tgn10->tg_mask = &optc_mask;
1232
1233         dcn32_timing_generator_init(tgn10);
1234
1235         return &tgn10->base;
1236 }
1237
1238 static const struct encoder_feature_support link_enc_feature = {
1239                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1240                 .max_hdmi_pixel_clock = 600000,
1241                 .hdmi_ycbcr420_supported = true,
1242                 .dp_ycbcr420_supported = true,
1243                 .fec_supported = true,
1244                 .flags.bits.IS_HBR2_CAPABLE = true,
1245                 .flags.bits.IS_HBR3_CAPABLE = true,
1246                 .flags.bits.IS_TPS3_CAPABLE = true,
1247                 .flags.bits.IS_TPS4_CAPABLE = true
1248 };
1249
1250 static struct link_encoder *dcn321_link_encoder_create(
1251         const struct encoder_init_data *enc_init_data)
1252 {
1253         struct dcn20_link_encoder *enc20 =
1254                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1255
1256         if (!enc20)
1257                 return NULL;
1258
1259         dcn32_link_encoder_construct(enc20,
1260                         enc_init_data,
1261                         &link_enc_feature,
1262                         &link_enc_regs[enc_init_data->transmitter],
1263                         &link_enc_aux_regs[enc_init_data->channel - 1],
1264                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1265                         &le_shift,
1266                         &le_mask);
1267
1268         return &enc20->enc10.base;
1269 }
1270
1271 static void read_dce_straps(
1272         struct dc_context *ctx,
1273         struct resource_straps *straps)
1274 {
1275         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1276                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1277
1278 }
1279
1280 static struct audio *dcn321_create_audio(
1281                 struct dc_context *ctx, unsigned int inst)
1282 {
1283         return dce_audio_create(ctx, inst,
1284                         &audio_regs[inst], &audio_shift, &audio_mask);
1285 }
1286
1287 static struct vpg *dcn321_vpg_create(
1288         struct dc_context *ctx,
1289         uint32_t inst)
1290 {
1291         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1292
1293         if (!vpg3)
1294                 return NULL;
1295
1296         vpg3_construct(vpg3, ctx, inst,
1297                         &vpg_regs[inst],
1298                         &vpg_shift,
1299                         &vpg_mask);
1300
1301         return &vpg3->base;
1302 }
1303
1304 static struct afmt *dcn321_afmt_create(
1305         struct dc_context *ctx,
1306         uint32_t inst)
1307 {
1308         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1309
1310         if (!afmt3)
1311                 return NULL;
1312
1313         afmt3_construct(afmt3, ctx, inst,
1314                         &afmt_regs[inst],
1315                         &afmt_shift,
1316                         &afmt_mask);
1317
1318         return &afmt3->base;
1319 }
1320
1321 static struct apg *dcn321_apg_create(
1322         struct dc_context *ctx,
1323         uint32_t inst)
1324 {
1325         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1326
1327         if (!apg31)
1328                 return NULL;
1329
1330         apg31_construct(apg31, ctx, inst,
1331                         &apg_regs[inst],
1332                         &apg_shift,
1333                         &apg_mask);
1334
1335         return &apg31->base;
1336 }
1337
1338 static struct stream_encoder *dcn321_stream_encoder_create(
1339         enum engine_id eng_id,
1340         struct dc_context *ctx)
1341 {
1342         struct dcn10_stream_encoder *enc1;
1343         struct vpg *vpg;
1344         struct afmt *afmt;
1345         int vpg_inst;
1346         int afmt_inst;
1347
1348         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1349         if (eng_id <= ENGINE_ID_DIGF) {
1350                 vpg_inst = eng_id;
1351                 afmt_inst = eng_id;
1352         } else
1353                 return NULL;
1354
1355         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1356         vpg = dcn321_vpg_create(ctx, vpg_inst);
1357         afmt = dcn321_afmt_create(ctx, afmt_inst);
1358
1359         if (!enc1 || !vpg || !afmt) {
1360                 kfree(enc1);
1361                 kfree(vpg);
1362                 kfree(afmt);
1363                 return NULL;
1364         }
1365
1366         dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1367                                         eng_id, vpg, afmt,
1368                                         &stream_enc_regs[eng_id],
1369                                         &se_shift, &se_mask);
1370
1371         return &enc1->base;
1372 }
1373
1374 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
1375         enum engine_id eng_id,
1376         struct dc_context *ctx)
1377 {
1378         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1379         struct vpg *vpg;
1380         struct apg *apg;
1381         uint32_t hpo_dp_inst;
1382         uint32_t vpg_inst;
1383         uint32_t apg_inst;
1384
1385         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1386         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1387
1388         /* Mapping of VPG register blocks to HPO DP block instance:
1389          * VPG[6] -> HPO_DP[0]
1390          * VPG[7] -> HPO_DP[1]
1391          * VPG[8] -> HPO_DP[2]
1392          * VPG[9] -> HPO_DP[3]
1393          */
1394         vpg_inst = hpo_dp_inst + 6;
1395
1396         /* Mapping of APG register blocks to HPO DP block instance:
1397          * APG[0] -> HPO_DP[0]
1398          * APG[1] -> HPO_DP[1]
1399          * APG[2] -> HPO_DP[2]
1400          * APG[3] -> HPO_DP[3]
1401          */
1402         apg_inst = hpo_dp_inst;
1403
1404         /* allocate HPO stream encoder and create VPG sub-block */
1405         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1406         vpg = dcn321_vpg_create(ctx, vpg_inst);
1407         apg = dcn321_apg_create(ctx, apg_inst);
1408
1409         if (!hpo_dp_enc31 || !vpg || !apg) {
1410                 kfree(hpo_dp_enc31);
1411                 kfree(vpg);
1412                 kfree(apg);
1413                 return NULL;
1414         }
1415
1416         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1417                                         hpo_dp_inst, eng_id, vpg, apg,
1418                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1419                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1420
1421         return &hpo_dp_enc31->base;
1422 }
1423
1424 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
1425         uint8_t inst,
1426         struct dc_context *ctx)
1427 {
1428         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1429
1430         /* allocate HPO link encoder */
1431         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1432
1433         hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1434                                         &hpo_dp_link_enc_regs[inst],
1435                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1436
1437         return &hpo_dp_enc31->base;
1438 }
1439
1440 static struct dce_hwseq *dcn321_hwseq_create(
1441         struct dc_context *ctx)
1442 {
1443         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1444
1445         if (hws) {
1446                 hws->ctx = ctx;
1447                 hws->regs = &hwseq_reg;
1448                 hws->shifts = &hwseq_shift;
1449                 hws->masks = &hwseq_mask;
1450         }
1451         return hws;
1452 }
1453 static const struct resource_create_funcs res_create_funcs = {
1454         .read_dce_straps = read_dce_straps,
1455         .create_audio = dcn321_create_audio,
1456         .create_stream_encoder = dcn321_stream_encoder_create,
1457         .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1458         .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1459         .create_hwseq = dcn321_hwseq_create,
1460 };
1461
1462 static const struct resource_create_funcs res_create_maximus_funcs = {
1463         .read_dce_straps = NULL,
1464         .create_audio = NULL,
1465         .create_stream_encoder = NULL,
1466         .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1467         .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1468         .create_hwseq = dcn321_hwseq_create,
1469 };
1470
1471 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
1472 {
1473         unsigned int i;
1474
1475         for (i = 0; i < pool->base.stream_enc_count; i++) {
1476                 if (pool->base.stream_enc[i] != NULL) {
1477                         if (pool->base.stream_enc[i]->vpg != NULL) {
1478                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1479                                 pool->base.stream_enc[i]->vpg = NULL;
1480                         }
1481                         if (pool->base.stream_enc[i]->afmt != NULL) {
1482                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1483                                 pool->base.stream_enc[i]->afmt = NULL;
1484                         }
1485                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1486                         pool->base.stream_enc[i] = NULL;
1487                 }
1488         }
1489
1490         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1491                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1492                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1493                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1494                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1495                         }
1496                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1497                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1498                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1499                         }
1500                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1501                         pool->base.hpo_dp_stream_enc[i] = NULL;
1502                 }
1503         }
1504
1505         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1506                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1507                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1508                         pool->base.hpo_dp_link_enc[i] = NULL;
1509                 }
1510         }
1511
1512         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1513                 if (pool->base.dscs[i] != NULL)
1514                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1515         }
1516
1517         if (pool->base.mpc != NULL) {
1518                 kfree(TO_DCN20_MPC(pool->base.mpc));
1519                 pool->base.mpc = NULL;
1520         }
1521         if (pool->base.hubbub != NULL) {
1522                 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1523                 pool->base.hubbub = NULL;
1524         }
1525         for (i = 0; i < pool->base.pipe_count; i++) {
1526                 if (pool->base.dpps[i] != NULL)
1527                         dcn321_dpp_destroy(&pool->base.dpps[i]);
1528
1529                 if (pool->base.ipps[i] != NULL)
1530                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1531
1532                 if (pool->base.hubps[i] != NULL) {
1533                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1534                         pool->base.hubps[i] = NULL;
1535                 }
1536
1537                 if (pool->base.irqs != NULL) {
1538                         dal_irq_service_destroy(&pool->base.irqs);
1539                 }
1540         }
1541
1542         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1543                 if (pool->base.engines[i] != NULL)
1544                         dce110_engine_destroy(&pool->base.engines[i]);
1545                 if (pool->base.hw_i2cs[i] != NULL) {
1546                         kfree(pool->base.hw_i2cs[i]);
1547                         pool->base.hw_i2cs[i] = NULL;
1548                 }
1549                 if (pool->base.sw_i2cs[i] != NULL) {
1550                         kfree(pool->base.sw_i2cs[i]);
1551                         pool->base.sw_i2cs[i] = NULL;
1552                 }
1553         }
1554
1555         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1556                 if (pool->base.opps[i] != NULL)
1557                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1558         }
1559
1560         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1561                 if (pool->base.timing_generators[i] != NULL)    {
1562                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1563                         pool->base.timing_generators[i] = NULL;
1564                 }
1565         }
1566
1567         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1568                 if (pool->base.dwbc[i] != NULL) {
1569                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1570                         pool->base.dwbc[i] = NULL;
1571                 }
1572                 if (pool->base.mcif_wb[i] != NULL) {
1573                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1574                         pool->base.mcif_wb[i] = NULL;
1575                 }
1576         }
1577
1578         for (i = 0; i < pool->base.audio_count; i++) {
1579                 if (pool->base.audios[i])
1580                         dce_aud_destroy(&pool->base.audios[i]);
1581         }
1582
1583         for (i = 0; i < pool->base.clk_src_count; i++) {
1584                 if (pool->base.clock_sources[i] != NULL) {
1585                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1586                         pool->base.clock_sources[i] = NULL;
1587                 }
1588         }
1589
1590         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1591                 if (pool->base.mpc_lut[i] != NULL) {
1592                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1593                         pool->base.mpc_lut[i] = NULL;
1594                 }
1595                 if (pool->base.mpc_shaper[i] != NULL) {
1596                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1597                         pool->base.mpc_shaper[i] = NULL;
1598                 }
1599         }
1600
1601         if (pool->base.dp_clock_source != NULL) {
1602                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1603                 pool->base.dp_clock_source = NULL;
1604         }
1605
1606         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1607                 if (pool->base.multiple_abms[i] != NULL)
1608                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1609         }
1610
1611         if (pool->base.psr != NULL)
1612                 dmub_psr_destroy(&pool->base.psr);
1613
1614         if (pool->base.dccg != NULL)
1615                 dcn_dccg_destroy(&pool->base.dccg);
1616
1617         if (pool->base.oem_device != NULL)
1618                 dal_ddc_service_destroy(&pool->base.oem_device);
1619 }
1620
1621
1622 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1623 {
1624         int i;
1625         uint32_t dwb_count = pool->res_cap->num_dwb;
1626
1627         for (i = 0; i < dwb_count; i++) {
1628                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1629                                                     GFP_KERNEL);
1630
1631                 if (!dwbc30) {
1632                         dm_error("DC: failed to create dwbc30!\n");
1633                         return false;
1634                 }
1635
1636                 dcn30_dwbc_construct(dwbc30, ctx,
1637                                 &dwbc30_regs[i],
1638                                 &dwbc30_shift,
1639                                 &dwbc30_mask,
1640                                 i);
1641
1642                 pool->dwbc[i] = &dwbc30->base;
1643         }
1644         return true;
1645 }
1646
1647 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1648 {
1649         int i;
1650         uint32_t dwb_count = pool->res_cap->num_dwb;
1651
1652         for (i = 0; i < dwb_count; i++) {
1653                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1654                                                     GFP_KERNEL);
1655
1656                 if (!mcif_wb30) {
1657                         dm_error("DC: failed to create mcif_wb30!\n");
1658                         return false;
1659                 }
1660
1661                 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1662                                 &mcif_wb30_regs[i],
1663                                 &mcif_wb30_shift,
1664                                 &mcif_wb30_mask,
1665                                 i);
1666
1667                 pool->mcif_wb[i] = &mcif_wb30->base;
1668         }
1669         return true;
1670 }
1671
1672 static struct display_stream_compressor *dcn321_dsc_create(
1673         struct dc_context *ctx, uint32_t inst)
1674 {
1675         struct dcn20_dsc *dsc =
1676                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1677
1678         if (!dsc) {
1679                 BREAK_TO_DEBUGGER();
1680                 return NULL;
1681         }
1682
1683         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1684         return &dsc->base;
1685 }
1686
1687 static void dcn321_destroy_resource_pool(struct resource_pool **pool)
1688 {
1689         struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
1690
1691         dcn321_resource_destruct(dcn321_pool);
1692         kfree(dcn321_pool);
1693         *pool = NULL;
1694 }
1695
1696 static struct dc_cap_funcs cap_funcs = {
1697         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1698 };
1699
1700
1701 static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
1702                 unsigned int *optimal_dcfclk,
1703                 unsigned int *optimal_fclk)
1704 {
1705         double bw_from_dram, bw_from_dram1, bw_from_dram2;
1706
1707         bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans *
1708                 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100);
1709         bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans *
1710                 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100);
1711
1712         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
1713
1714         if (optimal_fclk)
1715                 *optimal_fclk = bw_from_dram /
1716                 (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
1717
1718         if (optimal_dcfclk)
1719                 *optimal_dcfclk =  bw_from_dram /
1720                 (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
1721 }
1722
1723 /* dcn321_update_bw_bounding_box
1724  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
1725  * with actual values as per dGPU SKU:
1726  * -with passed few options from dc->config
1727  * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
1728  * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
1729  * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
1730  * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
1731  * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
1732  *  clocks (which might differ for certain dGPU SKU of the same ASIC)
1733  */
1734 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1735 {
1736         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1737                 /* Overrides from dc->config options */
1738                 dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1739
1740                 /* Override from passed dc->bb_overrides if available*/
1741                 if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
1742                                 && dc->bb_overrides.sr_exit_time_ns) {
1743                         dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1744                 }
1745
1746                 if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000)
1747                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
1748                                 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1749                         dcn3_21_soc.sr_enter_plus_exit_time_us =
1750                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1751                 }
1752
1753                 if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
1754                         && dc->bb_overrides.urgent_latency_ns) {
1755                         dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1756                 }
1757
1758                 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000)
1759                                 != dc->bb_overrides.dram_clock_change_latency_ns
1760                                 && dc->bb_overrides.dram_clock_change_latency_ns) {
1761                         dcn3_21_soc.dram_clock_change_latency_us =
1762                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1763                 }
1764
1765                 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000)
1766                                 != dc->bb_overrides.dummy_clock_change_latency_ns
1767                                 && dc->bb_overrides.dummy_clock_change_latency_ns) {
1768                         dcn3_21_soc.dummy_pstate_latency_us =
1769                                 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
1770                 }
1771
1772                 /* Override from VBIOS if VBIOS bb_info available */
1773                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1774                         struct bp_soc_bb_info bb_info = {0};
1775
1776                         if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1777                                 if (bb_info.dram_clock_change_latency_100ns > 0)
1778                                         dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1779
1780                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1781                                 dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1782
1783                         if (bb_info.dram_sr_exit_latency_100ns > 0)
1784                                 dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1785                         }
1786                 }
1787
1788                 /* Override from VBIOS for num_chan */
1789                 if (dc->ctx->dc_bios->vram_info.num_chans)
1790                         dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
1791
1792                 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
1793                         dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
1794
1795         }
1796
1797         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
1798         dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1799         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1800
1801         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
1802         if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
1803                 unsigned int i = 0, j = 0, num_states = 0;
1804
1805                 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
1806                 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
1807                 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
1808                 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
1809
1810                 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
1811                 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
1812                 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
1813
1814                 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
1815                         if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
1816                                 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
1817                         if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
1818                                 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
1819                         if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
1820                                 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
1821                         if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
1822                                 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
1823                 }
1824                 if (!max_dcfclk_mhz)
1825                         max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz;
1826                 if (!max_dispclk_mhz)
1827                         max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz;
1828                 if (!max_dppclk_mhz)
1829                         max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz;
1830                 if (!max_phyclk_mhz)
1831                         max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
1832
1833                 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1834                         // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
1835                         dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
1836                         num_dcfclk_sta_targets++;
1837                 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1838                         // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
1839                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
1840                                 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
1841                                         dcfclk_sta_targets[i] = max_dcfclk_mhz;
1842                                         break;
1843                                 }
1844                         }
1845                         // Update size of array since we "removed" duplicates
1846                         num_dcfclk_sta_targets = i + 1;
1847                 }
1848
1849                 num_uclk_states = bw_params->clk_table.num_entries;
1850
1851                 // Calculate optimal dcfclk for each uclk
1852                 for (i = 0; i < num_uclk_states; i++) {
1853                         dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
1854                                         &optimal_dcfclk_for_uclk[i], NULL);
1855                         if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
1856                                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
1857                         }
1858                 }
1859
1860                 // Calculate optimal uclk for each dcfclk sta target
1861                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
1862                         for (j = 0; j < num_uclk_states; j++) {
1863                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
1864                                         optimal_uclk_for_dcfclk_sta_targets[i] =
1865                                                         bw_params->clk_table.entries[j].memclk_mhz * 16;
1866                                         break;
1867                                 }
1868                         }
1869                 }
1870
1871                 i = 0;
1872                 j = 0;
1873                 // create the final dcfclk and uclk table
1874                 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
1875                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
1876                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1877                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1878                         } else {
1879                                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1880                                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1881                                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1882                                 } else {
1883                                         j = num_uclk_states;
1884                                 }
1885                         }
1886                 }
1887
1888                 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
1889                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1890                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1891                 }
1892
1893                 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
1894                                 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1895                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1896                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1897                 }
1898
1899                 dcn3_21_soc.num_states = num_states;
1900                 for (i = 0; i < dcn3_21_soc.num_states; i++) {
1901                         dcn3_21_soc.clock_limits[i].state = i;
1902                         dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
1903                         dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
1904                         dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
1905
1906                         /* Fill all states with max values of all these clocks */
1907                         dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
1908                         dcn3_21_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
1909                         dcn3_21_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
1910                         dcn3_21_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
1911
1912                         /* Populate from bw_params for DTBCLK, SOCCLK */
1913                         if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
1914                                 dcn3_21_soc.clock_limits[i].dtbclk_mhz  = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
1915                         else
1916                                 dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
1917
1918                         if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
1919                                 dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
1920                         else
1921                                 dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
1922
1923                         /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
1924                         /* PHYCLK_D18, PHYCLK_D32 */
1925                         dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
1926                         dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
1927                 }
1928
1929                 /* Re-init DML with updated bb */
1930                 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
1931                 if (dc->current_state)
1932                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
1933         }
1934 }
1935
1936 static struct resource_funcs dcn321_res_pool_funcs = {
1937         .destroy = dcn321_destroy_resource_pool,
1938         .link_enc_create = dcn321_link_encoder_create,
1939         .link_enc_create_minimal = NULL,
1940         .panel_cntl_create = dcn32_panel_cntl_create,
1941         .validate_bandwidth = dcn32_validate_bandwidth,
1942         .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1943         .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1944         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1945         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1946         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1947         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1948         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1949         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1950         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1951         .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1952         .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1953         .update_bw_bounding_box = dcn321_update_bw_bounding_box,
1954         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1955         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1956         .add_phantom_pipes = dcn32_add_phantom_pipes,
1957         .remove_phantom_pipes = dcn32_remove_phantom_pipes,
1958 };
1959
1960
1961 static bool dcn321_resource_construct(
1962         uint8_t num_virtual_links,
1963         struct dc *dc,
1964         struct dcn321_resource_pool *pool)
1965 {
1966         int i, j;
1967         struct dc_context *ctx = dc->ctx;
1968         struct irq_service_init_data init_data;
1969         struct ddc_service_init_data ddc_init_data = {0};
1970         uint32_t pipe_fuses = 0;
1971         uint32_t num_pipes  = 4;
1972
1973         ctx->dc_bios->regs = &bios_regs;
1974
1975         pool->base.res_cap = &res_cap_dcn321;
1976         /* max number of pipes for ASIC before checking for pipe fuses */
1977         num_pipes  = pool->base.res_cap->num_timing_generator;
1978         pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
1979
1980         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1981                 if (pipe_fuses & 1 << i)
1982                         num_pipes--;
1983
1984         if (pipe_fuses & 1)
1985                 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1986
1987         if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1988                 ASSERT(0); //Entire DCN is harvested!
1989
1990         /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
1991          * value will be changed, update max_num_dpp and max_num_otg for dml.
1992          */
1993         dcn3_21_ip.max_num_dpp = num_pipes;
1994         dcn3_21_ip.max_num_otg = num_pipes;
1995
1996         pool->base.funcs = &dcn321_res_pool_funcs;
1997
1998         /*************************************************
1999          *  Resource + asic cap harcoding                *
2000          *************************************************/
2001         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2002         pool->base.timing_generator_count = num_pipes;
2003         pool->base.pipe_count = num_pipes;
2004         pool->base.mpcc_count = num_pipes;
2005         dc->caps.max_downscale_ratio = 600;
2006         dc->caps.i2c_speed_in_khz = 100;
2007         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
2008         dc->caps.max_cursor_size = 256;
2009         dc->caps.min_horizontal_blanking_period = 80;
2010         dc->caps.dmdata_alloc_size = 2048;
2011         dc->caps.mall_size_per_mem_channel = 0;
2012         dc->caps.mall_size_total = 0;
2013         dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2014         dc->caps.cache_line_size = 64;
2015         dc->caps.cache_num_ways = 16;
2016         dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32
2017         dc->caps.subvp_fw_processing_delay_us = 15;
2018         dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2019         dc->caps.subvp_pstate_allow_width_us = 20;
2020
2021         dc->caps.max_slave_planes = 1;
2022         dc->caps.max_slave_yuv_planes = 1;
2023         dc->caps.max_slave_rgb_planes = 1;
2024         dc->caps.post_blend_color_processing = true;
2025         dc->caps.force_dp_tps4_for_cp2520 = true;
2026         dc->caps.dp_hpo = true;
2027         dc->caps.edp_dsc_support = true;
2028         dc->caps.extended_aux_timeout_support = true;
2029         dc->caps.dmcub_support = true;
2030
2031         /* Color pipeline capabilities */
2032         dc->caps.color.dpp.dcn_arch = 1;
2033         dc->caps.color.dpp.input_lut_shared = 0;
2034         dc->caps.color.dpp.icsc = 1;
2035         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2036         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2037         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2038         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2039         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2040         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2041         dc->caps.color.dpp.post_csc = 1;
2042         dc->caps.color.dpp.gamma_corr = 1;
2043         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2044
2045         dc->caps.color.dpp.hw_3d_lut = 0; //3DLUT removed from DPP
2046         dc->caps.color.dpp.ogam_ram = 0;  //Blnd Gam also removed
2047         // no OGAM ROM on DCN2 and later ASICs
2048         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2049         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2050         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2051         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2052         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2053         dc->caps.color.dpp.ocsc = 0;
2054
2055         dc->caps.color.mpc.gamut_remap = 1;
2056         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2057         dc->caps.color.mpc.ogam_ram = 1;
2058         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2059         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2060         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2061         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2062         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2063         dc->caps.color.mpc.ocsc = 1;
2064
2065         /* read VBIOS LTTPR caps */
2066         {
2067                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2068                         enum bp_result bp_query_result;
2069                         uint8_t is_vbios_lttpr_enable = 0;
2070
2071                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2072                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2073                 }
2074
2075                 /* interop bit is implicit */
2076                 {
2077                         dc->caps.vbios_lttpr_aware = true;
2078                 }
2079         }
2080
2081         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2082                 dc->debug = debug_defaults_drv;
2083         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2084                 dc->debug = debug_defaults_diags;
2085         } else
2086                 dc->debug = debug_defaults_diags;
2087         // Init the vm_helper
2088         if (dc->vm_helper)
2089                 vm_helper_init(dc->vm_helper, 16);
2090
2091         /*************************************************
2092          *  Create resources                             *
2093          *************************************************/
2094
2095         /* Clock Sources for Pixel Clock*/
2096         pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
2097                         dcn321_clock_source_create(ctx, ctx->dc_bios,
2098                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2099                                 &clk_src_regs[0], false);
2100         pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
2101                         dcn321_clock_source_create(ctx, ctx->dc_bios,
2102                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2103                                 &clk_src_regs[1], false);
2104         pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
2105                         dcn321_clock_source_create(ctx, ctx->dc_bios,
2106                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2107                                 &clk_src_regs[2], false);
2108         pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
2109                         dcn321_clock_source_create(ctx, ctx->dc_bios,
2110                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2111                                 &clk_src_regs[3], false);
2112         pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
2113                         dcn321_clock_source_create(ctx, ctx->dc_bios,
2114                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2115                                 &clk_src_regs[4], false);
2116
2117         pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
2118
2119         /* todo: not reuse phy_pll registers */
2120         pool->base.dp_clock_source =
2121                         dcn321_clock_source_create(ctx, ctx->dc_bios,
2122                                 CLOCK_SOURCE_ID_DP_DTO,
2123                                 &clk_src_regs[0], true);
2124
2125         for (i = 0; i < pool->base.clk_src_count; i++) {
2126                 if (pool->base.clock_sources[i] == NULL) {
2127                         dm_error("DC: failed to create clock sources!\n");
2128                         BREAK_TO_DEBUGGER();
2129                         goto create_fail;
2130                 }
2131         }
2132
2133         /* DCCG */
2134         pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2135         if (pool->base.dccg == NULL) {
2136                 dm_error("DC: failed to create dccg!\n");
2137                 BREAK_TO_DEBUGGER();
2138                 goto create_fail;
2139         }
2140
2141         /* DML */
2142         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2143                 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
2144
2145         /* IRQ Service */
2146         init_data.ctx = dc->ctx;
2147         pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2148         if (!pool->base.irqs)
2149                 goto create_fail;
2150
2151         /* HUBBUB */
2152         pool->base.hubbub = dcn321_hubbub_create(ctx);
2153         if (pool->base.hubbub == NULL) {
2154                 BREAK_TO_DEBUGGER();
2155                 dm_error("DC: failed to create hubbub!\n");
2156                 goto create_fail;
2157         }
2158
2159         /* HUBPs, DPPs, OPPs, TGs, ABMs */
2160         for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2161
2162                 /* if pipe is disabled, skip instance of HW pipe,
2163                  * i.e, skip ASIC register instance
2164                  */
2165                 if (pipe_fuses & 1 << i)
2166                         continue;
2167
2168                 pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
2169                 if (pool->base.hubps[j] == NULL) {
2170                         BREAK_TO_DEBUGGER();
2171                         dm_error(
2172                                 "DC: failed to create hubps!\n");
2173                         goto create_fail;
2174                 }
2175
2176                 pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
2177                 if (pool->base.dpps[j] == NULL) {
2178                         BREAK_TO_DEBUGGER();
2179                         dm_error(
2180                                 "DC: failed to create dpps!\n");
2181                         goto create_fail;
2182                 }
2183
2184                 pool->base.opps[j] = dcn321_opp_create(ctx, i);
2185                 if (pool->base.opps[j] == NULL) {
2186                         BREAK_TO_DEBUGGER();
2187                         dm_error(
2188                                 "DC: failed to create output pixel processor!\n");
2189                         goto create_fail;
2190                 }
2191
2192                 pool->base.timing_generators[j] = dcn321_timing_generator_create(
2193                                 ctx, i);
2194                 if (pool->base.timing_generators[j] == NULL) {
2195                         BREAK_TO_DEBUGGER();
2196                         dm_error("DC: failed to create tg!\n");
2197                         goto create_fail;
2198                 }
2199
2200                 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2201                                 &abm_regs[i],
2202                                 &abm_shift,
2203                                 &abm_mask);
2204                 if (pool->base.multiple_abms[j] == NULL) {
2205                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2206                         BREAK_TO_DEBUGGER();
2207                         goto create_fail;
2208                 }
2209
2210                 /* index for resource pool arrays for next valid pipe */
2211                 j++;
2212         }
2213
2214         /* PSR */
2215         pool->base.psr = dmub_psr_create(ctx);
2216         if (pool->base.psr == NULL) {
2217                 dm_error("DC: failed to create psr obj!\n");
2218                 BREAK_TO_DEBUGGER();
2219                 goto create_fail;
2220         }
2221
2222         /* MPCCs */
2223         pool->base.mpc = dcn321_mpc_create(ctx,  pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2224         if (pool->base.mpc == NULL) {
2225                 BREAK_TO_DEBUGGER();
2226                 dm_error("DC: failed to create mpc!\n");
2227                 goto create_fail;
2228         }
2229
2230         /* DSCs */
2231         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2232                 pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
2233                 if (pool->base.dscs[i] == NULL) {
2234                         BREAK_TO_DEBUGGER();
2235                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2236                         goto create_fail;
2237                 }
2238         }
2239
2240         /* DWB */
2241         if (!dcn321_dwbc_create(ctx, &pool->base)) {
2242                 BREAK_TO_DEBUGGER();
2243                 dm_error("DC: failed to create dwbc!\n");
2244                 goto create_fail;
2245         }
2246
2247         /* MMHUBBUB */
2248         if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
2249                 BREAK_TO_DEBUGGER();
2250                 dm_error("DC: failed to create mcif_wb!\n");
2251                 goto create_fail;
2252         }
2253
2254         /* AUX and I2C */
2255         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2256                 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
2257                 if (pool->base.engines[i] == NULL) {
2258                         BREAK_TO_DEBUGGER();
2259                         dm_error(
2260                                 "DC:failed to create aux engine!!\n");
2261                         goto create_fail;
2262                 }
2263                 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
2264                 if (pool->base.hw_i2cs[i] == NULL) {
2265                         BREAK_TO_DEBUGGER();
2266                         dm_error(
2267                                 "DC:failed to create hw i2c!!\n");
2268                         goto create_fail;
2269                 }
2270                 pool->base.sw_i2cs[i] = NULL;
2271         }
2272
2273         /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2274         if (!resource_construct(num_virtual_links, dc, &pool->base,
2275                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2276                         &res_create_funcs : &res_create_maximus_funcs)))
2277                         goto create_fail;
2278
2279         /* HW Sequencer init functions and Plane caps */
2280         dcn32_hw_sequencer_init_functions(dc);
2281
2282         dc->caps.max_planes =  pool->base.pipe_count;
2283
2284         for (i = 0; i < dc->caps.max_planes; ++i)
2285                 dc->caps.planes[i] = plane_cap;
2286
2287         dc->cap_funcs = cap_funcs;
2288
2289         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2290                 ddc_init_data.ctx = dc->ctx;
2291                 ddc_init_data.link = NULL;
2292                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2293                 ddc_init_data.id.enum_id = 0;
2294                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2295                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2296         } else {
2297                 pool->base.oem_device = NULL;
2298         }
2299
2300         return true;
2301
2302 create_fail:
2303
2304         dcn321_resource_destruct(pool);
2305
2306         return false;
2307 }
2308
2309 struct resource_pool *dcn321_create_resource_pool(
2310                 const struct dc_init_data *init_data,
2311                 struct dc *dc)
2312 {
2313         struct dcn321_resource_pool *pool =
2314                 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL);
2315
2316         if (!pool)
2317                 return NULL;
2318
2319         if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
2320                 return &pool->base;
2321
2322         BREAK_TO_DEBUGGER();
2323         kfree(pool);
2324         return NULL;
2325 }