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26 // header file of functions being implemented
27 #include "dcn32_resource.h"
28 #include "dcn20/dcn20_resource.h"
29 #include "dml/dcn32/display_mode_vba_util_32.h"
30 #include "dml/dcn32/dcn32_fpu.h"
32 static bool is_dual_plane(enum surface_pixel_format format)
34 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
38 uint32_t dcn32_helper_mall_bytes_to_ways(
40 uint32_t total_size_in_mall_bytes)
42 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;
44 /* add 2 lines for worst case alignment */
45 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
47 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
48 lines_per_way = total_cache_lines / dc->caps.cache_num_ways;
49 num_ways = cache_lines_used / lines_per_way;
50 if (cache_lines_used % lines_per_way > 0)
56 uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
58 struct pipe_ctx *pipe_ctx,
59 bool ignore_cursor_buf)
61 struct hubp *hubp = pipe_ctx->plane_res.hubp;
62 uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
63 uint32_t cursor_mall_size_bytes = 0;
65 switch (pipe_ctx->stream->cursor_attributes.color_format) {
66 case CURSOR_MODE_MONO:
69 case CURSOR_MODE_COLOR_1BIT_AND:
70 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
71 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
75 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
76 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
81 /* only count if cursor is enabled, and if additional allocation needed outside of the
84 if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||
85 cursor_size > 16384)) {
86 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1)
87 * Note: add 1 mblk in case of cursor misalignment
89 cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) /
90 DCN3_2_MALL_MBLK_SIZE_BYTES + 1) * DCN3_2_MALL_MBLK_SIZE_BYTES;
93 return cursor_mall_size_bytes;
97 * dcn32_helper_calculate_num_ways_for_subvp(): Calculate number of ways needed for SubVP
99 * Gets total allocation required for the phantom viewport calculated by DML in bytes and
100 * converts to number of cache ways.
102 * @dc: current dc state
103 * @context: new dc state
105 * Return: number of ways required for SubVP
107 uint32_t dcn32_helper_calculate_num_ways_for_subvp(
109 struct dc_state *context)
111 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) {
112 if (dc->debug.force_subvp_num_ways) {
113 return dc->debug.force_subvp_num_ways;
115 return dcn32_helper_mall_bytes_to_ways(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
122 void dcn32_merge_pipes_for_subvp(struct dc *dc,
123 struct dc_state *context)
127 /* merge pipes if necessary */
128 for (i = 0; i < dc->res_pool->pipe_count; i++) {
129 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
131 // For now merge all pipes for SubVP since pipe split case isn't supported yet
133 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
134 if (pipe->prev_odm_pipe) {
135 /*split off odm pipe*/
136 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
137 if (pipe->next_odm_pipe)
138 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
140 pipe->bottom_pipe = NULL;
141 pipe->next_odm_pipe = NULL;
142 pipe->plane_state = NULL;
144 pipe->top_pipe = NULL;
145 pipe->prev_odm_pipe = NULL;
146 if (pipe->stream_res.dsc)
147 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
148 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
149 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
150 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
151 struct pipe_ctx *top_pipe = pipe->top_pipe;
152 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
154 top_pipe->bottom_pipe = bottom_pipe;
156 bottom_pipe->top_pipe = top_pipe;
158 pipe->top_pipe = NULL;
159 pipe->bottom_pipe = NULL;
160 pipe->plane_state = NULL;
162 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
163 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
168 bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
169 struct dc_state *context)
173 for (i = 0; i < dc->res_pool->pipe_count; i++) {
174 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
179 if (!pipe->plane_state)
185 bool dcn32_subvp_in_use(struct dc *dc,
186 struct dc_state *context)
190 for (i = 0; i < dc->res_pool->pipe_count; i++) {
191 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
193 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE)
199 bool dcn32_mpo_in_use(struct dc_state *context)
203 for (i = 0; i < context->stream_count; i++) {
204 if (context->stream_status[i].plane_count > 1)
211 bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)
215 for (i = 0; i < dc->res_pool->pipe_count; i++) {
216 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
221 if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0)
227 bool dcn32_is_center_timing(struct pipe_ctx *pipe)
229 bool is_center_timing = false;
232 if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||
233 pipe->stream->timing.v_addressable != pipe->stream->src.height) {
234 is_center_timing = true;
238 if (pipe->plane_state) {
239 if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&
240 pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {
241 is_center_timing = true;
245 return is_center_timing;
248 bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
250 bool psr_capable = false;
252 if (pipe->stream && pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
258 #define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7
261 * dcn32_determine_det_override(): Determine DET allocation for each pipe
263 * This function determines how much DET to allocate for each pipe. The total number of
264 * DET segments will be split equally among each of the streams, and after that the DET
265 * segments per stream will be split equally among the planes for the given stream.
267 * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the
268 * number of DET for that given plane will be split among the pipes driving that plane.
270 * High level algorithm:
271 * 1. Split total DET among number of streams
272 * 2. For each stream, split DET among the planes
273 * 3. For each plane, check if there is a pipe split. If yes, split the DET allocation
275 * 4. Assign the DET override to the DML pipes.
279 * For two displays that have a large difference in pixel rate, we may experience
280 * underflow on the larger display when we divide the DET equally. For this, we
281 * will implement a modified algorithm to assign more DET to larger display.
283 * 1. Calculate difference in pixel rates ( multiplier ) between two displays
284 * 2. If the multiplier exceeds DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER, then
285 * implement the modified DET override algorithm.
286 * 3. Assign smaller DET size for lower pixel display and higher DET size for
287 * higher pixel display
289 * @dc: Current DC state
290 * @context: New DC state to be programmed
291 * @pipes: Array of DML pipes
295 void dcn32_determine_det_override(struct dc *dc,
296 struct dc_state *context,
297 display_e2e_pipe_params_st *pipes)
300 uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};
301 uint8_t pipe_counted[MAX_PIPES] = {0};
302 uint8_t pipe_cnt = 0;
303 struct dc_plane_state *current_plane = NULL;
304 uint8_t stream_count = 0;
306 int phy_pix_clk_mult, lower_mode_stream_index;
307 int phy_pix_clk[MAX_PIPES] = {0};
308 bool use_new_det_override_algorithm = false;
310 for (i = 0; i < context->stream_count; i++) {
311 /* Don't count SubVP streams for DET allocation */
312 if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) {
313 phy_pix_clk[i] = context->streams[i]->phy_pix_clk;
318 /* Check for special case with two displays, one with much higher pixel rate */
319 if (stream_count == 2) {
320 ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0));
321 if (phy_pix_clk[0] < phy_pix_clk[1]) {
322 lower_mode_stream_index = 0;
323 phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0];
325 lower_mode_stream_index = 1;
326 phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1];
329 if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER)
330 use_new_det_override_algorithm = true;
333 if (stream_count > 0) {
334 stream_segments = 18 / stream_count;
335 for (i = 0; i < context->stream_count; i++) {
336 if (context->streams[i]->mall_stream_config.type == SUBVP_PHANTOM)
339 if (use_new_det_override_algorithm) {
340 if (i == lower_mode_stream_index)
343 stream_segments = 14;
346 if (context->stream_status[i].plane_count > 0)
347 plane_segments = stream_segments / context->stream_status[i].plane_count;
349 plane_segments = stream_segments;
350 for (j = 0; j < dc->res_pool->pipe_count; j++) {
351 pipe_plane_count = 0;
352 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&
353 pipe_counted[j] != 1) {
354 /* Note: pipe_plane_count indicates the number of pipes to be used for a
355 * given plane. e.g. pipe_plane_count = 1 means single pipe (i.e. not split),
356 * pipe_plane_count = 2 means 2:1 split, etc.
360 current_plane = context->res_ctx.pipe_ctx[j].plane_state;
361 for (k = 0; k < dc->res_pool->pipe_count; k++) {
362 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
363 context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
369 pipe_segments[j] = plane_segments / pipe_plane_count;
370 for (k = 0; k < dc->res_pool->pipe_count; k++) {
371 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
372 context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
373 pipe_segments[k] = plane_segments / pipe_plane_count;
380 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
381 if (!context->res_ctx.pipe_ctx[i].stream)
383 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE;
387 for (i = 0; i < dc->res_pool->pipe_count; i++)
388 pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE
392 void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
393 display_e2e_pipe_params_st *pipes)
396 struct resource_context *res_ctx = &context->res_ctx;
397 struct pipe_ctx *pipe;
398 bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
400 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
402 if (!res_ctx->pipe_ctx[i].stream)
405 pipe = &res_ctx->pipe_ctx[i];
409 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
410 * the DET available for each pipe). Use the DET override input to maintain our driver
414 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;
415 if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
416 if (!is_dual_plane(pipe->plane_state->format)) {
417 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
418 pipes[0].pipe.src.unbounded_req_mode = true;
419 if (pipe->plane_state->src_rect.width >= 5120 &&
420 pipe->plane_state->src_rect.height >= 2880)
421 pipes[0].pipe.src.det_size_override = 320; // 5K or higher
425 dcn32_determine_det_override(dc, context, pipes);
429 * dcn32_save_mall_state(): Save MALL (SubVP) state for fast validation cases
431 * This function saves the MALL (SubVP) case for fast validation cases. For fast validation,
432 * there are situations where a shallow copy of the dc->current_state is created for the
433 * validation. In this case we want to save and restore the mall config because we always
434 * teardown subvp at the beginning of validation (and don't attempt to add it back if it's
435 * fast validation). If we don't restore the subvp config in cases of fast validation +
436 * shallow copy of the dc->current_state, the dc->current_state will have a partially
437 * removed subvp state when we did not intend to remove it.
439 * NOTE: This function ONLY works if the streams are not moved to a different pipe in the
440 * validation. We don't expect this to happen in fast_validation=1 cases.
442 * @dc: Current DC state
443 * @context: New DC state to be programmed
444 * @temp_config: struct used to cache the existing MALL state
448 void dcn32_save_mall_state(struct dc *dc,
449 struct dc_state *context,
450 struct mall_temp_config *temp_config)
454 for (i = 0; i < dc->res_pool->pipe_count; i++) {
455 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
458 temp_config->mall_stream_config[i] = pipe->stream->mall_stream_config;
460 if (pipe->plane_state)
461 temp_config->is_phantom_plane[i] = pipe->plane_state->is_phantom;
466 * dcn32_restore_mall_state(): Restore MALL (SubVP) state for fast validation cases
468 * Restore the MALL state based on the previously saved state from dcn32_save_mall_state
470 * @dc: Current DC state
471 * @context: New DC state to be programmed, restore MALL state into here
472 * @temp_config: struct that has the cached MALL state
476 void dcn32_restore_mall_state(struct dc *dc,
477 struct dc_state *context,
478 struct mall_temp_config *temp_config)
482 for (i = 0; i < dc->res_pool->pipe_count; i++) {
483 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
486 pipe->stream->mall_stream_config = temp_config->mall_stream_config[i];
488 if (pipe->plane_state)
489 pipe->plane_state->is_phantom = temp_config->is_phantom_plane[i];
493 #define MAX_STRETCHED_V_BLANK 1000 // in micro-seconds (must ensure to match value in FW)
495 * Scaling factor for v_blank stretch calculations considering timing in
496 * micro-seconds and pixel clock in 100hz.
497 * Note: the parenthesis are necessary to ensure the correct order of
498 * operation where V_SCALE is used.
500 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
502 static int get_frame_rate_at_max_stretch_100hz(
503 struct dc_stream_state *fpo_candidate_stream,
504 uint32_t fpo_vactive_margin_us)
506 struct dc_crtc_timing *timing = NULL;
507 uint32_t sec_per_100_lines;
508 uint32_t max_v_blank;
509 uint32_t curr_v_blank;
510 uint32_t v_stretch_max;
511 uint32_t stretched_frame_pix_cnt;
512 uint32_t scaled_stretched_frame_pix_cnt;
513 uint32_t scaled_refresh_rate;
516 if (fpo_candidate_stream == NULL)
519 /* check if refresh rate at least 120hz */
520 timing = &fpo_candidate_stream->timing;
524 v_scale = 10000 / (MAX_STRETCHED_V_BLANK + fpo_vactive_margin_us);
526 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
527 max_v_blank = sec_per_100_lines / v_scale + 1;
528 curr_v_blank = timing->v_total - timing->v_addressable;
529 v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
530 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
531 scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
532 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
534 return scaled_refresh_rate;
538 static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(
539 struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us)
541 int refresh_rate_max_stretch_100hz;
542 int min_refresh_100hz;
544 if (fpo_candidate_stream == NULL)
547 refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(fpo_candidate_stream, fpo_vactive_margin_us);
548 min_refresh_100hz = fpo_candidate_stream->timing.min_refresh_in_uhz / 10000;
550 if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
556 static int get_refresh_rate(struct dc_stream_state *fpo_candidate_stream)
558 int refresh_rate = 0;
560 struct dc_crtc_timing *timing = NULL;
562 if (fpo_candidate_stream == NULL)
565 /* check if refresh rate at least 120hz */
566 timing = &fpo_candidate_stream->timing;
570 h_v_total = timing->h_total * timing->v_total;
574 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
579 * dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch() - Determines if config can
582 * @dc: current dc state
583 * @context: new dc state
585 * Return: Pointer to FPO stream candidate if config can support FPO, otherwise NULL
587 struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, const struct dc_state *context)
589 int refresh_rate = 0;
590 const int minimum_refreshrate_supported = 120;
591 struct dc_stream_state *fpo_candidate_stream = NULL;
592 bool is_fpo_vactive = false;
593 uint32_t fpo_vactive_margin_us = 0;
598 if (dc->debug.disable_fams)
601 if (!dc->caps.dmub_caps.mclk_sw)
604 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
607 /* For FPO we can support up to 2 display configs if:
608 * - first display uses FPO
609 * - Second display switches in VACTIVE */
610 if (context->stream_count > 2)
612 else if (context->stream_count == 2) {
614 dcn32_assign_fpo_vactive_candidate(dc, context, &fpo_candidate_stream);
618 is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, dc->debug.fpo_vactive_min_active_margin_us);
620 if (!is_fpo_vactive || dc->debug.disable_fpo_vactive)
623 fpo_candidate_stream = context->streams[0];
625 if (!fpo_candidate_stream)
628 if (fpo_candidate_stream->sink->edid_caps.panel_patch.disable_fams)
631 refresh_rate = get_refresh_rate(fpo_candidate_stream);
632 if (refresh_rate < minimum_refreshrate_supported)
635 fpo_vactive_margin_us = is_fpo_vactive ? dc->debug.fpo_vactive_margin_us : 0; // For now hardcode the FPO + Vactive stretch margin to be 2000us
636 if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(fpo_candidate_stream, fpo_vactive_margin_us))
639 // check if freesync enabled
640 if (!fpo_candidate_stream->allow_freesync)
643 if (fpo_candidate_stream->vrr_active_variable)
646 return fpo_candidate_stream;
649 bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)
651 bool is_native_scaling = false;
653 if (pipe->stream->timing.h_addressable == width &&
654 pipe->stream->timing.v_addressable == height &&
655 pipe->plane_state->src_rect.width == width &&
656 pipe->plane_state->src_rect.height == height &&
657 pipe->plane_state->dst_rect.width == width &&
658 pipe->plane_state->dst_rect.height == height)
659 is_native_scaling = true;
661 return is_native_scaling;