drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn32_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn32_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn30/dcn30_hubbub.h"
  41 #include "dcn31/dcn31_hubbub.h"
  42 #include "dcn32/dcn32_hubbub.h"
  43 #include "dcn32/dcn32_mpc.h"
  44 #include "dcn32_hubp.h"
  45 #include "irq/dcn32/irq_service_dcn32.h"
  46 #include "dcn32/dcn32_dpp.h"
  47 #include "dcn32/dcn32_optc.h"
  48 #include "dcn20/dcn20_hwseq.h"
  49 #include "dcn30/dcn30_hwseq.h"
  50 #include "dce110/dce110_hw_sequencer.h"
  51 #include "dcn30/dcn30_opp.h"
  52 #include "dcn20/dcn20_dsc.h"
  53 #include "dcn30/dcn30_vpg.h"
  54 #include "dcn30/dcn30_afmt.h"
  55 #include "dcn30/dcn30_dio_stream_encoder.h"
  56 #include "dcn32/dcn32_dio_stream_encoder.h"
  57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  59 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
  60 #include "dc_link_dp.h"
  61 #include "dcn31/dcn31_apg.h"
  62 #include "dcn31/dcn31_dio_link_encoder.h"
  63 #include "dcn32/dcn32_dio_link_encoder.h"
  64 #include "dce/dce_clock_source.h"
  65 #include "dce/dce_audio.h"
  66 #include "dce/dce_hwseq.h"
  67 #include "clk_mgr.h"
  68 #include "virtual/virtual_stream_encoder.h"
  69 #include "dml/display_mode_vba.h"
  70 #include "dcn32/dcn32_dccg.h"
  71 #include "dcn10/dcn10_resource.h"
  72 #include "dc_link_ddc.h"
  73 #include "dcn31/dcn31_panel_cntl.h"
  74
  75 #include "dcn30/dcn30_dwb.h"
  76 #include "dcn32/dcn32_mmhubbub.h"
  77
  78 #include "dcn/dcn_3_2_0_offset.h"
  79 #include "dcn/dcn_3_2_0_sh_mask.h"
  80 #include "nbio/nbio_4_3_0_offset.h"
  81
  82 #include "reg_helper.h"
  83 #include "dce/dmub_abm.h"
  84 #include "dce/dmub_psr.h"
  85 #include "dce/dce_aux.h"
  86 #include "dce/dce_i2c.h"
  87
  88 #include "dml/dcn30/display_mode_vba_30.h"
  89 #include "vm_helper.h"
  90 #include "dcn20/dcn20_vmid.h"
  91
  92 #define DCN_BASE__INST0_SEG1                       0x000000C0
  93 #define DCN_BASE__INST0_SEG2                       0x000034C0
  94 #define DCN_BASE__INST0_SEG3                       0x00009000
  95 #define NBIO_BASE__INST0_SEG1                      0x00000014
  96
  97 #define MAX_INSTANCE                                        6
  98 #define MAX_SEGMENT                                         6
  99
 100 struct IP_BASE_INSTANCE {
 101         unsigned int segment[MAX_SEGMENT];
 102 };
 103
 104 struct IP_BASE {
 105         struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
 106 };
 107
 108 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
 109                                         { { 0, 0, 0, 0, 0, 0 } },
 110                                         { { 0, 0, 0, 0, 0, 0 } },
 111                                         { { 0, 0, 0, 0, 0, 0 } },
 112                                         { { 0, 0, 0, 0, 0, 0 } },
 113                                         { { 0, 0, 0, 0, 0, 0 } } } };
 114
 115 #define DC_LOGGER_INIT(logger)
 116
 117 #define DCN3_2_DEFAULT_DET_SIZE 256
 118 #define DCN3_2_MAX_DET_SIZE 1152
 119 #define DCN3_2_MIN_DET_SIZE 128
 120 #define DCN3_2_MIN_COMPBUF_SIZE_KB 128
 121
 122 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
 123         .gpuvm_enable = 1,
 124         .gpuvm_max_page_table_levels = 1,
 125         .hostvm_enable = 0,
 126         .rob_buffer_size_kbytes = 128,
 127         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
 128         .config_return_buffer_size_in_kbytes = 1280,
 129         .compressed_buffer_segment_size_in_kbytes = 64,
 130         .meta_fifo_size_in_kentries = 22,
 131         .zero_size_buffer_entries = 512,
 132         .compbuf_reserved_space_64b = 256,
 133         .compbuf_reserved_space_zs = 64,
 134         .dpp_output_buffer_pixels = 2560,
 135         .opp_output_buffer_lines = 1,
 136         .pixel_chunk_size_kbytes = 8,
 137         .alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team
 138         .min_pixel_chunk_size_bytes = 1024,
 139         .dcc_meta_buffer_size_bytes = 6272,
 140         .meta_chunk_size_kbytes = 2,
 141         .min_meta_chunk_size_bytes = 256,
 142         .writeback_chunk_size_kbytes = 8,
 143         .ptoi_supported = false,
 144         .num_dsc = 4,
 145         .maximum_dsc_bits_per_component = 12,
 146         .maximum_pixels_per_line_per_dsc_unit = 6016,
 147         .dsc422_native_support = true,
 148         .is_line_buffer_bpp_fixed = true,
 149         .line_buffer_fixed_bpp = 57,
 150         .line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp
 151         .max_line_buffer_lines = 32,
 152         .writeback_interface_buffer_size_kbytes = 90,
 153         .max_num_dpp = 4,
 154         .max_num_otg = 4,
 155         .max_num_hdmi_frl_outputs = 1,
 156         .max_num_wb = 1,
 157         .max_dchub_pscl_bw_pix_per_clk = 4,
 158         .max_pscl_lb_bw_pix_per_clk = 2,
 159         .max_lb_vscl_bw_pix_per_clk = 4,
 160         .max_vscl_hscl_bw_pix_per_clk = 4,
 161         .max_hscl_ratio = 6,
 162         .max_vscl_ratio = 6,
 163         .max_hscl_taps = 8,
 164         .max_vscl_taps = 8,
 165         .dpte_buffer_size_in_pte_reqs_luma = 64,
 166         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 167         .dispclk_ramp_margin_percent = 1,
 168         .max_inter_dcn_tile_repeaters = 8,
 169         .cursor_buffer_size = 16,
 170         .cursor_chunk_size = 2,
 171         .writeback_line_buffer_buffer_size = 0,
 172         .writeback_min_hscl_ratio = 1,
 173         .writeback_min_vscl_ratio = 1,
 174         .writeback_max_hscl_ratio = 1,
 175         .writeback_max_vscl_ratio = 1,
 176         .writeback_max_hscl_taps = 1,
 177         .writeback_max_vscl_taps = 1,
 178         .dppclk_delay_subtotal = 47,
 179         .dppclk_delay_scl = 50,
 180         .dppclk_delay_scl_lb_only = 16,
 181         .dppclk_delay_cnvc_formatter = 28,
 182         .dppclk_delay_cnvc_cursor = 6,
 183         .dispclk_delay_subtotal = 125,
 184         .dynamic_metadata_vm_enabled = false,
 185         .odm_combine_4to1_supported = false,
 186         .dcc_supported = true,
 187         .max_num_dp2p0_outputs = 2,
 188         .max_num_dp2p0_streams = 4,
 189 };
 190
 191 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 192         .clock_limits = {
 193                 {
 194                         .state = 0,
 195                         .dcfclk_mhz = 1564.0,
 196                         .fabricclk_mhz = 400.0,
 197                         .dispclk_mhz = 2150.0,
 198                         .dppclk_mhz = 2150.0,
 199                         .phyclk_mhz = 810.0,
 200                         .phyclk_d18_mhz = 667.0,
 201                         .phyclk_d32_mhz = 625.0,
 202                         .socclk_mhz = 1200.0,
 203                         .dscclk_mhz = 716.667,
 204                         .dram_speed_mts = 1600.0,
 205                         .dtbclk_mhz = 1564.0,
 206                 },
 207         },
 208         .num_states = 1,
 209         .sr_exit_time_us = 5.20,
 210         .sr_enter_plus_exit_time_us = 9.60,
 211         .sr_exit_z8_time_us = 285.0,
 212         .sr_enter_plus_exit_z8_time_us = 320,
 213         .writeback_latency_us = 12.0,
 214         .round_trip_ping_latency_dcfclk_cycles = 263,
 215         .urgent_latency_pixel_data_only_us = 4.0,
 216         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 217         .urgent_latency_vm_data_only_us = 4.0,
 218         .fclk_change_latency_us = 20,
 219         .usr_retraining_latency_us = 2,
 220         .smn_latency_us = 2,
 221         .mall_allocated_for_dcn_mbytes = 64,
 222         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 223         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 224         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 225         .pct_ideal_sdp_bw_after_urgent = 100.0,
 226         .pct_ideal_fabric_bw_after_urgent = 67.0,
 227         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 228         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 229         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 230         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 231         .max_avg_sdp_bw_use_normal_percent = 80.0,
 232         .max_avg_fabric_bw_use_normal_percent = 60.0,
 233         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 234         .max_avg_dram_bw_use_normal_percent = 15.0,
 235         .num_chans = 8,
 236         .dram_channel_width_bytes = 2,
 237         .fabric_datapath_to_dcn_data_return_bytes = 64,
 238         .return_bus_width_bytes = 64,
 239         .downspread_percent = 0.38,
 240         .dcn_downspread_percent = 0.5,
 241         .dram_clock_change_latency_us = 400,
 242         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 243         .do_urgent_latency_adjustment = true,
 244         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 245         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 246 };
 247
 248 enum dcn32_clk_src_array_id {
 249         DCN32_CLK_SRC_PLL0,
 250         DCN32_CLK_SRC_PLL1,
 251         DCN32_CLK_SRC_PLL2,
 252         DCN32_CLK_SRC_PLL3,
 253         DCN32_CLK_SRC_PLL4,
 254         DCN32_CLK_SRC_TOTAL
 255 };
 256
 257 /* begin *********************
 258  * macros to expend register list macro defined in HW object header file
 259  */
 260
 261 /* DCN */
 262 /* TODO awful hack. fixup dcn20_dwb.h */
 263 #undef BASE_INNER
 264 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 265
 266 #define BASE(seg) BASE_INNER(seg)
 267
 268 #define SR(reg_name)\
 269                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 270                                         reg ## reg_name
 271
 272 #define SRI(reg_name, block, id)\
 273         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 274                                         reg ## block ## id ## _ ## reg_name
 275
 276 #define SRI2(reg_name, block, id)\
 277         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 278                                         reg ## reg_name
 279
 280 #define SRIR(var_name, reg_name, block, id)\
 281         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 282                                         reg ## block ## id ## _ ## reg_name
 283
 284 #define SRII(reg_name, block, id)\
 285         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 286                                         reg ## block ## id ## _ ## reg_name
 287
 288 #define SRII_MPC_RMU(reg_name, block, id)\
 289         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 290                                         reg ## block ## id ## _ ## reg_name
 291
 292 #define SRII_DWB(reg_name, temp_name, block, id)\
 293         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 294                                         reg ## block ## id ## _ ## temp_name
 295
 296 #define DCCG_SRII(reg_name, block, id)\
 297         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 298                                         reg ## block ## id ## _ ## reg_name
 299
 300 #define VUPDATE_SRII(reg_name, block, id)\
 301         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 302                                         reg ## reg_name ## _ ## block ## id
 303
 304 /* NBIO */
 305 #define NBIO_BASE_INNER(seg) \
 306         NBIO_BASE__INST0_SEG ## seg
 307
 308 #define NBIO_BASE(seg) \
 309         NBIO_BASE_INNER(seg)
 310
 311 #define NBIO_SR(reg_name)\
 312                 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 313                                         regBIF_BX0_ ## reg_name
 314
 315 #define CTX ctx
 316 #define REG(reg_name) \
 317         (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 318
 319 static const struct bios_registers bios_regs = {
 320                 NBIO_SR(BIOS_SCRATCH_3),
 321                 NBIO_SR(BIOS_SCRATCH_6)
 322 };
 323
 324 #define clk_src_regs(index, pllid)\
 325 [index] = {\
 326         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 327 }
 328
 329 static const struct dce110_clk_src_regs clk_src_regs[] = {
 330         clk_src_regs(0, A),
 331         clk_src_regs(1, B),
 332         clk_src_regs(2, C),
 333         clk_src_regs(3, D),
 334         clk_src_regs(4, E)
 335 };
 336
 337 static const struct dce110_clk_src_shift cs_shift = {
 338                 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 339 };
 340
 341 static const struct dce110_clk_src_mask cs_mask = {
 342                 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 343 };
 344
 345 #define abm_regs(id)\
 346 [id] = {\
 347                 ABM_DCN32_REG_LIST(id)\
 348 }
 349
 350 static const struct dce_abm_registers abm_regs[] = {
 351                 abm_regs(0),
 352                 abm_regs(1),
 353                 abm_regs(2),
 354                 abm_regs(3),
 355 };
 356
 357 static const struct dce_abm_shift abm_shift = {
 358                 ABM_MASK_SH_LIST_DCN32(__SHIFT)
 359 };
 360
 361 static const struct dce_abm_mask abm_mask = {
 362                 ABM_MASK_SH_LIST_DCN32(_MASK)
 363 };
 364
 365 #define audio_regs(id)\
 366 [id] = {\
 367                 AUD_COMMON_REG_LIST(id)\
 368 }
 369
 370 static const struct dce_audio_registers audio_regs[] = {
 371         audio_regs(0),
 372         audio_regs(1),
 373         audio_regs(2),
 374         audio_regs(3),
 375         audio_regs(4)
 376 };
 377
 378 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 379                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 380                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 381                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 382
 383 static const struct dce_audio_shift audio_shift = {
 384                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 385 };
 386
 387 static const struct dce_audio_mask audio_mask = {
 388                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 389 };
 390
 391 #define vpg_regs(id)\
 392 [id] = {\
 393         VPG_DCN3_REG_LIST(id)\
 394 }
 395
 396 static const struct dcn30_vpg_registers vpg_regs[] = {
 397         vpg_regs(0),
 398         vpg_regs(1),
 399         vpg_regs(2),
 400         vpg_regs(3),
 401         vpg_regs(4),
 402         vpg_regs(5),
 403         vpg_regs(6),
 404         vpg_regs(7),
 405         vpg_regs(8),
 406         vpg_regs(9),
 407 };
 408
 409 static const struct dcn30_vpg_shift vpg_shift = {
 410         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 411 };
 412
 413 static const struct dcn30_vpg_mask vpg_mask = {
 414         DCN3_VPG_MASK_SH_LIST(_MASK)
 415 };
 416
 417 #define afmt_regs(id)\
 418 [id] = {\
 419         AFMT_DCN3_REG_LIST(id)\
 420 }
 421
 422 static const struct dcn30_afmt_registers afmt_regs[] = {
 423         afmt_regs(0),
 424         afmt_regs(1),
 425         afmt_regs(2),
 426         afmt_regs(3),
 427         afmt_regs(4),
 428         afmt_regs(5)
 429 };
 430
 431 static const struct dcn30_afmt_shift afmt_shift = {
 432         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 433 };
 434
 435 static const struct dcn30_afmt_mask afmt_mask = {
 436         DCN3_AFMT_MASK_SH_LIST(_MASK)
 437 };
 438
 439 #define apg_regs(id)\
 440 [id] = {\
 441         APG_DCN31_REG_LIST(id)\
 442 }
 443
 444 static const struct dcn31_apg_registers apg_regs[] = {
 445         apg_regs(0),
 446         apg_regs(1),
 447         apg_regs(2),
 448         apg_regs(3)
 449 };
 450
 451 static const struct dcn31_apg_shift apg_shift = {
 452         DCN31_APG_MASK_SH_LIST(__SHIFT)
 453 };
 454
 455 static const struct dcn31_apg_mask apg_mask = {
 456                 DCN31_APG_MASK_SH_LIST(_MASK)
 457 };
 458
 459 #define stream_enc_regs(id)\
 460 [id] = {\
 461         SE_DCN32_REG_LIST(id)\
 462 }
 463
 464 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 465         stream_enc_regs(0),
 466         stream_enc_regs(1),
 467         stream_enc_regs(2),
 468         stream_enc_regs(3),
 469         stream_enc_regs(4)
 470 };
 471
 472 static const struct dcn10_stream_encoder_shift se_shift = {
 473                 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 474 };
 475
 476 static const struct dcn10_stream_encoder_mask se_mask = {
 477                 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
 478 };
 479
 480
 481 #define aux_regs(id)\
 482 [id] = {\
 483         DCN2_AUX_REG_LIST(id)\
 484 }
 485
 486 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 487                 aux_regs(0),
 488                 aux_regs(1),
 489                 aux_regs(2),
 490                 aux_regs(3),
 491                 aux_regs(4)
 492 };
 493
 494 #define hpd_regs(id)\
 495 [id] = {\
 496         HPD_REG_LIST(id)\
 497 }
 498
 499 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 500                 hpd_regs(0),
 501                 hpd_regs(1),
 502                 hpd_regs(2),
 503                 hpd_regs(3),
 504                 hpd_regs(4)
 505 };
 506
 507 #define link_regs(id, phyid)\
 508 [id] = {\
 509         LE_DCN31_REG_LIST(id), \
 510         UNIPHY_DCN2_REG_LIST(phyid), \
 511         /*DPCS_DCN31_REG_LIST(id),*/ \
 512 }
 513
 514 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 515         link_regs(0, A),
 516         link_regs(1, B),
 517         link_regs(2, C),
 518         link_regs(3, D),
 519         link_regs(4, E)
 520 };
 521
 522 static const struct dcn10_link_enc_shift le_shift = {
 523         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 524         //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 525 };
 526
 527 static const struct dcn10_link_enc_mask le_mask = {
 528         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 529
 530         //DPCS_DCN31_MASK_SH_LIST(_MASK)
 531 };
 532
 533 #define hpo_dp_stream_encoder_reg_list(id)\
 534 [id] = {\
 535         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 536 }
 537
 538 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 539         hpo_dp_stream_encoder_reg_list(0),
 540         hpo_dp_stream_encoder_reg_list(1),
 541         hpo_dp_stream_encoder_reg_list(2),
 542         hpo_dp_stream_encoder_reg_list(3),
 543 };
 544
 545 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 546         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 547 };
 548
 549 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 550         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 551 };
 552
 553
 554 #define hpo_dp_link_encoder_reg_list(id)\
 555 [id] = {\
 556         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 557         /*DCN3_1_RDPCSTX_REG_LIST(0),*/\
 558         /*DCN3_1_RDPCSTX_REG_LIST(1),*/\
 559         /*DCN3_1_RDPCSTX_REG_LIST(2),*/\
 560         /*DCN3_1_RDPCSTX_REG_LIST(3),*/\
 561         /*DCN3_1_RDPCSTX_REG_LIST(4)*/\
 562 }
 563
 564 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 565         hpo_dp_link_encoder_reg_list(0),
 566         hpo_dp_link_encoder_reg_list(1),
 567 };
 568
 569 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 570         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 571 };
 572
 573 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 574         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 575 };
 576
 577 #define dpp_regs(id)\
 578 [id] = {\
 579         DPP_REG_LIST_DCN30_COMMON(id),\
 580 }
 581
 582 static const struct dcn3_dpp_registers dpp_regs[] = {
 583         dpp_regs(0),
 584         dpp_regs(1),
 585         dpp_regs(2),
 586         dpp_regs(3)
 587 };
 588
 589 static const struct dcn3_dpp_shift tf_shift = {
 590                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
 591 };
 592
 593 static const struct dcn3_dpp_mask tf_mask = {
 594                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
 595 };
 596
 597
 598 #define opp_regs(id)\
 599 [id] = {\
 600         OPP_REG_LIST_DCN30(id),\
 601 }
 602
 603 static const struct dcn20_opp_registers opp_regs[] = {
 604         opp_regs(0),
 605         opp_regs(1),
 606         opp_regs(2),
 607         opp_regs(3)
 608 };
 609
 610 static const struct dcn20_opp_shift opp_shift = {
 611         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 612 };
 613
 614 static const struct dcn20_opp_mask opp_mask = {
 615         OPP_MASK_SH_LIST_DCN20(_MASK)
 616 };
 617
 618 #define aux_engine_regs(id)\
 619 [id] = {\
 620         AUX_COMMON_REG_LIST0(id), \
 621         .AUXN_IMPCAL = 0, \
 622         .AUXP_IMPCAL = 0, \
 623         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 624 }
 625
 626 static const struct dce110_aux_registers aux_engine_regs[] = {
 627                 aux_engine_regs(0),
 628                 aux_engine_regs(1),
 629                 aux_engine_regs(2),
 630                 aux_engine_regs(3),
 631                 aux_engine_regs(4)
 632 };
 633
 634 static const struct dce110_aux_registers_shift aux_shift = {
 635         DCN_AUX_MASK_SH_LIST(__SHIFT)
 636 };
 637
 638 static const struct dce110_aux_registers_mask aux_mask = {
 639         DCN_AUX_MASK_SH_LIST(_MASK)
 640 };
 641
 642
 643 #define dwbc_regs_dcn3(id)\
 644 [id] = {\
 645         DWBC_COMMON_REG_LIST_DCN30(id),\
 646 }
 647
 648 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 649         dwbc_regs_dcn3(0),
 650 };
 651
 652 static const struct dcn30_dwbc_shift dwbc30_shift = {
 653         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 654 };
 655
 656 static const struct dcn30_dwbc_mask dwbc30_mask = {
 657         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 658 };
 659
 660 #define mcif_wb_regs_dcn3(id)\
 661 [id] = {\
 662         MCIF_WB_COMMON_REG_LIST_DCN32(id),\
 663 }
 664
 665 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 666         mcif_wb_regs_dcn3(0)
 667 };
 668
 669 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 670         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 671 };
 672
 673 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 674         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
 675 };
 676
 677 #define dsc_regsDCN20(id)\
 678 [id] = {\
 679         DSC_REG_LIST_DCN20(id)\
 680 }
 681
 682 static const struct dcn20_dsc_registers dsc_regs[] = {
 683         dsc_regsDCN20(0),
 684         dsc_regsDCN20(1),
 685         dsc_regsDCN20(2),
 686         dsc_regsDCN20(3)
 687 };
 688
 689 static const struct dcn20_dsc_shift dsc_shift = {
 690         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 691 };
 692
 693 static const struct dcn20_dsc_mask dsc_mask = {
 694         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 695 };
 696
 697 static const struct dcn30_mpc_registers mpc_regs = {
 698                 MPC_REG_LIST_DCN3_0(0),
 699                 MPC_REG_LIST_DCN3_0(1),
 700                 MPC_REG_LIST_DCN3_0(2),
 701                 MPC_REG_LIST_DCN3_0(3),
 702                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 703                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 704                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 705                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 706                 MPC_MCM_REG_LIST_DCN32(0),
 707                 MPC_MCM_REG_LIST_DCN32(1),
 708                 MPC_MCM_REG_LIST_DCN32(2),
 709                 MPC_MCM_REG_LIST_DCN32(3),
 710                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 711 };
 712
 713 static const struct dcn30_mpc_shift mpc_shift = {
 714         MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 715 };
 716
 717 static const struct dcn30_mpc_mask mpc_mask = {
 718         MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 719 };
 720
 721 #define optc_regs(id)\
 722 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
 723
 724 //#ifdef DIAGS_BUILD
 725 //static struct dcn_optc_registers optc_regs[] = {
 726 //#else
 727 static const struct dcn_optc_registers optc_regs[] = {
 728 //#endif
 729         optc_regs(0),
 730         optc_regs(1),
 731         optc_regs(2),
 732         optc_regs(3)
 733 };
 734
 735 static const struct dcn_optc_shift optc_shift = {
 736         OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 737 };
 738
 739 static const struct dcn_optc_mask optc_mask = {
 740         OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 741 };
 742
 743 #define hubp_regs(id)\
 744 [id] = {\
 745         HUBP_REG_LIST_DCN32(id)\
 746 }
 747
 748 static const struct dcn_hubp2_registers hubp_regs[] = {
 749                 hubp_regs(0),
 750                 hubp_regs(1),
 751                 hubp_regs(2),
 752                 hubp_regs(3)
 753 };
 754
 755
 756 static const struct dcn_hubp2_shift hubp_shift = {
 757                 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
 758 };
 759
 760 static const struct dcn_hubp2_mask hubp_mask = {
 761                 HUBP_MASK_SH_LIST_DCN32(_MASK)
 762 };
 763 static const struct dcn_hubbub_registers hubbub_reg = {
 764                 HUBBUB_REG_LIST_DCN32(0)
 765 };
 766
 767 static const struct dcn_hubbub_shift hubbub_shift = {
 768                 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
 769 };
 770
 771 static const struct dcn_hubbub_mask hubbub_mask = {
 772                 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
 773 };
 774
 775 static const struct dccg_registers dccg_regs = {
 776                 DCCG_REG_LIST_DCN32()
 777 };
 778
 779 static const struct dccg_shift dccg_shift = {
 780                 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
 781 };
 782
 783 static const struct dccg_mask dccg_mask = {
 784                 DCCG_MASK_SH_LIST_DCN32(_MASK)
 785 };
 786
 787
 788 #define SRII2(reg_name_pre, reg_name_post, id)\
 789         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 790                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 791                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 792
 793
 794 #define HWSEQ_DCN32_REG_LIST()\
 795         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 796         SR(DIO_MEM_PWR_CTRL), \
 797         SR(ODM_MEM_PWR_CTRL3), \
 798         SR(MMHUBBUB_MEM_PWR_CNTL), \
 799         SR(DCCG_GATE_DISABLE_CNTL), \
 800         SR(DCCG_GATE_DISABLE_CNTL2), \
 801         SR(DCFCLK_CNTL),\
 802         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 803         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 804         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 805         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 806         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 807         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 808         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 809         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 810         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 811         SR(MICROSECOND_TIME_BASE_DIV), \
 812         SR(MILLISECOND_TIME_BASE_DIV), \
 813         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 814         SR(RBBMIF_TIMEOUT_DIS), \
 815         SR(RBBMIF_TIMEOUT_DIS_2), \
 816         SR(DCHUBBUB_CRC_CTRL), \
 817         SR(DPP_TOP0_DPP_CRC_CTRL), \
 818         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 819         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 820         SR(MPC_CRC_CTRL), \
 821         SR(MPC_CRC_RESULT_GB), \
 822         SR(MPC_CRC_RESULT_C), \
 823         SR(MPC_CRC_RESULT_AR), \
 824         SR(DOMAIN0_PG_CONFIG), \
 825         SR(DOMAIN1_PG_CONFIG), \
 826         SR(DOMAIN2_PG_CONFIG), \
 827         SR(DOMAIN3_PG_CONFIG), \
 828         SR(DOMAIN16_PG_CONFIG), \
 829         SR(DOMAIN17_PG_CONFIG), \
 830         SR(DOMAIN18_PG_CONFIG), \
 831         SR(DOMAIN19_PG_CONFIG), \
 832         SR(DOMAIN0_PG_STATUS), \
 833         SR(DOMAIN1_PG_STATUS), \
 834         SR(DOMAIN2_PG_STATUS), \
 835         SR(DOMAIN3_PG_STATUS), \
 836         SR(DOMAIN16_PG_STATUS), \
 837         SR(DOMAIN17_PG_STATUS), \
 838         SR(DOMAIN18_PG_STATUS), \
 839         SR(DOMAIN19_PG_STATUS), \
 840         SR(D1VGA_CONTROL), \
 841         SR(D2VGA_CONTROL), \
 842         SR(D3VGA_CONTROL), \
 843         SR(D4VGA_CONTROL), \
 844         SR(D5VGA_CONTROL), \
 845         SR(D6VGA_CONTROL), \
 846         SR(DC_IP_REQUEST_CNTL), \
 847         SR(AZALIA_AUDIO_DTO), \
 848         SR(AZALIA_CONTROLLER_CLOCK_GATING)
 849
 850 static const struct dce_hwseq_registers hwseq_reg = {
 851                 HWSEQ_DCN32_REG_LIST()
 852 };
 853
 854 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
 855         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 856         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 857         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 858         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 859         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 860         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 861         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 862         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 863         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 864         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 865         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 866         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 867         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 868         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 869         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 870         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 871         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 872         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 873         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 874         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 875         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 876         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 877         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 878         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 879         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 880         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 881         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 882         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 883         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 884         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 885         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 886         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 887
 888 static const struct dce_hwseq_shift hwseq_shift = {
 889                 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
 890 };
 891
 892 static const struct dce_hwseq_mask hwseq_mask = {
 893                 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
 894 };
 895 #define vmid_regs(id)\
 896 [id] = {\
 897                 DCN20_VMID_REG_LIST(id)\
 898 }
 899
 900 static const struct dcn_vmid_registers vmid_regs[] = {
 901         vmid_regs(0),
 902         vmid_regs(1),
 903         vmid_regs(2),
 904         vmid_regs(3),
 905         vmid_regs(4),
 906         vmid_regs(5),
 907         vmid_regs(6),
 908         vmid_regs(7),
 909         vmid_regs(8),
 910         vmid_regs(9),
 911         vmid_regs(10),
 912         vmid_regs(11),
 913         vmid_regs(12),
 914         vmid_regs(13),
 915         vmid_regs(14),
 916         vmid_regs(15)
 917 };
 918
 919 static const struct dcn20_vmid_shift vmid_shifts = {
 920                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 921 };
 922
 923 static const struct dcn20_vmid_mask vmid_masks = {
 924                 DCN20_VMID_MASK_SH_LIST(_MASK)
 925 };
 926
 927 static const struct resource_caps res_cap_dcn32 = {
 928         .num_timing_generator = 4,
 929         .num_opp = 4,
 930         .num_video_plane = 4,
 931         .num_audio = 5,
 932         .num_stream_encoder = 5,
 933         .num_hpo_dp_stream_encoder = 4,
 934         .num_hpo_dp_link_encoder = 2,
 935         .num_pll = 5,
 936         .num_dwb = 1,
 937         .num_ddc = 5,
 938         .num_vmid = 16,
 939         .num_mpc_3dlut = 4,
 940         .num_dsc = 4,
 941 };
 942
 943 static const struct dc_plane_cap plane_cap = {
 944         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 945         .blends_with_above = true,
 946         .blends_with_below = true,
 947         .per_pixel_alpha = true,
 948
 949         .pixel_format_support = {
 950                         .argb8888 = true,
 951                         .nv12 = true,
 952                         .fp16 = true,
 953                         .p010 = true,
 954                         .ayuv = false,
 955         },
 956
 957         .max_upscale_factor = {
 958                         .argb8888 = 16000,
 959                         .nv12 = 16000,
 960                         .fp16 = 16000
 961         },
 962
 963         // 6:1 downscaling ratio: 1000/6 = 166.666
 964         .max_downscale_factor = {
 965                         .argb8888 = 167,
 966                         .nv12 = 167,
 967                         .fp16 = 167
 968         },
 969         64,
 970         64
 971 };
 972
 973 static const struct dc_debug_options debug_defaults_drv = {
 974         .disable_dmcu = true,
 975         .force_abm_enable = false,
 976         .timing_trace = false,
 977         .clock_trace = true,
 978         .disable_pplib_clock_request = false,
 979         .disable_idle_power_optimizations = true,
 980         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 981         .force_single_disp_pipe_split = false,
 982         .disable_dcc = DCC_ENABLE,
 983         .vsr_support = true,
 984         .performance_trace = false,
 985         .max_downscale_src_width = 7680,/*upto 8K*/
 986         .disable_pplib_wm_range = false,
 987         .scl_reset_length10 = true,
 988         .sanity_checks = false,
 989         .underflow_assert_delay_us = 0xFFFFFFFF,
 990         .dwb_fi_phase = -1, // -1 = disable,
 991         .dmub_command_table = true,
 992         .enable_mem_low_power = {
 993                 .bits = {
 994                         .vga = false,
 995                         .i2c = false,
 996                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 997                         .dscl = false,
 998                         .cm = false,
 999                         .mpc = false,
1000                         .optc = true,
1001                 }
1002         },
1003         .use_max_lb = true,
1004         .force_disable_subvp = true
1005 };
1006
1007 static const struct dc_debug_options debug_defaults_diags = {
1008         .disable_dmcu = true,
1009         .force_abm_enable = false,
1010         .timing_trace = true,
1011         .clock_trace = true,
1012         .disable_dpp_power_gate = true,
1013         .disable_hubp_power_gate = true,
1014         .disable_dsc_power_gate = true,
1015         .disable_clock_gate = true,
1016         .disable_pplib_clock_request = true,
1017         .disable_pplib_wm_range = true,
1018         .disable_stutter = false,
1019         .scl_reset_length10 = true,
1020         .dwb_fi_phase = -1, // -1 = disable
1021         .dmub_command_table = true,
1022         .enable_tri_buf = true,
1023         .use_max_lb = true,
1024         .force_disable_subvp = true
1025 };
1026
1027 static struct dce_aux *dcn32_aux_engine_create(
1028         struct dc_context *ctx,
1029         uint32_t inst)
1030 {
1031         struct aux_engine_dce110 *aux_engine =
1032                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1033
1034         if (!aux_engine)
1035                 return NULL;
1036
1037         dce110_aux_engine_construct(aux_engine, ctx, inst,
1038                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1039                                     &aux_engine_regs[inst],
1040                                         &aux_mask,
1041                                         &aux_shift,
1042                                         ctx->dc->caps.extended_aux_timeout_support);
1043
1044         return &aux_engine->base;
1045 }
1046 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1047
1048 static const struct dce_i2c_registers i2c_hw_regs[] = {
1049                 i2c_inst_regs(1),
1050                 i2c_inst_regs(2),
1051                 i2c_inst_regs(3),
1052                 i2c_inst_regs(4),
1053                 i2c_inst_regs(5),
1054 };
1055
1056 static const struct dce_i2c_shift i2c_shifts = {
1057                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1058 };
1059
1060 static const struct dce_i2c_mask i2c_masks = {
1061                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1062 };
1063
1064 static struct dce_i2c_hw *dcn32_i2c_hw_create(
1065         struct dc_context *ctx,
1066         uint32_t inst)
1067 {
1068         struct dce_i2c_hw *dce_i2c_hw =
1069                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1070
1071         if (!dce_i2c_hw)
1072                 return NULL;
1073
1074         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1075                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1076
1077         return dce_i2c_hw;
1078 }
1079
1080 static struct clock_source *dcn32_clock_source_create(
1081                 struct dc_context *ctx,
1082                 struct dc_bios *bios,
1083                 enum clock_source_id id,
1084                 const struct dce110_clk_src_regs *regs,
1085                 bool dp_clk_src)
1086 {
1087         struct dce110_clk_src *clk_src =
1088                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1089
1090         if (!clk_src)
1091                 return NULL;
1092
1093         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1094                         regs, &cs_shift, &cs_mask)) {
1095                 clk_src->base.dp_clk_src = dp_clk_src;
1096                 return &clk_src->base;
1097         }
1098
1099         BREAK_TO_DEBUGGER();
1100         return NULL;
1101 }
1102
1103 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
1104 {
1105         int i;
1106
1107         struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
1108                                           GFP_KERNEL);
1109
1110         if (!hubbub2)
1111                 return NULL;
1112
1113         hubbub32_construct(hubbub2, ctx,
1114                         &hubbub_reg,
1115                         &hubbub_shift,
1116                         &hubbub_mask,
1117                         ctx->dc->dml.ip.det_buffer_size_kbytes,
1118                         ctx->dc->dml.ip.pixel_chunk_size_kbytes,
1119                         ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
1120
1121
1122         for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
1123                 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
1124
1125                 vmid->ctx = ctx;
1126
1127                 vmid->regs = &vmid_regs[i];
1128                 vmid->shifts = &vmid_shifts;
1129                 vmid->masks = &vmid_masks;
1130         }
1131
1132         return &hubbub2->base;
1133 }
1134
1135 static struct hubp *dcn32_hubp_create(
1136         struct dc_context *ctx,
1137         uint32_t inst)
1138 {
1139         struct dcn20_hubp *hubp2 =
1140                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1141
1142         if (!hubp2)
1143                 return NULL;
1144
1145         if (hubp32_construct(hubp2, ctx, inst,
1146                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1147                 return &hubp2->base;
1148
1149         BREAK_TO_DEBUGGER();
1150         kfree(hubp2);
1151         return NULL;
1152 }
1153
1154 static void dcn32_dpp_destroy(struct dpp **dpp)
1155 {
1156         kfree(TO_DCN30_DPP(*dpp));
1157         *dpp = NULL;
1158 }
1159
1160 static struct dpp *dcn32_dpp_create(
1161         struct dc_context *ctx,
1162         uint32_t inst)
1163 {
1164         struct dcn3_dpp *dpp3 =
1165                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1166
1167         if (!dpp3)
1168                 return NULL;
1169
1170         if (dpp32_construct(dpp3, ctx, inst,
1171                         &dpp_regs[inst], &tf_shift, &tf_mask))
1172                 return &dpp3->base;
1173
1174         BREAK_TO_DEBUGGER();
1175         kfree(dpp3);
1176         return NULL;
1177 }
1178
1179 static struct mpc *dcn32_mpc_create(
1180                 struct dc_context *ctx,
1181                 int num_mpcc,
1182                 int num_rmu)
1183 {
1184         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1185                                           GFP_KERNEL);
1186
1187         if (!mpc30)
1188                 return NULL;
1189
1190         dcn32_mpc_construct(mpc30, ctx,
1191                         &mpc_regs,
1192                         &mpc_shift,
1193                         &mpc_mask,
1194                         num_mpcc,
1195                         num_rmu);
1196
1197         return &mpc30->base;
1198 }
1199
1200 static struct output_pixel_processor *dcn32_opp_create(
1201         struct dc_context *ctx, uint32_t inst)
1202 {
1203         struct dcn20_opp *opp2 =
1204                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1205
1206         if (!opp2) {
1207                 BREAK_TO_DEBUGGER();
1208                 return NULL;
1209         }
1210
1211         dcn20_opp_construct(opp2, ctx, inst,
1212                         &opp_regs[inst], &opp_shift, &opp_mask);
1213         return &opp2->base;
1214 }
1215
1216
1217 static struct timing_generator *dcn32_timing_generator_create(
1218                 struct dc_context *ctx,
1219                 uint32_t instance)
1220 {
1221         struct optc *tgn10 =
1222                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1223
1224         if (!tgn10)
1225                 return NULL;
1226
1227         tgn10->base.inst = instance;
1228         tgn10->base.ctx = ctx;
1229
1230         tgn10->tg_regs = &optc_regs[instance];
1231         tgn10->tg_shift = &optc_shift;
1232         tgn10->tg_mask = &optc_mask;
1233
1234         dcn32_timing_generator_init(tgn10);
1235
1236         return &tgn10->base;
1237 }
1238
1239 static const struct encoder_feature_support link_enc_feature = {
1240                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1241                 .max_hdmi_pixel_clock = 600000,
1242                 .hdmi_ycbcr420_supported = true,
1243                 .dp_ycbcr420_supported = true,
1244                 .fec_supported = true,
1245                 .flags.bits.IS_HBR2_CAPABLE = true,
1246                 .flags.bits.IS_HBR3_CAPABLE = true,
1247                 .flags.bits.IS_TPS3_CAPABLE = true,
1248                 .flags.bits.IS_TPS4_CAPABLE = true
1249 };
1250
1251 static struct link_encoder *dcn32_link_encoder_create(
1252         const struct encoder_init_data *enc_init_data)
1253 {
1254         struct dcn20_link_encoder *enc20 =
1255                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1256
1257         if (!enc20)
1258                 return NULL;
1259
1260         dcn32_link_encoder_construct(enc20,
1261                         enc_init_data,
1262                         &link_enc_feature,
1263                         &link_enc_regs[enc_init_data->transmitter],
1264                         &link_enc_aux_regs[enc_init_data->channel - 1],
1265                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1266                         &le_shift,
1267                         &le_mask);
1268
1269         return &enc20->enc10.base;
1270 }
1271
1272 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1273 {
1274         struct dcn31_panel_cntl *panel_cntl =
1275                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1276
1277         if (!panel_cntl)
1278                 return NULL;
1279
1280         dcn31_panel_cntl_construct(panel_cntl, init_data);
1281
1282         return &panel_cntl->base;
1283 }
1284
1285 static void read_dce_straps(
1286         struct dc_context *ctx,
1287         struct resource_straps *straps)
1288 {
1289         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1290                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1291
1292 }
1293
1294 static struct audio *dcn32_create_audio(
1295                 struct dc_context *ctx, unsigned int inst)
1296 {
1297         return dce_audio_create(ctx, inst,
1298                         &audio_regs[inst], &audio_shift, &audio_mask);
1299 }
1300
1301 static struct vpg *dcn32_vpg_create(
1302         struct dc_context *ctx,
1303         uint32_t inst)
1304 {
1305         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1306
1307         if (!vpg3)
1308                 return NULL;
1309
1310         vpg3_construct(vpg3, ctx, inst,
1311                         &vpg_regs[inst],
1312                         &vpg_shift,
1313                         &vpg_mask);
1314
1315         return &vpg3->base;
1316 }
1317
1318 static struct afmt *dcn32_afmt_create(
1319         struct dc_context *ctx,
1320         uint32_t inst)
1321 {
1322         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1323
1324         if (!afmt3)
1325                 return NULL;
1326
1327         afmt3_construct(afmt3, ctx, inst,
1328                         &afmt_regs[inst],
1329                         &afmt_shift,
1330                         &afmt_mask);
1331
1332         return &afmt3->base;
1333 }
1334
1335 static struct apg *dcn31_apg_create(
1336         struct dc_context *ctx,
1337         uint32_t inst)
1338 {
1339         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1340
1341         if (!apg31)
1342                 return NULL;
1343
1344         apg31_construct(apg31, ctx, inst,
1345                         &apg_regs[inst],
1346                         &apg_shift,
1347                         &apg_mask);
1348
1349         return &apg31->base;
1350 }
1351
1352 static struct stream_encoder *dcn32_stream_encoder_create(
1353         enum engine_id eng_id,
1354         struct dc_context *ctx)
1355 {
1356         struct dcn10_stream_encoder *enc1;
1357         struct vpg *vpg;
1358         struct afmt *afmt;
1359         int vpg_inst;
1360         int afmt_inst;
1361
1362         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1363         if (eng_id <= ENGINE_ID_DIGF) {
1364                 vpg_inst = eng_id;
1365                 afmt_inst = eng_id;
1366         } else
1367                 return NULL;
1368
1369         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1370         vpg = dcn32_vpg_create(ctx, vpg_inst);
1371         afmt = dcn32_afmt_create(ctx, afmt_inst);
1372
1373         if (!enc1 || !vpg || !afmt) {
1374                 kfree(enc1);
1375                 kfree(vpg);
1376                 kfree(afmt);
1377                 return NULL;
1378         }
1379
1380         dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1381                                         eng_id, vpg, afmt,
1382                                         &stream_enc_regs[eng_id],
1383                                         &se_shift, &se_mask);
1384
1385         return &enc1->base;
1386 }
1387
1388 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1389         enum engine_id eng_id,
1390         struct dc_context *ctx)
1391 {
1392         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1393         struct vpg *vpg;
1394         struct apg *apg;
1395         uint32_t hpo_dp_inst;
1396         uint32_t vpg_inst;
1397         uint32_t apg_inst;
1398
1399         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1400         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1401
1402         /* Mapping of VPG register blocks to HPO DP block instance:
1403          * VPG[6] -> HPO_DP[0]
1404          * VPG[7] -> HPO_DP[1]
1405          * VPG[8] -> HPO_DP[2]
1406          * VPG[9] -> HPO_DP[3]
1407          */
1408         vpg_inst = hpo_dp_inst + 6;
1409
1410         /* Mapping of APG register blocks to HPO DP block instance:
1411          * APG[0] -> HPO_DP[0]
1412          * APG[1] -> HPO_DP[1]
1413          * APG[2] -> HPO_DP[2]
1414          * APG[3] -> HPO_DP[3]
1415          */
1416         apg_inst = hpo_dp_inst;
1417
1418         /* allocate HPO stream encoder and create VPG sub-block */
1419         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1420         vpg = dcn32_vpg_create(ctx, vpg_inst);
1421         apg = dcn31_apg_create(ctx, apg_inst);
1422
1423         if (!hpo_dp_enc31 || !vpg || !apg) {
1424                 kfree(hpo_dp_enc31);
1425                 kfree(vpg);
1426                 kfree(apg);
1427                 return NULL;
1428         }
1429
1430         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1431                                         hpo_dp_inst, eng_id, vpg, apg,
1432                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1433                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1434
1435         return &hpo_dp_enc31->base;
1436 }
1437
1438 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1439         uint8_t inst,
1440         struct dc_context *ctx)
1441 {
1442         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1443
1444         /* allocate HPO link encoder */
1445         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1446
1447         hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1448                                         &hpo_dp_link_enc_regs[inst],
1449                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1450
1451         return &hpo_dp_enc31->base;
1452 }
1453
1454 static struct dce_hwseq *dcn32_hwseq_create(
1455         struct dc_context *ctx)
1456 {
1457         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1458
1459         if (hws) {
1460                 hws->ctx = ctx;
1461                 hws->regs = &hwseq_reg;
1462                 hws->shifts = &hwseq_shift;
1463                 hws->masks = &hwseq_mask;
1464         }
1465         return hws;
1466 }
1467 static const struct resource_create_funcs res_create_funcs = {
1468         .read_dce_straps = read_dce_straps,
1469         .create_audio = dcn32_create_audio,
1470         .create_stream_encoder = dcn32_stream_encoder_create,
1471         .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1472         .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1473         .create_hwseq = dcn32_hwseq_create,
1474 };
1475
1476 static const struct resource_create_funcs res_create_maximus_funcs = {
1477         .read_dce_straps = NULL,
1478         .create_audio = NULL,
1479         .create_stream_encoder = NULL,
1480         .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1481         .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1482         .create_hwseq = dcn32_hwseq_create,
1483 };
1484
1485 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1486 {
1487         unsigned int i;
1488
1489         for (i = 0; i < pool->base.stream_enc_count; i++) {
1490                 if (pool->base.stream_enc[i] != NULL) {
1491                         if (pool->base.stream_enc[i]->vpg != NULL) {
1492                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1493                                 pool->base.stream_enc[i]->vpg = NULL;
1494                         }
1495                         if (pool->base.stream_enc[i]->afmt != NULL) {
1496                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1497                                 pool->base.stream_enc[i]->afmt = NULL;
1498                         }
1499                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1500                         pool->base.stream_enc[i] = NULL;
1501                 }
1502         }
1503
1504         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1505                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1506                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1507                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1508                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1509                         }
1510                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1511                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1512                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1513                         }
1514                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1515                         pool->base.hpo_dp_stream_enc[i] = NULL;
1516                 }
1517         }
1518
1519         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1520                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1521                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1522                         pool->base.hpo_dp_link_enc[i] = NULL;
1523                 }
1524         }
1525
1526         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1527                 if (pool->base.dscs[i] != NULL)
1528                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1529         }
1530
1531         if (pool->base.mpc != NULL) {
1532                 kfree(TO_DCN20_MPC(pool->base.mpc));
1533                 pool->base.mpc = NULL;
1534         }
1535         if (pool->base.hubbub != NULL) {
1536                 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1537                 pool->base.hubbub = NULL;
1538         }
1539         for (i = 0; i < pool->base.pipe_count; i++) {
1540                 if (pool->base.dpps[i] != NULL)
1541                         dcn32_dpp_destroy(&pool->base.dpps[i]);
1542
1543                 if (pool->base.ipps[i] != NULL)
1544                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1545
1546                 if (pool->base.hubps[i] != NULL) {
1547                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1548                         pool->base.hubps[i] = NULL;
1549                 }
1550
1551                 if (pool->base.irqs != NULL) {
1552                         dal_irq_service_destroy(&pool->base.irqs);
1553                 }
1554         }
1555
1556         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1557                 if (pool->base.engines[i] != NULL)
1558                         dce110_engine_destroy(&pool->base.engines[i]);
1559                 if (pool->base.hw_i2cs[i] != NULL) {
1560                         kfree(pool->base.hw_i2cs[i]);
1561                         pool->base.hw_i2cs[i] = NULL;
1562                 }
1563                 if (pool->base.sw_i2cs[i] != NULL) {
1564                         kfree(pool->base.sw_i2cs[i]);
1565                         pool->base.sw_i2cs[i] = NULL;
1566                 }
1567         }
1568
1569         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1570                 if (pool->base.opps[i] != NULL)
1571                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1572         }
1573
1574         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1575                 if (pool->base.timing_generators[i] != NULL)    {
1576                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1577                         pool->base.timing_generators[i] = NULL;
1578                 }
1579         }
1580
1581         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1582                 if (pool->base.dwbc[i] != NULL) {
1583                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1584                         pool->base.dwbc[i] = NULL;
1585                 }
1586                 if (pool->base.mcif_wb[i] != NULL) {
1587                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1588                         pool->base.mcif_wb[i] = NULL;
1589                 }
1590         }
1591
1592         for (i = 0; i < pool->base.audio_count; i++) {
1593                 if (pool->base.audios[i])
1594                         dce_aud_destroy(&pool->base.audios[i]);
1595         }
1596
1597         for (i = 0; i < pool->base.clk_src_count; i++) {
1598                 if (pool->base.clock_sources[i] != NULL) {
1599                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1600                         pool->base.clock_sources[i] = NULL;
1601                 }
1602         }
1603
1604         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1605                 if (pool->base.mpc_lut[i] != NULL) {
1606                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1607                         pool->base.mpc_lut[i] = NULL;
1608                 }
1609                 if (pool->base.mpc_shaper[i] != NULL) {
1610                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1611                         pool->base.mpc_shaper[i] = NULL;
1612                 }
1613         }
1614
1615         if (pool->base.dp_clock_source != NULL) {
1616                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1617                 pool->base.dp_clock_source = NULL;
1618         }
1619
1620         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1621                 if (pool->base.multiple_abms[i] != NULL)
1622                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1623         }
1624
1625         if (pool->base.psr != NULL)
1626                 dmub_psr_destroy(&pool->base.psr);
1627
1628         if (pool->base.dccg != NULL)
1629                 dcn_dccg_destroy(&pool->base.dccg);
1630
1631         if (pool->base.oem_device != NULL)
1632                 dal_ddc_service_destroy(&pool->base.oem_device);
1633 }
1634
1635
1636 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1637 {
1638         int i;
1639         uint32_t dwb_count = pool->res_cap->num_dwb;
1640
1641         for (i = 0; i < dwb_count; i++) {
1642                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1643                                                     GFP_KERNEL);
1644
1645                 if (!dwbc30) {
1646                         dm_error("DC: failed to create dwbc30!\n");
1647                         return false;
1648                 }
1649
1650                 dcn30_dwbc_construct(dwbc30, ctx,
1651                                 &dwbc30_regs[i],
1652                                 &dwbc30_shift,
1653                                 &dwbc30_mask,
1654                                 i);
1655
1656                 pool->dwbc[i] = &dwbc30->base;
1657         }
1658         return true;
1659 }
1660
1661 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1662 {
1663         int i;
1664         uint32_t dwb_count = pool->res_cap->num_dwb;
1665
1666         for (i = 0; i < dwb_count; i++) {
1667                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1668                                                     GFP_KERNEL);
1669
1670                 if (!mcif_wb30) {
1671                         dm_error("DC: failed to create mcif_wb30!\n");
1672                         return false;
1673                 }
1674
1675                 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1676                                 &mcif_wb30_regs[i],
1677                                 &mcif_wb30_shift,
1678                                 &mcif_wb30_mask,
1679                                 i);
1680
1681                 pool->mcif_wb[i] = &mcif_wb30->base;
1682         }
1683         return true;
1684 }
1685
1686 static struct display_stream_compressor *dcn32_dsc_create(
1687         struct dc_context *ctx, uint32_t inst)
1688 {
1689         struct dcn20_dsc *dsc =
1690                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1691
1692         if (!dsc) {
1693                 BREAK_TO_DEBUGGER();
1694                 return NULL;
1695         }
1696
1697         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1698
1699         dsc->max_image_width = 6016;
1700
1701         return &dsc->base;
1702 }
1703
1704 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1705 {
1706         struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1707
1708         dcn32_resource_destruct(dcn32_pool);
1709         kfree(dcn32_pool);
1710         *pool = NULL;
1711 }
1712
1713 bool dcn32_acquire_post_bldn_3dlut(
1714                 struct resource_context *res_ctx,
1715                 const struct resource_pool *pool,
1716                 int mpcc_id,
1717                 struct dc_3dlut **lut,
1718                 struct dc_transfer_func **shaper)
1719 {
1720         bool ret = false;
1721         union dc_3dlut_state *state;
1722
1723         ASSERT(*lut == NULL && *shaper == NULL);
1724         *lut = NULL;
1725         *shaper = NULL;
1726
1727         if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1728                 *lut = pool->mpc_lut[mpcc_id];
1729                 *shaper = pool->mpc_shaper[mpcc_id];
1730                 state = &pool->mpc_lut[mpcc_id]->state;
1731                 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1732                 ret = true;
1733         }
1734         return ret;
1735 }
1736
1737 bool dcn32_release_post_bldn_3dlut(
1738                 struct resource_context *res_ctx,
1739                 const struct resource_pool *pool,
1740                 struct dc_3dlut **lut,
1741                 struct dc_transfer_func **shaper)
1742 {
1743         int i;
1744         bool ret = false;
1745
1746         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1747                 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1748                         res_ctx->is_mpc_3dlut_acquired[i] = false;
1749                         pool->mpc_lut[i]->state.raw = 0;
1750                         *lut = NULL;
1751                         *shaper = NULL;
1752                         ret = true;
1753                         break;
1754                 }
1755         }
1756         return ret;
1757 }
1758
1759 /**
1760  ********************************************************************************************
1761  * dcn32_get_num_free_pipes: Calculate number of free pipes
1762  *
1763  * This function assumes that a "used" pipe is a pipe that has
1764  * both a stream and a plane assigned to it.
1765  *
1766  * @param [in] dc: current dc state
1767  * @param [in] context: new dc state
1768  *
1769  * @return: Number of free pipes available in the context
1770  *
1771  ********************************************************************************************
1772  */
1773 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
1774 {
1775         unsigned int i;
1776         unsigned int free_pipes = 0;
1777         unsigned int num_pipes = 0;
1778
1779         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1780                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1781
1782                 if (pipe->stream && !pipe->top_pipe) {
1783                         while (pipe) {
1784                                 num_pipes++;
1785                                 pipe = pipe->bottom_pipe;
1786                         }
1787                 }
1788         }
1789
1790         free_pipes = dc->res_pool->pipe_count - num_pipes;
1791         return free_pipes;
1792 }
1793
1794 /**
1795  ********************************************************************************************
1796  * dcn32_assign_subvp_pipe: Function to decide which pipe will use Sub-VP.
1797  *
1798  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
1799  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
1800  * we are forcing SubVP P-State switching on the current config.
1801  *
1802  * The number of pipes used for the chosen surface must be less than or equal to the
1803  * number of free pipes available.
1804  *
1805  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
1806  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
1807  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
1808  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
1809  *
1810  * @param [in] dc: current dc state
1811  * @param [in] context: new dc state
1812  * @param [out] index: dc pipe index for the pipe chosen to have phantom pipes assigned
1813  *
1814  * @return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
1815  *
1816  ********************************************************************************************
1817  */
1818
1819 static bool dcn32_assign_subvp_pipe(struct dc *dc,
1820                 struct dc_state *context,
1821                 unsigned int *index)
1822 {
1823         unsigned int i, pipe_idx;
1824         unsigned int max_frame_time = 0;
1825         bool valid_assignment_found = false;
1826         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
1827         bool current_assignment_freesync = false;
1828
1829         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1830                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1831                 unsigned int num_pipes = 0;
1832
1833                 if (!pipe->stream)
1834                         continue;
1835
1836                 if (pipe->plane_state && !pipe->top_pipe &&
1837                                 pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1838                         while (pipe) {
1839                                 num_pipes++;
1840                                 pipe = pipe->bottom_pipe;
1841                         }
1842
1843                         pipe = &context->res_ctx.pipe_ctx[i];
1844                         if (num_pipes <= free_pipes) {
1845                                 struct dc_stream_state *stream = pipe->stream;
1846                                 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
1847                                                 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
1848                                 if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
1849                                         *index = i;
1850                                         max_frame_time = frame_us;
1851                                         valid_assignment_found = true;
1852                                         current_assignment_freesync = false;
1853                                 /* For the 2-Freesync display case, still choose the one with the
1854                              * longest frame time
1855                              */
1856                                 } else if (stream->ignore_msa_timing_param && (!valid_assignment_found ||
1857                                                 (current_assignment_freesync && frame_us > max_frame_time))) {
1858                                         *index = i;
1859                                         valid_assignment_found = true;
1860                                         current_assignment_freesync = true;
1861                                 }
1862                         }
1863                 }
1864                 pipe_idx++;
1865         }
1866         return valid_assignment_found;
1867 }
1868
1869 /**
1870  * ***************************************************************************************
1871  * dcn32_enough_pipes_for_subvp: Function to check if there are "enough" pipes for SubVP.
1872  *
1873  * This function returns true if there are enough free pipes
1874  * to create the required phantom pipes for any given stream
1875  * (that does not already have phantom pipe assigned).
1876  *
1877  * e.g. For a 2 stream config where the first stream uses one
1878  * pipe and the second stream uses 2 pipes (i.e. pipe split),
1879  * this function will return true because there is 1 remaining
1880  * pipe which can be used as the phantom pipe for the non pipe
1881  * split pipe.
1882  *
1883  * @param [in] dc: current dc state
1884  * @param [in] context: new dc state
1885  *
1886  * @return: True if there are enough free pipes to assign phantom pipes to at least one
1887  *          stream that does not already have phantom pipes assigned. Otherwise false.
1888  *
1889  * ***************************************************************************************
1890  */
1891 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
1892 {
1893         unsigned int i, split_cnt, free_pipes;
1894         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
1895         bool subvp_possible = false;
1896
1897         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1898                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1899
1900                 // Find the minimum pipe split count for non SubVP pipes
1901                 if (pipe->stream && !pipe->top_pipe &&
1902                                 pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1903                         split_cnt = 0;
1904                         while (pipe) {
1905                                 split_cnt++;
1906                                 pipe = pipe->bottom_pipe;
1907                         }
1908
1909                         if (split_cnt < min_pipe_split)
1910                                 min_pipe_split = split_cnt;
1911                 }
1912         }
1913
1914         free_pipes = dcn32_get_num_free_pipes(dc, context);
1915
1916         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
1917         // should not equal to the pipe_count)
1918         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
1919                 subvp_possible = true;
1920
1921         return subvp_possible;
1922 }
1923
1924 static void dcn32_enable_phantom_plane(struct dc *dc,
1925                 struct dc_state *context,
1926                 struct dc_stream_state *phantom_stream,
1927                 unsigned int dc_pipe_idx)
1928 {
1929         struct dc_plane_state *phantom_plane = NULL;
1930         struct dc_plane_state *prev_phantom_plane = NULL;
1931         struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1932
1933         while (curr_pipe) {
1934                 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1935                         phantom_plane = prev_phantom_plane;
1936                 else
1937                         phantom_plane = dc_create_plane_state(dc);
1938
1939                 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1940                 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1941                                 sizeof(phantom_plane->scaling_quality));
1942                 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1943                 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1944                 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1945                 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1946                                 sizeof(phantom_plane->plane_size));
1947                 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1948                                 sizeof(phantom_plane->tiling_info));
1949                 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1950                 phantom_plane->format = curr_pipe->plane_state->format;
1951                 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1952                 phantom_plane->visible = curr_pipe->plane_state->visible;
1953
1954                 /* Shadow pipe has small viewport. */
1955                 phantom_plane->clip_rect.y = 0;
1956                 phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable;
1957
1958                 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context);
1959
1960                 curr_pipe = curr_pipe->bottom_pipe;
1961                 prev_phantom_plane = phantom_plane;
1962         }
1963 }
1964
1965 /**
1966  * ***************************************************************************************
1967  * dcn32_set_phantom_stream_timing: Set timing params for the phantom stream
1968  *
1969  * Set timing params of the phantom stream based on calculated output from DML.
1970  * This function first gets the DML pipe index using the DC pipe index, then
1971  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
1972  * lines required for SubVP MCLK switching and assigns to the phantom stream
1973  * accordingly.
1974  *
1975  * - The number of SubVP lines calculated in DML does not take into account
1976  * FW processing delays and required pstate allow width, so we must include
1977  * that separately.
1978  *
1979  * - Set phantom backporch = vstartup of main pipe
1980  *
1981  * @param [in] dc: current dc state
1982  * @param [in] context: new dc state
1983  * @param [in] ref_pipe: Main pipe for the phantom stream
1984  * @param [in] pipes: DML pipe params
1985  * @param [in] pipe_cnt: number of DML pipes
1986  * @param [in] dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
1987  *
1988  * @return: void
1989  *
1990  * ***************************************************************************************
1991  */
1992 static void dcn32_set_phantom_stream_timing(struct dc *dc,
1993                 struct dc_state *context,
1994                 struct pipe_ctx *ref_pipe,
1995                 struct dc_stream_state *phantom_stream,
1996                 display_e2e_pipe_params_st *pipes,
1997                 unsigned int pipe_cnt,
1998                 unsigned int dc_pipe_idx)
1999 {
2000         unsigned int i, pipe_idx;
2001         struct pipe_ctx *pipe;
2002         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
2003         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
2004         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2005         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
2006
2007         // Find DML pipe index (pipe_idx) using dc_pipe_idx
2008         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2009                 pipe = &context->res_ctx.pipe_ctx[i];
2010
2011                 if (!pipe->stream)
2012                         continue;
2013
2014                 if (i == dc_pipe_idx)
2015                         break;
2016
2017                 pipe_idx++;
2018         }
2019
2020         // Calculate lines required for pstate allow width and FW processing delays
2021         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
2022                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
2023                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
2024                         (double)ref_pipe->stream->timing.h_total;
2025
2026         // Update clks_cfg for calling into recalculate
2027         pipes[0].clks_cfg.voltage = vlevel;
2028         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2029         pipes[0].clks_cfg.socclk_mhz = socclk;
2030
2031         // DML calculation for MALL region doesn't take into account FW delay
2032         // and required pstate allow width for multi-display cases
2033         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
2034                                 pstate_width_fw_delay_lines;
2035
2036         // For backporch of phantom pipe, use vstartup of the main pipe
2037         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2038
2039         phantom_stream->dst.y = 0;
2040         phantom_stream->dst.height = phantom_vactive;
2041         phantom_stream->src.y = 0;
2042         phantom_stream->src.height = phantom_vactive;
2043
2044         phantom_stream->timing.v_addressable = phantom_vactive;
2045         phantom_stream->timing.v_front_porch = 1;
2046         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
2047                                                 phantom_stream->timing.v_front_porch +
2048                                                 phantom_stream->timing.v_sync_width +
2049                                                 phantom_bp;
2050 }
2051
2052 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
2053                 struct dc_state *context,
2054                 display_e2e_pipe_params_st *pipes,
2055                 unsigned int pipe_cnt,
2056                 unsigned int dc_pipe_idx)
2057 {
2058         struct dc_stream_state *phantom_stream = NULL;
2059         struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
2060
2061         phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink);
2062         phantom_stream->signal = SIGNAL_TYPE_VIRTUAL;
2063         phantom_stream->dpms_off = true;
2064         phantom_stream->mall_stream_config.type = SUBVP_PHANTOM;
2065         phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream;
2066         ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN;
2067         ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream;
2068
2069         /* stream has limited viewport and small timing */
2070         memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
2071         memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
2072         memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
2073         dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
2074
2075         dc_add_stream_to_ctx(dc, context, phantom_stream);
2076         return phantom_stream;
2077 }
2078
2079 // return true if removed piped from ctx, false otherwise
2080 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context)
2081 {
2082         int i;
2083         bool removed_pipe = false;
2084
2085         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2086                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2087                 // build scaling params for phantom pipes
2088                 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
2089                         dc_rem_all_planes_for_stream(dc, pipe->stream, context);
2090                         dc_remove_stream_from_ctx(dc, context, pipe->stream);
2091                         removed_pipe = true;
2092                 }
2093
2094                 // Clear all phantom stream info
2095                 if (pipe->stream) {
2096                         pipe->stream->mall_stream_config.type = SUBVP_NONE;
2097                         pipe->stream->mall_stream_config.paired_stream = NULL;
2098                 }
2099         }
2100         return removed_pipe;
2101 }
2102
2103 /* TODO: Input to this function should indicate which pipe indexes (or streams)
2104  * require a phantom pipe / stream
2105  */
2106 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
2107                 display_e2e_pipe_params_st *pipes,
2108                 unsigned int pipe_cnt,
2109                 unsigned int index)
2110 {
2111         struct dc_stream_state *phantom_stream = NULL;
2112         unsigned int i;
2113
2114         // The index of the DC pipe passed into this function is guarenteed to
2115         // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
2116         // already have phantom pipe assigned, etc.) by previous checks.
2117         phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
2118         dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
2119
2120         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2121                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2122
2123                 // Build scaling params for phantom pipes which were newly added.
2124                 // We determine which phantom pipes were added by comparing with
2125                 // the phantom stream.
2126                 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
2127                                 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
2128                         pipe->stream->use_dynamic_meta = false;
2129                         pipe->plane_state->flip_immediate = false;
2130                         if (!resource_build_scaling_params(pipe)) {
2131                                 // Log / remove phantom pipes since failed to build scaling params
2132                         }
2133                 }
2134         }
2135 }
2136
2137 static bool dcn32_split_stream_for_mpc_or_odm(
2138                 const struct dc *dc,
2139                 struct resource_context *res_ctx,
2140                 struct pipe_ctx *pri_pipe,
2141                 struct pipe_ctx *sec_pipe,
2142                 bool odm)
2143 {
2144         int pipe_idx = sec_pipe->pipe_idx;
2145         const struct resource_pool *pool = dc->res_pool;
2146
2147         if (pri_pipe->plane_state) {
2148                 /* ODM + window MPO, where MPO window is on left half only */
2149                 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
2150                                 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2)
2151                         return true;
2152
2153                 /* ODM + window MPO, where MPO window is on right half only */
2154                 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.width/2)
2155                         return true;
2156         }
2157
2158         *sec_pipe = *pri_pipe;
2159
2160         sec_pipe->pipe_idx = pipe_idx;
2161         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
2162         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
2163         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
2164         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
2165         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
2166         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
2167         sec_pipe->stream_res.dsc = NULL;
2168         if (odm) {
2169                 if (pri_pipe->next_odm_pipe) {
2170                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
2171                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
2172                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
2173                 }
2174                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
2175                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
2176                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
2177                 }
2178                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
2179                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
2180                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
2181                 }
2182                 pri_pipe->next_odm_pipe = sec_pipe;
2183                 sec_pipe->prev_odm_pipe = pri_pipe;
2184                 ASSERT(sec_pipe->top_pipe == NULL);
2185
2186                 if (!sec_pipe->top_pipe)
2187                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
2188                 else
2189                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
2190                 if (sec_pipe->stream->timing.flags.DSC == 1) {
2191                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
2192                         ASSERT(sec_pipe->stream_res.dsc);
2193                         if (sec_pipe->stream_res.dsc == NULL)
2194                                 return false;
2195                 }
2196         } else {
2197                 if (pri_pipe->bottom_pipe) {
2198                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
2199                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
2200                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
2201                 }
2202                 pri_pipe->bottom_pipe = sec_pipe;
2203                 sec_pipe->top_pipe = pri_pipe;
2204
2205                 ASSERT(pri_pipe->plane_state);
2206         }
2207
2208         return true;
2209 }
2210
2211 static struct pipe_ctx *dcn32_find_split_pipe(
2212                 struct dc *dc,
2213                 struct dc_state *context,
2214                 int old_index)
2215 {
2216         struct pipe_ctx *pipe = NULL;
2217         int i;
2218
2219         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
2220                 pipe = &context->res_ctx.pipe_ctx[old_index];
2221                 pipe->pipe_idx = old_index;
2222         }
2223
2224         if (!pipe)
2225                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
2226                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
2227                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
2228                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
2229                                         pipe = &context->res_ctx.pipe_ctx[i];
2230                                         pipe->pipe_idx = i;
2231                                         break;
2232                                 }
2233                         }
2234                 }
2235
2236         /*
2237          * May need to fix pipes getting tossed from 1 opp to another on flip
2238          * Add for debugging transient underflow during topology updates:
2239          * ASSERT(pipe);
2240          */
2241         if (!pipe)
2242                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
2243                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
2244                                 pipe = &context->res_ctx.pipe_ctx[i];
2245                                 pipe->pipe_idx = i;
2246                                 break;
2247                         }
2248                 }
2249
2250         return pipe;
2251 }
2252
2253
2254 /**
2255  * ***************************************************************************************
2256  * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable
2257  *
2258  * High level algorithm:
2259  * 1. Find longest microschedule length (in us) between the two SubVP pipes
2260  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
2261  * pipes still allows for the maximum microschedule to fit in the active
2262  * region for both pipes.
2263  *
2264  * @param [in] dc: current dc state
2265  * @param [in] context: new dc state
2266  *
2267  * @return: bool - True if the SubVP + SubVP config is schedulable, false otherwise
2268  *
2269  * ***************************************************************************************
2270  */
2271 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
2272 {
2273         struct pipe_ctx *subvp_pipes[2];
2274         struct dc_stream_state *phantom = NULL;
2275         uint32_t microschedule_lines = 0;
2276         uint32_t index = 0;
2277         uint32_t i;
2278         uint32_t max_microschedule_us = 0;
2279         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
2280
2281         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2282                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2283                 uint32_t time_us = 0;
2284
2285                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
2286                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
2287                  */
2288                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
2289                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
2290                         phantom = pipe->stream->mall_stream_config.paired_stream;
2291                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
2292                                         phantom->timing.v_addressable;
2293
2294                         // Round up when calculating microschedule time (+ 1 at the end)
2295                         time_us = (microschedule_lines * phantom->timing.h_total) /
2296                                         (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
2297                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
2298                                                 dc->caps.subvp_fw_processing_delay_us + 1;
2299                         if (time_us > max_microschedule_us)
2300                                 max_microschedule_us = time_us;
2301
2302                         subvp_pipes[index] = pipe;
2303                         index++;
2304
2305                         // Maximum 2 SubVP pipes
2306                         if (index == 2)
2307                                 break;
2308                 }
2309         }
2310         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
2311                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2312         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
2313                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2314         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
2315                         subvp_pipes[0]->stream->timing.h_total) /
2316                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2317         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
2318                         subvp_pipes[1]->stream->timing.h_total) /
2319                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2320
2321         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
2322                         (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
2323                 return true;
2324
2325         return false;
2326 }
2327
2328 /**
2329  * ***************************************************************************************
2330  * subvp_drr_schedulable: Determine if SubVP + DRR config is schedulable
2331  *
2332  * High level algorithm:
2333  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
2334  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
2335  * (the margin is equal to the MALL region + DRR margin (500us))
2336  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
2337  * then report the configuration as supported
2338  *
2339  * @param [in] dc: current dc state
2340  * @param [in] context: new dc state
2341  * @param [in] drr_pipe: DRR pipe_ctx for the SubVP + DRR config
2342  *
2343  * @return: bool - True if the SubVP + DRR config is schedulable, false otherwise
2344  *
2345  * ***************************************************************************************
2346  */
2347 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
2348 {
2349         bool schedulable = false;
2350         uint32_t i;
2351         struct pipe_ctx *pipe = NULL;
2352         struct dc_crtc_timing *main_timing = NULL;
2353         struct dc_crtc_timing *phantom_timing = NULL;
2354         struct dc_crtc_timing *drr_timing = NULL;
2355         int16_t prefetch_us = 0;
2356         int16_t mall_region_us = 0;
2357         int16_t drr_frame_us = 0;       // nominal frame time
2358         int16_t subvp_active_us = 0;
2359         int16_t stretched_drr_us = 0;
2360         int16_t drr_stretched_vblank_us = 0;
2361         int16_t max_vblank_mallregion = 0;
2362
2363         // Find SubVP pipe
2364         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2365                 pipe = &context->res_ctx.pipe_ctx[i];
2366
2367                 // We check for master pipe, but it shouldn't matter since we only need
2368                 // the pipe for timing info (stream should be same for any pipe splits)
2369                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
2370                         continue;
2371
2372                 // Find the SubVP pipe
2373                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
2374                         break;
2375         }
2376
2377         main_timing = &pipe->stream->timing;
2378         phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
2379         drr_timing = &drr_pipe->stream->timing;
2380         prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
2381                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
2382                         dc->caps.subvp_prefetch_end_to_mall_start_us;
2383         subvp_active_us = main_timing->v_addressable * main_timing->h_total /
2384                         (double)(main_timing->pix_clk_100hz * 100) * 1000000;
2385         drr_frame_us = drr_timing->v_total * drr_timing->h_total /
2386                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
2387         // P-State allow width and FW delays already included phantom_timing->v_addressable
2388         mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
2389                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
2390         stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
2391         drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
2392                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
2393         max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
2394
2395         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
2396          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
2397          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
2398          * and the max of (VBLANK blanking time, MALL region)).
2399          */
2400         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
2401                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
2402                 schedulable = true;
2403
2404         return schedulable;
2405 }
2406
2407 /**
2408  * ***************************************************************************************
2409  * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable
2410  *
2411  * High level algorithm:
2412  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
2413  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
2414  * then report the configuration as supported
2415  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
2416  *
2417  * @param [in] dc: current dc state
2418  * @param [in] context: new dc state
2419  *
2420  * @return: bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
2421  *
2422  * ***************************************************************************************
2423  */
2424 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
2425 {
2426         struct pipe_ctx *pipe = NULL;
2427         struct pipe_ctx *subvp_pipe = NULL;
2428         bool found = false;
2429         bool schedulable = false;
2430         uint32_t i = 0;
2431         uint8_t vblank_index = 0;
2432         uint16_t prefetch_us = 0;
2433         uint16_t mall_region_us = 0;
2434         uint16_t vblank_frame_us = 0;
2435         uint16_t subvp_active_us = 0;
2436         uint16_t vblank_blank_us = 0;
2437         uint16_t max_vblank_mallregion = 0;
2438         struct dc_crtc_timing *main_timing = NULL;
2439         struct dc_crtc_timing *phantom_timing = NULL;
2440         struct dc_crtc_timing *vblank_timing = NULL;
2441
2442         /* For SubVP + VBLANK/DRR cases, we assume there can only be
2443          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
2444          * is supported, it is either a single VBLANK case or two VBLANK
2445          * displays which are synchronized (in which case they have identical
2446          * timings).
2447          */
2448         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2449                 pipe = &context->res_ctx.pipe_ctx[i];
2450
2451                 // We check for master pipe, but it shouldn't matter since we only need
2452                 // the pipe for timing info (stream should be same for any pipe splits)
2453                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
2454                         continue;
2455
2456                 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
2457                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
2458                         vblank_index = i;
2459                         found = true;
2460                 }
2461
2462                 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
2463                         subvp_pipe = pipe;
2464         }
2465         // Use ignore_msa_timing_param flag to identify as DRR
2466         if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {
2467                 // SUBVP + DRR case
2468                 schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
2469         } else if (found) {
2470                 main_timing = &subvp_pipe->stream->timing;
2471                 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
2472                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
2473                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
2474                 // Also include the prefetch end to mallstart delay time
2475                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
2476                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
2477                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
2478                 // P-State allow width and FW delays already included phantom_timing->v_addressable
2479                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
2480                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
2481                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
2482                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
2483                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
2484                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
2485                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
2486                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
2487                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
2488
2489                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
2490                 // and the max of (VBLANK blanking time, MALL region)
2491                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
2492                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
2493                         schedulable = true;
2494         }
2495         return schedulable;
2496 }
2497
2498 /**
2499  * ********************************************************************************************
2500  * subvp_validate_static_schedulability: Check which SubVP case is calculated and handle
2501  * static analysis based on the case.
2502  *
2503  * Three cases:
2504  * 1. SubVP + SubVP
2505  * 2. SubVP + VBLANK (DRR checked internally)
2506  * 3. SubVP + VACTIVE (currently unsupported)
2507  *
2508  * @param [in] dc: current dc state
2509  * @param [in] context: new dc state
2510  * @param [in] vlevel: Voltage level calculated by DML
2511  *
2512  * @return: bool - True if statically schedulable, false otherwise
2513  *
2514  * ********************************************************************************************
2515  */
2516 static bool subvp_validate_static_schedulability(struct dc *dc,
2517                                 struct dc_state *context,
2518                                 int vlevel)
2519 {
2520         bool schedulable = true;        // true by default for single display case
2521         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
2522         uint32_t i, pipe_idx;
2523         uint8_t subvp_count = 0;
2524         uint8_t vactive_count = 0;
2525
2526         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2527                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2528
2529                 if (!pipe->stream)
2530                         continue;
2531
2532                 if (pipe->plane_state && !pipe->top_pipe &&
2533                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
2534                         subvp_count++;
2535
2536                 // Count how many planes are capable of VACTIVE switching (SubVP + VACTIVE unsupported)
2537                 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0) {
2538                         vactive_count++;
2539                 }
2540                 pipe_idx++;
2541         }
2542
2543         if (subvp_count == 2) {
2544                 // Static schedulability check for SubVP + SubVP case
2545                 schedulable = subvp_subvp_schedulable(dc, context);
2546         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
2547                 // Static schedulability check for SubVP + VBLANK case. Also handle the case where
2548                 // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
2549                 if (vactive_count > 0)
2550                         schedulable = false;
2551                 else
2552                         schedulable = subvp_vblank_schedulable(dc, context);
2553         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp) {
2554                 // SubVP + VACTIVE currently unsupported
2555                 schedulable = false;
2556         }
2557         return schedulable;
2558 }
2559
2560 static void dcn32_full_validate_bw_helper(struct dc *dc,
2561                 struct dc_state *context,
2562                 display_e2e_pipe_params_st *pipes,
2563                 int *vlevel,
2564                 int *split,
2565                 bool *merge,
2566                 int *pipe_cnt)
2567 {
2568         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
2569         unsigned int dc_pipe_idx = 0;
2570         bool found_supported_config = false;
2571         struct pipe_ctx *pipe = NULL;
2572         uint32_t non_subvp_pipes = 0;
2573         bool drr_pipe_found = false;
2574         uint32_t drr_pipe_index = 0;
2575         uint32_t i = 0;
2576
2577         /*
2578          * DML favors voltage over p-state, but we're more interested in
2579          * supporting p-state over voltage. We can't support p-state in
2580          * prefetch mode > 0 so try capping the prefetch mode to start.
2581          */
2582         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2583                         dm_prefetch_support_uclk_fclk_and_stutter;
2584         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
2585         /* This may adjust vlevel and maxMpcComb */
2586         if (*vlevel < context->bw_ctx.dml.soc.num_states)
2587                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
2588
2589         /* Conditions for setting up phantom pipes for SubVP:
2590          * 1. Not force disable SubVP
2591          * 2. Full update (i.e. !fast_validate)
2592          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
2593          * 4. Display configuration passes validation
2594          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
2595          */
2596         if (!dc->debug.force_disable_subvp && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
2597                         (*vlevel == context->bw_ctx.dml.soc.num_states ||
2598                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
2599                         dc->debug.force_subvp_mclk_switch)) {
2600
2601                 dcn32_merge_pipes_for_subvp(dc, context);
2602
2603                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
2604                                 dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
2605
2606                         /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
2607                          * Adding phantom pipes won't change the validation result, so change the DML input param
2608                          * for P-State support before adding phantom pipes and recalculating the DML result.
2609                          * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
2610                          * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
2611                          * enough to support support MCLK switching.
2612                          */
2613                         if (*vlevel == context->bw_ctx.dml.soc.num_states) {
2614                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2615                                                                 dm_prefetch_support_stutter;
2616                                 /* There are params (such as FabricClock) that need to be recalculated
2617                                  * after validation fails (otherwise it will be 0). Calculation for
2618                                  * phantom vactive requires call into DML, so we must ensure all the
2619                                  * vba params are valid otherwise we'll get incorrect phantom vactive.
2620                                  */
2621                                 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
2622                         }
2623
2624                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
2625
2626                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
2627                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
2628
2629                         if (*vlevel < context->bw_ctx.dml.soc.num_states &&
2630                                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
2631                                         && subvp_validate_static_schedulability(dc, context, *vlevel)) {
2632                                 found_supported_config = true;
2633                         } else if (*vlevel < context->bw_ctx.dml.soc.num_states &&
2634                                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
2635                                 /* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles
2636                                  * the case for SubVP + DRR, where the DRR display does not support MCLK switch
2637                                  * at it's native refresh rate / timing.
2638                                  */
2639                                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2640                                         pipe = &context->res_ctx.pipe_ctx[i];
2641                                         if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
2642                                                         pipe->stream->mall_stream_config.type == SUBVP_NONE) {
2643                                                 non_subvp_pipes++;
2644                                                 // Use ignore_msa_timing_param flag to identify as DRR
2645                                                 if (pipe->stream->ignore_msa_timing_param) {
2646                                                         drr_pipe_found = true;
2647                                                         drr_pipe_index = i;
2648                                                 }
2649                                         }
2650                                 }
2651                                 // If there is only 1 remaining non SubVP pipe that is DRR, check static
2652                                 // schedulability for SubVP + DRR.
2653                                 if (non_subvp_pipes == 1 && drr_pipe_found) {
2654                                         found_supported_config = subvp_drr_schedulable(dc,
2655                                                         context, &context->res_ctx.pipe_ctx[drr_pipe_index]);
2656                                 }
2657                         }
2658                 }
2659
2660                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
2661                 // remove phantom pipes and repopulate dml pipes
2662                 if (!found_supported_config) {
2663                         dc->res_pool->funcs->remove_phantom_pipes(dc, context);
2664                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
2665                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
2666                 } else {
2667                         // only call dcn20_validate_apply_pipe_split_flags if we found a supported config
2668                         memset(split, 0, MAX_PIPES * sizeof(int));
2669                         memset(merge, 0, MAX_PIPES * sizeof(bool));
2670                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
2671
2672                         // Note: We can't apply the phantom pipes to hardware at this time. We have to wait
2673                         // until driver has acquired the DMCUB lock to do it safely.
2674                 }
2675         }
2676 }
2677
2678 static bool dcn32_internal_validate_bw(
2679                 struct dc *dc,
2680                 struct dc_state *context,
2681                 display_e2e_pipe_params_st *pipes,
2682                 int *pipe_cnt_out,
2683                 int *vlevel_out,
2684                 bool fast_validate)
2685 {
2686         bool out = false;
2687         bool repopulate_pipes = false;
2688         int split[MAX_PIPES] = { 0 };
2689         bool merge[MAX_PIPES] = { false };
2690         bool newly_split[MAX_PIPES] = { false };
2691         int pipe_cnt, i, pipe_idx, vlevel;
2692         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
2693
2694         ASSERT(pipes);
2695         if (!pipes)
2696                 return false;
2697
2698         // For each full update, remove all existing phantom pipes first
2699         dc->res_pool->funcs->remove_phantom_pipes(dc, context);
2700
2701         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
2702
2703         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2704
2705         if (!pipe_cnt) {
2706                 out = true;
2707                 goto validate_out;
2708         }
2709
2710         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
2711
2712         if (!fast_validate) {
2713                 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
2714         }
2715
2716         if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
2717                         vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
2718                 /*
2719                  * If mode is unsupported or there's still no p-state support then
2720                  * fall back to favoring voltage.
2721                  *
2722                  * We don't actually support prefetch mode 2, so require that we
2723                  * at least support prefetch mode 1.
2724                  */
2725                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2726                                 dm_prefetch_support_stutter;
2727
2728                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2729                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
2730                         memset(split, 0, MAX_PIPES * sizeof(int));
2731                         memset(merge, 0, MAX_PIPES * sizeof(bool));
2732                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2733                 }
2734         }
2735
2736         dml_log_mode_support_params(&context->bw_ctx.dml);
2737
2738         if (vlevel == context->bw_ctx.dml.soc.num_states)
2739                 goto validate_fail;
2740
2741         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2742                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2743                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
2744
2745                 if (!pipe->stream)
2746                         continue;
2747
2748                 /* We only support full screen mpo with ODM */
2749                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
2750                                 && pipe->plane_state && mpo_pipe
2751                                 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
2752                                                 &pipe->plane_res.scl_data.recout,
2753                                                 sizeof(struct rect)) != 0) {
2754                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
2755                         goto validate_fail;
2756                 }
2757                 pipe_idx++;
2758         }
2759
2760         /* merge pipes if necessary */
2761         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2762                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2763
2764                 /*skip pipes that don't need merging*/
2765                 if (!merge[i])
2766                         continue;
2767
2768                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
2769                 if (pipe->prev_odm_pipe) {
2770                         /*split off odm pipe*/
2771                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
2772                         if (pipe->next_odm_pipe)
2773                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
2774
2775                         pipe->bottom_pipe = NULL;
2776                         pipe->next_odm_pipe = NULL;
2777                         pipe->plane_state = NULL;
2778                         pipe->stream = NULL;
2779                         pipe->top_pipe = NULL;
2780                         pipe->prev_odm_pipe = NULL;
2781                         if (pipe->stream_res.dsc)
2782                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
2783                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2784                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2785                         repopulate_pipes = true;
2786                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2787                         struct pipe_ctx *top_pipe = pipe->top_pipe;
2788                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
2789
2790                         top_pipe->bottom_pipe = bottom_pipe;
2791                         if (bottom_pipe)
2792                                 bottom_pipe->top_pipe = top_pipe;
2793
2794                         pipe->top_pipe = NULL;
2795                         pipe->bottom_pipe = NULL;
2796                         pipe->plane_state = NULL;
2797                         pipe->stream = NULL;
2798                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2799                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2800                         repopulate_pipes = true;
2801                 } else
2802                         ASSERT(0); /* Should never try to merge master pipe */
2803
2804         }
2805
2806         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2807                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2808                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2809                 struct pipe_ctx *hsplit_pipe = NULL;
2810                 bool odm;
2811                 int old_index = -1;
2812
2813                 if (!pipe->stream || newly_split[i])
2814                         continue;
2815
2816                 pipe_idx++;
2817                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2818
2819                 if (!pipe->plane_state && !odm)
2820                         continue;
2821
2822                 if (split[i]) {
2823                         if (odm) {
2824                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2825                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2826                                 else if (old_pipe->next_odm_pipe)
2827                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
2828                         } else {
2829                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2830                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2831                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2832                                 else if (old_pipe->bottom_pipe &&
2833                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2834                                         old_index = old_pipe->bottom_pipe->pipe_idx;
2835                         }
2836                         hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
2837                         ASSERT(hsplit_pipe);
2838                         if (!hsplit_pipe)
2839                                 goto validate_fail;
2840
2841                         if (!dcn32_split_stream_for_mpc_or_odm(
2842                                         dc, &context->res_ctx,
2843                                         pipe, hsplit_pipe, odm))
2844                                 goto validate_fail;
2845
2846                         newly_split[hsplit_pipe->pipe_idx] = true;
2847                         repopulate_pipes = true;
2848                 }
2849                 if (split[i] == 4) {
2850                         struct pipe_ctx *pipe_4to1;
2851
2852                         if (odm && old_pipe->next_odm_pipe)
2853                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
2854                         else if (!odm && old_pipe->bottom_pipe &&
2855                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2856                                 old_index = old_pipe->bottom_pipe->pipe_idx;
2857                         else
2858                                 old_index = -1;
2859                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2860                         ASSERT(pipe_4to1);
2861                         if (!pipe_4to1)
2862                                 goto validate_fail;
2863                         if (!dcn32_split_stream_for_mpc_or_odm(
2864                                         dc, &context->res_ctx,
2865                                         pipe, pipe_4to1, odm))
2866                                 goto validate_fail;
2867                         newly_split[pipe_4to1->pipe_idx] = true;
2868
2869                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2870                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2871                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2872                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2873                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2874                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2875                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2876                         else
2877                                 old_index = -1;
2878                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2879                         ASSERT(pipe_4to1);
2880                         if (!pipe_4to1)
2881                                 goto validate_fail;
2882                         if (!dcn32_split_stream_for_mpc_or_odm(
2883                                         dc, &context->res_ctx,
2884                                         hsplit_pipe, pipe_4to1, odm))
2885                                 goto validate_fail;
2886                         newly_split[pipe_4to1->pipe_idx] = true;
2887                 }
2888                 if (odm)
2889                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2890         }
2891
2892         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2893                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2894
2895                 if (pipe->plane_state) {
2896                         if (!resource_build_scaling_params(pipe))
2897                                 goto validate_fail;
2898                 }
2899         }
2900
2901         /* Actual dsc count per stream dsc validation*/
2902         if (!dcn20_validate_dsc(dc, context)) {
2903                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2904                 goto validate_fail;
2905         }
2906
2907         if (repopulate_pipes)
2908                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2909         *vlevel_out = vlevel;
2910         *pipe_cnt_out = pipe_cnt;
2911
2912         out = true;
2913         goto validate_out;
2914
2915 validate_fail:
2916         out = false;
2917
2918 validate_out:
2919         return out;
2920 }
2921
2922 bool dcn32_validate_bandwidth(struct dc *dc,
2923                 struct dc_state *context,
2924                 bool fast_validate)
2925 {
2926         bool out = false;
2927
2928         BW_VAL_TRACE_SETUP();
2929
2930         int vlevel = 0;
2931         int pipe_cnt = 0;
2932         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2933         DC_LOGGER_INIT(dc->ctx->logger);
2934
2935         BW_VAL_TRACE_COUNT();
2936
2937     DC_FP_START();
2938         out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2939     DC_FP_END();
2940
2941         if (pipe_cnt == 0)
2942                 goto validate_out;
2943
2944         if (!out)
2945                 goto validate_fail;
2946
2947         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2948
2949         if (fast_validate) {
2950                 BW_VAL_TRACE_SKIP(fast);
2951                 goto validate_out;
2952         }
2953
2954         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2955
2956         BW_VAL_TRACE_END_WATERMARKS();
2957
2958         goto validate_out;
2959
2960 validate_fail:
2961         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2962                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2963
2964         BW_VAL_TRACE_SKIP(fail);
2965         out = false;
2966
2967 validate_out:
2968         kfree(pipes);
2969
2970         BW_VAL_TRACE_FINISH();
2971
2972         return out;
2973 }
2974
2975
2976 static bool is_dual_plane(enum surface_pixel_format format)
2977 {
2978         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
2979 }
2980
2981 int dcn32_populate_dml_pipes_from_context(
2982         struct dc *dc, struct dc_state *context,
2983         display_e2e_pipe_params_st *pipes,
2984         bool fast_validate)
2985 {
2986         int i, pipe_cnt;
2987         struct resource_context *res_ctx = &context->res_ctx;
2988         struct pipe_ctx *pipe;
2989
2990         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
2991
2992         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2993                 struct dc_crtc_timing *timing;
2994
2995                 if (!res_ctx->pipe_ctx[i].stream)
2996                         continue;
2997                 pipe = &res_ctx->pipe_ctx[i];
2998                 timing = &pipe->stream->timing;
2999
3000                 pipes[pipe_cnt].pipe.src.gpuvm = true;
3001                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
3002                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
3003                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
3004                 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
3005                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
3006                 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
3007
3008                 switch (pipe->stream->mall_stream_config.type) {
3009                 case SUBVP_MAIN:
3010                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
3011                         break;
3012                 case SUBVP_PHANTOM:
3013                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
3014                         pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
3015                         // Disallow unbounded req for SubVP according to DCHUB programming guide
3016                         pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
3017                         break;
3018                 case SUBVP_NONE:
3019                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
3020                         pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
3021                         break;
3022                 default:
3023                         break;
3024                 }
3025
3026                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
3027                 if (pipes[pipe_cnt].dout.dsc_enable) {
3028                         switch (timing->display_color_depth) {
3029                         case COLOR_DEPTH_888:
3030                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
3031                                 break;
3032                         case COLOR_DEPTH_101010:
3033                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
3034                                 break;
3035                         case COLOR_DEPTH_121212:
3036                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
3037                                 break;
3038                         default:
3039                                 ASSERT(0);
3040                                 break;
3041                         }
3042                 }
3043                 pipe_cnt++;
3044         }
3045
3046         switch (pipe_cnt) {
3047         case 1:
3048                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE;
3049                 if (pipe->plane_state && !dc->debug.disable_z9_mpc) {
3050                         if (!is_dual_plane(pipe->plane_state->format)) {
3051                                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;
3052                                 pipes[0].pipe.src.unbounded_req_mode = true;
3053                                 if (pipe->plane_state->src_rect.width >= 5120 &&
3054                                         pipe->plane_state->src_rect.height >= 2880)
3055                                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 320; // 5K or higher
3056                         }
3057                 }
3058                 break;
3059         case 2:
3060                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 2; // 576 KB (9 segments)
3061                 break;
3062         case 3:
3063                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 3; // 384 KB (6 segments)
3064                 break;
3065         case 4:
3066         default:
3067                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; // 256 KB (4 segments)
3068                 break;
3069         }
3070
3071         return pipe_cnt;
3072 }
3073
3074 void dcn32_calculate_wm_and_dlg_fp(
3075                 struct dc *dc, struct dc_state *context,
3076                 display_e2e_pipe_params_st *pipes,
3077                 int pipe_cnt,
3078                 int vlevel)
3079 {
3080         int i, pipe_idx, vlevel_temp = 0;
3081         double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
3082         double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
3083         unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
3084         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
3085                         dm_dram_clock_change_unsupported;
3086
3087         // Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK
3088         if (!pstate_en && dcn32_subvp_in_use(dc, context)) {
3089                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
3090                 pstate_en = true;
3091         }
3092
3093         /* Set B:
3094          * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
3095          * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
3096          * calculations to cover bootup clocks.
3097          * DCFCLK: soc.clock_limits[2] when available
3098          * UCLK: soc.clock_limits[2] when available
3099          */
3100         if (dcn3_2_soc.num_states > 2) {
3101                 vlevel_temp = 2;
3102                 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
3103         } else
3104                 dcfclk = 615; //DCFCLK Vmin_lv
3105
3106         pipes[0].clks_cfg.voltage = vlevel_temp;
3107         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
3108         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
3109
3110         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
3111                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
3112                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
3113                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
3114                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
3115         }
3116         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3117         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3118         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3119         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3120         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3121         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3122         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3123         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3124         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3125         context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3126
3127         /* Set D:
3128          * All clocks min.
3129          * DCFCLK: Min, as reported by PM FW when available
3130          * UCLK  : Min, as reported by PM FW when available
3131          * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
3132          */
3133
3134         if (dcn3_2_soc.num_states > 2) {
3135                 vlevel_temp = 0;
3136                 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
3137         } else
3138                 dcfclk = 615; //DCFCLK Vmin_lv
3139
3140         pipes[0].clks_cfg.voltage = vlevel_temp;
3141         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
3142         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
3143
3144         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
3145                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
3146                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
3147                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
3148                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
3149         }
3150         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3151         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3152         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3153         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3154         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3155         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3156         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3157         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3158         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3159         context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3160
3161         /* Set C, for Dummy P-State:
3162          * All clocks min.
3163          * DCFCLK: Min, as reported by PM FW, when available
3164          * UCLK  : Min,  as reported by PM FW, when available
3165          * pstate latency as per UCLK state dummy pstate latency
3166          */
3167         // For Set A and Set C use values from validation
3168         pipes[0].clks_cfg.voltage = vlevel;
3169         pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
3170         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3171
3172         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
3173                 unsigned int min_dram_speed_mts_margin = 160;
3174
3175                 if ((!pstate_en))
3176                         min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
3177
3178                 /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
3179                 for (i = 3; i > 0; i--)
3180                         if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
3181                                 break;
3182
3183                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
3184                 context->bw_ctx.dml.soc.dummy_pstate_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
3185                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
3186                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
3187                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
3188         }
3189         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3190         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3191         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3192         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3193         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3194         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3195         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3196         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3197         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3198         context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3199
3200         if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
3201                 /* The only difference between A and C is p-state latency, if p-state is not supported
3202                  * with full p-state latency we want to calculate DLG based on dummy p-state latency,
3203                  * Set A p-state watermark set to 0 on DCN32, when p-state unsupported, for now keep as DCN32.
3204                  */
3205                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
3206                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
3207         } else {
3208                 /* Set A:
3209                  * All clocks min.
3210                  * DCFCLK: Min, as reported by PM FW, when available
3211                  * UCLK: Min, as reported by PM FW, when available
3212                  */
3213                 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
3214                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3215                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3216                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3217                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3218                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3219                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3220                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3221                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3222                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3223                 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3224         }
3225
3226         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3227                 if (!context->res_ctx.pipe_ctx[i].stream)
3228                         continue;
3229
3230                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
3231                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3232
3233                 if (dc->config.forced_clocks) {
3234                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
3235                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
3236                 }
3237                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
3238                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
3239                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3240                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
3241
3242                 pipe_idx++;
3243         }
3244
3245         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
3246
3247         dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3248
3249         if (!pstate_en)
3250                 /* Restore full p-state latency */
3251                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
3252                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
3253 }
3254
3255 static struct dc_cap_funcs cap_funcs = {
3256         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3257 };
3258
3259
3260 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
3261                 unsigned int *optimal_dcfclk,
3262                 unsigned int *optimal_fclk)
3263 {
3264         double bw_from_dram, bw_from_dram1, bw_from_dram2;
3265
3266         bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
3267                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
3268         bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
3269                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
3270
3271         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
3272
3273         if (optimal_fclk)
3274                 *optimal_fclk = bw_from_dram /
3275                 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
3276
3277         if (optimal_dcfclk)
3278                 *optimal_dcfclk =  bw_from_dram /
3279                 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
3280 }
3281
3282 void dcn32_calculate_wm_and_dlg(
3283                 struct dc *dc, struct dc_state *context,
3284                 display_e2e_pipe_params_st *pipes,
3285                 int pipe_cnt,
3286                 int vlevel)
3287 {
3288     DC_FP_START();
3289     dcn32_calculate_wm_and_dlg_fp(
3290                 dc, context,
3291                 pipes,
3292                 pipe_cnt,
3293                 vlevel);
3294     DC_FP_END();
3295 }
3296
3297 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
3298 {
3299         int i;
3300
3301         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3302                 if (!context->res_ctx.pipe_ctx[i].stream)
3303                         continue;
3304                 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
3305                         return true;
3306         }
3307         return false;
3308 }
3309
3310 void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes,
3311                 int pipe_cnt, int vlevel)
3312 {
3313         int i, pipe_idx;
3314         bool usr_retraining_support = false;
3315
3316         /* Writeback MCIF_WB arbitration parameters */
3317         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3318
3319         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3320         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3321         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
3322         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3323         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
3324         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
3325         context->bw_ctx.bw.dcn.clk.p_state_change_support =
3326                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3327                                         != dm_dram_clock_change_unsupported;
3328         context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);
3329         /*
3330  *
3331          * TODO: needs FAMS
3332          * Pstate change might not be supported by hardware, but it might be
3333          * possible with firmware driven vertical blank stretching.
3334          */
3335         // context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
3336         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
3337         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
3338         context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
3339         if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
3340                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
3341         else
3342                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
3343
3344         usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
3345         ASSERT(usr_retraining_support);
3346
3347         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3348                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3349
3350         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3351                 if (!context->res_ctx.pipe_ctx[i].stream)
3352                         continue;
3353                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
3354                                 pipe_idx);
3355                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
3356                                 pipe_idx);
3357                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
3358                                 pipe_idx);
3359                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
3360                                 pipe_idx);
3361                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
3362                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
3363                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
3364                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
3365                 } else {
3366                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb =
3367                                         context->bw_ctx.dml.ip.det_buffer_size_kbytes;
3368                         context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
3369                 }
3370                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3371                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3372                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3373                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3374                 pipe_idx++;
3375         }
3376         /*save a original dppclock copy*/
3377         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3378         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
3379         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
3380                         * 1000;
3381         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
3382                         * 1000;
3383
3384         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
3385                         - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
3386
3387         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3388
3389                 if (!context->res_ctx.pipe_ctx[i].stream)
3390                         continue;
3391
3392                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
3393                                 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
3394                                 pipe_cnt, pipe_idx);
3395
3396                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
3397                                 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3398
3399                 pipe_idx++;
3400         }
3401 }
3402
3403 /* dcn32_update_bw_bounding_box
3404  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
3405  * with actual values as per dGPU SKU:
3406  * -with passed few options from dc->config
3407  * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
3408  * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
3409  * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
3410  * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
3411  * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
3412  *  clocks (which might differ for certain dGPU SKU of the same ASIC)
3413  */
3414 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
3415 {
3416         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3417
3418                 /* Overrides from dc->config options */
3419                 dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
3420
3421                 /* Override from passed dc->bb_overrides if available*/
3422                 if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3423                                 && dc->bb_overrides.sr_exit_time_ns) {
3424                         dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3425                 }
3426
3427                 if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
3428                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3429                                 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3430                         dcn3_2_soc.sr_enter_plus_exit_time_us =
3431                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3432                 }
3433
3434                 if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3435                         && dc->bb_overrides.urgent_latency_ns) {
3436                         dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3437                 }
3438
3439                 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
3440                                 != dc->bb_overrides.dram_clock_change_latency_ns
3441                                 && dc->bb_overrides.dram_clock_change_latency_ns) {
3442                         dcn3_2_soc.dram_clock_change_latency_us =
3443                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3444                 }
3445
3446                 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
3447                                 != dc->bb_overrides.dummy_clock_change_latency_ns
3448                                 && dc->bb_overrides.dummy_clock_change_latency_ns) {
3449                         dcn3_2_soc.dummy_pstate_latency_us =
3450                                 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3451                 }
3452
3453                 /* Override from VBIOS if VBIOS bb_info available */
3454                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
3455                         struct bp_soc_bb_info bb_info = {0};
3456
3457                         if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
3458                                 if (bb_info.dram_clock_change_latency_100ns > 0)
3459                                         dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
3460
3461                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
3462                                 dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
3463
3464                         if (bb_info.dram_sr_exit_latency_100ns > 0)
3465                                 dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
3466                         }
3467                 }
3468
3469                 /* Override from VBIOS for num_chan */
3470                 if (dc->ctx->dc_bios->vram_info.num_chans)
3471                         dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
3472
3473                 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
3474                         dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
3475
3476         }
3477
3478         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
3479         dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3480         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3481
3482         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
3483         if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
3484                 unsigned int i = 0, j = 0, num_states = 0;
3485
3486                 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
3487                 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
3488                 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
3489                 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
3490
3491                 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
3492                 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
3493                 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
3494
3495                 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
3496                         if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
3497                                 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
3498                         if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
3499                                 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
3500                         if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
3501                                 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
3502                         if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
3503                                 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
3504                 }
3505                 if (!max_dcfclk_mhz)
3506                         max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
3507                 if (!max_dispclk_mhz)
3508                         max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
3509                 if (!max_dppclk_mhz)
3510                         max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
3511                 if (!max_phyclk_mhz)
3512                         max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
3513
3514                 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3515                         // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
3516                         dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
3517                         num_dcfclk_sta_targets++;
3518                 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3519                         // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
3520                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
3521                                 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
3522                                         dcfclk_sta_targets[i] = max_dcfclk_mhz;
3523                                         break;
3524                                 }
3525                         }
3526                         // Update size of array since we "removed" duplicates
3527                         num_dcfclk_sta_targets = i + 1;
3528                 }
3529
3530                 num_uclk_states = bw_params->clk_table.num_entries;
3531
3532                 // Calculate optimal dcfclk for each uclk
3533                 for (i = 0; i < num_uclk_states; i++) {
3534                         dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
3535                                         &optimal_dcfclk_for_uclk[i], NULL);
3536                         if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
3537                                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
3538                         }
3539                 }
3540
3541                 // Calculate optimal uclk for each dcfclk sta target
3542                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
3543                         for (j = 0; j < num_uclk_states; j++) {
3544                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
3545                                         optimal_uclk_for_dcfclk_sta_targets[i] =
3546                                                         bw_params->clk_table.entries[j].memclk_mhz * 16;
3547                                         break;
3548                                 }
3549                         }
3550                 }
3551
3552                 i = 0;
3553                 j = 0;
3554                 // create the final dcfclk and uclk table
3555                 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
3556                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
3557                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3558                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3559                         } else {
3560                                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3561                                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3562                                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3563                                 } else {
3564                                         j = num_uclk_states;
3565                                 }
3566                         }
3567                 }
3568
3569                 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
3570                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3571                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3572                 }
3573
3574                 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
3575                                 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3576                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3577                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3578                 }
3579
3580                 dcn3_2_soc.num_states = num_states;
3581                 for (i = 0; i < dcn3_2_soc.num_states; i++) {
3582                         dcn3_2_soc.clock_limits[i].state = i;
3583                         dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
3584                         dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
3585
3586                         /* Fill all states with max values of all these clocks */
3587                         dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
3588                         dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
3589                         dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
3590                         dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
3591
3592                         /* Populate from bw_params for DTBCLK, SOCCLK */
3593                         if (i > 0) {
3594                                 if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
3595                                         dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
3596                                 } else {
3597                                         dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3598                                 }
3599                         } else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
3600                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3601                         }
3602
3603                         if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
3604                                 dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
3605                         else
3606                                 dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
3607
3608                         if (!dram_speed_mts[i] && i > 0)
3609                                 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
3610                         else
3611                                 dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
3612
3613                         /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
3614                         /* PHYCLK_D18, PHYCLK_D32 */
3615                         dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
3616                         dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
3617                 }
3618
3619                 /* Re-init DML with updated bb */
3620                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3621                 if (dc->current_state)
3622                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3623         }
3624 }
3625
3626 static struct resource_funcs dcn32_res_pool_funcs = {
3627         .destroy = dcn32_destroy_resource_pool,
3628         .link_enc_create = dcn32_link_encoder_create,
3629         .link_enc_create_minimal = NULL,
3630         .panel_cntl_create = dcn32_panel_cntl_create,
3631         .validate_bandwidth = dcn32_validate_bandwidth,
3632         .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
3633         .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
3634         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3635         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
3636         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
3637         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3638         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
3639         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
3640         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
3641         .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
3642         .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
3643         .update_bw_bounding_box = dcn32_update_bw_bounding_box,
3644         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
3645         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
3646         .add_phantom_pipes = dcn32_add_phantom_pipes,
3647         .remove_phantom_pipes = dcn32_remove_phantom_pipes,
3648 };
3649
3650
3651 static bool dcn32_resource_construct(
3652         uint8_t num_virtual_links,
3653         struct dc *dc,
3654         struct dcn32_resource_pool *pool)
3655 {
3656         int i, j;
3657         struct dc_context *ctx = dc->ctx;
3658         struct irq_service_init_data init_data;
3659         struct ddc_service_init_data ddc_init_data = {0};
3660         uint32_t pipe_fuses = 0;
3661         uint32_t num_pipes  = 4;
3662
3663     DC_FP_START();
3664
3665         ctx->dc_bios->regs = &bios_regs;
3666
3667         pool->base.res_cap = &res_cap_dcn32;
3668         /* max number of pipes for ASIC before checking for pipe fuses */
3669         num_pipes  = pool->base.res_cap->num_timing_generator;
3670         pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
3671
3672         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
3673                 if (pipe_fuses & 1 << i)
3674                         num_pipes--;
3675
3676         if (pipe_fuses & 1)
3677                 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
3678
3679         if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
3680                 ASSERT(0); //Entire DCN is harvested!
3681
3682         /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
3683          * value will be changed, update max_num_dpp and max_num_otg for dml.
3684          */
3685         dcn3_2_ip.max_num_dpp = num_pipes;
3686         dcn3_2_ip.max_num_otg = num_pipes;
3687
3688         pool->base.funcs = &dcn32_res_pool_funcs;
3689
3690         /*************************************************
3691          *  Resource + asic cap harcoding                *
3692          *************************************************/
3693         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3694         pool->base.timing_generator_count = num_pipes;
3695         pool->base.pipe_count = num_pipes;
3696         pool->base.mpcc_count = num_pipes;
3697         dc->caps.max_downscale_ratio = 600;
3698         dc->caps.i2c_speed_in_khz = 100;
3699         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
3700         dc->caps.max_cursor_size = 256;
3701         dc->caps.min_horizontal_blanking_period = 80;
3702         dc->caps.dmdata_alloc_size = 2048;
3703         dc->caps.mall_size_per_mem_channel = 0;
3704         dc->caps.mall_size_total = 0;
3705         dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
3706
3707         dc->caps.cache_line_size = 64;
3708         dc->caps.cache_num_ways = 16;
3709         dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64
3710         dc->caps.subvp_fw_processing_delay_us = 15;
3711         dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
3712         dc->caps.subvp_pstate_allow_width_us = 20;
3713         dc->caps.subvp_vertical_int_margin_us = 30;
3714
3715         dc->caps.max_slave_planes = 2;
3716         dc->caps.max_slave_yuv_planes = 2;
3717         dc->caps.max_slave_rgb_planes = 2;
3718         dc->caps.post_blend_color_processing = true;
3719         dc->caps.force_dp_tps4_for_cp2520 = true;
3720         dc->caps.dp_hpo = true;
3721         dc->caps.edp_dsc_support = true;
3722         dc->caps.extended_aux_timeout_support = true;
3723         dc->caps.dmcub_support = true;
3724
3725         /* Color pipeline capabilities */
3726         dc->caps.color.dpp.dcn_arch = 1;
3727         dc->caps.color.dpp.input_lut_shared = 0;
3728         dc->caps.color.dpp.icsc = 1;
3729         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
3730         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
3731         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
3732         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
3733         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
3734         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
3735         dc->caps.color.dpp.post_csc = 1;
3736         dc->caps.color.dpp.gamma_corr = 1;
3737         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
3738
3739         dc->caps.color.dpp.hw_3d_lut = 1;
3740         dc->caps.color.dpp.ogam_ram = 0;  //Blnd Gam also removed
3741         // no OGAM ROM on DCN2 and later ASICs
3742         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
3743         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
3744         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
3745         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
3746         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
3747         dc->caps.color.dpp.ocsc = 0;
3748
3749         dc->caps.color.mpc.gamut_remap = 1;
3750         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
3751         dc->caps.color.mpc.ogam_ram = 1;
3752         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
3753         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
3754         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
3755         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
3756         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
3757         dc->caps.color.mpc.ocsc = 1;
3758
3759         /* Use pipe context based otg sync logic */
3760         dc->config.use_pipe_ctx_sync_logic = true;
3761
3762         /* read VBIOS LTTPR caps */
3763         {
3764                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
3765                         enum bp_result bp_query_result;
3766                         uint8_t is_vbios_lttpr_enable = 0;
3767
3768                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
3769                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3770                 }
3771
3772                 /* interop bit is implicit */
3773                 {
3774                         dc->caps.vbios_lttpr_aware = true;
3775                 }
3776         }
3777
3778         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
3779                 dc->debug = debug_defaults_drv;
3780         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3781                 dc->debug = debug_defaults_diags;
3782         } else
3783                 dc->debug = debug_defaults_diags;
3784         // Init the vm_helper
3785         if (dc->vm_helper)
3786                 vm_helper_init(dc->vm_helper, 16);
3787
3788         /*************************************************
3789          *  Create resources                             *
3790          *************************************************/
3791
3792         /* Clock Sources for Pixel Clock*/
3793         pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
3794                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3795                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
3796                                 &clk_src_regs[0], false);
3797         pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
3798                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3799                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
3800                                 &clk_src_regs[1], false);
3801         pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
3802                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3803                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
3804                                 &clk_src_regs[2], false);
3805         pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
3806                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3807                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
3808                                 &clk_src_regs[3], false);
3809         pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
3810                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3811                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
3812                                 &clk_src_regs[4], false);
3813
3814         pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
3815
3816         /* todo: not reuse phy_pll registers */
3817         pool->base.dp_clock_source =
3818                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3819                                 CLOCK_SOURCE_ID_DP_DTO,
3820                                 &clk_src_regs[0], true);
3821
3822         for (i = 0; i < pool->base.clk_src_count; i++) {
3823                 if (pool->base.clock_sources[i] == NULL) {
3824                         dm_error("DC: failed to create clock sources!\n");
3825                         BREAK_TO_DEBUGGER();
3826                         goto create_fail;
3827                 }
3828         }
3829
3830         /* DCCG */
3831         pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3832         if (pool->base.dccg == NULL) {
3833                 dm_error("DC: failed to create dccg!\n");
3834                 BREAK_TO_DEBUGGER();
3835                 goto create_fail;
3836         }
3837
3838         /* DML */
3839         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3840                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3841
3842         /* IRQ Service */
3843         init_data.ctx = dc->ctx;
3844         pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
3845         if (!pool->base.irqs)
3846                 goto create_fail;
3847
3848         /* HUBBUB */
3849         pool->base.hubbub = dcn32_hubbub_create(ctx);
3850         if (pool->base.hubbub == NULL) {
3851                 BREAK_TO_DEBUGGER();
3852                 dm_error("DC: failed to create hubbub!\n");
3853                 goto create_fail;
3854         }
3855
3856         /* HUBPs, DPPs, OPPs, TGs, ABMs */
3857         for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3858
3859                 /* if pipe is disabled, skip instance of HW pipe,
3860                  * i.e, skip ASIC register instance
3861                  */
3862                 if (pipe_fuses & 1 << i)
3863                         continue;
3864
3865                 /* HUBPs */
3866                 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
3867                 if (pool->base.hubps[j] == NULL) {
3868                         BREAK_TO_DEBUGGER();
3869                         dm_error(
3870                                 "DC: failed to create hubps!\n");
3871                         goto create_fail;
3872                 }
3873
3874                 /* DPPs */
3875                 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
3876                 if (pool->base.dpps[j] == NULL) {
3877                         BREAK_TO_DEBUGGER();
3878                         dm_error(
3879                                 "DC: failed to create dpps!\n");
3880                         goto create_fail;
3881                 }
3882
3883                 /* OPPs */
3884                 pool->base.opps[j] = dcn32_opp_create(ctx, i);
3885                 if (pool->base.opps[j] == NULL) {
3886                         BREAK_TO_DEBUGGER();
3887                         dm_error(
3888                                 "DC: failed to create output pixel processor!\n");
3889                         goto create_fail;
3890                 }
3891
3892                 /* TGs */
3893                 pool->base.timing_generators[j] = dcn32_timing_generator_create(
3894                                 ctx, i);
3895                 if (pool->base.timing_generators[j] == NULL) {
3896                         BREAK_TO_DEBUGGER();
3897                         dm_error("DC: failed to create tg!\n");
3898                         goto create_fail;
3899                 }
3900
3901                 /* ABMs */
3902                 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
3903                                 &abm_regs[i],
3904                                 &abm_shift,
3905                                 &abm_mask);
3906                 if (pool->base.multiple_abms[j] == NULL) {
3907                         dm_error("DC: failed to create abm for pipe %d!\n", i);
3908                         BREAK_TO_DEBUGGER();
3909                         goto create_fail;
3910                 }
3911
3912                 /* index for resource pool arrays for next valid pipe */
3913                 j++;
3914         }
3915
3916         /* PSR */
3917         pool->base.psr = dmub_psr_create(ctx);
3918         if (pool->base.psr == NULL) {
3919                 dm_error("DC: failed to create psr obj!\n");
3920                 BREAK_TO_DEBUGGER();
3921                 goto create_fail;
3922         }
3923
3924         /* MPCCs */
3925         pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
3926         if (pool->base.mpc == NULL) {
3927                 BREAK_TO_DEBUGGER();
3928                 dm_error("DC: failed to create mpc!\n");
3929                 goto create_fail;
3930         }
3931
3932         /* DSCs */
3933         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3934                 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
3935                 if (pool->base.dscs[i] == NULL) {
3936                         BREAK_TO_DEBUGGER();
3937                         dm_error("DC: failed to create display stream compressor %d!\n", i);
3938                         goto create_fail;
3939                 }
3940         }
3941
3942         /* DWB */
3943         if (!dcn32_dwbc_create(ctx, &pool->base)) {
3944                 BREAK_TO_DEBUGGER();
3945                 dm_error("DC: failed to create dwbc!\n");
3946                 goto create_fail;
3947         }
3948
3949         /* MMHUBBUB */
3950         if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
3951                 BREAK_TO_DEBUGGER();
3952                 dm_error("DC: failed to create mcif_wb!\n");
3953                 goto create_fail;
3954         }
3955
3956         /* AUX and I2C */
3957         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3958                 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
3959                 if (pool->base.engines[i] == NULL) {
3960                         BREAK_TO_DEBUGGER();
3961                         dm_error(
3962                                 "DC:failed to create aux engine!!\n");
3963                         goto create_fail;
3964                 }
3965                 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
3966                 if (pool->base.hw_i2cs[i] == NULL) {
3967                         BREAK_TO_DEBUGGER();
3968                         dm_error(
3969                                 "DC:failed to create hw i2c!!\n");
3970                         goto create_fail;
3971                 }
3972                 pool->base.sw_i2cs[i] = NULL;
3973         }
3974
3975         /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
3976         if (!resource_construct(num_virtual_links, dc, &pool->base,
3977                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3978                         &res_create_funcs : &res_create_maximus_funcs)))
3979                         goto create_fail;
3980
3981         /* HW Sequencer init functions and Plane caps */
3982         dcn32_hw_sequencer_init_functions(dc);
3983
3984         dc->caps.max_planes =  pool->base.pipe_count;
3985
3986         for (i = 0; i < dc->caps.max_planes; ++i)
3987                 dc->caps.planes[i] = plane_cap;
3988
3989         dc->cap_funcs = cap_funcs;
3990
3991         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3992                 ddc_init_data.ctx = dc->ctx;
3993                 ddc_init_data.link = NULL;
3994                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3995                 ddc_init_data.id.enum_id = 0;
3996                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3997                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3998         } else {
3999                 pool->base.oem_device = NULL;
4000         }
4001
4002     DC_FP_END();
4003
4004         return true;
4005
4006 create_fail:
4007
4008     DC_FP_END();
4009
4010         dcn32_resource_destruct(pool);
4011
4012         return false;
4013 }
4014
4015 struct resource_pool *dcn32_create_resource_pool(
4016                 const struct dc_init_data *init_data,
4017                 struct dc *dc)
4018 {
4019         struct dcn32_resource_pool *pool =
4020                 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
4021
4022         if (!pool)
4023                 return NULL;
4024
4025         if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
4026                 return &pool->base;
4027
4028         BREAK_TO_DEBUGGER();
4029         kfree(pool);
4030         return NULL;
4031 }