drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dcn32_optc.h"
  27
  28 #include "dcn30/dcn30_optc.h"
  29 #include "dcn31/dcn31_optc.h"
  30 #include "reg_helper.h"
  31 #include "dc.h"
  32 #include "dcn_calc_math.h"
  33 #include "dc_dmub_srv.h"
  34
  35 #define REG(reg)\
  36         optc1->tg_regs->reg
  37
  38 #define CTX \
  39         optc1->base.ctx
  40
  41 #undef FN
  42 #define FN(reg_name, field_name) \
  43         optc1->tg_shift->field_name, optc1->tg_mask->field_name
  44
  45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
  46                 struct dc_crtc_timing *timing)
  47 {
  48         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  49         uint32_t memory_mask = 0;
  50         int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
  51         int mpcc_hactive = h_active / opp_cnt;
  52         /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
  53         int odm_mem_count = (h_active + 2047) / 2048;
  54
  55         /*
  56          * display <= 4k : 2 memories + 2 pipes
  57          * 4k < display <= 8k : 4 memories + 2 pipes
  58          * 8k < display <= 12k : 6 memories + 4 pipes
  59          */
  60         if (opp_cnt == 4) {
  61                 if (odm_mem_count <= 2)
  62                         memory_mask = 0x3;
  63                 else if (odm_mem_count <= 4)
  64                         memory_mask = 0xf;
  65                 else
  66                         memory_mask = 0x3f;
  67         } else {
  68                 if (odm_mem_count <= 2)
  69                         memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
  70                 else if (odm_mem_count <= 4)
  71                         memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
  72                 else
  73                         memory_mask = 0x77;
  74         }
  75
  76         REG_SET(OPTC_MEMORY_CONFIG, 0,
  77                 OPTC_MEM_SEL, memory_mask);
  78
  79         if (opp_cnt == 2) {
  80                 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
  81                                 OPTC_NUM_OF_INPUT_SEGMENT, 1,
  82                                 OPTC_SEG0_SRC_SEL, opp_id[0],
  83                                 OPTC_SEG1_SRC_SEL, opp_id[1]);
  84         } else if (opp_cnt == 4) {
  85                 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
  86                                 OPTC_NUM_OF_INPUT_SEGMENT, 3,
  87                                 OPTC_SEG0_SRC_SEL, opp_id[0],
  88                                 OPTC_SEG1_SRC_SEL, opp_id[1],
  89                                 OPTC_SEG2_SRC_SEL, opp_id[2],
  90                                 OPTC_SEG3_SRC_SEL, opp_id[3]);
  91         }
  92
  93         REG_UPDATE(OPTC_WIDTH_CONTROL,
  94                         OPTC_SEGMENT_WIDTH, mpcc_hactive);
  95
  96         REG_UPDATE(OTG_H_TIMING_CNTL,
  97                         OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
  98         optc1->opp_count = opp_cnt;
  99 }
 100
 101 static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
 102 {
 103         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 104
 105         REG_UPDATE(OTG_H_TIMING_CNTL,
 106                         OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
 107 }
 108 /**
 109  * Enable CRTC
 110  * Enable CRTC - call ASIC Control Object to enable Timing generator.
 111  */
 112 static bool optc32_enable_crtc(struct timing_generator *optc)
 113 {
 114         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 115
 116         /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
 117         REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
 118                         OPTC_SEG0_SRC_SEL, optc->inst);
 119
 120         /* VTG enable first is for HW workaround */
 121         REG_UPDATE(CONTROL,
 122                         VTG0_ENABLE, 1);
 123
 124         REG_SEQ_START();
 125
 126         /* Enable CRTC */
 127         REG_UPDATE_2(OTG_CONTROL,
 128                         OTG_DISABLE_POINT_CNTL, 2,
 129                         OTG_MASTER_EN, 1);
 130
 131         REG_SEQ_SUBMIT();
 132         REG_SEQ_WAIT_DONE();
 133
 134         return true;
 135 }
 136
 137 /* disable_crtc */
 138 static bool optc32_disable_crtc(struct timing_generator *optc)
 139 {
 140         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 141
 142         /* disable otg request until end of the first line
 143          * in the vertical blank region
 144          */
 145         REG_UPDATE(OTG_CONTROL,
 146                         OTG_MASTER_EN, 0);
 147
 148         REG_UPDATE(CONTROL,
 149                         VTG0_ENABLE, 0);
 150
 151         /* CRTC disabled, so disable  clock. */
 152         REG_WAIT(OTG_CLOCK_CONTROL,
 153                         OTG_BUSY, 0,
 154                         1, 100000);
 155
 156         return true;
 157 }
 158
 159 void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
 160 {
 161         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 162
 163         /* Disable immediately. */
 164         REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
 165
 166         /* CRTC disabled, so disable  clock. */
 167         REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
 168 }
 169
 170 static void optc32_set_odm_bypass(struct timing_generator *optc,
 171                 const struct dc_crtc_timing *dc_crtc_timing)
 172 {
 173         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 174         enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
 175
 176         REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
 177                         OPTC_NUM_OF_INPUT_SEGMENT, 0,
 178                         OPTC_SEG0_SRC_SEL, optc->inst,
 179                         OPTC_SEG1_SRC_SEL, 0xf,
 180                         OPTC_SEG2_SRC_SEL, 0xf,
 181                         OPTC_SEG3_SRC_SEL, 0xf
 182                         );
 183
 184         h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
 185         REG_UPDATE(OTG_H_TIMING_CNTL,
 186                         OTG_H_TIMING_DIV_MODE, h_div);
 187
 188         REG_SET(OPTC_MEMORY_CONFIG, 0,
 189                         OPTC_MEM_SEL, 0);
 190         optc1->opp_count = 1;
 191 }
 192
 193 void optc32_setup_manual_trigger(struct timing_generator *optc)
 194 {
 195         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 196         struct dc *dc = optc->ctx->dc;
 197
 198         if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
 199                 dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
 200         else {
 201                 /*
 202                  * MIN_MASK_EN is gone and MASK is now always enabled.
 203                  *
 204                  * To get it to it work with manual trigger we need to make sure
 205                  * we program the correct bit.
 206                  */
 207                 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
 208                                 OTG_V_TOTAL_MIN_SEL, 1,
 209                                 OTG_V_TOTAL_MAX_SEL, 1,
 210                                 OTG_FORCE_LOCK_ON_EVENT, 0,
 211                                 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
 212
 213                 // Setup manual flow control for EOF via TRIG_A
 214                 optc->funcs->setup_manual_trigger(optc);
 215         }
 216 }
 217
 218 void optc32_set_drr(
 219         struct timing_generator *optc,
 220         const struct drr_params *params)
 221 {
 222         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 223
 224         if (params != NULL &&
 225                 params->vertical_total_max > 0 &&
 226                 params->vertical_total_min > 0) {
 227
 228                 if (params->vertical_total_mid != 0) {
 229
 230                         REG_SET(OTG_V_TOTAL_MID, 0,
 231                                 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
 232
 233                         REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
 234                                         OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
 235                                         OTG_VTOTAL_MID_FRAME_NUM,
 236                                         (uint8_t)params->vertical_total_mid_frame_num);
 237
 238                 }
 239
 240                 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
 241                 optc32_setup_manual_trigger(optc);
 242         } else {
 243                 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
 244                                 OTG_SET_V_TOTAL_MIN_MASK, 0,
 245                                 OTG_V_TOTAL_MIN_SEL, 0,
 246                                 OTG_V_TOTAL_MAX_SEL, 0,
 247                                 OTG_FORCE_LOCK_ON_EVENT, 0);
 248
 249                 optc->funcs->set_vtotal_min_max(optc, 0, 0);
 250         }
 251 }
 252
 253 static struct timing_generator_funcs dcn32_tg_funcs = {
 254                 .validate_timing = optc1_validate_timing,
 255                 .program_timing = optc1_program_timing,
 256                 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
 257                 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
 258                 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
 259                 .program_global_sync = optc1_program_global_sync,
 260                 .enable_crtc = optc32_enable_crtc,
 261                 .disable_crtc = optc32_disable_crtc,
 262                 .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
 263                 /* used by enable_timing_synchronization. Not need for FPGA */
 264                 .is_counter_moving = optc1_is_counter_moving,
 265                 .get_position = optc1_get_position,
 266                 .get_frame_count = optc1_get_vblank_counter,
 267                 .get_scanoutpos = optc1_get_crtc_scanoutpos,
 268                 .get_otg_active_size = optc1_get_otg_active_size,
 269                 .set_early_control = optc1_set_early_control,
 270                 /* used by enable_timing_synchronization. Not need for FPGA */
 271                 .wait_for_state = optc1_wait_for_state,
 272                 .set_blank_color = optc3_program_blank_color,
 273                 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
 274                 .triplebuffer_lock = optc3_triplebuffer_lock,
 275                 .triplebuffer_unlock = optc2_triplebuffer_unlock,
 276                 .enable_reset_trigger = optc1_enable_reset_trigger,
 277                 .enable_crtc_reset = optc1_enable_crtc_reset,
 278                 .disable_reset_trigger = optc1_disable_reset_trigger,
 279                 .lock = optc3_lock,
 280                 .unlock = optc1_unlock,
 281                 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
 282                 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
 283                 .enable_optc_clock = optc1_enable_optc_clock,
 284                 .set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted
 285                 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 286                 .set_vtotal_min_max = optc3_set_vtotal_min_max,
 287                 .set_static_screen_control = optc1_set_static_screen_control,
 288                 .program_stereo = optc1_program_stereo,
 289                 .is_stereo_left_eye = optc1_is_stereo_left_eye,
 290                 .tg_init = optc3_tg_init,
 291                 .is_tg_enabled = optc1_is_tg_enabled,
 292                 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
 293                 .clear_optc_underflow = optc1_clear_optc_underflow,
 294                 .setup_global_swap_lock = NULL,
 295                 .get_crc = optc1_get_crc,
 296                 .configure_crc = optc1_configure_crc,
 297                 .set_dsc_config = optc3_set_dsc_config,
 298                 .get_dsc_status = optc2_get_dsc_status,
 299                 .set_dwb_source = NULL,
 300                 .set_odm_bypass = optc32_set_odm_bypass,
 301                 .set_odm_combine = optc32_set_odm_combine,
 302                 .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
 303                 .get_optc_source = optc2_get_optc_source,
 304                 .set_out_mux = optc3_set_out_mux,
 305                 .set_drr_trigger_window = optc3_set_drr_trigger_window,
 306                 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
 307                 .set_gsl = optc2_set_gsl,
 308                 .set_gsl_source_select = optc2_set_gsl_source_select,
 309                 .set_vtg_params = optc1_set_vtg_params,
 310                 .program_manual_trigger = optc2_program_manual_trigger,
 311                 .setup_manual_trigger = optc2_setup_manual_trigger,
 312                 .get_hw_timing = optc1_get_hw_timing,
 313 };
 314
 315 void dcn32_timing_generator_init(struct optc *optc1)
 316 {
 317         optc1->base.funcs = &dcn32_tg_funcs;
 318
 319         optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
 320         optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
 321
 322         optc1->min_h_blank = 32;
 323         optc1->min_v_blank = 3;
 324         optc1->min_v_blank_interlace = 5;
 325         optc1->min_h_sync_width = 4;
 326         optc1->min_v_sync_width = 1;
 327 }
 328