drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dm_helpers.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "dccg.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "dcn30/dcn30_cm_common.h"
  34 #include "reg_helper.h"
  35 #include "abm.h"
  36 #include "hubp.h"
  37 #include "dchubbub.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "mcif_wb.h"
  43 #include "dc_dmub_srv.h"
  44 #include "link_hwss.h"
  45 #include "dpcd_defs.h"
  46 #include "dcn32_hwseq.h"
  47 #include "clk_mgr.h"
  48 #include "dsc.h"
  49 #include "dcn20/dcn20_optc.h"
  50 #include "dmub_subvp_state.h"
  51 #include "dce/dmub_hw_lock_mgr.h"
  52 #include "dcn32_resource.h"
  53 #include "dc_link_dp.h"
  54 #include "dmub/inc/dmub_subvp_state.h"
  55
  56 #define DC_LOGGER_INIT(logger)
  57
  58 #define CTX \
  59         hws->ctx
  60 #define REG(reg)\
  61         hws->regs->reg
  62 #define DC_LOGGER \
  63                 dc->ctx->logger
  64
  65
  66 #undef FN
  67 #define FN(reg_name, field_name) \
  68         hws->shifts->field_name, hws->masks->field_name
  69
  70 void dcn32_dsc_pg_control(
  71                 struct dce_hwseq *hws,
  72                 unsigned int dsc_inst,
  73                 bool power_on)
  74 {
  75         uint32_t power_gate = power_on ? 0 : 1;
  76         uint32_t pwr_status = power_on ? 0 : 2;
  77         uint32_t org_ip_request_cntl = 0;
  78
  79         if (hws->ctx->dc->debug.disable_dsc_power_gate)
  80                 return;
  81
  82         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
  83         if (org_ip_request_cntl == 0)
  84                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
  85
  86         switch (dsc_inst) {
  87         case 0: /* DSC0 */
  88                 REG_UPDATE(DOMAIN16_PG_CONFIG,
  89                                 DOMAIN_POWER_GATE, power_gate);
  90
  91                 REG_WAIT(DOMAIN16_PG_STATUS,
  92                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
  93                                 1, 1000);
  94                 break;
  95         case 1: /* DSC1 */
  96                 REG_UPDATE(DOMAIN17_PG_CONFIG,
  97                                 DOMAIN_POWER_GATE, power_gate);
  98
  99                 REG_WAIT(DOMAIN17_PG_STATUS,
 100                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 101                                 1, 1000);
 102                 break;
 103         case 2: /* DSC2 */
 104                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 105                                 DOMAIN_POWER_GATE, power_gate);
 106
 107                 REG_WAIT(DOMAIN18_PG_STATUS,
 108                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 109                                 1, 1000);
 110                 break;
 111         case 3: /* DSC3 */
 112                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 113                                 DOMAIN_POWER_GATE, power_gate);
 114
 115                 REG_WAIT(DOMAIN19_PG_STATUS,
 116                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 117                                 1, 1000);
 118                 break;
 119         default:
 120                 BREAK_TO_DEBUGGER();
 121                 break;
 122         }
 123
 124         if (org_ip_request_cntl == 0)
 125                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 126 }
 127
 128
 129 void dcn32_enable_power_gating_plane(
 130         struct dce_hwseq *hws,
 131         bool enable)
 132 {
 133         bool force_on = true; /* disable power gating */
 134
 135         if (enable)
 136                 force_on = false;
 137
 138         /* DCHUBP0/1/2/3 */
 139         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 140         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 141         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 142         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 143
 144         /* DCS0/1/2/3 */
 145         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 146         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 147         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 148         REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 149 }
 150
 151 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
 152 {
 153         uint32_t power_gate = power_on ? 0 : 1;
 154         uint32_t pwr_status = power_on ? 0 : 2;
 155
 156         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 157                 return;
 158
 159         if (REG(DOMAIN0_PG_CONFIG) == 0)
 160                 return;
 161
 162         switch (hubp_inst) {
 163         case 0:
 164                 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 165                 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 166                 break;
 167         case 1:
 168                 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 169                 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 170                 break;
 171         case 2:
 172                 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 173                 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 174                 break;
 175         case 3:
 176                 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 177                 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 178                 break;
 179         default:
 180                 BREAK_TO_DEBUGGER();
 181                 break;
 182         }
 183 }
 184
 185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
 186 {
 187         int i;
 188
 189     /* First, check no-memory-request case */
 190         for (i = 0; i < dc->current_state->stream_count; i++) {
 191                 if (dc->current_state->stream_status[i].plane_count)
 192                         /* Fail eligibility on a visible stream */
 193                         break;
 194         }
 195
 196         if (i == dc->current_state->stream_count)
 197                 return true;
 198
 199         return false;
 200 }
 201
 202
 203 /* This function loops through every surface that needs to be cached in CAB for SS,
 204  * and calculates the total number of ways required to store all surfaces (primary,
 205  * meta, cursor).
 206  */
 207 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
 208 {
 209         uint8_t i;
 210         int j;
 211         struct dc_stream_state *stream = NULL;
 212         struct dc_plane_state *plane = NULL;
 213         uint32_t cursor_size = 0;
 214         uint32_t total_lines = 0;
 215         uint32_t lines_per_way = 0;
 216         uint8_t num_ways = 0;
 217         uint8_t bytes_per_pixel = 0;
 218         uint8_t cursor_bpp = 0;
 219         uint16_t mblk_width = 0;
 220         uint16_t mblk_height = 0;
 221         uint16_t mall_alloc_width_blk_aligned = 0;
 222         uint16_t mall_alloc_height_blk_aligned = 0;
 223         uint16_t num_mblks = 0;
 224         uint32_t bytes_in_mall = 0;
 225         uint32_t cache_lines_used = 0;
 226         uint32_t cache_lines_per_plane = 0;
 227
 228         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 229                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 230
 231                 if (!pipe->stream || !pipe->plane_state ||
 232                                 pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED ||
 233                                 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
 234                         continue;
 235
 236                 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;
 237                 mblk_width = DCN3_2_MBLK_WIDTH;
 238                 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE;
 239
 240                 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) -
 241                  * FLOOR(vp_x_start, blk_width)
 242                  *
 243                  * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c
 244                  */
 245                 mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x +
 246                                 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) -
 247                                                 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width);
 248
 249                 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) -
 250                  * FLOOR(vp_y_start, blk_height)
 251                  *
 252                  * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c
 253                  */
 254                 mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y +
 255                                 pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) -
 256                                                 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height);
 257
 258                 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
 259                                 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
 260
 261                 /* For DCC:
 262                  * meta_num_mblk = CEILING(full_mblk_width_ub_l*full_mblk_height_ub_l*Bpe/256/mblk_bytes, 1)
 263                  */
 264                 if (pipe->plane_state->dcc.enable)
 265                         num_mblks += (mall_alloc_width_blk_aligned * mall_alloc_width_blk_aligned * bytes_per_pixel +
 266                                         (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES);
 267
 268                 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;
 269
 270                 /* (cache lines used is total bytes / cache_line size. Add +2 for worst case alignment
 271                  * (MALL is 64-byte aligned)
 272                  */
 273                 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2;
 274                 cache_lines_used += cache_lines_per_plane;
 275         }
 276
 277         // Include cursor size for CAB allocation
 278         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 279                 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j];
 280                 struct hubp *hubp = pipe->plane_res.hubp;
 281
 282                 if (pipe->stream && pipe->plane_state && hubp)
 283                         /* Find the cursor plane and use the exact size instead of
 284                         using the max for calculation */
 285
 286                 if (hubp->curs_attr.width > 0) {
 287                                 // Round cursor width to next multiple of 64
 288                                 cursor_size = (((hubp->curs_attr.width + 63) / 64) * 64) * hubp->curs_attr.height;
 289
 290                                 switch (pipe->stream->cursor_attributes.color_format) {
 291                                 case CURSOR_MODE_MONO:
 292                                         cursor_size /= 2;
 293                                         cursor_bpp = 4;
 294                                         break;
 295                                 case CURSOR_MODE_COLOR_1BIT_AND:
 296                                 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
 297                                 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
 298                                         cursor_size *= 4;
 299                                         cursor_bpp = 4;
 300                                         break;
 301
 302                                 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
 303                                 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
 304                                         cursor_size *= 8;
 305                                         cursor_bpp = 8;
 306                                         break;
 307                                 }
 308
 309                                 if (pipe->stream->cursor_position.enable && !dc->debug.alloc_extra_way_for_cursor &&
 310                                                 cursor_size > 16384) {
 311                                         /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1)
 312                                          */
 313                                         cache_lines_used += (((hubp->curs_attr.width * hubp->curs_attr.height * cursor_bpp +
 314                                                                                 DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / DCN3_2_MALL_MBLK_SIZE_BYTES) *
 315                                                                                 DCN3_2_MALL_MBLK_SIZE_BYTES) / dc->caps.cache_line_size + 2;
 316                                 }
 317                                 break;
 318                         }
 319         }
 320
 321         // Convert number of cache lines required to number of ways
 322         total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
 323         lines_per_way = total_lines / dc->caps.cache_num_ways;
 324         num_ways = cache_lines_used / lines_per_way;
 325
 326         if (cache_lines_used % lines_per_way > 0)
 327                 num_ways++;
 328
 329         for (i = 0; i < ctx->stream_count; i++) {
 330                 stream = ctx->streams[i];
 331                 for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
 332                         plane = ctx->stream_status[i].plane_states[j];
 333
 334                         if (stream->cursor_position.enable && plane &&
 335                                         dc->debug.alloc_extra_way_for_cursor &&
 336                                         cursor_size > 16384) {
 337                                 /* Cursor caching is not supported since it won't be on the same line.
 338                                  * So we need an extra line to accommodate it. With large cursors and a single 4k monitor
 339                                  * this case triggers corruption. If we're at the edge, then dont trigger display refresh
 340                                  * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp.
 341                                  */
 342                                 num_ways++;
 343                                 /* We only expect one cursor plane */
 344                                 break;
 345                         }
 346                 }
 347         }
 348         if (dc->debug.force_mall_ss_num_ways > 0) {
 349                 num_ways = dc->debug.force_mall_ss_num_ways;
 350         }
 351         return num_ways;
 352 }
 353
 354 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
 355 {
 356         union dmub_rb_cmd cmd;
 357         uint8_t ways, i;
 358         int j;
 359         bool mall_ss_unsupported = false;
 360         struct dc_plane_state *plane = NULL;
 361
 362         if (!dc->ctx->dmub_srv)
 363                 return false;
 364
 365         if (enable) {
 366                 if (dc->current_state) {
 367
 368                         /* 1. Check no memory request case for CAB.
 369                          * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
 370                          */
 371                         if (dcn32_check_no_memory_request_for_cab(dc)) {
 372                                 /* Enable no-memory-requests case */
 373                                 memset(&cmd, 0, sizeof(cmd));
 374                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 375                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
 376                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 377
 378                                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 379                                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 380
 381                                 return true;
 382                         }
 383
 384                         /* 2. Check if all surfaces can fit in CAB.
 385                          * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
 386                          * and configure HUBP's to fetch from MALL
 387                          */
 388                         ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
 389
 390                         /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
 391                          * or TMZ surface, don't try to enter MALL.
 392                          */
 393                         for (i = 0; i < dc->current_state->stream_count; i++) {
 394                                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
 395                                         plane = dc->current_state->stream_status[i].plane_states[j];
 396
 397                                         if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
 398                                                         plane->address.tmz_surface) {
 399                                                 mall_ss_unsupported = true;
 400                                                 break;
 401                                         }
 402                                 }
 403                                 if (mall_ss_unsupported)
 404                                         break;
 405                         }
 406                         if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
 407                                 memset(&cmd, 0, sizeof(cmd));
 408                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 409                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
 410                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 411                                 cmd.cab.cab_alloc_ways = ways;
 412
 413                                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 414                                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 415
 416                                 return true;
 417                         }
 418
 419                 }
 420                 return false;
 421         }
 422
 423         /* Disable CAB */
 424         memset(&cmd, 0, sizeof(cmd));
 425         cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 426         cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
 427         cmd.cab.header.payload_bytes =
 428                         sizeof(cmd.cab) - sizeof(cmd.cab.header);
 429
 430         dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 431         dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 432         dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
 433
 434         return true;
 435 }
 436
 437 /* Send DMCUB message with SubVP pipe info
 438  * - For each pipe in context, populate payload with required SubVP information
 439  *   if the pipe is using SubVP for MCLK switch
 440  * - This function must be called while the DMUB HW lock is acquired by driver
 441  */
 442 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
 443 {
 444         int i;
 445         bool enable_subvp = false;
 446
 447         if (!dc->ctx || !dc->ctx->dmub_srv)
 448                 return;
 449
 450         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 451                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 452
 453                 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
 454                                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
 455                         // There is at least 1 SubVP pipe, so enable SubVP
 456                         enable_subvp = true;
 457                         break;
 458                 }
 459         }
 460         dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
 461 }
 462
 463 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
 464  * 1. Any full update for any SubVP main pipe
 465  * 2. Any immediate flip for any SubVP pipe
 466  * 3. Any flip for DRR pipe
 467  * 4. If SubVP was previously in use (i.e. in old context)
 468  */
 469 void dcn32_subvp_pipe_control_lock(struct dc *dc,
 470                 struct dc_state *context,
 471                 bool lock,
 472                 bool should_lock_all_pipes,
 473                 struct pipe_ctx *top_pipe_to_program,
 474                 bool subvp_prev_use)
 475 {
 476         unsigned int i = 0;
 477         bool subvp_immediate_flip = false;
 478         bool subvp_in_use = false;
 479         struct pipe_ctx *pipe;
 480
 481         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 482                 pipe = &context->res_ctx.pipe_ctx[i];
 483
 484                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 485                         subvp_in_use = true;
 486                         break;
 487                 }
 488         }
 489
 490         if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
 491                 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN &&
 492                                 top_pipe_to_program->plane_state->flip_immediate)
 493                         subvp_immediate_flip = true;
 494         }
 495
 496         // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
 497         if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
 498                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
 499
 500                 if (!lock) {
 501                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 502                                 pipe = &context->res_ctx.pipe_ctx[i];
 503                                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
 504                                                 should_lock_all_pipes)
 505                                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
 506                         }
 507                 }
 508
 509                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
 510                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
 511                 hw_lock_cmd.bits.lock = lock;
 512                 hw_lock_cmd.bits.should_release = !lock;
 513                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 514         }
 515 }
 516
 517
 518 static bool dcn32_set_mpc_shaper_3dlut(
 519         struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
 520 {
 521         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 522         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 523         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 524         bool result = false;
 525
 526         const struct pwl_params *shaper_lut = NULL;
 527         //get the shaper lut params
 528         if (stream->func_shaper) {
 529                 if (stream->func_shaper->type == TF_TYPE_HWPWL)
 530                         shaper_lut = &stream->func_shaper->pwl;
 531                 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
 532                         cm_helper_translate_curve_to_hw_format(
 533                                         stream->func_shaper,
 534                                         &dpp_base->shaper_params, true);
 535                         shaper_lut = &dpp_base->shaper_params;
 536                 }
 537         }
 538
 539         if (stream->lut3d_func &&
 540                 stream->lut3d_func->state.bits.initialized == 1) {
 541
 542                 result = mpc->funcs->program_3dlut(mpc,
 543                                                                 &stream->lut3d_func->lut_3d,
 544                                                                 mpcc_id);
 545
 546                 result = mpc->funcs->program_shaper(mpc,
 547                                                                 shaper_lut,
 548                                                                 mpcc_id);
 549         }
 550
 551         return result;
 552 }
 553
 554 bool dcn32_set_mcm_luts(
 555         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 556 {
 557         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 558         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 559         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 560         bool result = true;
 561         struct pwl_params *lut_params = NULL;
 562
 563         // 1D LUT
 564         if (plane_state->blend_tf) {
 565                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 566                         lut_params = &plane_state->blend_tf->pwl;
 567                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 568                         cm_helper_translate_curve_to_hw_format(
 569                                         plane_state->blend_tf,
 570                                         &dpp_base->regamma_params, false);
 571                         lut_params = &dpp_base->regamma_params;
 572                 }
 573         }
 574         result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
 575
 576         // Shaper
 577         if (plane_state->in_shaper_func) {
 578                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 579                         lut_params = &plane_state->in_shaper_func->pwl;
 580                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 581                         // TODO: dpp_base replace
 582                         ASSERT(false);
 583                         cm_helper_translate_curve_to_hw_format(
 584                                         plane_state->in_shaper_func,
 585                                         &dpp_base->shaper_params, true);
 586                         lut_params = &dpp_base->shaper_params;
 587                 }
 588         }
 589
 590         result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
 591
 592         // 3D
 593         if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
 594                 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
 595         else
 596                 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
 597
 598         return result;
 599 }
 600
 601 bool dcn32_set_input_transfer_func(struct dc *dc,
 602                                 struct pipe_ctx *pipe_ctx,
 603                                 const struct dc_plane_state *plane_state)
 604 {
 605         struct dce_hwseq *hws = dc->hwseq;
 606         struct mpc *mpc = dc->res_pool->mpc;
 607         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 608
 609         enum dc_transfer_func_predefined tf;
 610         bool result = true;
 611         struct pwl_params *params = NULL;
 612
 613         if (mpc == NULL || plane_state == NULL)
 614                 return false;
 615
 616         tf = TRANSFER_FUNCTION_UNITY;
 617
 618         if (plane_state->in_transfer_func &&
 619                 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
 620                 tf = plane_state->in_transfer_func->tf;
 621
 622         dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
 623
 624         if (plane_state->in_transfer_func) {
 625                 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
 626                         params = &plane_state->in_transfer_func->pwl;
 627                 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
 628                         cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
 629                                         &dpp_base->degamma_params, false))
 630                         params = &dpp_base->degamma_params;
 631         }
 632
 633         result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
 634
 635         if (result &&
 636                         pipe_ctx->stream_res.opp &&
 637                         pipe_ctx->stream_res.opp->ctx &&
 638                         hws->funcs.set_mcm_luts)
 639                 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
 640
 641         return result;
 642 }
 643
 644 bool dcn32_set_output_transfer_func(struct dc *dc,
 645                                 struct pipe_ctx *pipe_ctx,
 646                                 const struct dc_stream_state *stream)
 647 {
 648         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 649         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 650         struct pwl_params *params = NULL;
 651         bool ret = false;
 652
 653         /* program OGAM or 3DLUT only for the top pipe*/
 654         if (pipe_ctx->top_pipe == NULL) {
 655                 /*program shaper and 3dlut in MPC*/
 656                 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
 657                 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 658                         if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 659                                 params = &stream->out_transfer_func->pwl;
 660                         else if (pipe_ctx->stream->out_transfer_func->type ==
 661                                         TF_TYPE_DISTRIBUTED_POINTS &&
 662                                         cm3_helper_translate_curve_to_hw_format(
 663                                         stream->out_transfer_func,
 664                                         &mpc->blender_params, false))
 665                                 params = &mpc->blender_params;
 666                         /* there are no ROM LUTs in OUTGAM */
 667                         if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 668                                 BREAK_TO_DEBUGGER();
 669                 }
 670         }
 671
 672         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 673         return ret;
 674 }
 675
 676 /* Program P-State force value according to if pipe is using SubVP or not:
 677  * 1. Reset P-State force on all pipes first
 678  * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
 679  */
 680 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context)
 681 {
 682         int i;
 683         int num_subvp = 0;
 684         /* Unforce p-state for each pipe
 685          */
 686         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 687                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 688                 struct hubp *hubp = pipe->plane_res.hubp;
 689
 690                 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 691                         hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
 692                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 693                         num_subvp++;
 694         }
 695
 696         if (num_subvp == 0)
 697                 return;
 698
 699         /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
 700          */
 701         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 702                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 703
 704                 // For SubVP + DRR, also force disallow on the DRR pipe
 705                 // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have
 706                 // to force once the vblank is stretched).
 707                 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN ||
 708                                 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) {
 709                         struct hubp *hubp = pipe->plane_res.hubp;
 710
 711                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 712                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
 713                 }
 714         }
 715 }
 716
 717 /* Update MALL_SEL register based on if pipe / plane
 718  * is a phantom pipe, main pipe, and if using MALL
 719  * for SS.
 720  */
 721 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
 722 {
 723         int i;
 724         unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
 725         bool cache_cursor = false;
 726
 727         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 728                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 729                 struct hubp *hubp = pipe->plane_res.hubp;
 730
 731                 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
 732                         //Round cursor width up to next multiple of 64
 733                         int cursor_width = ((hubp->curs_attr.width + 63) / 64) * 64;
 734                         int cursor_height = hubp->curs_attr.height;
 735                         int cursor_size = cursor_width * cursor_height;
 736
 737                         switch (hubp->curs_attr.color_format) {
 738                         case CURSOR_MODE_MONO:
 739                                 cursor_size /= 2;
 740                                 break;
 741                         case CURSOR_MODE_COLOR_1BIT_AND:
 742                         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
 743                         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
 744                                 cursor_size *= 4;
 745                                 break;
 746
 747                         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
 748                         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
 749                         default:
 750                                 cursor_size *= 8;
 751                                 break;
 752                         }
 753
 754                         if (cursor_size > 16384)
 755                                 cache_cursor = true;
 756
 757                         if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 758                                         hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
 759                         } else {
 760                                 // MALL not supported with Stereo3D
 761                                 hubp->funcs->hubp_update_mall_sel(hubp,
 762                                         num_ways <= dc->caps.cache_num_ways &&
 763                                         pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
 764                                         pipe->plane_state->address.type !=  PLN_ADDR_TYPE_GRPH_STEREO &&
 765                                         !pipe->plane_state->address.tmz_surface ? 2 : 0,
 766                                                         cache_cursor);
 767                         }
 768                 }
 769         }
 770 }
 771
 772 /* Program the sub-viewport pipe configuration after the main / phantom pipes
 773  * have been programmed in hardware.
 774  * 1. Update force P-State for all the main pipes (disallow P-state)
 775  * 2. Update MALL_SEL register
 776  * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
 777  */
 778 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
 779 {
 780         int i;
 781         struct dce_hwseq *hws = dc->hwseq;
 782
 783         // Don't force p-state disallow -- can't block dummy p-state
 784
 785         // Update MALL_SEL register for each pipe
 786         if (hws && hws->funcs.update_mall_sel)
 787                 hws->funcs.update_mall_sel(dc, context);
 788
 789         // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
 790         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 791                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 792                 struct hubp *hubp = pipe->plane_res.hubp;
 793
 794                 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
 795                         /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
 796                          *      - need to investigate single pipe MPO + SubVP case to
 797                          *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
 798                          *        when it should be 0 for MPO
 799                          */
 800                         if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 801                                 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
 802                         }
 803                 }
 804         }
 805 }
 806
 807 void dcn32_init_hw(struct dc *dc)
 808 {
 809         struct abm **abms = dc->res_pool->multiple_abms;
 810         struct dce_hwseq *hws = dc->hwseq;
 811         struct dc_bios *dcb = dc->ctx->dc_bios;
 812         struct resource_pool *res_pool = dc->res_pool;
 813         int i;
 814         int edp_num;
 815         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 816
 817         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 818                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 819
 820         // Initialize the dccg
 821         if (res_pool->dccg->funcs->dccg_init)
 822                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 823
 824         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 825                 hws->funcs.bios_golden_init(dc);
 826                 hws->funcs.disable_vga(dc->hwseq);
 827         }
 828
 829         // Set default OPTC memory power states
 830         if (dc->debug.enable_mem_low_power.bits.optc) {
 831                 // Shutdown when unassigned and light sleep in VBLANK
 832                 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
 833         }
 834
 835         if (dc->debug.enable_mem_low_power.bits.vga) {
 836                 // Power down VGA memory
 837                 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
 838         }
 839
 840         if (dc->ctx->dc_bios->fw_info_valid) {
 841                 res_pool->ref_clocks.xtalin_clock_inKhz =
 842                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 843
 844                 if (res_pool->dccg && res_pool->hubbub) {
 845                         (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
 846                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
 847                                         &res_pool->ref_clocks.dccg_ref_clock_inKhz);
 848
 849                         (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
 850                                         res_pool->ref_clocks.dccg_ref_clock_inKhz,
 851                                         &res_pool->ref_clocks.dchub_ref_clock_inKhz);
 852                 } else {
 853                         // Not all ASICs have DCCG sw component
 854                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 855                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 856                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 857                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 858                 }
 859         } else
 860                 ASSERT_CRITICAL(false);
 861
 862         for (i = 0; i < dc->link_count; i++) {
 863                 /* Power up AND update implementation according to the
 864                  * required signal (which may be different from the
 865                  * default signal on connector).
 866                  */
 867                 struct dc_link *link = dc->links[i];
 868
 869                 link->link_enc->funcs->hw_init(link->link_enc);
 870
 871                 /* Check for enabled DIG to identify enabled display */
 872                 if (link->link_enc->funcs->is_dig_enabled &&
 873                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 874                         link->link_status.link_active = true;
 875                         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
 876                         if (link->link_enc->funcs->fec_is_active &&
 877                                         link->link_enc->funcs->fec_is_active(link->link_enc))
 878                                 link->fec_state = dc_link_fec_enabled;
 879                 }
 880         }
 881
 882         /* Power gate DSCs */
 883         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
 884                 if (hws->funcs.dsc_pg_control != NULL)
 885                         hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
 886
 887         /* we want to turn off all dp displays before doing detection */
 888         dc_link_blank_all_dp_displays(dc);
 889
 890         /* If taking control over from VBIOS, we may want to optimize our first
 891          * mode set, so we need to skip powering down pipes until we know which
 892          * pipes we want to use.
 893          * Otherwise, if taking control is not possible, we need to power
 894          * everything down.
 895          */
 896         if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
 897                 hws->funcs.init_pipes(dc, dc->current_state);
 898                 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 899                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 900                                         !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 901         }
 902
 903         /* In headless boot cases, DIG may be turned
 904          * on which causes HW/SW discrepancies.
 905          * To avoid this, power down hardware on boot
 906          * if DIG is turned on and seamless boot not enabled
 907          */
 908         if (!dc->config.seamless_boot_edp_requested) {
 909                 struct dc_link *edp_links[MAX_NUM_EDP];
 910                 struct dc_link *edp_link;
 911
 912                 get_edp_links(dc, edp_links, &edp_num);
 913                 if (edp_num) {
 914                         for (i = 0; i < edp_num; i++) {
 915                                 edp_link = edp_links[i];
 916                                 if (edp_link->link_enc->funcs->is_dig_enabled &&
 917                                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
 918                                                 dc->hwss.edp_backlight_control &&
 919                                                 dc->hwss.power_down &&
 920                                                 dc->hwss.edp_power_control) {
 921                                         dc->hwss.edp_backlight_control(edp_link, false);
 922                                         dc->hwss.power_down(dc);
 923                                         dc->hwss.edp_power_control(edp_link, false);
 924                                 }
 925                         }
 926                 } else {
 927                         for (i = 0; i < dc->link_count; i++) {
 928                                 struct dc_link *link = dc->links[i];
 929
 930                                 if (link->link_enc->funcs->is_dig_enabled &&
 931                                                 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
 932                                                 dc->hwss.power_down) {
 933                                         dc->hwss.power_down(dc);
 934                                         break;
 935                                 }
 936
 937                         }
 938                 }
 939         }
 940
 941         for (i = 0; i < res_pool->audio_count; i++) {
 942                 struct audio *audio = res_pool->audios[i];
 943
 944                 audio->funcs->hw_init(audio);
 945         }
 946
 947         for (i = 0; i < dc->link_count; i++) {
 948                 struct dc_link *link = dc->links[i];
 949
 950                 if (link->panel_cntl)
 951                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
 952         }
 953
 954         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 955                 if (abms[i] != NULL && abms[i]->funcs != NULL)
 956                         abms[i]->funcs->abm_init(abms[i], backlight);
 957         }
 958
 959         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 960         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 961
 962         if (!dc->debug.disable_clock_gate) {
 963                 /* enable all DCN clock gating */
 964                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 965
 966                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 967
 968                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 969         }
 970         if (hws->funcs.enable_power_gating_plane)
 971                 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 972
 973         if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
 974                 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 975
 976         if (dc->clk_mgr->funcs->notify_wm_ranges)
 977                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 978
 979         if (dc->clk_mgr->funcs->set_hard_max_memclk)
 980                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 981
 982         if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 983                 dc->res_pool->hubbub->funcs->force_pstate_change_control(
 984                                 dc->res_pool->hubbub, false, false);
 985
 986         if (dc->res_pool->hubbub->funcs->init_crb)
 987                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 988
 989         // Get DMCUB capabilities
 990         if (dc->ctx->dmub_srv) {
 991                 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
 992                 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
 993         }
 994
 995         /* Enable support for ODM and windowed MPO if policy flag is set */
 996         if (dc->debug.enable_single_display_2to1_odm_policy)
 997                 dc->config.enable_windowed_mpo_odm = true;
 998 }
 999
1000 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
1001                 int opp_cnt)
1002 {
1003         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
1004         int flow_ctrl_cnt;
1005
1006         if (opp_cnt >= 2)
1007                 hblank_halved = true;
1008
1009         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
1010                         stream->timing.h_border_left -
1011                         stream->timing.h_border_right;
1012
1013         if (hblank_halved)
1014                 flow_ctrl_cnt /= 2;
1015
1016         /* ODM combine 4:1 case */
1017         if (opp_cnt == 4)
1018                 flow_ctrl_cnt /= 2;
1019
1020         return flow_ctrl_cnt;
1021 }
1022
1023 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
1024 {
1025         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
1026         struct dc_stream_state *stream = pipe_ctx->stream;
1027         struct pipe_ctx *odm_pipe;
1028         int opp_cnt = 1;
1029
1030         ASSERT(dsc);
1031         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1032                 opp_cnt++;
1033
1034         if (enable) {
1035                 struct dsc_config dsc_cfg;
1036                 struct dsc_optc_config dsc_optc_cfg;
1037                 enum optc_dsc_mode optc_dsc_mode;
1038
1039                 /* Enable DSC hw block */
1040                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1041                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1042                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1043                 dsc_cfg.color_depth = stream->timing.display_color_depth;
1044                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1045                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1046                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1047                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1048
1049                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1050                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1051                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1052                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1053
1054                         ASSERT(odm_dsc);
1055                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1056                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1057                 }
1058                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
1059                 dsc_cfg.pic_width *= opp_cnt;
1060
1061                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1062
1063                 /* Enable DSC in OPTC */
1064                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1065                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1066                                                         optc_dsc_mode,
1067                                                         dsc_optc_cfg.bytes_per_pixel,
1068                                                         dsc_optc_cfg.slice_width);
1069         } else {
1070                 /* disable DSC in OPTC */
1071                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1072                                 pipe_ctx->stream_res.tg,
1073                                 OPTC_DSC_DISABLED, 0, 0);
1074
1075                 /* disable DSC block */
1076                 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
1077                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1078                         ASSERT(odm_pipe->stream_res.dsc);
1079                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
1080                 }
1081         }
1082 }
1083
1084 /*
1085 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1086 * the OPPids which are used
1087 * */
1088 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1089 {
1090         unsigned int opp_count = 1;
1091         struct pipe_ctx *odm_pipe;
1092
1093         /* First get to the top pipe */
1094         for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1095                 ;
1096
1097         /* First pipe is always used */
1098         if (opp_instances)
1099                 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1100
1101         /* Find and count odm pipes, if any */
1102         for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1103                 if (opp_instances)
1104                         opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1105                 opp_count++;
1106         }
1107
1108         return opp_count;
1109 }
1110
1111 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1112 {
1113         struct pipe_ctx *odm_pipe;
1114         int opp_cnt = 0;
1115         int opp_inst[MAX_PIPES] = {0};
1116         bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
1117         struct mpc_dwb_flow_control flow_control;
1118         struct mpc *mpc = dc->res_pool->mpc;
1119         int i;
1120
1121         opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1122
1123         if (opp_cnt > 1)
1124                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1125                                 pipe_ctx->stream_res.tg,
1126                                 opp_inst, opp_cnt,
1127                                 &pipe_ctx->stream->timing);
1128         else
1129                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1130                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1131
1132         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
1133         flow_control.flow_ctrl_mode = 0;
1134         flow_control.flow_ctrl_cnt0 = 0x80;
1135         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
1136         if (mpc->funcs->set_out_rate_control) {
1137                 for (i = 0; i < opp_cnt; ++i) {
1138                         mpc->funcs->set_out_rate_control(
1139                                         mpc, opp_inst[i],
1140                                         true,
1141                                         rate_control_2x_pclk,
1142                                         &flow_control);
1143                 }
1144         }
1145
1146         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1147                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1148                                 odm_pipe->stream_res.opp,
1149                                 true);
1150         }
1151
1152         // Don't program pixel clock after link is already enabled
1153 /*      if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1154                         pipe_ctx->clock_source,
1155                         &pipe_ctx->stream_res.pix_clk_params,
1156                         &pipe_ctx->pll_settings)) {
1157                 BREAK_TO_DEBUGGER();
1158         }*/
1159
1160         if (pipe_ctx->stream_res.dsc)
1161                 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1162 }
1163
1164 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1165 {
1166         struct dc_stream_state *stream = pipe_ctx->stream;
1167         unsigned int odm_combine_factor = 0;
1168         bool two_pix_per_container = false;
1169
1170         // For phantom pipes, use the same programming as the main pipes
1171         if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1172                 stream = pipe_ctx->stream->mall_stream_config.paired_stream;
1173         }
1174         two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1175         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1176
1177         if (pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
1178                 return odm_combine_factor;
1179
1180         if (is_dp_128b_132b_signal(pipe_ctx)) {
1181                 *k2_div = PIXEL_RATE_DIV_BY_1;
1182         } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
1183                 *k1_div = PIXEL_RATE_DIV_BY_1;
1184                 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1185                         *k2_div = PIXEL_RATE_DIV_BY_2;
1186                 else
1187                         *k2_div = PIXEL_RATE_DIV_BY_4;
1188         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1189                 if (two_pix_per_container) {
1190                         *k1_div = PIXEL_RATE_DIV_BY_1;
1191                         *k2_div = PIXEL_RATE_DIV_BY_2;
1192                 } else {
1193                         *k1_div = PIXEL_RATE_DIV_BY_1;
1194                         *k2_div = PIXEL_RATE_DIV_BY_4;
1195                         if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1196                                 *k2_div = PIXEL_RATE_DIV_BY_2;
1197                 }
1198         }
1199
1200         if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1201                 ASSERT(false);
1202
1203         return odm_combine_factor;
1204 }
1205
1206 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1207 {
1208         uint32_t pix_per_cycle = 1;
1209         uint32_t odm_combine_factor = 1;
1210
1211         if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1212                 return;
1213
1214         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1215         if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1216                 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1217                 pix_per_cycle = 2;
1218
1219         if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1220                 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1221                                 pix_per_cycle);
1222 }
1223
1224 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1225                 struct dc_link_settings *link_settings)
1226 {
1227         struct encoder_unblank_param params = {0};
1228         struct dc_stream_state *stream = pipe_ctx->stream;
1229         struct dc_link *link = stream->link;
1230         struct dce_hwseq *hws = link->dc->hwseq;
1231         struct pipe_ctx *odm_pipe;
1232         uint32_t pix_per_cycle = 1;
1233
1234         params.opp_cnt = 1;
1235         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1236                 params.opp_cnt++;
1237
1238         /* only 3 items below are used by unblank */
1239         params.timing = pipe_ctx->stream->timing;
1240
1241         params.link_settings.link_rate = link_settings->link_rate;
1242
1243         if (is_dp_128b_132b_signal(pipe_ctx)) {
1244                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1245                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1246                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1247                                 pipe_ctx->stream_res.tg->inst);
1248         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1249                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1250                         || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {
1251                         params.timing.pix_clk_100hz /= 2;
1252                         pix_per_cycle = 2;
1253                 }
1254                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1255                                 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1256                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1257         }
1258
1259         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1260                 hws->funcs.edp_backlight_control(link, true);
1261 }
1262
1263 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1264 {
1265         struct dc *dc = pipe_ctx->stream->ctx->dc;
1266
1267         if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
1268                 return false;
1269
1270         if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) &&
1271                 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1272                 return true;
1273         return false;
1274 }
1275
1276 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
1277 {
1278         /* There are use cases where SYMCLK is referenced by OTG. For instance
1279          * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
1280          * However current link interface will power off PHY when disabling link
1281          * output. This will turn off SYMCLK generated by PHY. The workaround is
1282          * to identify such case where SYMCLK is still in use by OTG when we
1283          * power off PHY. When this is detected, we will temporarily power PHY
1284          * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
1285          * program_pix_clk interface. When OTG is disabled, we will then power
1286          * off PHY by calling disable link output again.
1287          *
1288          * In future dcn generations, we plan to rework transmitter control
1289          * interface so that we could have an option to set SYMCLK ON TX OFF
1290          * state in one step without this workaround
1291          */
1292
1293         struct dc *dc = link->ctx->dc;
1294         struct pipe_ctx *pipe_ctx = NULL;
1295         uint8_t i;
1296
1297         if (link->phy_state.symclk_ref_cnts.otg > 0) {
1298                 for (i = 0; i < MAX_PIPES; i++) {
1299                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1300                         if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
1301                                 pipe_ctx->clock_source->funcs->program_pix_clk(
1302                                                 pipe_ctx->clock_source,
1303                                                 &pipe_ctx->stream_res.pix_clk_params,
1304                                                 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1305                                                 &pipe_ctx->pll_settings);
1306                                 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1307                                 break;
1308                         }
1309                 }
1310         }
1311 }
1312
1313 void dcn32_disable_link_output(struct dc_link *link,
1314                 const struct link_resource *link_res,
1315                 enum signal_type signal)
1316 {
1317         struct dc *dc = link->ctx->dc;
1318         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1319         struct dmcu *dmcu = dc->res_pool->dmcu;
1320
1321         if (signal == SIGNAL_TYPE_EDP &&
1322                         link->dc->hwss.edp_backlight_control)
1323                 link->dc->hwss.edp_backlight_control(link, false);
1324         else if (dmcu != NULL && dmcu->funcs->lock_phy)
1325                 dmcu->funcs->lock_phy(dmcu);
1326
1327         link_hwss->disable_link_output(link, link_res, signal);
1328         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1329
1330         if (signal == SIGNAL_TYPE_EDP &&
1331                         link->dc->hwss.edp_backlight_control)
1332                 link->dc->hwss.edp_power_control(link, false);
1333         else if (dmcu != NULL && dmcu->funcs->lock_phy)
1334                 dmcu->funcs->unlock_phy(dmcu);
1335
1336         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
1337
1338         apply_symclk_on_tx_off_wa(link);
1339 }
1340
1341 /* For SubVP the main pipe can have a viewport position change
1342  * without a full update. In this case we must also update the
1343  * viewport positions for the phantom pipe accordingly.
1344  */
1345 void dcn32_update_phantom_vp_position(struct dc *dc,
1346                 struct dc_state *context,
1347                 struct pipe_ctx *phantom_pipe)
1348 {
1349         uint32_t i;
1350         struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
1351
1352         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1353                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1354
1355                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
1356                                 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) {
1357                         if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
1358
1359                                 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
1360                                 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
1361                                 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
1362                                 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
1363                                 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
1364
1365                                 phantom_pipe->plane_state->update_flags.bits.position_change = 1;
1366                                 resource_build_scaling_params(phantom_pipe);
1367                                 return;
1368                         }
1369                 }
1370         }
1371 }
1372
1373 bool dcn32_dsc_pg_status(
1374                 struct dce_hwseq *hws,
1375                 unsigned int dsc_inst)
1376 {
1377         uint32_t pwr_status = 0;
1378
1379         switch (dsc_inst) {
1380         case 0: /* DSC0 */
1381                 REG_GET(DOMAIN16_PG_STATUS,
1382                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1383                 break;
1384         case 1: /* DSC1 */
1385
1386                 REG_GET(DOMAIN17_PG_STATUS,
1387                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1388                 break;
1389         case 2: /* DSC2 */
1390                 REG_GET(DOMAIN18_PG_STATUS,
1391                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1392                 break;
1393         case 3: /* DSC3 */
1394                 REG_GET(DOMAIN19_PG_STATUS,
1395                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1396                 break;
1397         default:
1398                 BREAK_TO_DEBUGGER();
1399                 break;
1400         }
1401
1402         return pwr_status == 0 ? true : false;
1403 }
1404
1405 void dcn32_update_dsc_pg(struct dc *dc,
1406                 struct dc_state *context,
1407                 bool safe_to_disable)
1408 {
1409         struct dce_hwseq *hws = dc->hwseq;
1410         int i;
1411
1412         for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1413                 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1414                 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
1415
1416                 if (context->res_ctx.is_dsc_acquired[i]) {
1417                         if (!is_dsc_ungated) {
1418                                 hws->funcs.dsc_pg_control(hws, dsc->inst, true);
1419                         }
1420                 } else if (safe_to_disable) {
1421                         if (is_dsc_ungated) {
1422                                 hws->funcs.dsc_pg_control(hws, dsc->inst, false);
1423                         }
1424                 }
1425         }
1426 }