drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn31_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn30/dcn30_hubbub.h"
  41 #include "dcn31/dcn31_hubbub.h"
  42 #include "dcn30/dcn30_mpc.h"
  43 #include "dcn31/dcn31_hubp.h"
  44 #include "irq/dcn31/irq_service_dcn31.h"
  45 #include "dcn30/dcn30_dpp.h"
  46 #include "dcn31/dcn31_optc.h"
  47 #include "dcn20/dcn20_hwseq.h"
  48 #include "dcn30/dcn30_hwseq.h"
  49 #include "dce110/dce110_hw_sequencer.h"
  50 #include "dcn30/dcn30_opp.h"
  51 #include "dcn20/dcn20_dsc.h"
  52 #include "dcn30/dcn30_vpg.h"
  53 #include "dcn30/dcn30_afmt.h"
  54 #include "dcn30/dcn30_dio_stream_encoder.h"
  55 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  56 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  57 #include "dcn31/dcn31_apg.h"
  58 #include "dcn31/dcn31_dio_link_encoder.h"
  59 #include "dcn31/dcn31_vpg.h"
  60 #include "dcn31/dcn31_afmt.h"
  61 #include "dce/dce_clock_source.h"
  62 #include "dce/dce_audio.h"
  63 #include "dce/dce_hwseq.h"
  64 #include "clk_mgr.h"
  65 #include "virtual/virtual_stream_encoder.h"
  66 #include "dce110/dce110_resource.h"
  67 #include "dml/display_mode_vba.h"
  68 #include "dcn31/dcn31_dccg.h"
  69 #include "dcn10/dcn10_resource.h"
  70 #include "dcn31_panel_cntl.h"
  71
  72 #include "dcn30/dcn30_dwb.h"
  73 #include "dcn30/dcn30_mmhubbub.h"
  74
  75 // TODO: change include headers /amd/include/asic_reg after upstream
  76 #include "yellow_carp_offset.h"
  77 #include "dcn/dcn_3_1_2_offset.h"
  78 #include "dcn/dcn_3_1_2_sh_mask.h"
  79 #include "nbio/nbio_7_2_0_offset.h"
  80 #include "dpcs/dpcs_4_2_0_offset.h"
  81 #include "dpcs/dpcs_4_2_0_sh_mask.h"
  82 #include "mmhub/mmhub_2_3_0_offset.h"
  83 #include "mmhub/mmhub_2_3_0_sh_mask.h"
  84
  85
  86 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
  87 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
  88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
  89 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
  90
  91 #include "reg_helper.h"
  92 #include "dce/dmub_abm.h"
  93 #include "dce/dmub_psr.h"
  94 #include "dce/dce_aux.h"
  95 #include "dce/dce_i2c.h"
  96
  97 #include "dml/dcn30/display_mode_vba_30.h"
  98 #include "vm_helper.h"
  99 #include "dcn20/dcn20_vmid.h"
 100
 101 #include "link_enc_cfg.h"
 102
 103 #define DC_LOGGER_INIT(logger)
 104
 105 #define DCN3_1_DEFAULT_DET_SIZE 384
 106
 107 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
 108         .gpuvm_enable = 1,
 109         .gpuvm_max_page_table_levels = 1,
 110         .hostvm_enable = 1,
 111         .hostvm_max_page_table_levels = 2,
 112         .rob_buffer_size_kbytes = 64,
 113         .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
 114         .config_return_buffer_size_in_kbytes = 1792,
 115         .compressed_buffer_segment_size_in_kbytes = 64,
 116         .meta_fifo_size_in_kentries = 32,
 117         .zero_size_buffer_entries = 512,
 118         .compbuf_reserved_space_64b = 256,
 119         .compbuf_reserved_space_zs = 64,
 120         .dpp_output_buffer_pixels = 2560,
 121         .opp_output_buffer_lines = 1,
 122         .pixel_chunk_size_kbytes = 8,
 123         .meta_chunk_size_kbytes = 2,
 124         .min_meta_chunk_size_bytes = 256,
 125         .writeback_chunk_size_kbytes = 8,
 126         .ptoi_supported = false,
 127         .num_dsc = 3,
 128         .maximum_dsc_bits_per_component = 10,
 129         .dsc422_native_support = false,
 130         .is_line_buffer_bpp_fixed = true,
 131         .line_buffer_fixed_bpp = 48,
 132         .line_buffer_size_bits = 789504,
 133         .max_line_buffer_lines = 12,
 134         .writeback_interface_buffer_size_kbytes = 90,
 135         .max_num_dpp = 4,
 136         .max_num_otg = 4,
 137         .max_num_hdmi_frl_outputs = 1,
 138         .max_num_wb = 1,
 139         .max_dchub_pscl_bw_pix_per_clk = 4,
 140         .max_pscl_lb_bw_pix_per_clk = 2,
 141         .max_lb_vscl_bw_pix_per_clk = 4,
 142         .max_vscl_hscl_bw_pix_per_clk = 4,
 143         .max_hscl_ratio = 6,
 144         .max_vscl_ratio = 6,
 145         .max_hscl_taps = 8,
 146         .max_vscl_taps = 8,
 147         .dpte_buffer_size_in_pte_reqs_luma = 64,
 148         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 149         .dispclk_ramp_margin_percent = 1,
 150         .max_inter_dcn_tile_repeaters = 8,
 151         .cursor_buffer_size = 16,
 152         .cursor_chunk_size = 2,
 153         .writeback_line_buffer_buffer_size = 0,
 154         .writeback_min_hscl_ratio = 1,
 155         .writeback_min_vscl_ratio = 1,
 156         .writeback_max_hscl_ratio = 1,
 157         .writeback_max_vscl_ratio = 1,
 158         .writeback_max_hscl_taps = 1,
 159         .writeback_max_vscl_taps = 1,
 160         .dppclk_delay_subtotal = 46,
 161         .dppclk_delay_scl = 50,
 162         .dppclk_delay_scl_lb_only = 16,
 163         .dppclk_delay_cnvc_formatter = 27,
 164         .dppclk_delay_cnvc_cursor = 6,
 165         .dispclk_delay_subtotal = 119,
 166         .dynamic_metadata_vm_enabled = false,
 167         .odm_combine_4to1_supported = false,
 168         .dcc_supported = true,
 169 };
 170
 171 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
 172                 /*TODO: correct dispclk/dppclk voltage level determination*/
 173         .clock_limits = {
 174                 {
 175                         .state = 0,
 176                         .dispclk_mhz = 1200.0,
 177                         .dppclk_mhz = 1200.0,
 178                         .phyclk_mhz = 600.0,
 179                         .phyclk_d18_mhz = 667.0,
 180                         .dscclk_mhz = 186.0,
 181                         .dtbclk_mhz = 625.0,
 182                 },
 183                 {
 184                         .state = 1,
 185                         .dispclk_mhz = 1200.0,
 186                         .dppclk_mhz = 1200.0,
 187                         .phyclk_mhz = 810.0,
 188                         .phyclk_d18_mhz = 667.0,
 189                         .dscclk_mhz = 209.0,
 190                         .dtbclk_mhz = 625.0,
 191                 },
 192                 {
 193                         .state = 2,
 194                         .dispclk_mhz = 1200.0,
 195                         .dppclk_mhz = 1200.0,
 196                         .phyclk_mhz = 810.0,
 197                         .phyclk_d18_mhz = 667.0,
 198                         .dscclk_mhz = 209.0,
 199                         .dtbclk_mhz = 625.0,
 200                 },
 201                 {
 202                         .state = 3,
 203                         .dispclk_mhz = 1200.0,
 204                         .dppclk_mhz = 1200.0,
 205                         .phyclk_mhz = 810.0,
 206                         .phyclk_d18_mhz = 667.0,
 207                         .dscclk_mhz = 371.0,
 208                         .dtbclk_mhz = 625.0,
 209                 },
 210                 {
 211                         .state = 4,
 212                         .dispclk_mhz = 1200.0,
 213                         .dppclk_mhz = 1200.0,
 214                         .phyclk_mhz = 810.0,
 215                         .phyclk_d18_mhz = 667.0,
 216                         .dscclk_mhz = 417.0,
 217                         .dtbclk_mhz = 625.0,
 218                 },
 219         },
 220         .num_states = 5,
 221         .sr_exit_time_us = 9.0,
 222         .sr_enter_plus_exit_time_us = 11.0,
 223         .sr_exit_z8_time_us = 442.0,
 224         .sr_enter_plus_exit_z8_time_us = 560.0,
 225         .writeback_latency_us = 12.0,
 226         .dram_channel_width_bytes = 4,
 227         .round_trip_ping_latency_dcfclk_cycles = 106,
 228         .urgent_latency_pixel_data_only_us = 4.0,
 229         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 230         .urgent_latency_vm_data_only_us = 4.0,
 231         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 232         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 233         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 234         .pct_ideal_sdp_bw_after_urgent = 80.0,
 235         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 236         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 237         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 238         .max_avg_sdp_bw_use_normal_percent = 60.0,
 239         .max_avg_dram_bw_use_normal_percent = 60.0,
 240         .fabric_datapath_to_dcn_data_return_bytes = 32,
 241         .return_bus_width_bytes = 64,
 242         .downspread_percent = 0.38,
 243         .dcn_downspread_percent = 0.5,
 244         .gpuvm_min_page_size_bytes = 4096,
 245         .hostvm_min_page_size_bytes = 4096,
 246         .do_urgent_latency_adjustment = false,
 247         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 248         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 249 };
 250
 251 enum dcn31_clk_src_array_id {
 252         DCN31_CLK_SRC_PLL0,
 253         DCN31_CLK_SRC_PLL1,
 254         DCN31_CLK_SRC_PLL2,
 255         DCN31_CLK_SRC_PLL3,
 256         DCN31_CLK_SRC_PLL4,
 257         DCN30_CLK_SRC_TOTAL
 258 };
 259
 260 /* begin *********************
 261  * macros to expend register list macro defined in HW object header file
 262  */
 263
 264 /* DCN */
 265 /* TODO awful hack. fixup dcn20_dwb.h */
 266 #undef BASE_INNER
 267 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 268
 269 #define BASE(seg) BASE_INNER(seg)
 270
 271 #define SR(reg_name)\
 272                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 273                                         reg ## reg_name
 274
 275 #define SRI(reg_name, block, id)\
 276         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 277                                         reg ## block ## id ## _ ## reg_name
 278
 279 #define SRI2(reg_name, block, id)\
 280         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 281                                         reg ## reg_name
 282
 283 #define SRIR(var_name, reg_name, block, id)\
 284         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 285                                         reg ## block ## id ## _ ## reg_name
 286
 287 #define SRII(reg_name, block, id)\
 288         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 289                                         reg ## block ## id ## _ ## reg_name
 290
 291 #define SRII_MPC_RMU(reg_name, block, id)\
 292         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 293                                         reg ## block ## id ## _ ## reg_name
 294
 295 #define SRII_DWB(reg_name, temp_name, block, id)\
 296         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 297                                         reg ## block ## id ## _ ## temp_name
 298
 299 #define DCCG_SRII(reg_name, block, id)\
 300         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 301                                         reg ## block ## id ## _ ## reg_name
 302
 303 #define VUPDATE_SRII(reg_name, block, id)\
 304         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 305                                         reg ## reg_name ## _ ## block ## id
 306
 307 /* NBIO */
 308 #define NBIO_BASE_INNER(seg) \
 309         NBIO_BASE__INST0_SEG ## seg
 310
 311 #define NBIO_BASE(seg) \
 312         NBIO_BASE_INNER(seg)
 313
 314 #define NBIO_SR(reg_name)\
 315                 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 316                                         regBIF_BX1_ ## reg_name
 317
 318 /* MMHUB */
 319 #define MMHUB_BASE_INNER(seg) \
 320         MMHUB_BASE__INST0_SEG ## seg
 321
 322 #define MMHUB_BASE(seg) \
 323         MMHUB_BASE_INNER(seg)
 324
 325 #define MMHUB_SR(reg_name)\
 326                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
 327                                         mm ## reg_name
 328
 329 /* CLOCK */
 330 #define CLK_BASE_INNER(seg) \
 331         CLK_BASE__INST0_SEG ## seg
 332
 333 #define CLK_BASE(seg) \
 334         CLK_BASE_INNER(seg)
 335
 336 #define CLK_SRI(reg_name, block, inst)\
 337         .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 338                                         reg ## block ## _ ## inst ## _ ## reg_name
 339
 340
 341 static const struct bios_registers bios_regs = {
 342                 NBIO_SR(BIOS_SCRATCH_3),
 343                 NBIO_SR(BIOS_SCRATCH_6)
 344 };
 345
 346 #define clk_src_regs(index, pllid)\
 347 [index] = {\
 348         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 349 }
 350
 351 static const struct dce110_clk_src_regs clk_src_regs[] = {
 352         clk_src_regs(0, A),
 353         clk_src_regs(1, B),
 354         clk_src_regs(2, C),
 355         clk_src_regs(3, D),
 356         clk_src_regs(4, E)
 357 };
 358
 359 static const struct dce110_clk_src_shift cs_shift = {
 360                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 361 };
 362
 363 static const struct dce110_clk_src_mask cs_mask = {
 364                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 365 };
 366
 367 #define abm_regs(id)\
 368 [id] = {\
 369                 ABM_DCN302_REG_LIST(id)\
 370 }
 371
 372 static const struct dce_abm_registers abm_regs[] = {
 373                 abm_regs(0),
 374                 abm_regs(1),
 375                 abm_regs(2),
 376                 abm_regs(3),
 377 };
 378
 379 static const struct dce_abm_shift abm_shift = {
 380                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 381 };
 382
 383 static const struct dce_abm_mask abm_mask = {
 384                 ABM_MASK_SH_LIST_DCN30(_MASK)
 385 };
 386
 387 #define audio_regs(id)\
 388 [id] = {\
 389                 AUD_COMMON_REG_LIST(id)\
 390 }
 391
 392 static const struct dce_audio_registers audio_regs[] = {
 393         audio_regs(0),
 394         audio_regs(1),
 395         audio_regs(2),
 396         audio_regs(3),
 397         audio_regs(4),
 398         audio_regs(5),
 399         audio_regs(6)
 400 };
 401
 402 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 403                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 404                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 405                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 406
 407 static const struct dce_audio_shift audio_shift = {
 408                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 409 };
 410
 411 static const struct dce_audio_mask audio_mask = {
 412                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 413 };
 414
 415 #define vpg_regs(id)\
 416 [id] = {\
 417         VPG_DCN31_REG_LIST(id)\
 418 }
 419
 420 static const struct dcn31_vpg_registers vpg_regs[] = {
 421         vpg_regs(0),
 422         vpg_regs(1),
 423         vpg_regs(2),
 424         vpg_regs(3),
 425         vpg_regs(4),
 426         vpg_regs(5),
 427         vpg_regs(6),
 428         vpg_regs(7),
 429         vpg_regs(8),
 430         vpg_regs(9),
 431 };
 432
 433 static const struct dcn31_vpg_shift vpg_shift = {
 434         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 435 };
 436
 437 static const struct dcn31_vpg_mask vpg_mask = {
 438         DCN31_VPG_MASK_SH_LIST(_MASK)
 439 };
 440
 441 #define afmt_regs(id)\
 442 [id] = {\
 443         AFMT_DCN31_REG_LIST(id)\
 444 }
 445
 446 static const struct dcn31_afmt_registers afmt_regs[] = {
 447         afmt_regs(0),
 448         afmt_regs(1),
 449         afmt_regs(2),
 450         afmt_regs(3),
 451         afmt_regs(4),
 452         afmt_regs(5)
 453 };
 454
 455 static const struct dcn31_afmt_shift afmt_shift = {
 456         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 457 };
 458
 459 static const struct dcn31_afmt_mask afmt_mask = {
 460         DCN31_AFMT_MASK_SH_LIST(_MASK)
 461 };
 462
 463 #define apg_regs(id)\
 464 [id] = {\
 465         APG_DCN31_REG_LIST(id)\
 466 }
 467
 468 static const struct dcn31_apg_registers apg_regs[] = {
 469         apg_regs(0),
 470         apg_regs(1),
 471         apg_regs(2),
 472         apg_regs(3)
 473 };
 474
 475 static const struct dcn31_apg_shift apg_shift = {
 476         DCN31_APG_MASK_SH_LIST(__SHIFT)
 477 };
 478
 479 static const struct dcn31_apg_mask apg_mask = {
 480                 DCN31_APG_MASK_SH_LIST(_MASK)
 481 };
 482
 483 #define stream_enc_regs(id)\
 484 [id] = {\
 485         SE_DCN3_REG_LIST(id)\
 486 }
 487
 488 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 489         stream_enc_regs(0),
 490         stream_enc_regs(1),
 491         stream_enc_regs(2),
 492         stream_enc_regs(3),
 493         stream_enc_regs(4)
 494 };
 495
 496 static const struct dcn10_stream_encoder_shift se_shift = {
 497                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 498 };
 499
 500 static const struct dcn10_stream_encoder_mask se_mask = {
 501                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 502 };
 503
 504
 505 #define aux_regs(id)\
 506 [id] = {\
 507         DCN2_AUX_REG_LIST(id)\
 508 }
 509
 510 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 511                 aux_regs(0),
 512                 aux_regs(1),
 513                 aux_regs(2),
 514                 aux_regs(3),
 515                 aux_regs(4)
 516 };
 517
 518 #define hpd_regs(id)\
 519 [id] = {\
 520         HPD_REG_LIST(id)\
 521 }
 522
 523 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 524                 hpd_regs(0),
 525                 hpd_regs(1),
 526                 hpd_regs(2),
 527                 hpd_regs(3),
 528                 hpd_regs(4)
 529 };
 530
 531 #define link_regs(id, phyid)\
 532 [id] = {\
 533         LE_DCN31_REG_LIST(id), \
 534         UNIPHY_DCN2_REG_LIST(phyid), \
 535         DPCS_DCN31_REG_LIST(id), \
 536 }
 537
 538 static const struct dce110_aux_registers_shift aux_shift = {
 539         DCN_AUX_MASK_SH_LIST(__SHIFT)
 540 };
 541
 542 static const struct dce110_aux_registers_mask aux_mask = {
 543         DCN_AUX_MASK_SH_LIST(_MASK)
 544 };
 545
 546 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 547         link_regs(0, A),
 548         link_regs(1, B),
 549         link_regs(2, C),
 550         link_regs(3, D),
 551         link_regs(4, E)
 552 };
 553
 554 static const struct dcn10_link_enc_shift le_shift = {
 555         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 556         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 557 };
 558
 559 static const struct dcn10_link_enc_mask le_mask = {
 560         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 561         DPCS_DCN31_MASK_SH_LIST(_MASK)
 562 };
 563
 564 #define hpo_dp_stream_encoder_reg_list(id)\
 565 [id] = {\
 566         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 567 }
 568
 569 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 570         hpo_dp_stream_encoder_reg_list(0),
 571         hpo_dp_stream_encoder_reg_list(1),
 572         hpo_dp_stream_encoder_reg_list(2),
 573         hpo_dp_stream_encoder_reg_list(3),
 574 };
 575
 576 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 577         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 578 };
 579
 580 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 581         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 582 };
 583
 584 #define hpo_dp_link_encoder_reg_list(id)\
 585 [id] = {\
 586         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 587         DCN3_1_RDPCSTX_REG_LIST(0),\
 588         DCN3_1_RDPCSTX_REG_LIST(1),\
 589         DCN3_1_RDPCSTX_REG_LIST(2),\
 590         DCN3_1_RDPCSTX_REG_LIST(3),\
 591         DCN3_1_RDPCSTX_REG_LIST(4)\
 592 }
 593
 594 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 595         hpo_dp_link_encoder_reg_list(0),
 596         hpo_dp_link_encoder_reg_list(1),
 597 };
 598
 599 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 600         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 601 };
 602
 603 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 604         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 605 };
 606
 607 #define dpp_regs(id)\
 608 [id] = {\
 609         DPP_REG_LIST_DCN30(id),\
 610 }
 611
 612 static const struct dcn3_dpp_registers dpp_regs[] = {
 613         dpp_regs(0),
 614         dpp_regs(1),
 615         dpp_regs(2),
 616         dpp_regs(3)
 617 };
 618
 619 static const struct dcn3_dpp_shift tf_shift = {
 620                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 621 };
 622
 623 static const struct dcn3_dpp_mask tf_mask = {
 624                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 625 };
 626
 627 #define opp_regs(id)\
 628 [id] = {\
 629         OPP_REG_LIST_DCN30(id),\
 630 }
 631
 632 static const struct dcn20_opp_registers opp_regs[] = {
 633         opp_regs(0),
 634         opp_regs(1),
 635         opp_regs(2),
 636         opp_regs(3)
 637 };
 638
 639 static const struct dcn20_opp_shift opp_shift = {
 640         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 641 };
 642
 643 static const struct dcn20_opp_mask opp_mask = {
 644         OPP_MASK_SH_LIST_DCN20(_MASK)
 645 };
 646
 647 #define aux_engine_regs(id)\
 648 [id] = {\
 649         AUX_COMMON_REG_LIST0(id), \
 650         .AUXN_IMPCAL = 0, \
 651         .AUXP_IMPCAL = 0, \
 652         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 653 }
 654
 655 static const struct dce110_aux_registers aux_engine_regs[] = {
 656                 aux_engine_regs(0),
 657                 aux_engine_regs(1),
 658                 aux_engine_regs(2),
 659                 aux_engine_regs(3),
 660                 aux_engine_regs(4)
 661 };
 662
 663 #define dwbc_regs_dcn3(id)\
 664 [id] = {\
 665         DWBC_COMMON_REG_LIST_DCN30(id),\
 666 }
 667
 668 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 669         dwbc_regs_dcn3(0),
 670 };
 671
 672 static const struct dcn30_dwbc_shift dwbc30_shift = {
 673         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 674 };
 675
 676 static const struct dcn30_dwbc_mask dwbc30_mask = {
 677         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 678 };
 679
 680 #define mcif_wb_regs_dcn3(id)\
 681 [id] = {\
 682         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 683 }
 684
 685 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 686         mcif_wb_regs_dcn3(0)
 687 };
 688
 689 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 690         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 691 };
 692
 693 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 694         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 695 };
 696
 697 #define dsc_regsDCN20(id)\
 698 [id] = {\
 699         DSC_REG_LIST_DCN20(id)\
 700 }
 701
 702 static const struct dcn20_dsc_registers dsc_regs[] = {
 703         dsc_regsDCN20(0),
 704         dsc_regsDCN20(1),
 705         dsc_regsDCN20(2)
 706 };
 707
 708 static const struct dcn20_dsc_shift dsc_shift = {
 709         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 710 };
 711
 712 static const struct dcn20_dsc_mask dsc_mask = {
 713         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 714 };
 715
 716 static const struct dcn30_mpc_registers mpc_regs = {
 717                 MPC_REG_LIST_DCN3_0(0),
 718                 MPC_REG_LIST_DCN3_0(1),
 719                 MPC_REG_LIST_DCN3_0(2),
 720                 MPC_REG_LIST_DCN3_0(3),
 721                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 722                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 723                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 724                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 725                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 726                 MPC_RMU_REG_LIST_DCN3AG(0),
 727                 MPC_RMU_REG_LIST_DCN3AG(1),
 728                 //MPC_RMU_REG_LIST_DCN3AG(2),
 729                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 730 };
 731
 732 static const struct dcn30_mpc_shift mpc_shift = {
 733         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 734 };
 735
 736 static const struct dcn30_mpc_mask mpc_mask = {
 737         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 738 };
 739
 740 #define optc_regs(id)\
 741 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 742
 743 static const struct dcn_optc_registers optc_regs[] = {
 744         optc_regs(0),
 745         optc_regs(1),
 746         optc_regs(2),
 747         optc_regs(3)
 748 };
 749
 750 static const struct dcn_optc_shift optc_shift = {
 751         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 752 };
 753
 754 static const struct dcn_optc_mask optc_mask = {
 755         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 756 };
 757
 758 #define hubp_regs(id)\
 759 [id] = {\
 760         HUBP_REG_LIST_DCN30(id)\
 761 }
 762
 763 static const struct dcn_hubp2_registers hubp_regs[] = {
 764                 hubp_regs(0),
 765                 hubp_regs(1),
 766                 hubp_regs(2),
 767                 hubp_regs(3)
 768 };
 769
 770
 771 static const struct dcn_hubp2_shift hubp_shift = {
 772                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 773 };
 774
 775 static const struct dcn_hubp2_mask hubp_mask = {
 776                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 777 };
 778 static const struct dcn_hubbub_registers hubbub_reg = {
 779                 HUBBUB_REG_LIST_DCN31(0)
 780 };
 781
 782 static const struct dcn_hubbub_shift hubbub_shift = {
 783                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 784 };
 785
 786 static const struct dcn_hubbub_mask hubbub_mask = {
 787                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 788 };
 789
 790 static const struct dccg_registers dccg_regs = {
 791                 DCCG_REG_LIST_DCN31()
 792 };
 793
 794 static const struct dccg_shift dccg_shift = {
 795                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 796 };
 797
 798 static const struct dccg_mask dccg_mask = {
 799                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 800 };
 801
 802
 803 #define SRII2(reg_name_pre, reg_name_post, id)\
 804         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 805                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 806                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 807
 808
 809 #define HWSEQ_DCN31_REG_LIST()\
 810         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 811         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 812         SR(DIO_MEM_PWR_CTRL), \
 813         SR(ODM_MEM_PWR_CTRL3), \
 814         SR(DMU_MEM_PWR_CNTL), \
 815         SR(MMHUBBUB_MEM_PWR_CNTL), \
 816         SR(DCCG_GATE_DISABLE_CNTL), \
 817         SR(DCCG_GATE_DISABLE_CNTL2), \
 818         SR(DCFCLK_CNTL),\
 819         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 820         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 821         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 822         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 823         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 824         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 825         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 826         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 827         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 828         SR(MICROSECOND_TIME_BASE_DIV), \
 829         SR(MILLISECOND_TIME_BASE_DIV), \
 830         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 831         SR(RBBMIF_TIMEOUT_DIS), \
 832         SR(RBBMIF_TIMEOUT_DIS_2), \
 833         SR(DCHUBBUB_CRC_CTRL), \
 834         SR(DPP_TOP0_DPP_CRC_CTRL), \
 835         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 836         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 837         SR(MPC_CRC_CTRL), \
 838         SR(MPC_CRC_RESULT_GB), \
 839         SR(MPC_CRC_RESULT_C), \
 840         SR(MPC_CRC_RESULT_AR), \
 841         SR(DOMAIN0_PG_CONFIG), \
 842         SR(DOMAIN1_PG_CONFIG), \
 843         SR(DOMAIN2_PG_CONFIG), \
 844         SR(DOMAIN3_PG_CONFIG), \
 845         SR(DOMAIN16_PG_CONFIG), \
 846         SR(DOMAIN17_PG_CONFIG), \
 847         SR(DOMAIN18_PG_CONFIG), \
 848         SR(DOMAIN0_PG_STATUS), \
 849         SR(DOMAIN1_PG_STATUS), \
 850         SR(DOMAIN2_PG_STATUS), \
 851         SR(DOMAIN3_PG_STATUS), \
 852         SR(DOMAIN16_PG_STATUS), \
 853         SR(DOMAIN17_PG_STATUS), \
 854         SR(DOMAIN18_PG_STATUS), \
 855         SR(D1VGA_CONTROL), \
 856         SR(D2VGA_CONTROL), \
 857         SR(D3VGA_CONTROL), \
 858         SR(D4VGA_CONTROL), \
 859         SR(D5VGA_CONTROL), \
 860         SR(D6VGA_CONTROL), \
 861         SR(DC_IP_REQUEST_CNTL), \
 862         SR(AZALIA_AUDIO_DTO), \
 863         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 864         SR(HPO_TOP_HW_CONTROL)
 865
 866 static const struct dce_hwseq_registers hwseq_reg = {
 867                 HWSEQ_DCN31_REG_LIST()
 868 };
 869
 870 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 871         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 872         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 873         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 874         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 875         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 876         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 877         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 878         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 879         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 880         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 881         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 882         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 883         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 884         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 885         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 886         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 887         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 888         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 889         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 890         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 891         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 892         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 893         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 894         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 895         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 896         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 897         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 898         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 899         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 900         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 901         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 902         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 903         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 904
 905 static const struct dce_hwseq_shift hwseq_shift = {
 906                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 907 };
 908
 909 static const struct dce_hwseq_mask hwseq_mask = {
 910                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 911 };
 912 #define vmid_regs(id)\
 913 [id] = {\
 914                 DCN20_VMID_REG_LIST(id)\
 915 }
 916
 917 static const struct dcn_vmid_registers vmid_regs[] = {
 918         vmid_regs(0),
 919         vmid_regs(1),
 920         vmid_regs(2),
 921         vmid_regs(3),
 922         vmid_regs(4),
 923         vmid_regs(5),
 924         vmid_regs(6),
 925         vmid_regs(7),
 926         vmid_regs(8),
 927         vmid_regs(9),
 928         vmid_regs(10),
 929         vmid_regs(11),
 930         vmid_regs(12),
 931         vmid_regs(13),
 932         vmid_regs(14),
 933         vmid_regs(15)
 934 };
 935
 936 static const struct dcn20_vmid_shift vmid_shifts = {
 937                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 938 };
 939
 940 static const struct dcn20_vmid_mask vmid_masks = {
 941                 DCN20_VMID_MASK_SH_LIST(_MASK)
 942 };
 943
 944 static const struct resource_caps res_cap_dcn31 = {
 945         .num_timing_generator = 4,
 946         .num_opp = 4,
 947         .num_video_plane = 4,
 948         .num_audio = 5,
 949         .num_stream_encoder = 5,
 950         .num_dig_link_enc = 5,
 951         .num_hpo_dp_stream_encoder = 4,
 952         .num_hpo_dp_link_encoder = 2,
 953         .num_pll = 5,
 954         .num_dwb = 1,
 955         .num_ddc = 5,
 956         .num_vmid = 16,
 957         .num_mpc_3dlut = 2,
 958         .num_dsc = 3,
 959 };
 960
 961 static const struct dc_plane_cap plane_cap = {
 962         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 963         .blends_with_above = true,
 964         .blends_with_below = true,
 965         .per_pixel_alpha = true,
 966
 967         .pixel_format_support = {
 968                         .argb8888 = true,
 969                         .nv12 = true,
 970                         .fp16 = true,
 971                         .p010 = false,
 972                         .ayuv = false,
 973         },
 974
 975         .max_upscale_factor = {
 976                         .argb8888 = 16000,
 977                         .nv12 = 16000,
 978                         .fp16 = 16000
 979         },
 980
 981         // 6:1 downscaling ratio: 1000/6 = 166.666
 982         .max_downscale_factor = {
 983                         .argb8888 = 167,
 984                         .nv12 = 167,
 985                         .fp16 = 167
 986         },
 987         64,
 988         64
 989 };
 990
 991 static const struct dc_debug_options debug_defaults_drv = {
 992         .disable_dmcu = true,
 993         .force_abm_enable = false,
 994         .timing_trace = false,
 995         .clock_trace = true,
 996         .disable_pplib_clock_request = false,
 997         .pipe_split_policy = MPC_SPLIT_AVOID,
 998         .force_single_disp_pipe_split = false,
 999         .disable_dcc = DCC_ENABLE,
1000         .vsr_support = true,
1001         .performance_trace = false,
1002         .max_downscale_src_width = 4096,/*upto true 4K*/
1003         .disable_pplib_wm_range = false,
1004         .scl_reset_length10 = true,
1005         .sanity_checks = false,
1006         .underflow_assert_delay_us = 0xFFFFFFFF,
1007         .dwb_fi_phase = -1, // -1 = disable,
1008         .dmub_command_table = true,
1009         .pstate_enabled = true,
1010         .use_max_lb = true,
1011         .enable_mem_low_power = {
1012                 .bits = {
1013                         .vga = true,
1014                         .i2c = true,
1015                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
1016                         .dscl = true,
1017                         .cm = true,
1018                         .mpc = true,
1019                         .optc = true,
1020                         .vpg = true,
1021                         .afmt = true,
1022                 }
1023         },
1024         .optimize_edp_link_rate = true,
1025         .enable_sw_cntl_psr = true,
1026 };
1027
1028 static const struct dc_debug_options debug_defaults_diags = {
1029         .disable_dmcu = true,
1030         .force_abm_enable = false,
1031         .timing_trace = true,
1032         .clock_trace = true,
1033         .disable_dpp_power_gate = true,
1034         .disable_hubp_power_gate = true,
1035         .disable_clock_gate = true,
1036         .disable_pplib_clock_request = true,
1037         .disable_pplib_wm_range = true,
1038         .disable_stutter = false,
1039         .scl_reset_length10 = true,
1040         .dwb_fi_phase = -1, // -1 = disable
1041         .dmub_command_table = true,
1042         .enable_tri_buf = true,
1043         .use_max_lb = true
1044 };
1045
1046 static void dcn31_dpp_destroy(struct dpp **dpp)
1047 {
1048         kfree(TO_DCN20_DPP(*dpp));
1049         *dpp = NULL;
1050 }
1051
1052 static struct dpp *dcn31_dpp_create(
1053         struct dc_context *ctx,
1054         uint32_t inst)
1055 {
1056         struct dcn3_dpp *dpp =
1057                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1058
1059         if (!dpp)
1060                 return NULL;
1061
1062         if (dpp3_construct(dpp, ctx, inst,
1063                         &dpp_regs[inst], &tf_shift, &tf_mask))
1064                 return &dpp->base;
1065
1066         BREAK_TO_DEBUGGER();
1067         kfree(dpp);
1068         return NULL;
1069 }
1070
1071 static struct output_pixel_processor *dcn31_opp_create(
1072         struct dc_context *ctx, uint32_t inst)
1073 {
1074         struct dcn20_opp *opp =
1075                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1076
1077         if (!opp) {
1078                 BREAK_TO_DEBUGGER();
1079                 return NULL;
1080         }
1081
1082         dcn20_opp_construct(opp, ctx, inst,
1083                         &opp_regs[inst], &opp_shift, &opp_mask);
1084         return &opp->base;
1085 }
1086
1087 static struct dce_aux *dcn31_aux_engine_create(
1088         struct dc_context *ctx,
1089         uint32_t inst)
1090 {
1091         struct aux_engine_dce110 *aux_engine =
1092                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1093
1094         if (!aux_engine)
1095                 return NULL;
1096
1097         dce110_aux_engine_construct(aux_engine, ctx, inst,
1098                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1099                                     &aux_engine_regs[inst],
1100                                         &aux_mask,
1101                                         &aux_shift,
1102                                         ctx->dc->caps.extended_aux_timeout_support);
1103
1104         return &aux_engine->base;
1105 }
1106 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1107
1108 static const struct dce_i2c_registers i2c_hw_regs[] = {
1109                 i2c_inst_regs(1),
1110                 i2c_inst_regs(2),
1111                 i2c_inst_regs(3),
1112                 i2c_inst_regs(4),
1113                 i2c_inst_regs(5),
1114 };
1115
1116 static const struct dce_i2c_shift i2c_shifts = {
1117                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1118 };
1119
1120 static const struct dce_i2c_mask i2c_masks = {
1121                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1122 };
1123
1124 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1125         struct dc_context *ctx,
1126         uint32_t inst)
1127 {
1128         struct dce_i2c_hw *dce_i2c_hw =
1129                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1130
1131         if (!dce_i2c_hw)
1132                 return NULL;
1133
1134         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1135                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1136
1137         return dce_i2c_hw;
1138 }
1139 static struct mpc *dcn31_mpc_create(
1140                 struct dc_context *ctx,
1141                 int num_mpcc,
1142                 int num_rmu)
1143 {
1144         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1145                                           GFP_KERNEL);
1146
1147         if (!mpc30)
1148                 return NULL;
1149
1150         dcn30_mpc_construct(mpc30, ctx,
1151                         &mpc_regs,
1152                         &mpc_shift,
1153                         &mpc_mask,
1154                         num_mpcc,
1155                         num_rmu);
1156
1157         return &mpc30->base;
1158 }
1159
1160 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1161 {
1162         int i;
1163
1164         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1165                                           GFP_KERNEL);
1166
1167         if (!hubbub3)
1168                 return NULL;
1169
1170         hubbub31_construct(hubbub3, ctx,
1171                         &hubbub_reg,
1172                         &hubbub_shift,
1173                         &hubbub_mask,
1174                         dcn3_1_ip.det_buffer_size_kbytes,
1175                         dcn3_1_ip.pixel_chunk_size_kbytes,
1176                         dcn3_1_ip.config_return_buffer_size_in_kbytes);
1177
1178
1179         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1180                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1181
1182                 vmid->ctx = ctx;
1183
1184                 vmid->regs = &vmid_regs[i];
1185                 vmid->shifts = &vmid_shifts;
1186                 vmid->masks = &vmid_masks;
1187         }
1188
1189         return &hubbub3->base;
1190 }
1191
1192 static struct timing_generator *dcn31_timing_generator_create(
1193                 struct dc_context *ctx,
1194                 uint32_t instance)
1195 {
1196         struct optc *tgn10 =
1197                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1198
1199         if (!tgn10)
1200                 return NULL;
1201
1202         tgn10->base.inst = instance;
1203         tgn10->base.ctx = ctx;
1204
1205         tgn10->tg_regs = &optc_regs[instance];
1206         tgn10->tg_shift = &optc_shift;
1207         tgn10->tg_mask = &optc_mask;
1208
1209         dcn31_timing_generator_init(tgn10);
1210
1211         return &tgn10->base;
1212 }
1213
1214 static const struct encoder_feature_support link_enc_feature = {
1215                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1216                 .max_hdmi_pixel_clock = 600000,
1217                 .hdmi_ycbcr420_supported = true,
1218                 .dp_ycbcr420_supported = true,
1219                 .fec_supported = true,
1220                 .flags.bits.IS_HBR2_CAPABLE = true,
1221                 .flags.bits.IS_HBR3_CAPABLE = true,
1222                 .flags.bits.IS_TPS3_CAPABLE = true,
1223                 .flags.bits.IS_TPS4_CAPABLE = true
1224 };
1225
1226 static struct link_encoder *dcn31_link_encoder_create(
1227         const struct encoder_init_data *enc_init_data)
1228 {
1229         struct dcn20_link_encoder *enc20 =
1230                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1231
1232         if (!enc20)
1233                 return NULL;
1234
1235         dcn31_link_encoder_construct(enc20,
1236                         enc_init_data,
1237                         &link_enc_feature,
1238                         &link_enc_regs[enc_init_data->transmitter],
1239                         &link_enc_aux_regs[enc_init_data->channel - 1],
1240                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1241                         &le_shift,
1242                         &le_mask);
1243
1244         return &enc20->enc10.base;
1245 }
1246
1247 /* Create a minimal link encoder object not associated with a particular
1248  * physical connector.
1249  * resource_funcs.link_enc_create_minimal
1250  */
1251 static struct link_encoder *dcn31_link_enc_create_minimal(
1252                 struct dc_context *ctx, enum engine_id eng_id)
1253 {
1254         struct dcn20_link_encoder *enc20;
1255
1256         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1257                 return NULL;
1258
1259         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1260         if (!enc20)
1261                 return NULL;
1262
1263         dcn31_link_encoder_construct_minimal(
1264                         enc20,
1265                         ctx,
1266                         &link_enc_feature,
1267                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1268                         eng_id);
1269
1270         return &enc20->enc10.base;
1271 }
1272
1273 struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1274 {
1275         struct dcn31_panel_cntl *panel_cntl =
1276                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1277
1278         if (!panel_cntl)
1279                 return NULL;
1280
1281         dcn31_panel_cntl_construct(panel_cntl, init_data);
1282
1283         return &panel_cntl->base;
1284 }
1285
1286 static void read_dce_straps(
1287         struct dc_context *ctx,
1288         struct resource_straps *straps)
1289 {
1290         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1291                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1292
1293 }
1294
1295 static struct audio *dcn31_create_audio(
1296                 struct dc_context *ctx, unsigned int inst)
1297 {
1298         return dce_audio_create(ctx, inst,
1299                         &audio_regs[inst], &audio_shift, &audio_mask);
1300 }
1301
1302 static struct vpg *dcn31_vpg_create(
1303         struct dc_context *ctx,
1304         uint32_t inst)
1305 {
1306         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1307
1308         if (!vpg31)
1309                 return NULL;
1310
1311         vpg31_construct(vpg31, ctx, inst,
1312                         &vpg_regs[inst],
1313                         &vpg_shift,
1314                         &vpg_mask);
1315
1316         return &vpg31->base;
1317 }
1318
1319 static struct afmt *dcn31_afmt_create(
1320         struct dc_context *ctx,
1321         uint32_t inst)
1322 {
1323         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1324
1325         if (!afmt31)
1326                 return NULL;
1327
1328         afmt31_construct(afmt31, ctx, inst,
1329                         &afmt_regs[inst],
1330                         &afmt_shift,
1331                         &afmt_mask);
1332
1333         // Light sleep by default, no need to power down here
1334
1335         return &afmt31->base;
1336 }
1337
1338 static struct apg *dcn31_apg_create(
1339         struct dc_context *ctx,
1340         uint32_t inst)
1341 {
1342         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1343
1344         if (!apg31)
1345                 return NULL;
1346
1347         apg31_construct(apg31, ctx, inst,
1348                         &apg_regs[inst],
1349                         &apg_shift,
1350                         &apg_mask);
1351
1352         return &apg31->base;
1353 }
1354
1355 static struct stream_encoder *dcn31_stream_encoder_create(
1356         enum engine_id eng_id,
1357         struct dc_context *ctx)
1358 {
1359         struct dcn10_stream_encoder *enc1;
1360         struct vpg *vpg;
1361         struct afmt *afmt;
1362         int vpg_inst;
1363         int afmt_inst;
1364
1365         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1366         if (eng_id <= ENGINE_ID_DIGF) {
1367                 vpg_inst = eng_id;
1368                 afmt_inst = eng_id;
1369         } else
1370                 return NULL;
1371
1372         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1373         vpg = dcn31_vpg_create(ctx, vpg_inst);
1374         afmt = dcn31_afmt_create(ctx, afmt_inst);
1375
1376         if (!enc1 || !vpg || !afmt) {
1377                 kfree(enc1);
1378                 kfree(vpg);
1379                 kfree(afmt);
1380                 return NULL;
1381         }
1382
1383         if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
1384                         ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1385                 if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD))
1386                         eng_id = eng_id + 3; // For B0 only. C->F, D->G.
1387         }
1388
1389         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1390                                         eng_id, vpg, afmt,
1391                                         &stream_enc_regs[eng_id],
1392                                         &se_shift, &se_mask);
1393
1394         return &enc1->base;
1395 }
1396
1397 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1398         enum engine_id eng_id,
1399         struct dc_context *ctx)
1400 {
1401         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1402         struct vpg *vpg;
1403         struct apg *apg;
1404         uint32_t hpo_dp_inst;
1405         uint32_t vpg_inst;
1406         uint32_t apg_inst;
1407
1408         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1409         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1410
1411         /* Mapping of VPG register blocks to HPO DP block instance:
1412          * VPG[6] -> HPO_DP[0]
1413          * VPG[7] -> HPO_DP[1]
1414          * VPG[8] -> HPO_DP[2]
1415          * VPG[9] -> HPO_DP[3]
1416          */
1417         vpg_inst = hpo_dp_inst + 6;
1418
1419         /* Mapping of APG register blocks to HPO DP block instance:
1420          * APG[0] -> HPO_DP[0]
1421          * APG[1] -> HPO_DP[1]
1422          * APG[2] -> HPO_DP[2]
1423          * APG[3] -> HPO_DP[3]
1424          */
1425         apg_inst = hpo_dp_inst;
1426
1427         /* allocate HPO stream encoder and create VPG sub-block */
1428         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1429         vpg = dcn31_vpg_create(ctx, vpg_inst);
1430         apg = dcn31_apg_create(ctx, apg_inst);
1431
1432         if (!hpo_dp_enc31 || !vpg || !apg) {
1433                 kfree(hpo_dp_enc31);
1434                 kfree(vpg);
1435                 kfree(apg);
1436                 return NULL;
1437         }
1438
1439         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1440                                         hpo_dp_inst, eng_id, vpg, apg,
1441                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1442                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1443
1444         return &hpo_dp_enc31->base;
1445 }
1446
1447 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1448         uint8_t inst,
1449         struct dc_context *ctx)
1450 {
1451         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1452
1453         /* allocate HPO link encoder */
1454         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1455
1456         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1457                                         &hpo_dp_link_enc_regs[inst],
1458                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1459
1460         return &hpo_dp_enc31->base;
1461 }
1462
1463 static struct dce_hwseq *dcn31_hwseq_create(
1464         struct dc_context *ctx)
1465 {
1466         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1467
1468         if (hws) {
1469                 hws->ctx = ctx;
1470                 hws->regs = &hwseq_reg;
1471                 hws->shifts = &hwseq_shift;
1472                 hws->masks = &hwseq_mask;
1473                 /* DCN3.1 FPGA Workaround
1474                  * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1475                  * To do so, move calling function enable_stream_timing to only be done AFTER calling
1476                  * function core_link_enable_stream
1477                  */
1478                 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1479                         hws->wa.dp_hpo_and_otg_sequence = true;
1480         }
1481         return hws;
1482 }
1483 static const struct resource_create_funcs res_create_funcs = {
1484         .read_dce_straps = read_dce_straps,
1485         .create_audio = dcn31_create_audio,
1486         .create_stream_encoder = dcn31_stream_encoder_create,
1487         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1488         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1489         .create_hwseq = dcn31_hwseq_create,
1490 };
1491
1492 static const struct resource_create_funcs res_create_maximus_funcs = {
1493         .read_dce_straps = NULL,
1494         .create_audio = NULL,
1495         .create_stream_encoder = NULL,
1496         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1497         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1498         .create_hwseq = dcn31_hwseq_create,
1499 };
1500
1501 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1502 {
1503         unsigned int i;
1504
1505         for (i = 0; i < pool->base.stream_enc_count; i++) {
1506                 if (pool->base.stream_enc[i] != NULL) {
1507                         if (pool->base.stream_enc[i]->vpg != NULL) {
1508                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1509                                 pool->base.stream_enc[i]->vpg = NULL;
1510                         }
1511                         if (pool->base.stream_enc[i]->afmt != NULL) {
1512                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1513                                 pool->base.stream_enc[i]->afmt = NULL;
1514                         }
1515                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1516                         pool->base.stream_enc[i] = NULL;
1517                 }
1518         }
1519
1520         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1521                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1522                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1523                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1524                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1525                         }
1526                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1527                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1528                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1529                         }
1530                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1531                         pool->base.hpo_dp_stream_enc[i] = NULL;
1532                 }
1533         }
1534
1535         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1536                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1537                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1538                         pool->base.hpo_dp_link_enc[i] = NULL;
1539                 }
1540         }
1541
1542         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1543                 if (pool->base.dscs[i] != NULL)
1544                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1545         }
1546
1547         if (pool->base.mpc != NULL) {
1548                 kfree(TO_DCN20_MPC(pool->base.mpc));
1549                 pool->base.mpc = NULL;
1550         }
1551         if (pool->base.hubbub != NULL) {
1552                 kfree(pool->base.hubbub);
1553                 pool->base.hubbub = NULL;
1554         }
1555         for (i = 0; i < pool->base.pipe_count; i++) {
1556                 if (pool->base.dpps[i] != NULL)
1557                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1558
1559                 if (pool->base.ipps[i] != NULL)
1560                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1561
1562                 if (pool->base.hubps[i] != NULL) {
1563                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1564                         pool->base.hubps[i] = NULL;
1565                 }
1566
1567                 if (pool->base.irqs != NULL) {
1568                         dal_irq_service_destroy(&pool->base.irqs);
1569                 }
1570         }
1571
1572         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1573                 if (pool->base.engines[i] != NULL)
1574                         dce110_engine_destroy(&pool->base.engines[i]);
1575                 if (pool->base.hw_i2cs[i] != NULL) {
1576                         kfree(pool->base.hw_i2cs[i]);
1577                         pool->base.hw_i2cs[i] = NULL;
1578                 }
1579                 if (pool->base.sw_i2cs[i] != NULL) {
1580                         kfree(pool->base.sw_i2cs[i]);
1581                         pool->base.sw_i2cs[i] = NULL;
1582                 }
1583         }
1584
1585         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1586                 if (pool->base.opps[i] != NULL)
1587                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1588         }
1589
1590         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1591                 if (pool->base.timing_generators[i] != NULL)    {
1592                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1593                         pool->base.timing_generators[i] = NULL;
1594                 }
1595         }
1596
1597         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1598                 if (pool->base.dwbc[i] != NULL) {
1599                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1600                         pool->base.dwbc[i] = NULL;
1601                 }
1602                 if (pool->base.mcif_wb[i] != NULL) {
1603                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1604                         pool->base.mcif_wb[i] = NULL;
1605                 }
1606         }
1607
1608         for (i = 0; i < pool->base.audio_count; i++) {
1609                 if (pool->base.audios[i])
1610                         dce_aud_destroy(&pool->base.audios[i]);
1611         }
1612
1613         for (i = 0; i < pool->base.clk_src_count; i++) {
1614                 if (pool->base.clock_sources[i] != NULL) {
1615                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1616                         pool->base.clock_sources[i] = NULL;
1617                 }
1618         }
1619
1620         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1621                 if (pool->base.mpc_lut[i] != NULL) {
1622                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1623                         pool->base.mpc_lut[i] = NULL;
1624                 }
1625                 if (pool->base.mpc_shaper[i] != NULL) {
1626                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1627                         pool->base.mpc_shaper[i] = NULL;
1628                 }
1629         }
1630
1631         if (pool->base.dp_clock_source != NULL) {
1632                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1633                 pool->base.dp_clock_source = NULL;
1634         }
1635
1636         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1637                 if (pool->base.multiple_abms[i] != NULL)
1638                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1639         }
1640
1641         if (pool->base.psr != NULL)
1642                 dmub_psr_destroy(&pool->base.psr);
1643
1644         if (pool->base.dccg != NULL)
1645                 dcn_dccg_destroy(&pool->base.dccg);
1646 }
1647
1648 static struct hubp *dcn31_hubp_create(
1649         struct dc_context *ctx,
1650         uint32_t inst)
1651 {
1652         struct dcn20_hubp *hubp2 =
1653                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1654
1655         if (!hubp2)
1656                 return NULL;
1657
1658         if (hubp31_construct(hubp2, ctx, inst,
1659                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1660                 return &hubp2->base;
1661
1662         BREAK_TO_DEBUGGER();
1663         kfree(hubp2);
1664         return NULL;
1665 }
1666
1667 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1668 {
1669         int i;
1670         uint32_t pipe_count = pool->res_cap->num_dwb;
1671
1672         for (i = 0; i < pipe_count; i++) {
1673                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1674                                                     GFP_KERNEL);
1675
1676                 if (!dwbc30) {
1677                         dm_error("DC: failed to create dwbc30!\n");
1678                         return false;
1679                 }
1680
1681                 dcn30_dwbc_construct(dwbc30, ctx,
1682                                 &dwbc30_regs[i],
1683                                 &dwbc30_shift,
1684                                 &dwbc30_mask,
1685                                 i);
1686
1687                 pool->dwbc[i] = &dwbc30->base;
1688         }
1689         return true;
1690 }
1691
1692 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1693 {
1694         int i;
1695         uint32_t pipe_count = pool->res_cap->num_dwb;
1696
1697         for (i = 0; i < pipe_count; i++) {
1698                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1699                                                     GFP_KERNEL);
1700
1701                 if (!mcif_wb30) {
1702                         dm_error("DC: failed to create mcif_wb30!\n");
1703                         return false;
1704                 }
1705
1706                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1707                                 &mcif_wb30_regs[i],
1708                                 &mcif_wb30_shift,
1709                                 &mcif_wb30_mask,
1710                                 i);
1711
1712                 pool->mcif_wb[i] = &mcif_wb30->base;
1713         }
1714         return true;
1715 }
1716
1717 static struct display_stream_compressor *dcn31_dsc_create(
1718         struct dc_context *ctx, uint32_t inst)
1719 {
1720         struct dcn20_dsc *dsc =
1721                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1722
1723         if (!dsc) {
1724                 BREAK_TO_DEBUGGER();
1725                 return NULL;
1726         }
1727
1728         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1729         return &dsc->base;
1730 }
1731
1732 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1733 {
1734         struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1735
1736         dcn31_resource_destruct(dcn31_pool);
1737         kfree(dcn31_pool);
1738         *pool = NULL;
1739 }
1740
1741 static struct clock_source *dcn31_clock_source_create(
1742                 struct dc_context *ctx,
1743                 struct dc_bios *bios,
1744                 enum clock_source_id id,
1745                 const struct dce110_clk_src_regs *regs,
1746                 bool dp_clk_src)
1747 {
1748         struct dce110_clk_src *clk_src =
1749                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1750
1751         if (!clk_src)
1752                 return NULL;
1753
1754         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1755                         regs, &cs_shift, &cs_mask)) {
1756                 clk_src->base.dp_clk_src = dp_clk_src;
1757                 return &clk_src->base;
1758         }
1759
1760         BREAK_TO_DEBUGGER();
1761         return NULL;
1762 }
1763
1764 static bool is_dual_plane(enum surface_pixel_format format)
1765 {
1766         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1767 }
1768
1769 static int dcn31_populate_dml_pipes_from_context(
1770         struct dc *dc, struct dc_state *context,
1771         display_e2e_pipe_params_st *pipes,
1772         bool fast_validate)
1773 {
1774         int i, pipe_cnt;
1775         struct resource_context *res_ctx = &context->res_ctx;
1776         struct pipe_ctx *pipe;
1777
1778         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1779
1780         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1781                 struct dc_crtc_timing *timing;
1782
1783                 if (!res_ctx->pipe_ctx[i].stream)
1784                         continue;
1785                 pipe = &res_ctx->pipe_ctx[i];
1786                 timing = &pipe->stream->timing;
1787
1788                 /*
1789                  * Immediate flip can be set dynamically after enabling the plane.
1790                  * We need to require support for immediate flip or underflow can be
1791                  * intermittently experienced depending on peak b/w requirements.
1792                  */
1793                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1794
1795                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1796                 pipes[pipe_cnt].pipe.src.gpuvm = true;
1797                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1798                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1799                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1800                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1801                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1802
1803                 if (pipes[pipe_cnt].dout.dsc_enable) {
1804                         switch (timing->display_color_depth) {
1805                         case COLOR_DEPTH_888:
1806                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1807                                 break;
1808                         case COLOR_DEPTH_101010:
1809                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1810                                 break;
1811                         case COLOR_DEPTH_121212:
1812                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1813                                 break;
1814                         default:
1815                                 ASSERT(0);
1816                                 break;
1817                         }
1818                 }
1819
1820                 pipe_cnt++;
1821         }
1822         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1823         dc->config.enable_4to1MPC = false;
1824         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1825                 if (is_dual_plane(pipe->plane_state->format)
1826                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1827                         dc->config.enable_4to1MPC = true;
1828                 } else if (!is_dual_plane(pipe->plane_state->format)) {
1829                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1830                         pipes[0].pipe.src.unbounded_req_mode = true;
1831                 }
1832         }
1833
1834         return pipe_cnt;
1835 }
1836
1837 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
1838 {
1839         if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
1840                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
1841                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
1842                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
1843         }
1844 }
1845
1846 static void dcn31_calculate_wm_and_dlg_fp(
1847                 struct dc *dc, struct dc_state *context,
1848                 display_e2e_pipe_params_st *pipes,
1849                 int pipe_cnt,
1850                 int vlevel)
1851 {
1852         int i, pipe_idx;
1853         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1854
1855         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
1856                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
1857
1858         /* We don't recalculate clocks for 0 pipe configs, which can block
1859          * S0i3 as high clocks will block low power states
1860          * Override any clocks that can block S0i3 to min here
1861          */
1862         if (pipe_cnt == 0) {
1863                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
1864                 return;
1865         }
1866
1867         pipes[0].clks_cfg.voltage = vlevel;
1868         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1869         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1870
1871 #if 0 // TODO
1872         /* Set B:
1873          * TODO
1874          */
1875         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1876                 if (vlevel == 0) {
1877                         pipes[0].clks_cfg.voltage = 1;
1878                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
1879                 }
1880                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1881                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1882                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1883         }
1884         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1885         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1886         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1887         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1888         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1889         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1890         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1891         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1892         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1893         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1894
1895         pipes[0].clks_cfg.voltage = vlevel;
1896         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1897
1898         /* Set C:
1899          * TODO
1900          */
1901         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1902                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
1903                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1904                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1905         }
1906         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1907         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1908         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1909         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1910         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1911         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1912         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1913         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1914         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1915         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1916
1917         /* Set D:
1918          * TODO
1919          */
1920         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1921                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1922                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1923                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1924         }
1925         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1926         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1927         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1928         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1929         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1930         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1931         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1932         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1933         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1934         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1935 #endif
1936
1937         /* Set A:
1938          * All clocks min required
1939          *
1940          * Set A calculated last so that following calculations are based on Set A
1941          */
1942         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1943         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1944         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1945         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1946         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1947         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1948         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1949         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1950         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1951         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1952         context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1953         /* TODO: remove: */
1954         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1955         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1956         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1957         /* end remove*/
1958
1959         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1960                 if (!context->res_ctx.pipe_ctx[i].stream)
1961                         continue;
1962
1963                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1964                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1965
1966                 if (dc->config.forced_clocks) {
1967                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1968                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1969                 }
1970                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1971                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1972                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1973                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1974
1975                 pipe_idx++;
1976         }
1977
1978         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1979 }
1980
1981 void dcn31_calculate_wm_and_dlg(
1982                 struct dc *dc, struct dc_state *context,
1983                 display_e2e_pipe_params_st *pipes,
1984                 int pipe_cnt,
1985                 int vlevel)
1986 {
1987         DC_FP_START();
1988         dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1989         DC_FP_END();
1990 }
1991
1992 bool dcn31_validate_bandwidth(struct dc *dc,
1993                 struct dc_state *context,
1994                 bool fast_validate)
1995 {
1996         bool out = false;
1997
1998         BW_VAL_TRACE_SETUP();
1999
2000         int vlevel = 0;
2001         int pipe_cnt = 0;
2002         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2003         DC_LOGGER_INIT(dc->ctx->logger);
2004
2005         BW_VAL_TRACE_COUNT();
2006
2007         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2008
2009         // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
2010         if (pipe_cnt == 0)
2011                 fast_validate = false;
2012
2013         if (!out)
2014                 goto validate_fail;
2015
2016         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2017
2018         if (fast_validate) {
2019                 BW_VAL_TRACE_SKIP(fast);
2020                 goto validate_out;
2021         }
2022
2023         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2024
2025         BW_VAL_TRACE_END_WATERMARKS();
2026
2027         goto validate_out;
2028
2029 validate_fail:
2030         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2031                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2032
2033         BW_VAL_TRACE_SKIP(fail);
2034         out = false;
2035
2036 validate_out:
2037         kfree(pipes);
2038
2039         BW_VAL_TRACE_FINISH();
2040
2041         return out;
2042 }
2043
2044 static struct dc_cap_funcs cap_funcs = {
2045         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2046 };
2047
2048 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2049 {
2050         struct clk_limit_table *clk_table = &bw_params->clk_table;
2051         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
2052         unsigned int i, closest_clk_lvl;
2053         int j;
2054
2055         // Default clock levels are used for diags, which may lead to overclocking.
2056         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2057                 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
2058
2059                 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
2060                 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
2061                 dcn3_1_soc.num_chans = bw_params->num_channels;
2062
2063                 ASSERT(clk_table->num_entries);
2064
2065                 /* Prepass to find max clocks independent of voltage level. */
2066                 for (i = 0; i < clk_table->num_entries; ++i) {
2067                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
2068                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
2069                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
2070                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
2071                 }
2072
2073                 for (i = 0; i < clk_table->num_entries; i++) {
2074                         /* loop backwards*/
2075                         for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
2076                                 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2077                                         closest_clk_lvl = j;
2078                                         break;
2079                                 }
2080                         }
2081
2082                         clock_limits[i].state = i;
2083
2084                         /* Clocks dependent on voltage level. */
2085                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2086                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2087                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
2088                         clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
2089
2090                         /* Clocks independent of voltage level. */
2091                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
2092                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2093
2094                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
2095                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2096
2097                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2098                         clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2099                         clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2100                         clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2101                         clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2102                 }
2103                 for (i = 0; i < clk_table->num_entries; i++)
2104                         dcn3_1_soc.clock_limits[i] = clock_limits[i];
2105                 if (clk_table->num_entries) {
2106                         dcn3_1_soc.num_states = clk_table->num_entries;
2107                 }
2108         }
2109
2110         dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2111         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2112
2113         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2114                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
2115         else
2116                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
2117 }
2118
2119 static struct resource_funcs dcn31_res_pool_funcs = {
2120         .destroy = dcn31_destroy_resource_pool,
2121         .link_enc_create = dcn31_link_encoder_create,
2122         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
2123         .link_encs_assign = link_enc_cfg_link_encs_assign,
2124         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
2125         .panel_cntl_create = dcn31_panel_cntl_create,
2126         .validate_bandwidth = dcn31_validate_bandwidth,
2127         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
2128         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
2129         .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
2130         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2131         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2132         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2133         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2134         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2135         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2136         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2137         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2138         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2139         .update_bw_bounding_box = dcn31_update_bw_bounding_box,
2140         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2141 };
2142
2143 static struct clock_source *dcn30_clock_source_create(
2144                 struct dc_context *ctx,
2145                 struct dc_bios *bios,
2146                 enum clock_source_id id,
2147                 const struct dce110_clk_src_regs *regs,
2148                 bool dp_clk_src)
2149 {
2150         struct dce110_clk_src *clk_src =
2151                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
2152
2153         if (!clk_src)
2154                 return NULL;
2155
2156         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
2157                         regs, &cs_shift, &cs_mask)) {
2158                 clk_src->base.dp_clk_src = dp_clk_src;
2159                 return &clk_src->base;
2160         }
2161
2162         BREAK_TO_DEBUGGER();
2163         return NULL;
2164 }
2165
2166 static bool dcn31_resource_construct(
2167         uint8_t num_virtual_links,
2168         struct dc *dc,
2169         struct dcn31_resource_pool *pool)
2170 {
2171         int i;
2172         struct dc_context *ctx = dc->ctx;
2173         struct irq_service_init_data init_data;
2174
2175         DC_FP_START();
2176
2177         ctx->dc_bios->regs = &bios_regs;
2178
2179         pool->base.res_cap = &res_cap_dcn31;
2180
2181         pool->base.funcs = &dcn31_res_pool_funcs;
2182
2183         /*************************************************
2184          *  Resource + asic cap harcoding                *
2185          *************************************************/
2186         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2187         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2188         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2189         dc->caps.max_downscale_ratio = 600;
2190         dc->caps.i2c_speed_in_khz = 100;
2191         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
2192         dc->caps.max_cursor_size = 256;
2193         dc->caps.min_horizontal_blanking_period = 80;
2194         dc->caps.dmdata_alloc_size = 2048;
2195
2196         dc->caps.max_slave_planes = 1;
2197         dc->caps.max_slave_yuv_planes = 1;
2198         dc->caps.max_slave_rgb_planes = 1;
2199         dc->caps.post_blend_color_processing = true;
2200         dc->caps.force_dp_tps4_for_cp2520 = true;
2201         dc->caps.dp_hpo = true;
2202         dc->caps.hdmi_frl_pcon_support = true;
2203         dc->caps.edp_dsc_support = true;
2204         dc->caps.extended_aux_timeout_support = true;
2205         dc->caps.dmcub_support = true;
2206         dc->caps.is_apu = true;
2207
2208         /* Color pipeline capabilities */
2209         dc->caps.color.dpp.dcn_arch = 1;
2210         dc->caps.color.dpp.input_lut_shared = 0;
2211         dc->caps.color.dpp.icsc = 1;
2212         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2213         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2214         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2215         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2216         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2217         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2218         dc->caps.color.dpp.post_csc = 1;
2219         dc->caps.color.dpp.gamma_corr = 1;
2220         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2221
2222         dc->caps.color.dpp.hw_3d_lut = 1;
2223         dc->caps.color.dpp.ogam_ram = 1;
2224         // no OGAM ROM on DCN301
2225         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2226         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2227         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2228         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2229         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2230         dc->caps.color.dpp.ocsc = 0;
2231
2232         dc->caps.color.mpc.gamut_remap = 1;
2233         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
2234         dc->caps.color.mpc.ogam_ram = 1;
2235         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2236         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2237         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2238         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2239         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2240         dc->caps.color.mpc.ocsc = 1;
2241
2242         /* read VBIOS LTTPR caps */
2243         {
2244                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2245                         enum bp_result bp_query_result;
2246                         uint8_t is_vbios_lttpr_enable = 0;
2247
2248                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2249                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2250                 }
2251
2252                 /* interop bit is implicit */
2253                 {
2254                         dc->caps.vbios_lttpr_aware = true;
2255                 }
2256         }
2257
2258         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2259                 dc->debug = debug_defaults_drv;
2260         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2261                 dc->debug = debug_defaults_diags;
2262         } else
2263                 dc->debug = debug_defaults_diags;
2264         // Init the vm_helper
2265         if (dc->vm_helper)
2266                 vm_helper_init(dc->vm_helper, 16);
2267
2268         /*************************************************
2269          *  Create resources                             *
2270          *************************************************/
2271
2272         /* Clock Sources for Pixel Clock*/
2273         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2274                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2275                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2276                                 &clk_src_regs[0], false);
2277         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2278                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2279                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2280                                 &clk_src_regs[1], false);
2281         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2282                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2283                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2284                                 &clk_src_regs[2], false);
2285         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2286                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2287                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2288                                 &clk_src_regs[3], false);
2289         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2290                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2291                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2292                                 &clk_src_regs[4], false);
2293
2294         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2295
2296         /* todo: not reuse phy_pll registers */
2297         pool->base.dp_clock_source =
2298                         dcn31_clock_source_create(ctx, ctx->dc_bios,
2299                                 CLOCK_SOURCE_ID_DP_DTO,
2300                                 &clk_src_regs[0], true);
2301
2302         for (i = 0; i < pool->base.clk_src_count; i++) {
2303                 if (pool->base.clock_sources[i] == NULL) {
2304                         dm_error("DC: failed to create clock sources!\n");
2305                         BREAK_TO_DEBUGGER();
2306                         goto create_fail;
2307                 }
2308         }
2309
2310         /* TODO: DCCG */
2311         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2312         if (pool->base.dccg == NULL) {
2313                 dm_error("DC: failed to create dccg!\n");
2314                 BREAK_TO_DEBUGGER();
2315                 goto create_fail;
2316         }
2317
2318         /* TODO: IRQ */
2319         init_data.ctx = dc->ctx;
2320         pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2321         if (!pool->base.irqs)
2322                 goto create_fail;
2323
2324         /* HUBBUB */
2325         pool->base.hubbub = dcn31_hubbub_create(ctx);
2326         if (pool->base.hubbub == NULL) {
2327                 BREAK_TO_DEBUGGER();
2328                 dm_error("DC: failed to create hubbub!\n");
2329                 goto create_fail;
2330         }
2331
2332         /* HUBPs, DPPs, OPPs and TGs */
2333         for (i = 0; i < pool->base.pipe_count; i++) {
2334                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2335                 if (pool->base.hubps[i] == NULL) {
2336                         BREAK_TO_DEBUGGER();
2337                         dm_error(
2338                                 "DC: failed to create hubps!\n");
2339                         goto create_fail;
2340                 }
2341
2342                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2343                 if (pool->base.dpps[i] == NULL) {
2344                         BREAK_TO_DEBUGGER();
2345                         dm_error(
2346                                 "DC: failed to create dpps!\n");
2347                         goto create_fail;
2348                 }
2349         }
2350
2351         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2352                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2353                 if (pool->base.opps[i] == NULL) {
2354                         BREAK_TO_DEBUGGER();
2355                         dm_error(
2356                                 "DC: failed to create output pixel processor!\n");
2357                         goto create_fail;
2358                 }
2359         }
2360
2361         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2362                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2363                                 ctx, i);
2364                 if (pool->base.timing_generators[i] == NULL) {
2365                         BREAK_TO_DEBUGGER();
2366                         dm_error("DC: failed to create tg!\n");
2367                         goto create_fail;
2368                 }
2369         }
2370         pool->base.timing_generator_count = i;
2371
2372         /* PSR */
2373         pool->base.psr = dmub_psr_create(ctx);
2374         if (pool->base.psr == NULL) {
2375                 dm_error("DC: failed to create psr obj!\n");
2376                 BREAK_TO_DEBUGGER();
2377                 goto create_fail;
2378         }
2379
2380         /* ABM */
2381         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2382                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2383                                 &abm_regs[i],
2384                                 &abm_shift,
2385                                 &abm_mask);
2386                 if (pool->base.multiple_abms[i] == NULL) {
2387                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2388                         BREAK_TO_DEBUGGER();
2389                         goto create_fail;
2390                 }
2391         }
2392
2393         /* MPC and DSC */
2394         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2395         if (pool->base.mpc == NULL) {
2396                 BREAK_TO_DEBUGGER();
2397                 dm_error("DC: failed to create mpc!\n");
2398                 goto create_fail;
2399         }
2400
2401         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2402                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2403                 if (pool->base.dscs[i] == NULL) {
2404                         BREAK_TO_DEBUGGER();
2405                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2406                         goto create_fail;
2407                 }
2408         }
2409
2410         /* DWB and MMHUBBUB */
2411         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2412                 BREAK_TO_DEBUGGER();
2413                 dm_error("DC: failed to create dwbc!\n");
2414                 goto create_fail;
2415         }
2416
2417         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2418                 BREAK_TO_DEBUGGER();
2419                 dm_error("DC: failed to create mcif_wb!\n");
2420                 goto create_fail;
2421         }
2422
2423         /* AUX and I2C */
2424         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2425                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2426                 if (pool->base.engines[i] == NULL) {
2427                         BREAK_TO_DEBUGGER();
2428                         dm_error(
2429                                 "DC:failed to create aux engine!!\n");
2430                         goto create_fail;
2431                 }
2432                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2433                 if (pool->base.hw_i2cs[i] == NULL) {
2434                         BREAK_TO_DEBUGGER();
2435                         dm_error(
2436                                 "DC:failed to create hw i2c!!\n");
2437                         goto create_fail;
2438                 }
2439                 pool->base.sw_i2cs[i] = NULL;
2440         }
2441
2442         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2443             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2444             !dc->debug.dpia_debug.bits.disable_dpia) {
2445                 /* YELLOW CARP B0 has 4 DPIA's */
2446                 pool->base.usb4_dpia_count = 4;
2447         }
2448
2449         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2450         if (!resource_construct(num_virtual_links, dc, &pool->base,
2451                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2452                         &res_create_funcs : &res_create_maximus_funcs)))
2453                         goto create_fail;
2454
2455         /* HW Sequencer and Plane caps */
2456         dcn31_hw_sequencer_construct(dc);
2457
2458         dc->caps.max_planes =  pool->base.pipe_count;
2459
2460         for (i = 0; i < dc->caps.max_planes; ++i)
2461                 dc->caps.planes[i] = plane_cap;
2462
2463         dc->cap_funcs = cap_funcs;
2464
2465         dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2466
2467         DC_FP_END();
2468
2469         return true;
2470
2471 create_fail:
2472
2473         DC_FP_END();
2474         dcn31_resource_destruct(pool);
2475
2476         return false;
2477 }
2478
2479 struct resource_pool *dcn31_create_resource_pool(
2480                 const struct dc_init_data *init_data,
2481                 struct dc *dc)
2482 {
2483         struct dcn31_resource_pool *pool =
2484                 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2485
2486         if (!pool)
2487                 return NULL;
2488
2489         if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2490                 return &pool->base;
2491
2492         BREAK_TO_DEBUGGER();
2493         kfree(pool);
2494         return NULL;
2495 }