2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
30 #include "dcn30_init.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
36 #include "dcn30_resource.h"
38 #include "dcn10/dcn10_ipp.h"
39 #include "dcn30/dcn30_hubbub.h"
40 #include "dcn30/dcn30_mpc.h"
41 #include "dcn30/dcn30_hubp.h"
42 #include "irq/dcn30/irq_service_dcn30.h"
43 #include "dcn30/dcn30_dpp.h"
44 #include "dcn30/dcn30_optc.h"
45 #include "dcn20/dcn20_hwseq.h"
46 #include "dcn30/dcn30_hwseq.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn30/dcn30_opp.h"
49 #include "dcn20/dcn20_dsc.h"
50 #include "dcn30/dcn30_vpg.h"
51 #include "dcn30/dcn30_afmt.h"
52 #include "dcn30/dcn30_dio_stream_encoder.h"
53 #include "dcn30/dcn30_dio_link_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn30/dcn30_dccg.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "dc_link_ddc.h"
64 #include "dce/dce_panel_cntl.h"
66 #include "dcn30/dcn30_dwb.h"
67 #include "dcn30/dcn30_mmhubbub.h"
69 #include "sienna_cichlid_ip_offset.h"
70 #include "dcn/dcn_3_0_0_offset.h"
71 #include "dcn/dcn_3_0_0_sh_mask.h"
73 #include "nbio/nbio_7_4_offset.h"
75 #include "dpcs/dpcs_3_0_0_offset.h"
76 #include "dpcs/dpcs_3_0_0_sh_mask.h"
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
87 #include "dml/dcn30/dcn30_fpu.h"
88 #include "dml/dcn30/display_mode_vba_30.h"
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91 #include "amdgpu_socbb.h"
92 #include "dc_dmub_srv.h"
94 #define DC_LOGGER_INIT(logger)
96 enum dcn30_clk_src_array_id {
106 /* begin *********************
107 * macros to expend register list macro defined in HW object header file
111 /* TODO awful hack. fixup dcn20_dwb.h */
113 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
115 #define BASE(seg) BASE_INNER(seg)
117 #define SR(reg_name)\
118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
121 #define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
125 #define SRI2(reg_name, block, id)\
126 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
129 #define SRIR(var_name, reg_name, block, id)\
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
133 #define SRII(reg_name, block, id)\
134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## id ## _ ## reg_name
137 #define SRII_MPC_RMU(reg_name, block, id)\
138 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 mm ## block ## id ## _ ## reg_name
141 #define SRII_DWB(reg_name, temp_name, block, id)\
142 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## temp_name
145 #define DCCG_SRII(reg_name, block, id)\
146 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 mm ## block ## id ## _ ## reg_name
149 #define VUPDATE_SRII(reg_name, block, id)\
150 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
151 mm ## reg_name ## _ ## block ## id
154 #define NBIO_BASE_INNER(seg) \
155 NBIO_BASE__INST0_SEG ## seg
157 #define NBIO_BASE(seg) \
160 #define NBIO_SR(reg_name)\
161 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
165 #define MMHUB_BASE_INNER(seg) \
166 MMHUB_BASE__INST0_SEG ## seg
168 #define MMHUB_BASE(seg) \
169 MMHUB_BASE_INNER(seg)
171 #define MMHUB_SR(reg_name)\
172 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
176 #define CLK_BASE_INNER(seg) \
177 CLK_BASE__INST0_SEG ## seg
179 #define CLK_BASE(seg) \
182 #define CLK_SRI(reg_name, block, inst)\
183 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
184 mm ## block ## _ ## inst ## _ ## reg_name
187 static const struct bios_registers bios_regs = {
188 NBIO_SR(BIOS_SCRATCH_3),
189 NBIO_SR(BIOS_SCRATCH_6)
192 #define clk_src_regs(index, pllid)\
194 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
197 static const struct dce110_clk_src_regs clk_src_regs[] = {
206 static const struct dce110_clk_src_shift cs_shift = {
207 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
210 static const struct dce110_clk_src_mask cs_mask = {
211 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
214 #define abm_regs(id)\
216 ABM_DCN30_REG_LIST(id)\
219 static const struct dce_abm_registers abm_regs[] = {
228 static const struct dce_abm_shift abm_shift = {
229 ABM_MASK_SH_LIST_DCN30(__SHIFT)
232 static const struct dce_abm_mask abm_mask = {
233 ABM_MASK_SH_LIST_DCN30(_MASK)
238 #define audio_regs(id)\
240 AUD_COMMON_REG_LIST(id)\
243 static const struct dce_audio_registers audio_regs[] = {
253 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
258 static const struct dce_audio_shift audio_shift = {
259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
262 static const struct dce_audio_mask audio_mask = {
263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
266 #define vpg_regs(id)\
268 VPG_DCN3_REG_LIST(id)\
271 static const struct dcn30_vpg_registers vpg_regs[] = {
281 static const struct dcn30_vpg_shift vpg_shift = {
282 DCN3_VPG_MASK_SH_LIST(__SHIFT)
285 static const struct dcn30_vpg_mask vpg_mask = {
286 DCN3_VPG_MASK_SH_LIST(_MASK)
289 #define afmt_regs(id)\
291 AFMT_DCN3_REG_LIST(id)\
294 static const struct dcn30_afmt_registers afmt_regs[] = {
304 static const struct dcn30_afmt_shift afmt_shift = {
305 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
308 static const struct dcn30_afmt_mask afmt_mask = {
309 DCN3_AFMT_MASK_SH_LIST(_MASK)
312 #define stream_enc_regs(id)\
314 SE_DCN3_REG_LIST(id)\
317 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
326 static const struct dcn10_stream_encoder_shift se_shift = {
327 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
330 static const struct dcn10_stream_encoder_mask se_mask = {
331 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
335 #define aux_regs(id)\
337 DCN2_AUX_REG_LIST(id)\
340 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
349 #define hpd_regs(id)\
354 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
363 #define link_regs(id, phyid)\
365 LE_DCN3_REG_LIST(id), \
366 UNIPHY_DCN2_REG_LIST(phyid), \
367 DPCS_DCN2_REG_LIST(id), \
368 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
371 static const struct dce110_aux_registers_shift aux_shift = {
372 DCN_AUX_MASK_SH_LIST(__SHIFT)
375 static const struct dce110_aux_registers_mask aux_mask = {
376 DCN_AUX_MASK_SH_LIST(_MASK)
379 static const struct dcn10_link_enc_registers link_enc_regs[] = {
388 static const struct dcn10_link_enc_shift le_shift = {
389 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
390 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
393 static const struct dcn10_link_enc_mask le_mask = {
394 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
395 DPCS_DCN2_MASK_SH_LIST(_MASK)
399 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
400 { DCN_PANEL_CNTL_REG_LIST() }
403 static const struct dce_panel_cntl_shift panel_cntl_shift = {
404 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
407 static const struct dce_panel_cntl_mask panel_cntl_mask = {
408 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
411 #define dpp_regs(id)\
413 DPP_REG_LIST_DCN30(id),\
416 static const struct dcn3_dpp_registers dpp_regs[] = {
425 static const struct dcn3_dpp_shift tf_shift = {
426 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
429 static const struct dcn3_dpp_mask tf_mask = {
430 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
433 #define opp_regs(id)\
435 OPP_REG_LIST_DCN30(id),\
438 static const struct dcn20_opp_registers opp_regs[] = {
447 static const struct dcn20_opp_shift opp_shift = {
448 OPP_MASK_SH_LIST_DCN20(__SHIFT)
451 static const struct dcn20_opp_mask opp_mask = {
452 OPP_MASK_SH_LIST_DCN20(_MASK)
455 #define aux_engine_regs(id)\
457 AUX_COMMON_REG_LIST0(id), \
460 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
463 static const struct dce110_aux_registers aux_engine_regs[] = {
472 #define dwbc_regs_dcn3(id)\
474 DWBC_COMMON_REG_LIST_DCN30(id),\
477 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
481 static const struct dcn30_dwbc_shift dwbc30_shift = {
482 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
485 static const struct dcn30_dwbc_mask dwbc30_mask = {
486 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
489 #define mcif_wb_regs_dcn3(id)\
491 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
494 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
498 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
499 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
502 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
503 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
506 #define dsc_regsDCN20(id)\
508 DSC_REG_LIST_DCN20(id)\
511 static const struct dcn20_dsc_registers dsc_regs[] = {
520 static const struct dcn20_dsc_shift dsc_shift = {
521 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
524 static const struct dcn20_dsc_mask dsc_mask = {
525 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
528 static const struct dcn30_mpc_registers mpc_regs = {
529 MPC_REG_LIST_DCN3_0(0),
530 MPC_REG_LIST_DCN3_0(1),
531 MPC_REG_LIST_DCN3_0(2),
532 MPC_REG_LIST_DCN3_0(3),
533 MPC_REG_LIST_DCN3_0(4),
534 MPC_REG_LIST_DCN3_0(5),
535 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
536 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
537 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
538 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
539 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
540 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
541 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
542 MPC_RMU_REG_LIST_DCN3AG(0),
543 MPC_RMU_REG_LIST_DCN3AG(1),
544 MPC_RMU_REG_LIST_DCN3AG(2),
545 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
548 static const struct dcn30_mpc_shift mpc_shift = {
549 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
552 static const struct dcn30_mpc_mask mpc_mask = {
553 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
556 #define optc_regs(id)\
557 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
560 static const struct dcn_optc_registers optc_regs[] = {
569 static const struct dcn_optc_shift optc_shift = {
570 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
573 static const struct dcn_optc_mask optc_mask = {
574 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
577 #define hubp_regs(id)\
579 HUBP_REG_LIST_DCN30(id)\
582 static const struct dcn_hubp2_registers hubp_regs[] = {
591 static const struct dcn_hubp2_shift hubp_shift = {
592 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
595 static const struct dcn_hubp2_mask hubp_mask = {
596 HUBP_MASK_SH_LIST_DCN30(_MASK)
599 static const struct dcn_hubbub_registers hubbub_reg = {
600 HUBBUB_REG_LIST_DCN30(0)
603 static const struct dcn_hubbub_shift hubbub_shift = {
604 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
607 static const struct dcn_hubbub_mask hubbub_mask = {
608 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
611 static const struct dccg_registers dccg_regs = {
612 DCCG_REG_LIST_DCN30()
615 static const struct dccg_shift dccg_shift = {
616 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
619 static const struct dccg_mask dccg_mask = {
620 DCCG_MASK_SH_LIST_DCN3(_MASK)
623 static const struct dce_hwseq_registers hwseq_reg = {
624 HWSEQ_DCN30_REG_LIST()
627 static const struct dce_hwseq_shift hwseq_shift = {
628 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
631 static const struct dce_hwseq_mask hwseq_mask = {
632 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
634 #define vmid_regs(id)\
636 DCN20_VMID_REG_LIST(id)\
639 static const struct dcn_vmid_registers vmid_regs[] = {
658 static const struct dcn20_vmid_shift vmid_shifts = {
659 DCN20_VMID_MASK_SH_LIST(__SHIFT)
662 static const struct dcn20_vmid_mask vmid_masks = {
663 DCN20_VMID_MASK_SH_LIST(_MASK)
666 static const struct resource_caps res_cap_dcn3 = {
667 .num_timing_generator = 6,
669 .num_video_plane = 6,
671 .num_stream_encoder = 6,
680 static const struct dc_plane_cap plane_cap = {
681 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
682 .blends_with_above = true,
683 .blends_with_below = true,
684 .per_pixel_alpha = true,
686 .pixel_format_support = {
694 .max_upscale_factor = {
700 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
701 .max_downscale_factor = {
708 static const struct dc_debug_options debug_defaults_drv = {
709 .disable_dmcu = true, //No DMCU on DCN30
710 .force_abm_enable = false,
711 .timing_trace = false,
713 .disable_pplib_clock_request = true,
714 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
715 .force_single_disp_pipe_split = false,
716 .disable_dcc = DCC_ENABLE,
718 .performance_trace = false,
719 .max_downscale_src_width = 7680,/*upto 8K*/
720 .disable_pplib_wm_range = false,
721 .scl_reset_length10 = true,
722 .sanity_checks = false,
723 .underflow_assert_delay_us = 0xFFFFFFFF,
724 .dwb_fi_phase = -1, // -1 = disable,
725 .dmub_command_table = true,
726 .disable_psr = false,
728 .exit_idle_opt_for_cursor_updates = true
731 static const struct dc_debug_options debug_defaults_diags = {
732 .disable_dmcu = true, //No dmcu on DCN30
733 .force_abm_enable = false,
734 .timing_trace = true,
736 .disable_dpp_power_gate = true,
737 .disable_hubp_power_gate = true,
738 .disable_clock_gate = true,
739 .disable_pplib_clock_request = true,
740 .disable_pplib_wm_range = true,
741 .disable_stutter = false,
742 .scl_reset_length10 = true,
743 .dwb_fi_phase = -1, // -1 = disable
744 .dmub_command_table = true,
746 .enable_tri_buf = true,
750 static void dcn30_dpp_destroy(struct dpp **dpp)
752 kfree(TO_DCN20_DPP(*dpp));
756 static struct dpp *dcn30_dpp_create(
757 struct dc_context *ctx,
760 struct dcn3_dpp *dpp =
761 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
766 if (dpp3_construct(dpp, ctx, inst,
767 &dpp_regs[inst], &tf_shift, &tf_mask))
775 static struct output_pixel_processor *dcn30_opp_create(
776 struct dc_context *ctx, uint32_t inst)
778 struct dcn20_opp *opp =
779 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
786 dcn20_opp_construct(opp, ctx, inst,
787 &opp_regs[inst], &opp_shift, &opp_mask);
791 static struct dce_aux *dcn30_aux_engine_create(
792 struct dc_context *ctx,
795 struct aux_engine_dce110 *aux_engine =
796 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
801 dce110_aux_engine_construct(aux_engine, ctx, inst,
802 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
803 &aux_engine_regs[inst],
806 ctx->dc->caps.extended_aux_timeout_support);
808 return &aux_engine->base;
811 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
813 static const struct dce_i2c_registers i2c_hw_regs[] = {
822 static const struct dce_i2c_shift i2c_shifts = {
823 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
826 static const struct dce_i2c_mask i2c_masks = {
827 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
830 static struct dce_i2c_hw *dcn30_i2c_hw_create(
831 struct dc_context *ctx,
834 struct dce_i2c_hw *dce_i2c_hw =
835 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
840 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
841 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
846 static struct mpc *dcn30_mpc_create(
847 struct dc_context *ctx,
851 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
857 dcn30_mpc_construct(mpc30, ctx,
867 static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
871 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
877 hubbub3_construct(hubbub3, ctx,
883 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
884 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
888 vmid->regs = &vmid_regs[i];
889 vmid->shifts = &vmid_shifts;
890 vmid->masks = &vmid_masks;
893 return &hubbub3->base;
896 static struct timing_generator *dcn30_timing_generator_create(
897 struct dc_context *ctx,
901 kzalloc(sizeof(struct optc), GFP_KERNEL);
906 tgn10->base.inst = instance;
907 tgn10->base.ctx = ctx;
909 tgn10->tg_regs = &optc_regs[instance];
910 tgn10->tg_shift = &optc_shift;
911 tgn10->tg_mask = &optc_mask;
913 dcn30_timing_generator_init(tgn10);
918 static const struct encoder_feature_support link_enc_feature = {
919 .max_hdmi_deep_color = COLOR_DEPTH_121212,
920 .max_hdmi_pixel_clock = 600000,
921 .hdmi_ycbcr420_supported = true,
922 .dp_ycbcr420_supported = true,
923 .fec_supported = true,
924 .flags.bits.IS_HBR2_CAPABLE = true,
925 .flags.bits.IS_HBR3_CAPABLE = true,
926 .flags.bits.IS_TPS3_CAPABLE = true,
927 .flags.bits.IS_TPS4_CAPABLE = true
930 static struct link_encoder *dcn30_link_encoder_create(
931 struct dc_context *ctx,
932 const struct encoder_init_data *enc_init_data)
934 struct dcn20_link_encoder *enc20 =
935 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
940 dcn30_link_encoder_construct(enc20,
943 &link_enc_regs[enc_init_data->transmitter],
944 &link_enc_aux_regs[enc_init_data->channel - 1],
945 &link_enc_hpd_regs[enc_init_data->hpd_source],
949 return &enc20->enc10.base;
952 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
954 struct dce_panel_cntl *panel_cntl =
955 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
960 dce_panel_cntl_construct(panel_cntl,
962 &panel_cntl_regs[init_data->inst],
966 return &panel_cntl->base;
969 static void read_dce_straps(
970 struct dc_context *ctx,
971 struct resource_straps *straps)
973 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
974 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
978 static struct audio *dcn30_create_audio(
979 struct dc_context *ctx, unsigned int inst)
981 return dce_audio_create(ctx, inst,
982 &audio_regs[inst], &audio_shift, &audio_mask);
985 static struct vpg *dcn30_vpg_create(
986 struct dc_context *ctx,
989 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
994 vpg3_construct(vpg3, ctx, inst,
1002 static struct afmt *dcn30_afmt_create(
1003 struct dc_context *ctx,
1006 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1011 afmt3_construct(afmt3, ctx, inst,
1016 return &afmt3->base;
1019 static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1020 struct dc_context *ctx)
1022 struct dcn10_stream_encoder *enc1;
1028 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1029 if (eng_id <= ENGINE_ID_DIGF) {
1035 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1036 vpg = dcn30_vpg_create(ctx, vpg_inst);
1037 afmt = dcn30_afmt_create(ctx, afmt_inst);
1039 if (!enc1 || !vpg || !afmt) {
1046 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1048 &stream_enc_regs[eng_id],
1049 &se_shift, &se_mask);
1054 static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1056 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1060 hws->regs = &hwseq_reg;
1061 hws->shifts = &hwseq_shift;
1062 hws->masks = &hwseq_mask;
1066 static const struct resource_create_funcs res_create_funcs = {
1067 .read_dce_straps = read_dce_straps,
1068 .create_audio = dcn30_create_audio,
1069 .create_stream_encoder = dcn30_stream_encoder_create,
1070 .create_hwseq = dcn30_hwseq_create,
1073 static const struct resource_create_funcs res_create_maximus_funcs = {
1074 .read_dce_straps = NULL,
1075 .create_audio = NULL,
1076 .create_stream_encoder = NULL,
1077 .create_hwseq = dcn30_hwseq_create,
1080 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1084 for (i = 0; i < pool->base.stream_enc_count; i++) {
1085 if (pool->base.stream_enc[i] != NULL) {
1086 if (pool->base.stream_enc[i]->vpg != NULL) {
1087 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1088 pool->base.stream_enc[i]->vpg = NULL;
1090 if (pool->base.stream_enc[i]->afmt != NULL) {
1091 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1092 pool->base.stream_enc[i]->afmt = NULL;
1094 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1095 pool->base.stream_enc[i] = NULL;
1099 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1100 if (pool->base.dscs[i] != NULL)
1101 dcn20_dsc_destroy(&pool->base.dscs[i]);
1104 if (pool->base.mpc != NULL) {
1105 kfree(TO_DCN20_MPC(pool->base.mpc));
1106 pool->base.mpc = NULL;
1108 if (pool->base.hubbub != NULL) {
1109 kfree(pool->base.hubbub);
1110 pool->base.hubbub = NULL;
1112 for (i = 0; i < pool->base.pipe_count; i++) {
1113 if (pool->base.dpps[i] != NULL)
1114 dcn30_dpp_destroy(&pool->base.dpps[i]);
1116 if (pool->base.ipps[i] != NULL)
1117 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1119 if (pool->base.hubps[i] != NULL) {
1120 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1121 pool->base.hubps[i] = NULL;
1124 if (pool->base.irqs != NULL) {
1125 dal_irq_service_destroy(&pool->base.irqs);
1129 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1130 if (pool->base.engines[i] != NULL)
1131 dce110_engine_destroy(&pool->base.engines[i]);
1132 if (pool->base.hw_i2cs[i] != NULL) {
1133 kfree(pool->base.hw_i2cs[i]);
1134 pool->base.hw_i2cs[i] = NULL;
1136 if (pool->base.sw_i2cs[i] != NULL) {
1137 kfree(pool->base.sw_i2cs[i]);
1138 pool->base.sw_i2cs[i] = NULL;
1142 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1143 if (pool->base.opps[i] != NULL)
1144 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1147 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1148 if (pool->base.timing_generators[i] != NULL) {
1149 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1150 pool->base.timing_generators[i] = NULL;
1154 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1155 if (pool->base.dwbc[i] != NULL) {
1156 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1157 pool->base.dwbc[i] = NULL;
1159 if (pool->base.mcif_wb[i] != NULL) {
1160 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1161 pool->base.mcif_wb[i] = NULL;
1165 for (i = 0; i < pool->base.audio_count; i++) {
1166 if (pool->base.audios[i])
1167 dce_aud_destroy(&pool->base.audios[i]);
1170 for (i = 0; i < pool->base.clk_src_count; i++) {
1171 if (pool->base.clock_sources[i] != NULL) {
1172 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1173 pool->base.clock_sources[i] = NULL;
1177 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1178 if (pool->base.mpc_lut[i] != NULL) {
1179 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1180 pool->base.mpc_lut[i] = NULL;
1182 if (pool->base.mpc_shaper[i] != NULL) {
1183 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1184 pool->base.mpc_shaper[i] = NULL;
1188 if (pool->base.dp_clock_source != NULL) {
1189 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1190 pool->base.dp_clock_source = NULL;
1193 for (i = 0; i < pool->base.pipe_count; i++) {
1194 if (pool->base.multiple_abms[i] != NULL)
1195 dce_abm_destroy(&pool->base.multiple_abms[i]);
1198 if (pool->base.psr != NULL)
1199 dmub_psr_destroy(&pool->base.psr);
1201 if (pool->base.dccg != NULL)
1202 dcn_dccg_destroy(&pool->base.dccg);
1204 if (pool->base.oem_device != NULL)
1205 dal_ddc_service_destroy(&pool->base.oem_device);
1208 static struct hubp *dcn30_hubp_create(
1209 struct dc_context *ctx,
1212 struct dcn20_hubp *hubp2 =
1213 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1218 if (hubp3_construct(hubp2, ctx, inst,
1219 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1220 return &hubp2->base;
1222 BREAK_TO_DEBUGGER();
1227 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1230 uint32_t pipe_count = pool->res_cap->num_dwb;
1232 for (i = 0; i < pipe_count; i++) {
1233 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1237 dm_error("DC: failed to create dwbc30!\n");
1241 dcn30_dwbc_construct(dwbc30, ctx,
1247 pool->dwbc[i] = &dwbc30->base;
1252 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1255 uint32_t pipe_count = pool->res_cap->num_dwb;
1257 for (i = 0; i < pipe_count; i++) {
1258 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1262 dm_error("DC: failed to create mcif_wb30!\n");
1266 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1272 pool->mcif_wb[i] = &mcif_wb30->base;
1277 static struct display_stream_compressor *dcn30_dsc_create(
1278 struct dc_context *ctx, uint32_t inst)
1280 struct dcn20_dsc *dsc =
1281 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1284 BREAK_TO_DEBUGGER();
1288 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1292 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1295 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1298 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1300 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1302 dcn30_resource_destruct(dcn30_pool);
1307 static struct clock_source *dcn30_clock_source_create(
1308 struct dc_context *ctx,
1309 struct dc_bios *bios,
1310 enum clock_source_id id,
1311 const struct dce110_clk_src_regs *regs,
1314 struct dce110_clk_src *clk_src =
1315 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1320 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1321 regs, &cs_shift, &cs_mask)) {
1322 clk_src->base.dp_clk_src = dp_clk_src;
1323 return &clk_src->base;
1326 BREAK_TO_DEBUGGER();
1330 int dcn30_populate_dml_pipes_from_context(
1331 struct dc *dc, struct dc_state *context,
1332 display_e2e_pipe_params_st *pipes,
1336 struct resource_context *res_ctx = &context->res_ctx;
1339 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1342 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1343 if (!res_ctx->pipe_ctx[i].stream)
1346 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1353 void dcn30_populate_dml_writeback_from_context(
1354 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1357 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1361 unsigned int dcn30_calc_max_scaled_time(
1362 unsigned int time_per_pixel,
1363 enum mmhubbub_wbif_mode mode,
1364 unsigned int urgent_watermark)
1366 unsigned int time_per_byte = 0;
1367 unsigned int total_free_entry = 0xb40;
1368 unsigned int buf_lh_capability;
1369 unsigned int max_scaled_time;
1371 if (mode == PACKED_444) /* packed mode 32 bpp */
1372 time_per_byte = time_per_pixel/4;
1373 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1374 time_per_byte = time_per_pixel/8;
1376 if (time_per_byte == 0)
1379 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1380 max_scaled_time = buf_lh_capability - urgent_watermark;
1381 return max_scaled_time;
1384 void dcn30_set_mcif_arb_params(
1386 struct dc_state *context,
1387 display_e2e_pipe_params_st *pipes,
1390 enum mmhubbub_wbif_mode wbif_mode;
1391 struct display_mode_lib *dml = &context->bw_ctx.dml;
1392 struct mcif_arb_params *wb_arb_params;
1395 /* Writeback MCIF_WB arbitration parameters */
1397 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1399 if (!context->res_ctx.pipe_ctx[i].stream)
1402 for (j = 0; j < MAX_DWB_PIPES; j++) {
1403 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1405 if (writeback_info->wb_enabled == false)
1408 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1409 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1411 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1412 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1413 wbif_mode = PACKED_444_FP16;
1415 wbif_mode = PACKED_444;
1418 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1420 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1421 wb_arb_params->slice_lines = 32;
1422 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1423 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1425 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1429 if (dwb_pipe >= MAX_DWB_PIPES)
1432 if (dwb_pipe >= MAX_DWB_PIPES)
1438 static struct dc_cap_funcs cap_funcs = {
1439 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1442 bool dcn30_acquire_post_bldn_3dlut(
1443 struct resource_context *res_ctx,
1444 const struct resource_pool *pool,
1446 struct dc_3dlut **lut,
1447 struct dc_transfer_func **shaper)
1451 union dc_3dlut_state *state;
1453 ASSERT(*lut == NULL && *shaper == NULL);
1457 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1458 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1459 *lut = pool->mpc_lut[i];
1460 *shaper = pool->mpc_shaper[i];
1461 state = &pool->mpc_lut[i]->state;
1462 res_ctx->is_mpc_3dlut_acquired[i] = true;
1463 state->bits.rmu_idx_valid = 1;
1464 state->bits.rmu_mux_num = i;
1465 if (state->bits.rmu_mux_num == 0)
1466 state->bits.mpc_rmu0_mux = mpcc_id;
1467 else if (state->bits.rmu_mux_num == 1)
1468 state->bits.mpc_rmu1_mux = mpcc_id;
1469 else if (state->bits.rmu_mux_num == 2)
1470 state->bits.mpc_rmu2_mux = mpcc_id;
1478 bool dcn30_release_post_bldn_3dlut(
1479 struct resource_context *res_ctx,
1480 const struct resource_pool *pool,
1481 struct dc_3dlut **lut,
1482 struct dc_transfer_func **shaper)
1487 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1488 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1489 res_ctx->is_mpc_3dlut_acquired[i] = false;
1490 pool->mpc_lut[i]->state.raw = 0;
1500 static bool is_soc_bounding_box_valid(struct dc *dc)
1502 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1504 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1510 static bool init_soc_bounding_box(struct dc *dc,
1511 struct dcn30_resource_pool *pool)
1513 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1514 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1516 DC_LOGGER_INIT(dc->ctx->logger);
1518 if (!is_soc_bounding_box_valid(dc)) {
1519 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1523 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1524 loaded_ip->max_num_dpp = pool->base.pipe_count;
1525 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1526 dcn20_patch_bounding_box(dc, loaded_bb);
1528 patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);
1534 static bool dcn30_split_stream_for_mpc_or_odm(
1535 const struct dc *dc,
1536 struct resource_context *res_ctx,
1537 struct pipe_ctx *pri_pipe,
1538 struct pipe_ctx *sec_pipe,
1541 int pipe_idx = sec_pipe->pipe_idx;
1542 const struct resource_pool *pool = dc->res_pool;
1544 *sec_pipe = *pri_pipe;
1546 sec_pipe->pipe_idx = pipe_idx;
1547 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1548 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1549 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1550 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1551 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1552 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1553 sec_pipe->stream_res.dsc = NULL;
1555 if (pri_pipe->next_odm_pipe) {
1556 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1557 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1558 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1560 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1561 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1562 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1564 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1565 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1566 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1568 pri_pipe->next_odm_pipe = sec_pipe;
1569 sec_pipe->prev_odm_pipe = pri_pipe;
1571 if (!sec_pipe->top_pipe)
1572 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1574 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1575 if (sec_pipe->stream->timing.flags.DSC == 1) {
1576 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1577 ASSERT(sec_pipe->stream_res.dsc);
1578 if (sec_pipe->stream_res.dsc == NULL)
1582 if (pri_pipe->bottom_pipe) {
1583 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1584 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1585 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1587 pri_pipe->bottom_pipe = sec_pipe;
1588 sec_pipe->top_pipe = pri_pipe;
1590 ASSERT(pri_pipe->plane_state);
1596 static struct pipe_ctx *dcn30_find_split_pipe(
1598 struct dc_state *context,
1601 struct pipe_ctx *pipe = NULL;
1604 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1605 pipe = &context->res_ctx.pipe_ctx[old_index];
1606 pipe->pipe_idx = old_index;
1610 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1611 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1612 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1613 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1614 pipe = &context->res_ctx.pipe_ctx[i];
1622 * May need to fix pipes getting tossed from 1 opp to another on flip
1623 * Add for debugging transient underflow during topology updates:
1627 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1628 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1629 pipe = &context->res_ctx.pipe_ctx[i];
1638 noinline bool dcn30_internal_validate_bw(
1640 struct dc_state *context,
1641 display_e2e_pipe_params_st *pipes,
1647 bool repopulate_pipes = false;
1648 int split[MAX_PIPES] = { 0 };
1649 bool merge[MAX_PIPES] = { false };
1650 bool newly_split[MAX_PIPES] = { false };
1651 int pipe_cnt, i, pipe_idx, vlevel;
1652 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1658 context->bw_ctx.dml.vba.maxMpcComb = 0;
1659 context->bw_ctx.dml.vba.VoltageLevel = 0;
1660 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
1661 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1662 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1669 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1671 if (!fast_validate) {
1673 * DML favors voltage over p-state, but we're more interested in
1674 * supporting p-state over voltage. We can't support p-state in
1675 * prefetch mode > 0 so try capping the prefetch mode to start.
1677 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1678 dm_allow_self_refresh_and_mclk_switch;
1679 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1680 /* This may adjust vlevel and maxMpcComb */
1681 if (vlevel < context->bw_ctx.dml.soc.num_states)
1682 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1684 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1685 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1687 * If mode is unsupported or there's still no p-state support then
1688 * fall back to favoring voltage.
1690 * We don't actually support prefetch mode 2, so require that we
1691 * at least support prefetch mode 1.
1693 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1694 dm_allow_self_refresh;
1696 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1697 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1698 memset(split, 0, sizeof(split));
1699 memset(merge, 0, sizeof(merge));
1700 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1704 dml_log_mode_support_params(&context->bw_ctx.dml);
1706 if (vlevel == context->bw_ctx.dml.soc.num_states)
1709 if (!dc->config.enable_windowed_mpo_odm) {
1710 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1711 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1712 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1717 /* We only support full screen mpo with ODM */
1718 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1719 && pipe->plane_state && mpo_pipe
1720 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1721 &pipe->plane_res.scl_data.recout,
1722 sizeof(struct rect)) != 0) {
1723 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1730 /* merge pipes if necessary */
1731 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1732 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1734 /*skip pipes that don't need merging*/
1738 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1739 if (pipe->prev_odm_pipe) {
1740 /*split off odm pipe*/
1741 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1742 if (pipe->next_odm_pipe)
1743 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1745 pipe->bottom_pipe = NULL;
1746 pipe->next_odm_pipe = NULL;
1747 pipe->plane_state = NULL;
1748 pipe->stream = NULL;
1749 pipe->top_pipe = NULL;
1750 pipe->prev_odm_pipe = NULL;
1751 if (pipe->stream_res.dsc)
1752 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1753 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1754 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1755 repopulate_pipes = true;
1756 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1757 struct pipe_ctx *top_pipe = pipe->top_pipe;
1758 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1760 top_pipe->bottom_pipe = bottom_pipe;
1762 bottom_pipe->top_pipe = top_pipe;
1764 pipe->top_pipe = NULL;
1765 pipe->bottom_pipe = NULL;
1766 pipe->plane_state = NULL;
1767 pipe->stream = NULL;
1768 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1769 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1770 repopulate_pipes = true;
1772 ASSERT(0); /* Should never try to merge master pipe */
1776 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1777 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1778 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1779 struct pipe_ctx *hsplit_pipe = NULL;
1783 if (!pipe->stream || newly_split[i])
1787 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1789 if (!pipe->plane_state && !odm)
1794 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1795 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1796 else if (old_pipe->next_odm_pipe)
1797 old_index = old_pipe->next_odm_pipe->pipe_idx;
1799 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1800 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1801 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1802 else if (old_pipe->bottom_pipe &&
1803 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1804 old_index = old_pipe->bottom_pipe->pipe_idx;
1806 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1807 ASSERT(hsplit_pipe);
1811 if (!dcn30_split_stream_for_mpc_or_odm(
1812 dc, &context->res_ctx,
1813 pipe, hsplit_pipe, odm))
1816 newly_split[hsplit_pipe->pipe_idx] = true;
1817 repopulate_pipes = true;
1819 if (split[i] == 4) {
1820 struct pipe_ctx *pipe_4to1;
1822 if (odm && old_pipe->next_odm_pipe)
1823 old_index = old_pipe->next_odm_pipe->pipe_idx;
1824 else if (!odm && old_pipe->bottom_pipe &&
1825 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1826 old_index = old_pipe->bottom_pipe->pipe_idx;
1829 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1833 if (!dcn30_split_stream_for_mpc_or_odm(
1834 dc, &context->res_ctx,
1835 pipe, pipe_4to1, odm))
1837 newly_split[pipe_4to1->pipe_idx] = true;
1839 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1840 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1841 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1842 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1843 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1844 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1845 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1848 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1852 if (!dcn30_split_stream_for_mpc_or_odm(
1853 dc, &context->res_ctx,
1854 hsplit_pipe, pipe_4to1, odm))
1856 newly_split[pipe_4to1->pipe_idx] = true;
1859 dcn20_build_mapped_resource(dc, context, pipe->stream);
1862 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1863 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1865 if (pipe->plane_state) {
1866 if (!resource_build_scaling_params(pipe))
1871 /* Actual dsc count per stream dsc validation*/
1872 if (!dcn20_validate_dsc(dc, context)) {
1873 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1877 if (repopulate_pipes)
1878 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1879 context->bw_ctx.dml.vba.VoltageLevel = vlevel;
1880 *vlevel_out = vlevel;
1881 *pipe_cnt_out = pipe_cnt;
1893 static int get_refresh_rate(struct dc_state *context)
1895 int refresh_rate = 0;
1897 struct dc_crtc_timing *timing = NULL;
1899 if (context == NULL || context->streams[0] == NULL)
1902 /* check if refresh rate at least 120hz */
1903 timing = &context->streams[0]->timing;
1907 h_v_total = timing->h_total * timing->v_total;
1911 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1912 return refresh_rate;
1915 #define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
1917 * Scaling factor for v_blank stretch calculations considering timing in
1918 * micro-seconds and pixel clock in 100hz.
1919 * Note: the parenthesis are necessary to ensure the correct order of
1920 * operation where V_SCALE is used.
1922 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
1924 static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
1926 struct dc_crtc_timing *timing = NULL;
1927 uint32_t sec_per_100_lines;
1928 uint32_t max_v_blank;
1929 uint32_t curr_v_blank;
1930 uint32_t v_stretch_max;
1931 uint32_t stretched_frame_pix_cnt;
1932 uint32_t scaled_stretched_frame_pix_cnt;
1933 uint32_t scaled_refresh_rate;
1935 if (context == NULL || context->streams[0] == NULL)
1938 /* check if refresh rate at least 120hz */
1939 timing = &context->streams[0]->timing;
1943 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1944 max_v_blank = sec_per_100_lines / V_SCALE + 1;
1945 curr_v_blank = timing->v_total - timing->v_addressable;
1946 v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
1947 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
1948 scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
1949 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
1951 return scaled_refresh_rate;
1954 static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
1956 int refresh_rate_max_stretch_100hz;
1957 int min_refresh_100hz;
1959 if (context == NULL || context->streams[0] == NULL)
1962 refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
1963 min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
1965 if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
1971 bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
1973 int refresh_rate = 0;
1974 const int minimum_refreshrate_supported = 120;
1976 if (context == NULL || context->streams[0] == NULL)
1979 if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
1982 if (dc->debug.disable_fams)
1985 if (!dc->caps.dmub_caps.mclk_sw)
1988 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
1991 /* more then 1 monitor connected */
1992 if (context->stream_count != 1)
1995 refresh_rate = get_refresh_rate(context);
1996 if (refresh_rate < minimum_refreshrate_supported)
1999 if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
2002 // check if freesync enabled
2003 if (!context->streams[0]->allow_freesync)
2006 if (context->streams[0]->vrr_active_variable)
2013 * set up FPO watermarks, pstate, dram latency
2015 void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2017 ASSERT(dc != NULL && context != NULL);
2018 if (dc == NULL || context == NULL)
2021 /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2022 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2025 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2028 dcn30_fpu_update_soc_for_wm_a(dc, context);
2032 void dcn30_calculate_wm_and_dlg(
2033 struct dc *dc, struct dc_state *context,
2034 display_e2e_pipe_params_st *pipes,
2039 dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2043 bool dcn30_validate_bandwidth(struct dc *dc,
2044 struct dc_state *context,
2049 BW_VAL_TRACE_SETUP();
2053 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2054 DC_LOGGER_INIT(dc->ctx->logger);
2056 BW_VAL_TRACE_COUNT();
2059 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2068 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2070 if (fast_validate) {
2071 BW_VAL_TRACE_SKIP(fast);
2076 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2079 BW_VAL_TRACE_END_WATERMARKS();
2084 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2085 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2087 BW_VAL_TRACE_SKIP(fail);
2093 BW_VAL_TRACE_FINISH();
2098 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2101 unsigned int num_states = 0;
2103 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2104 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2105 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2106 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2108 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2109 unsigned int num_dcfclk_sta_targets = 4;
2110 unsigned int num_uclk_states;
2112 struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2114 memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2116 if (dc->ctx->dc_bios->vram_info.num_chans)
2117 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2120 dcn30_fpu_update_dram_channel_width_bytes(dc);
2123 if (bw_params->clk_table.entries[0].memclk_mhz) {
2125 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2126 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2127 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2128 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
2129 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2130 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
2131 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2132 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
2133 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2137 dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
2140 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2141 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2142 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2143 num_dcfclk_sta_targets++;
2144 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2145 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2146 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2147 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2148 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2152 // Update size of array since we "removed" duplicates
2153 num_dcfclk_sta_targets = i + 1;
2156 num_uclk_states = bw_params->clk_table.num_entries;
2158 // Calculate optimal dcfclk for each uclk
2159 for (i = 0; i < num_uclk_states; i++) {
2161 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2162 &optimal_dcfclk_for_uclk[i], NULL);
2164 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2165 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2169 // Calculate optimal uclk for each dcfclk sta target
2170 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2171 for (j = 0; j < num_uclk_states; j++) {
2172 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2173 optimal_uclk_for_dcfclk_sta_targets[i] =
2174 bw_params->clk_table.entries[j].memclk_mhz * 16;
2182 // create the final dcfclk and uclk table
2183 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2184 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2185 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2186 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2188 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2189 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2190 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2192 j = num_uclk_states;
2197 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2198 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2199 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2202 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2203 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2204 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2205 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2208 dcn3_0_soc.num_states = num_states;
2210 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2215 static const struct resource_funcs dcn30_res_pool_funcs = {
2216 .destroy = dcn30_destroy_resource_pool,
2217 .link_enc_create = dcn30_link_encoder_create,
2218 .panel_cntl_create = dcn30_panel_cntl_create,
2219 .validate_bandwidth = dcn30_validate_bandwidth,
2220 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2221 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2222 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2223 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2224 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2225 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2226 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2227 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2228 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2229 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2230 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2231 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2232 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2233 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2238 #define REG(reg_name) \
2239 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2241 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2243 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2244 /* Support for max 6 pipes */
2245 value = value & 0x3f;
2249 static bool dcn30_resource_construct(
2250 uint8_t num_virtual_links,
2252 struct dcn30_resource_pool *pool)
2255 struct dc_context *ctx = dc->ctx;
2256 struct irq_service_init_data init_data;
2257 struct ddc_service_init_data ddc_init_data = {0};
2258 uint32_t pipe_fuses = read_pipe_fuses(ctx);
2259 uint32_t num_pipes = 0;
2261 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2262 BREAK_TO_DEBUGGER();
2263 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2264 /* fault to single pipe */
2270 ctx->dc_bios->regs = &bios_regs;
2272 pool->base.res_cap = &res_cap_dcn3;
2274 pool->base.funcs = &dcn30_res_pool_funcs;
2276 /*************************************************
2277 * Resource + asic cap harcoding *
2278 *************************************************/
2279 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2280 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2281 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2282 dc->caps.max_downscale_ratio = 600;
2283 dc->caps.i2c_speed_in_khz = 100;
2284 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2285 dc->caps.max_cursor_size = 256;
2286 dc->caps.min_horizontal_blanking_period = 80;
2287 dc->caps.dmdata_alloc_size = 2048;
2288 dc->caps.mall_size_per_mem_channel = 8;
2289 /* total size = mall per channel * num channels * 1024 * 1024 */
2290 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2291 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2293 dc->caps.max_slave_planes = 2;
2294 dc->caps.max_slave_yuv_planes = 2;
2295 dc->caps.max_slave_rgb_planes = 2;
2296 dc->caps.post_blend_color_processing = true;
2297 dc->caps.force_dp_tps4_for_cp2520 = true;
2298 dc->caps.extended_aux_timeout_support = true;
2299 dc->caps.dmcub_support = true;
2301 /* Color pipeline capabilities */
2302 dc->caps.color.dpp.dcn_arch = 1;
2303 dc->caps.color.dpp.input_lut_shared = 0;
2304 dc->caps.color.dpp.icsc = 1;
2305 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2306 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2307 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2308 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2309 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2310 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2311 dc->caps.color.dpp.post_csc = 1;
2312 dc->caps.color.dpp.gamma_corr = 1;
2313 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2315 dc->caps.color.dpp.hw_3d_lut = 1;
2316 dc->caps.color.dpp.ogam_ram = 1;
2317 // no OGAM ROM on DCN3
2318 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2319 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2320 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2321 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2322 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2323 dc->caps.color.dpp.ocsc = 0;
2325 dc->caps.color.mpc.gamut_remap = 1;
2326 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2327 dc->caps.color.mpc.ogam_ram = 1;
2328 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2329 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2330 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2331 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2332 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2333 dc->caps.color.mpc.ocsc = 1;
2335 dc->caps.dp_hdmi21_pcon_support = true;
2337 /* read VBIOS LTTPR caps */
2339 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2340 enum bp_result bp_query_result;
2341 uint8_t is_vbios_lttpr_enable = 0;
2343 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2344 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2347 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2348 enum bp_result bp_query_result;
2349 uint8_t is_vbios_interop_enabled = 0;
2351 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2352 &is_vbios_interop_enabled);
2353 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2357 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2358 dc->debug = debug_defaults_drv;
2359 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2360 dc->debug = debug_defaults_diags;
2362 dc->debug = debug_defaults_diags;
2363 // Init the vm_helper
2365 vm_helper_init(dc->vm_helper, 16);
2367 /*************************************************
2368 * Create resources *
2369 *************************************************/
2371 /* Clock Sources for Pixel Clock*/
2372 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2373 dcn30_clock_source_create(ctx, ctx->dc_bios,
2374 CLOCK_SOURCE_COMBO_PHY_PLL0,
2375 &clk_src_regs[0], false);
2376 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2377 dcn30_clock_source_create(ctx, ctx->dc_bios,
2378 CLOCK_SOURCE_COMBO_PHY_PLL1,
2379 &clk_src_regs[1], false);
2380 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2381 dcn30_clock_source_create(ctx, ctx->dc_bios,
2382 CLOCK_SOURCE_COMBO_PHY_PLL2,
2383 &clk_src_regs[2], false);
2384 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2385 dcn30_clock_source_create(ctx, ctx->dc_bios,
2386 CLOCK_SOURCE_COMBO_PHY_PLL3,
2387 &clk_src_regs[3], false);
2388 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2389 dcn30_clock_source_create(ctx, ctx->dc_bios,
2390 CLOCK_SOURCE_COMBO_PHY_PLL4,
2391 &clk_src_regs[4], false);
2392 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2393 dcn30_clock_source_create(ctx, ctx->dc_bios,
2394 CLOCK_SOURCE_COMBO_PHY_PLL5,
2395 &clk_src_regs[5], false);
2397 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2399 /* todo: not reuse phy_pll registers */
2400 pool->base.dp_clock_source =
2401 dcn30_clock_source_create(ctx, ctx->dc_bios,
2402 CLOCK_SOURCE_ID_DP_DTO,
2403 &clk_src_regs[0], true);
2405 for (i = 0; i < pool->base.clk_src_count; i++) {
2406 if (pool->base.clock_sources[i] == NULL) {
2407 dm_error("DC: failed to create clock sources!\n");
2408 BREAK_TO_DEBUGGER();
2414 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2415 if (pool->base.dccg == NULL) {
2416 dm_error("DC: failed to create dccg!\n");
2417 BREAK_TO_DEBUGGER();
2421 /* PP Lib and SMU interfaces */
2422 init_soc_bounding_box(dc, pool);
2424 num_pipes = dcn3_0_ip.max_num_dpp;
2426 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2427 if (pipe_fuses & 1 << i)
2430 dcn3_0_ip.max_num_dpp = num_pipes;
2431 dcn3_0_ip.max_num_otg = num_pipes;
2433 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2436 init_data.ctx = dc->ctx;
2437 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2438 if (!pool->base.irqs)
2442 pool->base.hubbub = dcn30_hubbub_create(ctx);
2443 if (pool->base.hubbub == NULL) {
2444 BREAK_TO_DEBUGGER();
2445 dm_error("DC: failed to create hubbub!\n");
2449 /* HUBPs, DPPs, OPPs and TGs */
2450 for (i = 0; i < pool->base.pipe_count; i++) {
2451 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2452 if (pool->base.hubps[i] == NULL) {
2453 BREAK_TO_DEBUGGER();
2455 "DC: failed to create hubps!\n");
2459 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2460 if (pool->base.dpps[i] == NULL) {
2461 BREAK_TO_DEBUGGER();
2463 "DC: failed to create dpps!\n");
2468 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2469 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2470 if (pool->base.opps[i] == NULL) {
2471 BREAK_TO_DEBUGGER();
2473 "DC: failed to create output pixel processor!\n");
2478 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2479 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2481 if (pool->base.timing_generators[i] == NULL) {
2482 BREAK_TO_DEBUGGER();
2483 dm_error("DC: failed to create tg!\n");
2487 pool->base.timing_generator_count = i;
2489 pool->base.psr = dmub_psr_create(ctx);
2491 if (pool->base.psr == NULL) {
2492 dm_error("DC: failed to create PSR obj!\n");
2493 BREAK_TO_DEBUGGER();
2498 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2499 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2503 if (pool->base.multiple_abms[i] == NULL) {
2504 dm_error("DC: failed to create abm for pipe %d!\n", i);
2505 BREAK_TO_DEBUGGER();
2510 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2511 if (pool->base.mpc == NULL) {
2512 BREAK_TO_DEBUGGER();
2513 dm_error("DC: failed to create mpc!\n");
2517 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2518 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2519 if (pool->base.dscs[i] == NULL) {
2520 BREAK_TO_DEBUGGER();
2521 dm_error("DC: failed to create display stream compressor %d!\n", i);
2526 /* DWB and MMHUBBUB */
2527 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2528 BREAK_TO_DEBUGGER();
2529 dm_error("DC: failed to create dwbc!\n");
2533 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2534 BREAK_TO_DEBUGGER();
2535 dm_error("DC: failed to create mcif_wb!\n");
2540 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2541 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2542 if (pool->base.engines[i] == NULL) {
2543 BREAK_TO_DEBUGGER();
2545 "DC:failed to create aux engine!!\n");
2548 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2549 if (pool->base.hw_i2cs[i] == NULL) {
2550 BREAK_TO_DEBUGGER();
2552 "DC:failed to create hw i2c!!\n");
2555 pool->base.sw_i2cs[i] = NULL;
2558 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2559 if (!resource_construct(num_virtual_links, dc, &pool->base,
2560 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2561 &res_create_funcs : &res_create_maximus_funcs)))
2564 /* HW Sequencer and Plane caps */
2565 dcn30_hw_sequencer_construct(dc);
2567 dc->caps.max_planes = pool->base.pipe_count;
2569 for (i = 0; i < dc->caps.max_planes; ++i)
2570 dc->caps.planes[i] = plane_cap;
2572 dc->cap_funcs = cap_funcs;
2574 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2575 ddc_init_data.ctx = dc->ctx;
2576 ddc_init_data.link = NULL;
2577 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2578 ddc_init_data.id.enum_id = 0;
2579 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2580 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2582 pool->base.oem_device = NULL;
2592 dcn30_resource_destruct(pool);
2597 struct resource_pool *dcn30_create_resource_pool(
2598 const struct dc_init_data *init_data,
2601 struct dcn30_resource_pool *pool =
2602 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2607 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2610 BREAK_TO_DEBUGGER();