drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dcn20/dcn20_resource.h"
  34
  35 #include "dcn10/dcn10_hubp.h"
  36 #include "dcn10/dcn10_ipp.h"
  37 #include "dcn20_hubbub.h"
  38 #include "dcn20_mpc.h"
  39 #include "dcn20_hubp.h"
  40 #include "irq/dcn20/irq_service_dcn20.h"
  41 #include "dcn20_dpp.h"
  42 #include "dcn20_optc.h"
  43 #include "dcn20_hwseq.h"
  44 #include "dce110/dce110_hw_sequencer.h"
  45 #include "dcn10/dcn10_resource.h"
  46 #include "dcn20_opp.h"
  47
  48 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  49 #include "dcn20_dsc.h"
  50 #endif
  51
  52 #include "dcn20_link_encoder.h"
  53 #include "dcn20_stream_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "virtual/virtual_stream_encoder.h"
  58 #include "dce110/dce110_resource.h"
  59 #include "dml/display_mode_vba.h"
  60 #include "dcn20_dccg.h"
  61 #include "dcn20_vmid.h"
  62
  63 #include "navi10_ip_offset.h"
  64
  65 #include "dcn/dcn_2_0_0_offset.h"
  66 #include "dcn/dcn_2_0_0_sh_mask.h"
  67
  68 #include "nbio/nbio_2_3_offset.h"
  69
  70 #include "dcn20/dcn20_dwb.h"
  71 #include "dcn20/dcn20_mmhubbub.h"
  72
  73 #include "mmhub/mmhub_2_0_0_offset.h"
  74 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  75
  76 #include "reg_helper.h"
  77 #include "dce/dce_abm.h"
  78 #include "dce/dce_dmcu.h"
  79 #include "dce/dce_aux.h"
  80 #include "dce/dce_i2c.h"
  81 #include "vm_helper.h"
  82
  83 #include "amdgpu_socbb.h"
  84
  85 #define SOC_BOUNDING_BOX_VALID false
  86 #define DC_LOGGER_INIT(logger)
  87
  88 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  89         .odm_capable = 1,
  90         .gpuvm_enable = 0,
  91         .hostvm_enable = 0,
  92         .gpuvm_max_page_table_levels = 4,
  93         .hostvm_max_page_table_levels = 4,
  94         .hostvm_cached_page_table_levels = 0,
  95         .pte_group_size_bytes = 2048,
  96 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  97         .num_dsc = 6,
  98 #else
  99         .num_dsc = 0,
 100 #endif
 101         .rob_buffer_size_kbytes = 168,
 102         .det_buffer_size_kbytes = 164,
 103         .dpte_buffer_size_in_pte_reqs_luma = 84,
 104         .pde_proc_buffer_size_64k_reqs = 48,
 105         .dpp_output_buffer_pixels = 2560,
 106         .opp_output_buffer_lines = 1,
 107         .pixel_chunk_size_kbytes = 8,
 108         .pte_chunk_size_kbytes = 2,
 109         .meta_chunk_size_kbytes = 2,
 110         .writeback_chunk_size_kbytes = 2,
 111         .line_buffer_size_bits = 789504,
 112         .is_line_buffer_bpp_fixed = 0,
 113         .line_buffer_fixed_bpp = 0,
 114         .dcc_supported = true,
 115         .max_line_buffer_lines = 12,
 116         .writeback_luma_buffer_size_kbytes = 12,
 117         .writeback_chroma_buffer_size_kbytes = 8,
 118         .writeback_chroma_line_buffer_width_pixels = 4,
 119         .writeback_max_hscl_ratio = 1,
 120         .writeback_max_vscl_ratio = 1,
 121         .writeback_min_hscl_ratio = 1,
 122         .writeback_min_vscl_ratio = 1,
 123         .writeback_max_hscl_taps = 12,
 124         .writeback_max_vscl_taps = 12,
 125         .writeback_line_buffer_luma_buffer_size = 0,
 126         .writeback_line_buffer_chroma_buffer_size = 14643,
 127         .cursor_buffer_size = 8,
 128         .cursor_chunk_size = 2,
 129         .max_num_otg = 6,
 130         .max_num_dpp = 6,
 131         .max_num_wb = 1,
 132         .max_dchub_pscl_bw_pix_per_clk = 4,
 133         .max_pscl_lb_bw_pix_per_clk = 2,
 134         .max_lb_vscl_bw_pix_per_clk = 4,
 135         .max_vscl_hscl_bw_pix_per_clk = 4,
 136         .max_hscl_ratio = 8,
 137         .max_vscl_ratio = 8,
 138         .hscl_mults = 4,
 139         .vscl_mults = 4,
 140         .max_hscl_taps = 8,
 141         .max_vscl_taps = 8,
 142         .dispclk_ramp_margin_percent = 1,
 143         .underscan_factor = 1.10,
 144         .min_vblank_lines = 32, //
 145         .dppclk_delay_subtotal = 77, //
 146         .dppclk_delay_scl_lb_only = 16,
 147         .dppclk_delay_scl = 50,
 148         .dppclk_delay_cnvc_formatter = 8,
 149         .dppclk_delay_cnvc_cursor = 6,
 150         .dispclk_delay_subtotal = 87, //
 151         .dcfclk_cstate_latency = 10, // SRExitTime
 152         .max_inter_dcn_tile_repeaters = 8,
 153
 154         .xfc_supported = true,
 155         .xfc_fill_bw_overhead_percent = 10.0,
 156         .xfc_fill_constant_bytes = 0,
 157 };
 158
 159 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 };
 160
 161
 162 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 163         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 164         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 165         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 166         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 167         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 168         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 169         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 170         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 171         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 172         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 173         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 174         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 175         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 176         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 177 #endif
 178
 179
 180 enum dcn20_clk_src_array_id {
 181         DCN20_CLK_SRC_PLL0,
 182         DCN20_CLK_SRC_PLL1,
 183         DCN20_CLK_SRC_PLL2,
 184         DCN20_CLK_SRC_PLL3,
 185         DCN20_CLK_SRC_PLL4,
 186         DCN20_CLK_SRC_PLL5,
 187         DCN20_CLK_SRC_TOTAL
 188 };
 189
 190 /* begin *********************
 191  * macros to expend register list macro defined in HW object header file */
 192
 193 /* DCN */
 194 /* TODO awful hack. fixup dcn20_dwb.h */
 195 #undef BASE_INNER
 196 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 197
 198 #define BASE(seg) BASE_INNER(seg)
 199
 200 #define SR(reg_name)\
 201                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 202                                         mm ## reg_name
 203
 204 #define SRI(reg_name, block, id)\
 205         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 206                                         mm ## block ## id ## _ ## reg_name
 207
 208 #define SRIR(var_name, reg_name, block, id)\
 209         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 210                                         mm ## block ## id ## _ ## reg_name
 211
 212 #define SRII(reg_name, block, id)\
 213         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 214                                         mm ## block ## id ## _ ## reg_name
 215
 216 #define DCCG_SRII(reg_name, block, id)\
 217         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 218                                         mm ## block ## id ## _ ## reg_name
 219
 220 /* NBIO */
 221 #define NBIO_BASE_INNER(seg) \
 222         NBIO_BASE__INST0_SEG ## seg
 223
 224 #define NBIO_BASE(seg) \
 225         NBIO_BASE_INNER(seg)
 226
 227 #define NBIO_SR(reg_name)\
 228                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 229                                         mm ## reg_name
 230
 231 /* MMHUB */
 232 #define MMHUB_BASE_INNER(seg) \
 233         MMHUB_BASE__INST0_SEG ## seg
 234
 235 #define MMHUB_BASE(seg) \
 236         MMHUB_BASE_INNER(seg)
 237
 238 #define MMHUB_SR(reg_name)\
 239                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 240                                         mmMM ## reg_name
 241
 242 static const struct bios_registers bios_regs = {
 243                 NBIO_SR(BIOS_SCRATCH_3),
 244                 NBIO_SR(BIOS_SCRATCH_6)
 245 };
 246
 247 #define clk_src_regs(index, pllid)\
 248 [index] = {\
 249         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 250 }
 251
 252 static const struct dce110_clk_src_regs clk_src_regs[] = {
 253         clk_src_regs(0, A),
 254         clk_src_regs(1, B),
 255         clk_src_regs(2, C),
 256         clk_src_regs(3, D),
 257         clk_src_regs(4, E),
 258         clk_src_regs(5, F)
 259 };
 260
 261 static const struct dce110_clk_src_shift cs_shift = {
 262                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 263 };
 264
 265 static const struct dce110_clk_src_mask cs_mask = {
 266                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 267 };
 268
 269 static const struct dce_dmcu_registers dmcu_regs = {
 270                 DMCU_DCN10_REG_LIST()
 271 };
 272
 273 static const struct dce_dmcu_shift dmcu_shift = {
 274                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 275 };
 276
 277 static const struct dce_dmcu_mask dmcu_mask = {
 278                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 279 };
 280
 281 static const struct dce_abm_registers abm_regs = {
 282                 ABM_DCN20_REG_LIST()
 283 };
 284
 285 static const struct dce_abm_shift abm_shift = {
 286                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 287 };
 288
 289 static const struct dce_abm_mask abm_mask = {
 290                 ABM_MASK_SH_LIST_DCN20(_MASK)
 291 };
 292
 293 #define audio_regs(id)\
 294 [id] = {\
 295                 AUD_COMMON_REG_LIST(id)\
 296 }
 297
 298 static const struct dce_audio_registers audio_regs[] = {
 299         audio_regs(0),
 300         audio_regs(1),
 301         audio_regs(2),
 302         audio_regs(3),
 303         audio_regs(4),
 304         audio_regs(5),
 305         audio_regs(6),
 306 };
 307
 308 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 309                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 310                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 311                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 312
 313 static const struct dce_audio_shift audio_shift = {
 314                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 315 };
 316
 317 static const struct dce_aduio_mask audio_mask = {
 318                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 319 };
 320
 321 #define stream_enc_regs(id)\
 322 [id] = {\
 323         SE_DCN2_REG_LIST(id)\
 324 }
 325
 326 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 327         stream_enc_regs(0),
 328         stream_enc_regs(1),
 329         stream_enc_regs(2),
 330         stream_enc_regs(3),
 331         stream_enc_regs(4),
 332         stream_enc_regs(5),
 333 };
 334
 335 static const struct dcn10_stream_encoder_shift se_shift = {
 336                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 337 };
 338
 339 static const struct dcn10_stream_encoder_mask se_mask = {
 340                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 341 };
 342
 343
 344 #define aux_regs(id)\
 345 [id] = {\
 346         DCN2_AUX_REG_LIST(id)\
 347 }
 348
 349 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 350                 aux_regs(0),
 351                 aux_regs(1),
 352                 aux_regs(2),
 353                 aux_regs(3),
 354                 aux_regs(4),
 355                 aux_regs(5)
 356 };
 357
 358 #define hpd_regs(id)\
 359 [id] = {\
 360         HPD_REG_LIST(id)\
 361 }
 362
 363 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 364                 hpd_regs(0),
 365                 hpd_regs(1),
 366                 hpd_regs(2),
 367                 hpd_regs(3),
 368                 hpd_regs(4),
 369                 hpd_regs(5)
 370 };
 371
 372 #define link_regs(id, phyid)\
 373 [id] = {\
 374         LE_DCN10_REG_LIST(id), \
 375         UNIPHY_DCN2_REG_LIST(phyid), \
 376         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 377 }
 378
 379 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 380         link_regs(0, A),
 381         link_regs(1, B),
 382         link_regs(2, C),
 383         link_regs(3, D),
 384         link_regs(4, E),
 385         link_regs(5, F)
 386 };
 387
 388 static const struct dcn10_link_enc_shift le_shift = {
 389         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
 390 };
 391
 392 static const struct dcn10_link_enc_mask le_mask = {
 393         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
 394 };
 395
 396 #define ipp_regs(id)\
 397 [id] = {\
 398         IPP_REG_LIST_DCN20(id),\
 399 }
 400
 401 static const struct dcn10_ipp_registers ipp_regs[] = {
 402         ipp_regs(0),
 403         ipp_regs(1),
 404         ipp_regs(2),
 405         ipp_regs(3),
 406         ipp_regs(4),
 407         ipp_regs(5),
 408 };
 409
 410 static const struct dcn10_ipp_shift ipp_shift = {
 411                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 412 };
 413
 414 static const struct dcn10_ipp_mask ipp_mask = {
 415                 IPP_MASK_SH_LIST_DCN20(_MASK),
 416 };
 417
 418 #define opp_regs(id)\
 419 [id] = {\
 420         OPP_REG_LIST_DCN20(id),\
 421 }
 422
 423 static const struct dcn20_opp_registers opp_regs[] = {
 424         opp_regs(0),
 425         opp_regs(1),
 426         opp_regs(2),
 427         opp_regs(3),
 428         opp_regs(4),
 429         opp_regs(5),
 430 };
 431
 432 static const struct dcn20_opp_shift opp_shift = {
 433                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 434 };
 435
 436 static const struct dcn20_opp_mask opp_mask = {
 437                 OPP_MASK_SH_LIST_DCN20(_MASK)
 438 };
 439
 440 #define aux_engine_regs(id)\
 441 [id] = {\
 442         AUX_COMMON_REG_LIST0(id), \
 443         .AUXN_IMPCAL = 0, \
 444         .AUXP_IMPCAL = 0, \
 445         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 446 }
 447
 448 static const struct dce110_aux_registers aux_engine_regs[] = {
 449                 aux_engine_regs(0),
 450                 aux_engine_regs(1),
 451                 aux_engine_regs(2),
 452                 aux_engine_regs(3),
 453                 aux_engine_regs(4),
 454                 aux_engine_regs(5)
 455 };
 456
 457 #define tf_regs(id)\
 458 [id] = {\
 459         TF_REG_LIST_DCN20(id),\
 460 }
 461
 462 static const struct dcn2_dpp_registers tf_regs[] = {
 463         tf_regs(0),
 464         tf_regs(1),
 465         tf_regs(2),
 466         tf_regs(3),
 467         tf_regs(4),
 468         tf_regs(5),
 469 };
 470
 471 static const struct dcn2_dpp_shift tf_shift = {
 472                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
 473 };
 474
 475 static const struct dcn2_dpp_mask tf_mask = {
 476                 TF_REG_LIST_SH_MASK_DCN20(_MASK)
 477 };
 478
 479 #define dwbc_regs_dcn2(id)\
 480 [id] = {\
 481         DWBC_COMMON_REG_LIST_DCN2_0(id),\
 482                 }
 483
 484 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
 485         dwbc_regs_dcn2(0),
 486 };
 487
 488 static const struct dcn20_dwbc_shift dwbc20_shift = {
 489         DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 490 };
 491
 492 static const struct dcn20_dwbc_mask dwbc20_mask = {
 493         DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 494 };
 495
 496 #define mcif_wb_regs_dcn2(id)\
 497 [id] = {\
 498         MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
 499                 }
 500
 501 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
 502         mcif_wb_regs_dcn2(0),
 503 };
 504
 505 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
 506         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 507 };
 508
 509 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
 510         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 511 };
 512
 513 static const struct dcn20_mpc_registers mpc_regs = {
 514                 MPC_REG_LIST_DCN2_0(0),
 515                 MPC_REG_LIST_DCN2_0(1),
 516                 MPC_REG_LIST_DCN2_0(2),
 517                 MPC_REG_LIST_DCN2_0(3),
 518                 MPC_REG_LIST_DCN2_0(4),
 519                 MPC_REG_LIST_DCN2_0(5),
 520                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 521                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 522                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 523                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 524                 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
 525                 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
 526 };
 527
 528 static const struct dcn20_mpc_shift mpc_shift = {
 529         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 530 };
 531
 532 static const struct dcn20_mpc_mask mpc_mask = {
 533         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 534 };
 535
 536 #define tg_regs(id)\
 537 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 538
 539
 540 static const struct dcn_optc_registers tg_regs[] = {
 541         tg_regs(0),
 542         tg_regs(1),
 543         tg_regs(2),
 544         tg_regs(3),
 545         tg_regs(4),
 546         tg_regs(5)
 547 };
 548
 549 static const struct dcn_optc_shift tg_shift = {
 550         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 551 };
 552
 553 static const struct dcn_optc_mask tg_mask = {
 554         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 555 };
 556
 557 #define hubp_regs(id)\
 558 [id] = {\
 559         HUBP_REG_LIST_DCN20(id)\
 560 }
 561
 562 static const struct dcn_hubp2_registers hubp_regs[] = {
 563                 hubp_regs(0),
 564                 hubp_regs(1),
 565                 hubp_regs(2),
 566                 hubp_regs(3),
 567                 hubp_regs(4),
 568                 hubp_regs(5)
 569 };
 570
 571 static const struct dcn_hubp2_shift hubp_shift = {
 572                 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
 573 };
 574
 575 static const struct dcn_hubp2_mask hubp_mask = {
 576                 HUBP_MASK_SH_LIST_DCN20(_MASK)
 577 };
 578
 579 static const struct dcn_hubbub_registers hubbub_reg = {
 580                 HUBBUB_REG_LIST_DCN20(0)
 581 };
 582
 583 static const struct dcn_hubbub_shift hubbub_shift = {
 584                 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
 585 };
 586
 587 static const struct dcn_hubbub_mask hubbub_mask = {
 588                 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
 589 };
 590
 591 #define vmid_regs(id)\
 592 [id] = {\
 593                 DCN20_VMID_REG_LIST(id)\
 594 }
 595
 596 static const struct dcn_vmid_registers vmid_regs[] = {
 597         vmid_regs(0),
 598         vmid_regs(1),
 599         vmid_regs(2),
 600         vmid_regs(3),
 601         vmid_regs(4),
 602         vmid_regs(5),
 603         vmid_regs(6),
 604         vmid_regs(7),
 605         vmid_regs(8),
 606         vmid_regs(9),
 607         vmid_regs(10),
 608         vmid_regs(11),
 609         vmid_regs(12),
 610         vmid_regs(13),
 611         vmid_regs(14),
 612         vmid_regs(15)
 613 };
 614
 615 static const struct dcn20_vmid_shift vmid_shifts = {
 616                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 617 };
 618
 619 static const struct dcn20_vmid_mask vmid_masks = {
 620                 DCN20_VMID_MASK_SH_LIST(_MASK)
 621 };
 622
 623 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 624 #define dsc_regsDCN20(id)\
 625 [id] = {\
 626         DSC_REG_LIST_DCN20(id)\
 627 }
 628
 629 static const struct dcn20_dsc_registers dsc_regs[] = {
 630         dsc_regsDCN20(0),
 631         dsc_regsDCN20(1),
 632         dsc_regsDCN20(2),
 633         dsc_regsDCN20(3),
 634         dsc_regsDCN20(4),
 635         dsc_regsDCN20(5)
 636 };
 637
 638 static const struct dcn20_dsc_shift dsc_shift = {
 639         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 640 };
 641
 642 static const struct dcn20_dsc_mask dsc_mask = {
 643         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 644 };
 645 #endif
 646
 647 static const struct dccg_registers dccg_regs = {
 648                 DCCG_REG_LIST_DCN2()
 649 };
 650
 651 static const struct dccg_shift dccg_shift = {
 652                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 653 };
 654
 655 static const struct dccg_mask dccg_mask = {
 656                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 657 };
 658
 659 static const struct resource_caps res_cap_nv10 = {
 660                 .num_timing_generator = 6,
 661                 .num_opp = 6,
 662                 .num_video_plane = 6,
 663                 .num_audio = 7,
 664                 .num_stream_encoder = 6,
 665                 .num_pll = 6,
 666                 .num_dwb = 1,
 667                 .num_ddc = 6,
 668                 .num_vmid = 16,
 669 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 670                 .num_dsc = 6,
 671 #endif
 672 };
 673
 674 static const struct dc_plane_cap plane_cap = {
 675         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 676         .blends_with_above = true,
 677         .blends_with_below = true,
 678         .per_pixel_alpha = true,
 679
 680         .pixel_format_support = {
 681                         .argb8888 = true,
 682                         .nv12 = true,
 683                         .fp16 = true
 684         },
 685
 686         .max_upscale_factor = {
 687                         .argb8888 = 16000,
 688                         .nv12 = 16000,
 689                         .fp16 = 1
 690         },
 691
 692         .max_downscale_factor = {
 693                         .argb8888 = 250,
 694                         .nv12 = 250,
 695                         .fp16 = 1
 696         }
 697 };
 698
 699 static const struct dc_debug_options debug_defaults_drv = {
 700                 .disable_dmcu = true,
 701                 .force_abm_enable = false,
 702                 .timing_trace = false,
 703                 .clock_trace = true,
 704                 .disable_pplib_clock_request = true,
 705                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 706                 .force_single_disp_pipe_split = true,
 707                 .disable_dcc = DCC_ENABLE,
 708                 .vsr_support = true,
 709                 .performance_trace = false,
 710                 .max_downscale_src_width = 5120,/*upto 5K*/
 711                 .disable_pplib_wm_range = false,
 712                 .scl_reset_length10 = true,
 713                 .sanity_checks = false,
 714                 .disable_tri_buf = true,
 715                 .underflow_assert_delay_us = 0xFFFFFFFF,
 716 };
 717
 718 static const struct dc_debug_options debug_defaults_diags = {
 719                 .disable_dmcu = true,
 720                 .force_abm_enable = false,
 721                 .timing_trace = true,
 722                 .clock_trace = true,
 723                 .disable_dpp_power_gate = true,
 724                 .disable_hubp_power_gate = true,
 725                 .disable_clock_gate = true,
 726                 .disable_pplib_clock_request = true,
 727                 .disable_pplib_wm_range = true,
 728                 .disable_stutter = true,
 729                 .scl_reset_length10 = true,
 730                 .underflow_assert_delay_us = 0xFFFFFFFF,
 731 };
 732
 733 void dcn20_dpp_destroy(struct dpp **dpp)
 734 {
 735         kfree(TO_DCN20_DPP(*dpp));
 736         *dpp = NULL;
 737 }
 738
 739 struct dpp *dcn20_dpp_create(
 740         struct dc_context *ctx,
 741         uint32_t inst)
 742 {
 743         struct dcn20_dpp *dpp =
 744                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 745
 746         if (!dpp)
 747                 return NULL;
 748
 749         if (dpp2_construct(dpp, ctx, inst,
 750                         &tf_regs[inst], &tf_shift, &tf_mask))
 751                 return &dpp->base;
 752
 753         BREAK_TO_DEBUGGER();
 754         kfree(dpp);
 755         return NULL;
 756 }
 757
 758 struct input_pixel_processor *dcn20_ipp_create(
 759         struct dc_context *ctx, uint32_t inst)
 760 {
 761         struct dcn10_ipp *ipp =
 762                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 763
 764         if (!ipp) {
 765                 BREAK_TO_DEBUGGER();
 766                 return NULL;
 767         }
 768
 769         dcn20_ipp_construct(ipp, ctx, inst,
 770                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 771         return &ipp->base;
 772 }
 773
 774
 775 struct output_pixel_processor *dcn20_opp_create(
 776         struct dc_context *ctx, uint32_t inst)
 777 {
 778         struct dcn20_opp *opp =
 779                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 780
 781         if (!opp) {
 782                 BREAK_TO_DEBUGGER();
 783                 return NULL;
 784         }
 785
 786         dcn20_opp_construct(opp, ctx, inst,
 787                         &opp_regs[inst], &opp_shift, &opp_mask);
 788         return &opp->base;
 789 }
 790
 791 struct dce_aux *dcn20_aux_engine_create(
 792         struct dc_context *ctx,
 793         uint32_t inst)
 794 {
 795         struct aux_engine_dce110 *aux_engine =
 796                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 797
 798         if (!aux_engine)
 799                 return NULL;
 800
 801         dce110_aux_engine_construct(aux_engine, ctx, inst,
 802                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 803                                     &aux_engine_regs[inst]);
 804
 805         return &aux_engine->base;
 806 }
 807 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 808
 809 static const struct dce_i2c_registers i2c_hw_regs[] = {
 810                 i2c_inst_regs(1),
 811                 i2c_inst_regs(2),
 812                 i2c_inst_regs(3),
 813                 i2c_inst_regs(4),
 814                 i2c_inst_regs(5),
 815                 i2c_inst_regs(6),
 816 };
 817
 818 static const struct dce_i2c_shift i2c_shifts = {
 819                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 820 };
 821
 822 static const struct dce_i2c_mask i2c_masks = {
 823                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 824 };
 825
 826 struct dce_i2c_hw *dcn20_i2c_hw_create(
 827         struct dc_context *ctx,
 828         uint32_t inst)
 829 {
 830         struct dce_i2c_hw *dce_i2c_hw =
 831                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 832
 833         if (!dce_i2c_hw)
 834                 return NULL;
 835
 836         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 837                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 838
 839         return dce_i2c_hw;
 840 }
 841 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
 842 {
 843         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
 844                                           GFP_KERNEL);
 845
 846         if (!mpc20)
 847                 return NULL;
 848
 849         dcn20_mpc_construct(mpc20, ctx,
 850                         &mpc_regs,
 851                         &mpc_shift,
 852                         &mpc_mask,
 853                         6);
 854
 855         return &mpc20->base;
 856 }
 857
 858 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
 859 {
 860         int i;
 861         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
 862                                           GFP_KERNEL);
 863
 864         if (!hubbub)
 865                 return NULL;
 866
 867         hubbub2_construct(hubbub, ctx,
 868                         &hubbub_reg,
 869                         &hubbub_shift,
 870                         &hubbub_mask);
 871
 872         for (i = 0; i < res_cap_nv10.num_vmid; i++) {
 873                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
 874
 875                 vmid->ctx = ctx;
 876
 877                 vmid->regs = &vmid_regs[i];
 878                 vmid->shifts = &vmid_shifts;
 879                 vmid->masks = &vmid_masks;
 880         }
 881
 882         return &hubbub->base;
 883 }
 884
 885 struct timing_generator *dcn20_timing_generator_create(
 886                 struct dc_context *ctx,
 887                 uint32_t instance)
 888 {
 889         struct optc *tgn10 =
 890                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 891
 892         if (!tgn10)
 893                 return NULL;
 894
 895         tgn10->base.inst = instance;
 896         tgn10->base.ctx = ctx;
 897
 898         tgn10->tg_regs = &tg_regs[instance];
 899         tgn10->tg_shift = &tg_shift;
 900         tgn10->tg_mask = &tg_mask;
 901
 902         dcn20_timing_generator_init(tgn10);
 903
 904         return &tgn10->base;
 905 }
 906
 907 static const struct encoder_feature_support link_enc_feature = {
 908                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 909                 .max_hdmi_pixel_clock = 600000,
 910                 .hdmi_ycbcr420_supported = true,
 911                 .dp_ycbcr420_supported = true,
 912                 .flags.bits.IS_HBR2_CAPABLE = true,
 913                 .flags.bits.IS_HBR3_CAPABLE = true,
 914                 .flags.bits.IS_TPS3_CAPABLE = true,
 915                 .flags.bits.IS_TPS4_CAPABLE = true
 916 };
 917
 918 struct link_encoder *dcn20_link_encoder_create(
 919         const struct encoder_init_data *enc_init_data)
 920 {
 921         struct dcn20_link_encoder *enc20 =
 922                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
 923
 924         if (!enc20)
 925                 return NULL;
 926
 927         dcn20_link_encoder_construct(enc20,
 928                                       enc_init_data,
 929                                       &link_enc_feature,
 930                                       &link_enc_regs[enc_init_data->transmitter],
 931                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 932                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
 933                                       &le_shift,
 934                                       &le_mask);
 935
 936         return &enc20->enc10.base;
 937 }
 938
 939 struct clock_source *dcn20_clock_source_create(
 940         struct dc_context *ctx,
 941         struct dc_bios *bios,
 942         enum clock_source_id id,
 943         const struct dce110_clk_src_regs *regs,
 944         bool dp_clk_src)
 945 {
 946         struct dce110_clk_src *clk_src =
 947                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 948
 949         if (!clk_src)
 950                 return NULL;
 951
 952         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
 953                         regs, &cs_shift, &cs_mask)) {
 954                 clk_src->base.dp_clk_src = dp_clk_src;
 955                 return &clk_src->base;
 956         }
 957
 958         BREAK_TO_DEBUGGER();
 959         return NULL;
 960 }
 961
 962 static void read_dce_straps(
 963         struct dc_context *ctx,
 964         struct resource_straps *straps)
 965 {
 966         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 967                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 968 }
 969
 970 static struct audio *dcn20_create_audio(
 971                 struct dc_context *ctx, unsigned int inst)
 972 {
 973         return dce_audio_create(ctx, inst,
 974                         &audio_regs[inst], &audio_shift, &audio_mask);
 975 }
 976
 977 struct stream_encoder *dcn20_stream_encoder_create(
 978         enum engine_id eng_id,
 979         struct dc_context *ctx)
 980 {
 981         struct dcn10_stream_encoder *enc1 =
 982                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 983
 984         if (!enc1)
 985                 return NULL;
 986
 987         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 988                                         &stream_enc_regs[eng_id],
 989                                         &se_shift, &se_mask);
 990
 991         return &enc1->base;
 992 }
 993
 994 static const struct dce_hwseq_registers hwseq_reg = {
 995                 HWSEQ_DCN2_REG_LIST()
 996 };
 997
 998 static const struct dce_hwseq_shift hwseq_shift = {
 999                 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1000 };
1001
1002 static const struct dce_hwseq_mask hwseq_mask = {
1003                 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1004 };
1005
1006 struct dce_hwseq *dcn20_hwseq_create(
1007         struct dc_context *ctx)
1008 {
1009         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1010
1011         if (hws) {
1012                 hws->ctx = ctx;
1013                 hws->regs = &hwseq_reg;
1014                 hws->shifts = &hwseq_shift;
1015                 hws->masks = &hwseq_mask;
1016         }
1017         return hws;
1018 }
1019
1020 static const struct resource_create_funcs res_create_funcs = {
1021         .read_dce_straps = read_dce_straps,
1022         .create_audio = dcn20_create_audio,
1023         .create_stream_encoder = dcn20_stream_encoder_create,
1024         .create_hwseq = dcn20_hwseq_create,
1025 };
1026
1027 static const struct resource_create_funcs res_create_maximus_funcs = {
1028         .read_dce_straps = NULL,
1029         .create_audio = NULL,
1030         .create_stream_encoder = NULL,
1031         .create_hwseq = dcn20_hwseq_create,
1032 };
1033
1034 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1035 {
1036         kfree(TO_DCE110_CLK_SRC(*clk_src));
1037         *clk_src = NULL;
1038 }
1039
1040 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1041
1042 struct display_stream_compressor *dcn20_dsc_create(
1043         struct dc_context *ctx, uint32_t inst)
1044 {
1045         struct dcn20_dsc *dsc =
1046                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1047
1048         if (!dsc) {
1049                 BREAK_TO_DEBUGGER();
1050                 return NULL;
1051         }
1052
1053         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1054         return &dsc->base;
1055 }
1056
1057 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1058 {
1059         kfree(container_of(*dsc, struct dcn20_dsc, base));
1060         *dsc = NULL;
1061 }
1062
1063 #endif
1064
1065 static void destruct(struct dcn20_resource_pool *pool)
1066 {
1067         unsigned int i;
1068
1069         for (i = 0; i < pool->base.stream_enc_count; i++) {
1070                 if (pool->base.stream_enc[i] != NULL) {
1071                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1072                         pool->base.stream_enc[i] = NULL;
1073                 }
1074         }
1075
1076 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1077         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1078                 if (pool->base.dscs[i] != NULL)
1079                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1080         }
1081 #endif
1082
1083         if (pool->base.mpc != NULL) {
1084                 kfree(TO_DCN20_MPC(pool->base.mpc));
1085                 pool->base.mpc = NULL;
1086         }
1087         if (pool->base.hubbub != NULL) {
1088                 kfree(pool->base.hubbub);
1089                 pool->base.hubbub = NULL;
1090         }
1091         for (i = 0; i < pool->base.pipe_count; i++) {
1092                 if (pool->base.dpps[i] != NULL)
1093                         dcn20_dpp_destroy(&pool->base.dpps[i]);
1094
1095                 if (pool->base.ipps[i] != NULL)
1096                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1097
1098                 if (pool->base.hubps[i] != NULL) {
1099                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1100                         pool->base.hubps[i] = NULL;
1101                 }
1102
1103                 if (pool->base.irqs != NULL) {
1104                         dal_irq_service_destroy(&pool->base.irqs);
1105                 }
1106         }
1107
1108         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1109                 if (pool->base.engines[i] != NULL)
1110                         dce110_engine_destroy(&pool->base.engines[i]);
1111                 if (pool->base.hw_i2cs[i] != NULL) {
1112                         kfree(pool->base.hw_i2cs[i]);
1113                         pool->base.hw_i2cs[i] = NULL;
1114                 }
1115                 if (pool->base.sw_i2cs[i] != NULL) {
1116                         kfree(pool->base.sw_i2cs[i]);
1117                         pool->base.sw_i2cs[i] = NULL;
1118                 }
1119         }
1120
1121         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1122                 if (pool->base.opps[i] != NULL)
1123                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1124         }
1125
1126         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1127                 if (pool->base.timing_generators[i] != NULL)    {
1128                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1129                         pool->base.timing_generators[i] = NULL;
1130                 }
1131         }
1132
1133         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1134                 if (pool->base.dwbc[i] != NULL) {
1135                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1136                         pool->base.dwbc[i] = NULL;
1137                 }
1138                 if (pool->base.mcif_wb[i] != NULL) {
1139                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1140                         pool->base.mcif_wb[i] = NULL;
1141                 }
1142         }
1143
1144         for (i = 0; i < pool->base.audio_count; i++) {
1145                 if (pool->base.audios[i])
1146                         dce_aud_destroy(&pool->base.audios[i]);
1147         }
1148
1149         for (i = 0; i < pool->base.clk_src_count; i++) {
1150                 if (pool->base.clock_sources[i] != NULL) {
1151                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1152                         pool->base.clock_sources[i] = NULL;
1153                 }
1154         }
1155
1156         if (pool->base.dp_clock_source != NULL) {
1157                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1158                 pool->base.dp_clock_source = NULL;
1159         }
1160
1161
1162         if (pool->base.abm != NULL)
1163                 dce_abm_destroy(&pool->base.abm);
1164
1165         if (pool->base.dmcu != NULL)
1166                 dce_dmcu_destroy(&pool->base.dmcu);
1167
1168         if (pool->base.dccg != NULL)
1169                 dcn_dccg_destroy(&pool->base.dccg);
1170
1171         if (pool->base.pp_smu != NULL)
1172                 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1173
1174 }
1175
1176 struct hubp *dcn20_hubp_create(
1177         struct dc_context *ctx,
1178         uint32_t inst)
1179 {
1180         struct dcn20_hubp *hubp2 =
1181                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1182
1183         if (!hubp2)
1184                 return NULL;
1185
1186         if (hubp2_construct(hubp2, ctx, inst,
1187                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1188                 return &hubp2->base;
1189
1190         BREAK_TO_DEBUGGER();
1191         kfree(hubp2);
1192         return NULL;
1193 }
1194
1195 static void get_pixel_clock_parameters(
1196         struct pipe_ctx *pipe_ctx,
1197         struct pixel_clk_params *pixel_clk_params)
1198 {
1199         const struct dc_stream_state *stream = pipe_ctx->stream;
1200         bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
1201
1202         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1203         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1204         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1205         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1206         /* TODO: un-hardcode*/
1207         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1208                 LINK_RATE_REF_FREQ_IN_KHZ;
1209         pixel_clk_params->flags.ENABLE_SS = 0;
1210         pixel_clk_params->color_depth =
1211                 stream->timing.display_color_depth;
1212         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1213         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1214
1215         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1216                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1217
1218         if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
1219                 pixel_clk_params->requested_pix_clk_100hz /= 2;
1220
1221         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1222                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1223
1224 }
1225
1226 static void build_clamping_params(struct dc_stream_state *stream)
1227 {
1228         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1229         stream->clamping.c_depth = stream->timing.display_color_depth;
1230         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1231 }
1232
1233 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1234 {
1235
1236         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1237
1238         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1239                 pipe_ctx->clock_source,
1240                 &pipe_ctx->stream_res.pix_clk_params,
1241                 &pipe_ctx->pll_settings);
1242
1243         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1244
1245         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1246                                         &pipe_ctx->stream->bit_depth_params);
1247         build_clamping_params(pipe_ctx->stream);
1248
1249         return DC_OK;
1250 }
1251
1252 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1253 {
1254         enum dc_status status = DC_OK;
1255         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1256
1257         /*TODO Seems unneeded anymore */
1258         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1259                         if (stream != NULL && old_context->streams[i] != NULL) {
1260                                  todo: shouldn't have to copy missing parameter here
1261                                 resource_build_bit_depth_reduction_params(stream,
1262                                                 &stream->bit_depth_params);
1263                                 stream->clamping.pixel_encoding =
1264                                                 stream->timing.pixel_encoding;
1265
1266                                 resource_build_bit_depth_reduction_params(stream,
1267                                                                 &stream->bit_depth_params);
1268                                 build_clamping_params(stream);
1269
1270                                 continue;
1271                         }
1272                 }
1273         */
1274
1275         if (!pipe_ctx)
1276                 return DC_ERROR_UNEXPECTED;
1277
1278
1279         status = build_pipe_hw_param(pipe_ctx);
1280
1281         return status;
1282 }
1283
1284 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1285
1286 static void acquire_dsc(struct resource_context *res_ctx,
1287                         const struct resource_pool *pool,
1288                         struct display_stream_compressor **dsc)
1289 {
1290         int i;
1291
1292         ASSERT(*dsc == NULL);
1293         *dsc = NULL;
1294
1295         /* Find first free DSC */
1296         for (i = 0; i < pool->res_cap->num_dsc; i++)
1297                 if (!res_ctx->is_dsc_acquired[i]) {
1298                         *dsc = pool->dscs[i];
1299                         res_ctx->is_dsc_acquired[i] = true;
1300                         break;
1301                 }
1302 }
1303
1304 static void release_dsc(struct resource_context *res_ctx,
1305                         const struct resource_pool *pool,
1306                         struct display_stream_compressor **dsc)
1307 {
1308         int i;
1309
1310         for (i = 0; i < pool->res_cap->num_dsc; i++)
1311                 if (pool->dscs[i] == *dsc) {
1312                         res_ctx->is_dsc_acquired[i] = false;
1313                         *dsc = NULL;
1314                         break;
1315                 }
1316 }
1317
1318 #endif
1319
1320
1321 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1322 static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
1323                 struct dc_state *dc_ctx,
1324                 struct dc_stream_state *dc_stream)
1325 {
1326         enum dc_status result = DC_OK;
1327         int i;
1328         const struct resource_pool *pool = dc->res_pool;
1329
1330         /* Get a DSC if required and available */
1331         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1332                 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1333
1334                 if (pipe_ctx->stream != dc_stream)
1335                         continue;
1336
1337                 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
1338
1339                 /* The number of DSCs can be less than the number of pipes */
1340                 if (!pipe_ctx->stream_res.dsc) {
1341                         dm_output_to_console("No DSCs available\n");
1342                         result = DC_NO_DSC_RESOURCE;
1343                 }
1344
1345                 break;
1346         }
1347
1348         return result;
1349 }
1350
1351
1352 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1353                 struct dc_state *new_ctx,
1354                 struct dc_stream_state *dc_stream)
1355 {
1356         struct pipe_ctx *pipe_ctx = NULL;
1357         int i;
1358
1359         for (i = 0; i < MAX_PIPES; i++) {
1360                 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1361                         pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1362                         break;
1363                 }
1364         }
1365
1366         if (!pipe_ctx)
1367                 return DC_ERROR_UNEXPECTED;
1368
1369         if (pipe_ctx->stream_res.dsc) {
1370                 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1371
1372                 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1373                 if (odm_pipe)
1374                         release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
1375         }
1376
1377         return DC_OK;
1378 }
1379 #endif
1380
1381
1382 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1383 {
1384         enum dc_status result = DC_ERROR_UNEXPECTED;
1385
1386         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1387
1388         if (result == DC_OK)
1389                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1390
1391 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1392         /* Get a DSC if required and available */
1393         if (result == DC_OK && dc_stream->timing.flags.DSC)
1394                 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1395 #endif
1396
1397         if (result == DC_OK)
1398                 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1399
1400         return result;
1401 }
1402
1403
1404 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1405 {
1406         enum dc_status result = DC_OK;
1407
1408 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1409         result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1410 #endif
1411
1412         return result;
1413 }
1414
1415
1416 static void swizzle_to_dml_params(
1417                 enum swizzle_mode_values swizzle,
1418                 unsigned int *sw_mode)
1419 {
1420         switch (swizzle) {
1421         case DC_SW_LINEAR:
1422                 *sw_mode = dm_sw_linear;
1423                 break;
1424         case DC_SW_4KB_S:
1425                 *sw_mode = dm_sw_4kb_s;
1426                 break;
1427         case DC_SW_4KB_S_X:
1428                 *sw_mode = dm_sw_4kb_s_x;
1429                 break;
1430         case DC_SW_4KB_D:
1431                 *sw_mode = dm_sw_4kb_d;
1432                 break;
1433         case DC_SW_4KB_D_X:
1434                 *sw_mode = dm_sw_4kb_d_x;
1435                 break;
1436         case DC_SW_64KB_S:
1437                 *sw_mode = dm_sw_64kb_s;
1438                 break;
1439         case DC_SW_64KB_S_X:
1440                 *sw_mode = dm_sw_64kb_s_x;
1441                 break;
1442         case DC_SW_64KB_S_T:
1443                 *sw_mode = dm_sw_64kb_s_t;
1444                 break;
1445         case DC_SW_64KB_D:
1446                 *sw_mode = dm_sw_64kb_d;
1447                 break;
1448         case DC_SW_64KB_D_X:
1449                 *sw_mode = dm_sw_64kb_d_x;
1450                 break;
1451         case DC_SW_64KB_D_T:
1452                 *sw_mode = dm_sw_64kb_d_t;
1453                 break;
1454         case DC_SW_64KB_R_X:
1455                 *sw_mode = dm_sw_64kb_r_x;
1456                 break;
1457         case DC_SW_VAR_S:
1458                 *sw_mode = dm_sw_var_s;
1459                 break;
1460         case DC_SW_VAR_S_X:
1461                 *sw_mode = dm_sw_var_s_x;
1462                 break;
1463         case DC_SW_VAR_D:
1464                 *sw_mode = dm_sw_var_d;
1465                 break;
1466         case DC_SW_VAR_D_X:
1467                 *sw_mode = dm_sw_var_d_x;
1468                 break;
1469
1470         default:
1471                 ASSERT(0); /* Not supported */
1472                 break;
1473         }
1474 }
1475
1476 static bool dcn20_split_stream_for_combine(
1477                 struct resource_context *res_ctx,
1478                 const struct resource_pool *pool,
1479                 struct pipe_ctx *primary_pipe,
1480                 struct pipe_ctx *secondary_pipe,
1481                 bool is_odm_combine)
1482 {
1483         int pipe_idx = secondary_pipe->pipe_idx;
1484         struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
1485         struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1486         int new_width;
1487
1488         *secondary_pipe = *primary_pipe;
1489         secondary_pipe->bottom_pipe = sec_bot_pipe;
1490
1491         secondary_pipe->pipe_idx = pipe_idx;
1492         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1493         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1494         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1495         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1496         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1497         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1498 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1499         secondary_pipe->stream_res.dsc = NULL;
1500 #endif
1501         if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1502                 ASSERT(!secondary_pipe->bottom_pipe);
1503                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1504                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1505         }
1506         primary_pipe->bottom_pipe = secondary_pipe;
1507         secondary_pipe->top_pipe = primary_pipe;
1508
1509         if (is_odm_combine) {
1510                 if (primary_pipe->plane_state) {
1511                         /* HACTIVE halved for odm combine */
1512                         sd->h_active /= 2;
1513                         /* Copy scl_data to secondary pipe */
1514                         secondary_pipe->plane_res.scl_data = *sd;
1515
1516                         /* Calculate new vp and recout for left pipe */
1517                         /* Need at least 16 pixels width per side */
1518                         if (sd->recout.x + 16 >= sd->h_active)
1519                                 return false;
1520                         new_width = sd->h_active - sd->recout.x;
1521                         sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1522                                         sd->ratios.horz, sd->recout.width - new_width));
1523                         sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1524                                         sd->ratios.horz_c, sd->recout.width - new_width));
1525                         sd->recout.width = new_width;
1526
1527                         /* Calculate new vp and recout for right pipe */
1528                         sd = &secondary_pipe->plane_res.scl_data;
1529                         new_width = sd->recout.width + sd->recout.x - sd->h_active;
1530                         /* Need at least 16 pixels width per side */
1531                         if (new_width <= 16)
1532                                 return false;
1533                         sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1534                                         sd->ratios.horz, sd->recout.width - new_width));
1535                         sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1536                                         sd->ratios.horz_c, sd->recout.width - new_width));
1537                         sd->recout.width = new_width;
1538                         sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1539                                         sd->ratios.horz, sd->h_active - sd->recout.x));
1540                         sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1541                                         sd->ratios.horz_c, sd->h_active - sd->recout.x));
1542                         sd->recout.x = 0;
1543                 }
1544                 secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
1545 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1546                 if (secondary_pipe->stream->timing.flags.DSC == 1) {
1547                         acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc);
1548                         ASSERT(secondary_pipe->stream_res.dsc);
1549                         if (secondary_pipe->stream_res.dsc == NULL)
1550                                 return false;
1551                 }
1552 #endif
1553         } else {
1554                 ASSERT(primary_pipe->plane_state);
1555                 resource_build_scaling_params(primary_pipe);
1556                 resource_build_scaling_params(secondary_pipe);
1557         }
1558
1559         return true;
1560 }
1561
1562 void dcn20_populate_dml_writeback_from_context(
1563                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1564 {
1565         int pipe_cnt, i;
1566
1567         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1568                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1569
1570                 if (!res_ctx->pipe_ctx[i].stream)
1571                         continue;
1572
1573                 /* Set writeback information */
1574                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1575                 pipes[pipe_cnt].dout.num_active_wb++;
1576                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1577                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1578                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1579                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1580                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1581                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1582                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1583                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1584                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1585                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1586                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1587                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1588                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1589                         else
1590                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1591                 } else
1592                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1593
1594                 pipe_cnt++;
1595         }
1596
1597 }
1598
1599 int dcn20_populate_dml_pipes_from_context(
1600                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1601 {
1602         int pipe_cnt, i;
1603         bool synchronized_vblank = true;
1604
1605         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1606                 if (!res_ctx->pipe_ctx[i].stream)
1607                         continue;
1608
1609                 if (pipe_cnt < 0) {
1610                         pipe_cnt = i;
1611                         continue;
1612                 }
1613                 if (!resource_are_streams_timing_synchronizable(
1614                                 res_ctx->pipe_ctx[pipe_cnt].stream,
1615                                 res_ctx->pipe_ctx[i].stream)) {
1616                         synchronized_vblank = false;
1617                         break;
1618                 }
1619         }
1620
1621         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1622                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1623                 int output_bpc;
1624
1625                 if (!res_ctx->pipe_ctx[i].stream)
1626                         continue;
1627                 /* todo:
1628                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1629                 pipes[pipe_cnt].pipe.src.dcc = 0;
1630                 pipes[pipe_cnt].pipe.src.vm = 0;*/
1631
1632 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1633                 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1634                 /* todo: rotation?*/
1635                 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1636 #endif
1637                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1638                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1639                         /* 1/2 vblank */
1640                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1641                                 (timing->v_total - timing->v_addressable
1642                                         - timing->v_border_top - timing->v_border_bottom) / 2;
1643                         /* 36 bytes dp, 32 hdmi */
1644                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1645                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1646                 }
1647                 pipes[pipe_cnt].pipe.src.dcc = false;
1648                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1649                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1650                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1651                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1652                                 - timing->h_addressable
1653                                 - timing->h_border_left
1654                                 - timing->h_border_right;
1655                 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1656                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1657                                 - timing->v_addressable
1658                                 - timing->v_border_top
1659                                 - timing->v_border_bottom;
1660                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1661                 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1662                 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1663                 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1664                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1665                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1666                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1667                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1668                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1669                 pipes[pipe_cnt].dout.dp_lanes = 4;
1670                 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1671                 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1672
1673                 switch (res_ctx->pipe_ctx[i].stream->signal) {
1674                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1675                 case SIGNAL_TYPE_DISPLAY_PORT:
1676                         pipes[pipe_cnt].dout.output_type = dm_dp;
1677                         break;
1678                 case SIGNAL_TYPE_EDP:
1679                         pipes[pipe_cnt].dout.output_type = dm_edp;
1680                         break;
1681                 case SIGNAL_TYPE_HDMI_TYPE_A:
1682                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1683                 case SIGNAL_TYPE_DVI_DUAL_LINK:
1684                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
1685                         break;
1686                 default:
1687                         /* In case there is no signal, set dp with 4 lanes to allow max config */
1688                         pipes[pipe_cnt].dout.output_type = dm_dp;
1689                         pipes[pipe_cnt].dout.dp_lanes = 4;
1690                 }
1691
1692                 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1693                 case COLOR_DEPTH_666:
1694                         output_bpc = 6;
1695                         break;
1696                 case COLOR_DEPTH_888:
1697                         output_bpc = 8;
1698                         break;
1699                 case COLOR_DEPTH_101010:
1700                         output_bpc = 10;
1701                         break;
1702                 case COLOR_DEPTH_121212:
1703                         output_bpc = 12;
1704                         break;
1705                 case COLOR_DEPTH_141414:
1706                         output_bpc = 14;
1707                         break;
1708                 case COLOR_DEPTH_161616:
1709                         output_bpc = 16;
1710                         break;
1711 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1712                 case COLOR_DEPTH_999:
1713                         output_bpc = 9;
1714                         break;
1715                 case COLOR_DEPTH_111111:
1716                         output_bpc = 11;
1717                         break;
1718 #endif
1719                 default:
1720                         output_bpc = 8;
1721                         break;
1722                 }
1723
1724
1725                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1726                 case PIXEL_ENCODING_RGB:
1727                 case PIXEL_ENCODING_YCBCR444:
1728                         pipes[pipe_cnt].dout.output_format = dm_444;
1729                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1730                         break;
1731                 case PIXEL_ENCODING_YCBCR420:
1732                         pipes[pipe_cnt].dout.output_format = dm_420;
1733                         pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
1734                         break;
1735                 case PIXEL_ENCODING_YCBCR422:
1736                         if (true) /* todo */
1737                                 pipes[pipe_cnt].dout.output_format = dm_s422;
1738                         else
1739                                 pipes[pipe_cnt].dout.output_format = dm_n422;
1740                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1741                         break;
1742                 default:
1743                         pipes[pipe_cnt].dout.output_format = dm_444;
1744                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1745                 }
1746                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1747                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1748                                 == res_ctx->pipe_ctx[i].plane_state)
1749                         pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1750
1751                 /* todo: default max for now, until there is logic reflecting this in dc*/
1752                 pipes[pipe_cnt].dout.output_bpc = 12;
1753                 /*
1754                  * Use max cursor settings for calculations to minimize
1755                  * bw calculations due to cursor on/off
1756                  */
1757                 pipes[pipe_cnt].pipe.src.num_cursors = 2;
1758                 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1759                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1760                 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
1761                 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
1762
1763                 if (!res_ctx->pipe_ctx[i].plane_state) {
1764                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1765                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
1766                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1767                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1768                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1769                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1770                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1771                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1772                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1773                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
1774                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1775                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1776                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1777                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
1778                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1779                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1780                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1781                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1782                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1783                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1784                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1785                         pipes[pipe_cnt].pipe.src.is_hsplit = 0;
1786                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1787                         pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
1788                         pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
1789                 } else {
1790                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1791                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1792
1793                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1794                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
1795                                         && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1796                                         || (res_ctx->pipe_ctx[i].top_pipe
1797                                         && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
1798                         pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
1799                                         && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
1800                                         && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
1801                                                 != res_ctx->pipe_ctx[i].stream_res.opp)
1802                                 || (res_ctx->pipe_ctx[i].top_pipe
1803                                         && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
1804                                         && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
1805                                                 != res_ctx->pipe_ctx[i].stream_res.opp);
1806                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1807                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1808                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1809                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1810                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1811                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1812                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1813                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1814                         if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1815                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch;
1816                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch;
1817                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l;
1818                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c;
1819                         } else {
1820                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch;
1821                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch;
1822                         }
1823                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1824                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1825                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1826                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1827                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1828                         if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
1829                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1830                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
1831                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1832                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
1833                         } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
1834                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1835                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
1836                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1837                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
1838                         }
1839
1840                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1841                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1842                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1843                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1844                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1845                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1846                                         scl->ratios.vert.value != dc_fixpt_one.value
1847                                         || scl->ratios.horz.value != dc_fixpt_one.value
1848                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
1849                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1850                                         || dc->debug.always_scale; /*support always scale*/
1851                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1852                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1853                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1854                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1855
1856                         pipes[pipe_cnt].pipe.src.macro_tile_size =
1857                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1858                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1859                                         &pipes[pipe_cnt].pipe.src.sw_mode);
1860
1861                         switch (pln->format) {
1862                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1863                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1864                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1865                                 break;
1866                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1867                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1868                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1869                                 break;
1870                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1871                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1872                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1873                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1874                                 break;
1875                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1876                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1877                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1878                                 break;
1879                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1880                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1881                                 break;
1882                         default:
1883                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1884                                 break;
1885                         }
1886                 }
1887
1888                 pipe_cnt++;
1889         }
1890
1891         /* populate writeback information */
1892         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1893
1894         return pipe_cnt;
1895 }
1896
1897 unsigned int dcn20_calc_max_scaled_time(
1898                 unsigned int time_per_pixel,
1899                 enum mmhubbub_wbif_mode mode,
1900                 unsigned int urgent_watermark)
1901 {
1902         unsigned int time_per_byte = 0;
1903         unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1904         unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1905         unsigned int small_free_entry, max_free_entry;
1906         unsigned int buf_lh_capability;
1907         unsigned int max_scaled_time;
1908
1909         if (mode == PACKED_444) /* packed mode */
1910                 time_per_byte = time_per_pixel/4;
1911         else if (mode == PLANAR_420_8BPC)
1912                 time_per_byte  = time_per_pixel;
1913         else if (mode == PLANAR_420_10BPC) /* p010 */
1914                 time_per_byte  = time_per_pixel * 819/1024;
1915
1916         if (time_per_byte == 0)
1917                 time_per_byte = 1;
1918
1919         small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
1920         max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1921         buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1922         max_scaled_time   = buf_lh_capability - urgent_watermark;
1923         return max_scaled_time;
1924 }
1925
1926 void dcn20_set_mcif_arb_params(
1927                 struct dc *dc,
1928                 struct dc_state *context,
1929                 display_e2e_pipe_params_st *pipes,
1930                 int pipe_cnt)
1931 {
1932         enum mmhubbub_wbif_mode wbif_mode;
1933         struct mcif_arb_params *wb_arb_params;
1934         int i, j, k, dwb_pipe;
1935
1936         /* Writeback MCIF_WB arbitration parameters */
1937         dwb_pipe = 0;
1938         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1939
1940                 if (!context->res_ctx.pipe_ctx[i].stream)
1941                         continue;
1942
1943                 for (j = 0; j < MAX_DWB_PIPES; j++) {
1944                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1945                                 continue;
1946
1947                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1948                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1949
1950                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1951                                 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1952                                         wbif_mode = PLANAR_420_8BPC;
1953                                 else
1954                                         wbif_mode = PLANAR_420_10BPC;
1955                         } else
1956                                 wbif_mode = PACKED_444;
1957
1958                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1959                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1960                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1961                         }
1962                         wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
1963                         wb_arb_params->slice_lines = 32;
1964                         wb_arb_params->arbitration_slice = 2;
1965                         wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1966                                 wbif_mode,
1967                                 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1968
1969                         dwb_pipe++;
1970
1971                         if (dwb_pipe >= MAX_DWB_PIPES)
1972                                 return;
1973                 }
1974                 if (dwb_pipe >= MAX_DWB_PIPES)
1975                         return;
1976         }
1977 }
1978
1979 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1980 static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
1981 {
1982         int i;
1983
1984         /* Validate DSC config, dsc count validation is already done */
1985         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1986                 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1987                 struct dc_stream_state *stream = pipe_ctx->stream;
1988                 struct dsc_config dsc_cfg;
1989
1990                 /* Only need to validate top pipe */
1991                 if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
1992                         continue;
1993
1994                 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left
1995                                 + stream->timing.h_border_right;
1996                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1997                                 + stream->timing.v_border_bottom;
1998                 if (dc_res_get_odm_bottom_pipe(pipe_ctx))
1999                         dsc_cfg.pic_width /= 2;
2000                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2001                 dsc_cfg.color_depth = stream->timing.display_color_depth;
2002                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2003
2004                 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2005                         return false;
2006         }
2007         return true;
2008 }
2009 #endif
2010
2011 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2012                 bool fast_validate)
2013 {
2014         bool out = false;
2015
2016         BW_VAL_TRACE_SETUP();
2017
2018         int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
2019         int pipe_split_from[MAX_PIPES];
2020         bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
2021         bool force_split = false;
2022 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2023         bool failed_non_odm_dsc = false;
2024 #endif
2025         int split_threshold = dc->res_pool->pipe_count / 2;
2026         bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
2027         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2028         DC_LOGGER_INIT(dc->ctx->logger);
2029
2030         BW_VAL_TRACE_COUNT();
2031
2032         ASSERT(pipes);
2033         if (!pipes)
2034                 return false;
2035
2036         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2037                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2038                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2039
2040                 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2041                         continue;
2042
2043                 /* merge previously split pipe since mode support needs to make the decision */
2044                 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2045                 if (hsplit_pipe->bottom_pipe)
2046                         hsplit_pipe->bottom_pipe->top_pipe = pipe;
2047                 hsplit_pipe->plane_state = NULL;
2048                 hsplit_pipe->stream = NULL;
2049                 hsplit_pipe->top_pipe = NULL;
2050                 hsplit_pipe->bottom_pipe = NULL;
2051 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2052                 if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc)
2053                         release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc);
2054 #endif
2055                 /* Clear plane_res and stream_res */
2056                 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2057                 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2058                 if (pipe->plane_state)
2059                         resource_build_scaling_params(pipe);
2060         }
2061
2062         if (dc->res_pool->funcs->populate_dml_pipes)
2063                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2064                         &context->res_ctx, pipes);
2065         else
2066                 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2067                         &context->res_ctx, pipes);
2068
2069         if (!pipe_cnt) {
2070                 BW_VAL_TRACE_SKIP(pass);
2071                 out = true;
2072                 goto validate_out;
2073         }
2074
2075         context->bw_ctx.dml.ip.odm_capable = 0;
2076
2077         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2078
2079         context->bw_ctx.dml.ip.odm_capable = odm_capable;
2080
2081 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2082         /* 1 dsc per stream dsc validation */
2083         if (vlevel <= context->bw_ctx.dml.soc.num_states)
2084                 if (!dcn20_validate_dsc(dc, context)) {
2085                         failed_non_odm_dsc = true;
2086                         vlevel = context->bw_ctx.dml.soc.num_states + 1;
2087                 }
2088 #endif
2089
2090         if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
2091                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2092
2093         if (vlevel > context->bw_ctx.dml.soc.num_states)
2094                 goto validate_fail;
2095
2096         if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
2097                 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
2098                 context->commit_hints.full_update_needed = true;
2099
2100         /*initialize pipe_just_split_from to invalid idx*/
2101         for (i = 0; i < MAX_PIPES; i++)
2102                 pipe_split_from[i] = -1;
2103
2104         /* Single display only conditionals get set here */
2105         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2106                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2107                 bool exit_loop = false;
2108
2109                 if (!pipe->stream || pipe->top_pipe)
2110                         continue;
2111
2112                 if (dc->debug.force_single_disp_pipe_split) {
2113                         if (!force_split)
2114                                 force_split = true;
2115                         else {
2116                                 force_split = false;
2117                                 exit_loop = true;
2118                         }
2119                 }
2120                 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2121                         if (avoid_split)
2122                                 avoid_split = false;
2123                         else {
2124                                 avoid_split = true;
2125                                 exit_loop = true;
2126                         }
2127                 }
2128                 if (exit_loop)
2129                         break;
2130         }
2131
2132         if (context->stream_count > split_threshold)
2133                 avoid_split = true;
2134
2135         vlevel_unsplit = vlevel;
2136         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2137                 if (!context->res_ctx.pipe_ctx[i].stream)
2138                         continue;
2139                 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
2140                         if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
2141                                 break;
2142                 pipe_idx++;
2143         }
2144
2145         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2146                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2147                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2148                 bool need_split = true;
2149                 bool need_split3d;
2150
2151                 if (!pipe->stream || pipe_split_from[i] >= 0)
2152                         continue;
2153
2154                 pipe_idx++;
2155
2156                 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2157                         force_split = true;
2158                         context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
2159                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2160                 }
2161                 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2162                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2163                 if (dc->config.forced_clocks == true) {
2164                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] =
2165                                         context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2166                 }
2167                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2168                         hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2169                         ASSERT(hsplit_pipe);
2170                         if (!dcn20_split_stream_for_combine(
2171                                         &context->res_ctx, dc->res_pool,
2172                                         pipe, hsplit_pipe,
2173                                         true))
2174                                 goto validate_fail;
2175                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2176                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2177                 }
2178
2179                 if (!pipe->plane_state)
2180                         continue;
2181                 /* Skip 2nd half of already split pipe */
2182                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2183                         continue;
2184
2185                 need_split3d = ((pipe->stream->view_format ==
2186                                 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2187                                 pipe->stream->view_format ==
2188                                 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2189                                 (pipe->stream->timing.timing_3d_format ==
2190                                 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2191                                  pipe->stream->timing.timing_3d_format ==
2192                                 TIMING_3D_FORMAT_SIDE_BY_SIDE));
2193
2194                 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
2195                         need_split = false;
2196                         vlevel = vlevel_unsplit;
2197                         context->bw_ctx.dml.vba.maxMpcComb = 0;
2198                 } else
2199                         need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
2200
2201                 /* We do not support mpo + odm at the moment */
2202                 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2203                                 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2204                         goto validate_fail;
2205
2206                 if (need_split3d || need_split || force_split) {
2207                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2208                                 /* pipe not split previously needs split */
2209                                 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2210                                 ASSERT(hsplit_pipe || force_split);
2211                                 if (!hsplit_pipe)
2212                                         continue;
2213
2214                                 if (!dcn20_split_stream_for_combine(
2215                                                 &context->res_ctx, dc->res_pool,
2216                                                 pipe, hsplit_pipe,
2217                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
2218                                         goto validate_fail;
2219                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2220                         }
2221                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2222                         /* merge should already have been done */
2223                         ASSERT(0);
2224                 }
2225         }
2226 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2227         /* Actual dsc count per stream dsc validation*/
2228         if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
2229                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2230                                 DML_FAIL_DSC_VALIDATION_FAILURE;
2231                 goto validate_fail;
2232         }
2233 #endif
2234
2235         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2236
2237         if (fast_validate) {
2238                 BW_VAL_TRACE_SKIP(fast);
2239                 out = true;
2240                 goto validate_out;
2241         }
2242
2243         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2244                 if (!context->res_ctx.pipe_ctx[i].stream)
2245                         continue;
2246
2247                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2248                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2249
2250                 if (pipe_split_from[i] < 0) {
2251                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2252                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2253                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2254                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2255                                                 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2256                         else
2257                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2258                         pipe_idx++;
2259                 } else {
2260                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2261                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2262                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2263                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2264                                                 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
2265                         else
2266                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2267                 }
2268                 if (dc->config.forced_clocks) {
2269                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2270                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2271                 }
2272                 pipe_cnt++;
2273         }
2274
2275         if (pipe_cnt != pipe_idx) {
2276                 if (dc->res_pool->funcs->populate_dml_pipes)
2277                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2278                                 &context->res_ctx, pipes);
2279                 else
2280                         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2281                                 &context->res_ctx, pipes);
2282         }
2283
2284         pipes[0].clks_cfg.voltage = vlevel;
2285         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2286         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2287
2288         /* only pipe 0 is read for voltage and dcf/soc clocks */
2289         if (vlevel < 1) {
2290                 pipes[0].clks_cfg.voltage = 1;
2291                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2292                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2293         }
2294         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2295         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2296         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2297         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2298         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2299
2300         if (vlevel < 2) {
2301                 pipes[0].clks_cfg.voltage = 2;
2302                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2303                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2304         }
2305         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2306         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2307         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2308         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2309         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2310
2311         if (vlevel < 3) {
2312                 pipes[0].clks_cfg.voltage = 3;
2313                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2314                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2315         }
2316         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2317         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2318         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2319         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2320         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2321
2322         pipes[0].clks_cfg.voltage = vlevel;
2323         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2324         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2325         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2326         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2327         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2328         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2329         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2330         /* Writeback MCIF_WB arbitration parameters */
2331         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2332
2333         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2334         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2335         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
2336         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
2337         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2338         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
2339         context->bw_ctx.bw.dcn.clk.p_state_change_support =
2340                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2341                                                         != dm_dram_clock_change_unsupported;
2342         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2343
2344         BW_VAL_TRACE_END_WATERMARKS();
2345
2346         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2347                 if (!context->res_ctx.pipe_ctx[i].stream)
2348                         continue;
2349                 pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];
2350                 pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
2351                 pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
2352                 pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
2353                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2354                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2355                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2356                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2357 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2358                 context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
2359                                 context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
2360 #endif
2361                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2362                 pipe_idx++;
2363         }
2364
2365         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2366                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2367
2368                 if (!context->res_ctx.pipe_ctx[i].stream)
2369                         continue;
2370
2371                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2372                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2373                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
2374                                 pipes,
2375                                 pipe_cnt,
2376                                 pipe_idx,
2377                                 cstate_en,
2378                                 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2379                                 false, false, false);
2380
2381                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2382                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2383                                 pipes[pipe_idx].pipe);
2384                 pipe_idx++;
2385         }
2386
2387         out = true;
2388         goto validate_out;
2389
2390 validate_fail:
2391         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2392                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2393
2394         BW_VAL_TRACE_SKIP(fail);
2395         out = false;
2396
2397 validate_out:
2398         kfree(pipes);
2399
2400         BW_VAL_TRACE_FINISH();
2401
2402         return out;
2403 }
2404
2405 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2406                 struct dc_state *state,
2407                 const struct resource_pool *pool,
2408                 struct dc_stream_state *stream)
2409 {
2410         struct resource_context *res_ctx = &state->res_ctx;
2411         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2412         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2413
2414         if (!head_pipe)
2415                 ASSERT(0);
2416
2417         if (!idle_pipe)
2418                 return NULL;
2419
2420         idle_pipe->stream = head_pipe->stream;
2421         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2422         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2423
2424         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2425         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2426         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2427         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2428
2429         return idle_pipe;
2430 }
2431
2432 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2433                 const struct dc_dcc_surface_param *input,
2434                 struct dc_surface_dcc_cap *output)
2435 {
2436         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2437                         dc->res_pool->hubbub,
2438                         input,
2439                         output);
2440 }
2441
2442 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2443 {
2444         struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2445
2446         destruct(dcn20_pool);
2447         kfree(dcn20_pool);
2448         *pool = NULL;
2449 }
2450
2451
2452 static struct dc_cap_funcs cap_funcs = {
2453         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2454 };
2455
2456
2457 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2458 {
2459         enum dc_status result = DC_OK;
2460
2461         enum surface_pixel_format surf_pix_format = plane_state->format;
2462         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2463
2464         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2465
2466         if (bpp == 64)
2467                 swizzle = DC_SW_64KB_D;
2468         else
2469                 swizzle = DC_SW_64KB_S;
2470
2471         plane_state->tiling_info.gfx9.swizzle = swizzle;
2472         return result;
2473 }
2474
2475 static struct resource_funcs dcn20_res_pool_funcs = {
2476         .destroy = dcn20_destroy_resource_pool,
2477         .link_enc_create = dcn20_link_encoder_create,
2478         .validate_bandwidth = dcn20_validate_bandwidth,
2479         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2480         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2481         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2482         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2483         .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
2484         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
2485         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
2486 };
2487
2488 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2489 {
2490         int i;
2491         uint32_t pipe_count = pool->res_cap->num_dwb;
2492
2493         ASSERT(pipe_count > 0);
2494
2495         for (i = 0; i < pipe_count; i++) {
2496                 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2497                                                     GFP_KERNEL);
2498
2499                 if (!dwbc20) {
2500                         dm_error("DC: failed to create dwbc20!\n");
2501                         return false;
2502                 }
2503                 dcn20_dwbc_construct(dwbc20, ctx,
2504                                 &dwbc20_regs[i],
2505                                 &dwbc20_shift,
2506                                 &dwbc20_mask,
2507                                 i);
2508                 pool->dwbc[i] = &dwbc20->base;
2509         }
2510         return true;
2511 }
2512
2513 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2514 {
2515         int i;
2516         uint32_t pipe_count = pool->res_cap->num_dwb;
2517
2518         ASSERT(pipe_count > 0);
2519
2520         for (i = 0; i < pipe_count; i++) {
2521                 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2522                                                     GFP_KERNEL);
2523
2524                 if (!mcif_wb20) {
2525                         dm_error("DC: failed to create mcif_wb20!\n");
2526                         return false;
2527                 }
2528
2529                 dcn20_mmhubbub_construct(mcif_wb20, ctx,
2530                                 &mcif_wb20_regs[i],
2531                                 &mcif_wb20_shift,
2532                                 &mcif_wb20_mask,
2533                                 i);
2534
2535                 pool->mcif_wb[i] = &mcif_wb20->base;
2536         }
2537         return true;
2538 }
2539
2540 struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2541 {
2542         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
2543
2544         if (!pp_smu)
2545                 return pp_smu;
2546
2547         dm_pp_get_funcs(ctx, pp_smu);
2548
2549         if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2550                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2551
2552         return pp_smu;
2553 }
2554
2555 void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2556 {
2557         if (pp_smu && *pp_smu) {
2558                 kfree(*pp_smu);
2559                 *pp_smu = NULL;
2560         }
2561 }
2562
2563 static void cap_soc_clocks(
2564                 struct _vcs_dpi_soc_bounding_box_st *bb,
2565                 struct pp_smu_nv_clock_table max_clocks)
2566 {
2567         int i;
2568
2569         // First pass - cap all clocks higher than the reported max
2570         for (i = 0; i < bb->num_states; i++) {
2571                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
2572                                 && max_clocks.dcfClockInKhz != 0)
2573                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
2574
2575                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
2576                                                 && max_clocks.uClockInKhz != 0)
2577                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2578
2579                 // HACK: Force every uclk to max for now to "disable" uclk switching.
2580                 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2581
2582                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
2583                                                 && max_clocks.fabricClockInKhz != 0)
2584                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
2585
2586                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
2587                                                 && max_clocks.displayClockInKhz != 0)
2588                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
2589
2590                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
2591                                                 && max_clocks.dppClockInKhz != 0)
2592                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
2593
2594                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
2595                                                 && max_clocks.phyClockInKhz != 0)
2596                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
2597
2598                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
2599                                                 && max_clocks.socClockInKhz != 0)
2600                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
2601
2602                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
2603                                                 && max_clocks.dscClockInKhz != 0)
2604                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
2605         }
2606
2607         // Second pass - remove all duplicate clock states
2608         for (i = bb->num_states - 1; i > 1; i--) {
2609                 bool duplicate = true;
2610
2611                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
2612                         duplicate = false;
2613                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
2614                         duplicate = false;
2615                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
2616                         duplicate = false;
2617                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
2618                         duplicate = false;
2619                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
2620                         duplicate = false;
2621                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
2622                         duplicate = false;
2623                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
2624                         duplicate = false;
2625                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
2626                         duplicate = false;
2627
2628                 if (duplicate)
2629                         bb->num_states--;
2630         }
2631 }
2632
2633 static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
2634                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
2635 {
2636         struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
2637         int i;
2638         int num_calculated_states = 0;
2639         int min_dcfclk = 0;
2640
2641         if (num_states == 0)
2642                 return;
2643
2644         if (dc->bb_overrides.min_dcfclk_mhz > 0)
2645                 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
2646         else
2647                 // Accounting for SOC/DCF relationship, we can go as high as
2648                 // 506Mhz in Vmin.  We need to code 507 since SMU will round down to 506.
2649                 min_dcfclk = 507;
2650
2651         for (i = 0; i < num_states; i++) {
2652                 int min_fclk_required_by_uclk;
2653                 calculated_states[i].state = i;
2654                 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
2655
2656                 // FCLK:UCLK ratio is 1.08
2657                 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
2658
2659                 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
2660                                 min_dcfclk : min_fclk_required_by_uclk;
2661
2662                 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
2663                                 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
2664
2665                 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
2666                                 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
2667
2668                 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
2669                 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
2670                 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
2671
2672                 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
2673
2674                 num_calculated_states++;
2675         }
2676
2677         memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
2678         bb->num_states = num_calculated_states;
2679
2680         // Duplicate the last state, DML always an extra state identical to max state to work
2681         memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
2682         bb->clock_limits[num_calculated_states].state = bb->num_states;
2683 }
2684
2685 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2686 {
2687         kernel_fpu_begin();
2688         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2689                         && dc->bb_overrides.sr_exit_time_ns) {
2690                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2691         }
2692
2693         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
2694                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
2695                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2696                 bb->sr_enter_plus_exit_time_us =
2697                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2698         }
2699
2700         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2701                         && dc->bb_overrides.urgent_latency_ns) {
2702                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2703         }
2704
2705         if ((int)(bb->dram_clock_change_latency_us * 1000)
2706                                 != dc->bb_overrides.dram_clock_change_latency_ns
2707                         && dc->bb_overrides.dram_clock_change_latency_ns) {
2708                 bb->dram_clock_change_latency_us =
2709                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2710         }
2711         kernel_fpu_end();
2712 }
2713
2714 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
2715 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
2716
2717 static bool init_soc_bounding_box(struct dc *dc,
2718                                   struct dcn20_resource_pool *pool)
2719 {
2720         const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
2721         DC_LOGGER_INIT(dc->ctx->logger);
2722
2723         if (!bb && !SOC_BOUNDING_BOX_VALID) {
2724                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
2725                 return false;
2726         }
2727
2728         if (bb && !SOC_BOUNDING_BOX_VALID) {
2729                 int i;
2730
2731                 dcn2_0_soc.sr_exit_time_us =
2732                                 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
2733                 dcn2_0_soc.sr_enter_plus_exit_time_us =
2734                                 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
2735                 dcn2_0_soc.urgent_latency_us =
2736                                 fixed16_to_double_to_cpu(bb->urgent_latency_us);
2737                 dcn2_0_soc.urgent_latency_pixel_data_only_us =
2738                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
2739                 dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
2740                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
2741                 dcn2_0_soc.urgent_latency_vm_data_only_us =
2742                                 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
2743                 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
2744                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
2745                 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
2746                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
2747                 dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
2748                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
2749                 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
2750                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
2751                 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
2752                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
2753                 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
2754                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
2755                 dcn2_0_soc.max_avg_sdp_bw_use_normal_percent =
2756                                 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
2757                 dcn2_0_soc.max_avg_dram_bw_use_normal_percent =
2758                                 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
2759                 dcn2_0_soc.writeback_latency_us =
2760                                 fixed16_to_double_to_cpu(bb->writeback_latency_us);
2761                 dcn2_0_soc.ideal_dram_bw_after_urgent_percent =
2762                                 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
2763                 dcn2_0_soc.max_request_size_bytes =
2764                                 le32_to_cpu(bb->max_request_size_bytes);
2765                 dcn2_0_soc.dram_channel_width_bytes =
2766                                 le32_to_cpu(bb->dram_channel_width_bytes);
2767                 dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes =
2768                                 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
2769                 dcn2_0_soc.dcn_downspread_percent =
2770                                 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
2771                 dcn2_0_soc.downspread_percent =
2772                                 fixed16_to_double_to_cpu(bb->downspread_percent);
2773                 dcn2_0_soc.dram_page_open_time_ns =
2774                                 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
2775                 dcn2_0_soc.dram_rw_turnaround_time_ns =
2776                                 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
2777                 dcn2_0_soc.dram_return_buffer_per_channel_bytes =
2778                                 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
2779                 dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles =
2780                                 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
2781                 dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes =
2782                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
2783                 dcn2_0_soc.channel_interleave_bytes =
2784                                 le32_to_cpu(bb->channel_interleave_bytes);
2785                 dcn2_0_soc.num_banks =
2786                                 le32_to_cpu(bb->num_banks);
2787                 dcn2_0_soc.num_chans =
2788                                 le32_to_cpu(bb->num_chans);
2789                 dcn2_0_soc.vmm_page_size_bytes =
2790                                 le32_to_cpu(bb->vmm_page_size_bytes);
2791                 dcn2_0_soc.dram_clock_change_latency_us =
2792                                 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
2793                 // HACK!! Lower uclock latency switch time so we don't switch
2794                 dcn2_0_soc.dram_clock_change_latency_us = 10;
2795                 dcn2_0_soc.writeback_dram_clock_change_latency_us =
2796                                 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
2797                 dcn2_0_soc.return_bus_width_bytes =
2798                                 le32_to_cpu(bb->return_bus_width_bytes);
2799                 dcn2_0_soc.dispclk_dppclk_vco_speed_mhz =
2800                                 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
2801                 dcn2_0_soc.xfc_bus_transport_time_us =
2802                                 le32_to_cpu(bb->xfc_bus_transport_time_us);
2803                 dcn2_0_soc.xfc_xbuf_latency_tolerance_us =
2804                                 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
2805                 dcn2_0_soc.use_urgent_burst_bw =
2806                                 le32_to_cpu(bb->use_urgent_burst_bw);
2807                 dcn2_0_soc.num_states =
2808                                 le32_to_cpu(bb->num_states);
2809
2810                 for (i = 0; i < dcn2_0_soc.num_states; i++) {
2811                         dcn2_0_soc.clock_limits[i].state =
2812                                         le32_to_cpu(bb->clock_limits[i].state);
2813                         dcn2_0_soc.clock_limits[i].dcfclk_mhz =
2814                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
2815                         dcn2_0_soc.clock_limits[i].fabricclk_mhz =
2816                                         fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
2817                         dcn2_0_soc.clock_limits[i].dispclk_mhz =
2818                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
2819                         dcn2_0_soc.clock_limits[i].dppclk_mhz =
2820                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
2821                         dcn2_0_soc.clock_limits[i].phyclk_mhz =
2822                                         fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
2823                         dcn2_0_soc.clock_limits[i].socclk_mhz =
2824                                         fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
2825                         dcn2_0_soc.clock_limits[i].dscclk_mhz =
2826                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
2827                         dcn2_0_soc.clock_limits[i].dram_speed_mts =
2828                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
2829                 }
2830         }
2831
2832         if (pool->base.pp_smu) {
2833                 struct pp_smu_nv_clock_table max_clocks = {0};
2834                 unsigned int uclk_states[8] = {0};
2835                 unsigned int num_states = 0;
2836                 int i;
2837                 enum pp_smu_status status;
2838                 bool clock_limits_available = false;
2839                 bool uclk_states_available = false;
2840
2841                 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2842                         status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2843                                 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2844
2845                         uclk_states_available = (status == PP_SMU_RESULT_OK);
2846                 }
2847
2848                 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2849                         status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2850                                         (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
2851                         /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
2852                          */
2853                         if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
2854                                 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
2855                         clock_limits_available = (status == PP_SMU_RESULT_OK);
2856                 }
2857
2858                 // HACK: Use the max uclk_states value for all elements.
2859                 for (i = 0; i < num_states; i++)
2860                         uclk_states[i] = uclk_states[num_states - 1];
2861
2862                 if (clock_limits_available && uclk_states_available && num_states)
2863                         update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
2864                 else if (clock_limits_available)
2865                         cap_soc_clocks(&dcn2_0_soc, max_clocks);
2866         }
2867
2868         dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2869         dcn2_0_ip.max_num_dpp = pool->base.pipe_count;
2870         patch_bounding_box(dc, &dcn2_0_soc);
2871
2872         return true;
2873 }
2874
2875 static bool construct(
2876         uint8_t num_virtual_links,
2877         struct dc *dc,
2878         struct dcn20_resource_pool *pool)
2879 {
2880         int i;
2881         struct dc_context *ctx = dc->ctx;
2882         struct irq_service_init_data init_data;
2883
2884         ctx->dc_bios->regs = &bios_regs;
2885
2886         pool->base.res_cap = &res_cap_nv10;
2887         pool->base.funcs = &dcn20_res_pool_funcs;
2888
2889         /*************************************************
2890          *  Resource + asic cap harcoding                *
2891          *************************************************/
2892         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2893
2894         pool->base.pipe_count = 6;
2895         pool->base.mpcc_count = 6;
2896         dc->caps.max_downscale_ratio = 200;
2897         dc->caps.i2c_speed_in_khz = 100;
2898         dc->caps.max_cursor_size = 256;
2899         dc->caps.dmdata_alloc_size = 2048;
2900
2901         dc->caps.max_slave_planes = 1;
2902         dc->caps.post_blend_color_processing = true;
2903         dc->caps.force_dp_tps4_for_cp2520 = true;
2904         dc->caps.hw_3d_lut = true;
2905
2906         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
2907                 dc->debug = debug_defaults_drv;
2908         } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2909                 pool->base.pipe_count = 4;
2910                 pool->base.mpcc_count = pool->base.pipe_count;
2911                 dc->debug = debug_defaults_diags;
2912         } else {
2913                 dc->debug = debug_defaults_diags;
2914         }
2915         //dcn2.0x
2916         dc->work_arounds.dedcn20_305_wa = true;
2917
2918         // Init the vm_helper
2919         if (dc->vm_helper)
2920                 vm_helper_init(dc->vm_helper, 16);
2921
2922         /*************************************************
2923          *  Create resources                             *
2924          *************************************************/
2925
2926         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2927                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2928                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2929                                 &clk_src_regs[0], false);
2930         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2931                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2932                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2933                                 &clk_src_regs[1], false);
2934         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2935                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2936                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2937                                 &clk_src_regs[2], false);
2938         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2939                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2940                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2941                                 &clk_src_regs[3], false);
2942         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2943                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2944                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2945                                 &clk_src_regs[4], false);
2946         pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2947                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2948                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
2949                                 &clk_src_regs[5], false);
2950         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2951         /* todo: not reuse phy_pll registers */
2952         pool->base.dp_clock_source =
2953                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2954                                 CLOCK_SOURCE_ID_DP_DTO,
2955                                 &clk_src_regs[0], true);
2956
2957         for (i = 0; i < pool->base.clk_src_count; i++) {
2958                 if (pool->base.clock_sources[i] == NULL) {
2959                         dm_error("DC: failed to create clock sources!\n");
2960                         BREAK_TO_DEBUGGER();
2961                         goto create_fail;
2962                 }
2963         }
2964
2965         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2966         if (pool->base.dccg == NULL) {
2967                 dm_error("DC: failed to create dccg!\n");
2968                 BREAK_TO_DEBUGGER();
2969                 goto create_fail;
2970         }
2971
2972         pool->base.dmcu = dcn20_dmcu_create(ctx,
2973                         &dmcu_regs,
2974                         &dmcu_shift,
2975                         &dmcu_mask);
2976         if (pool->base.dmcu == NULL) {
2977                 dm_error("DC: failed to create dmcu!\n");
2978                 BREAK_TO_DEBUGGER();
2979                 goto create_fail;
2980         }
2981
2982         pool->base.abm = dce_abm_create(ctx,
2983                         &abm_regs,
2984                         &abm_shift,
2985                         &abm_mask);
2986         if (pool->base.abm == NULL) {
2987                 dm_error("DC: failed to create abm!\n");
2988                 BREAK_TO_DEBUGGER();
2989                 goto create_fail;
2990         }
2991
2992         pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2993
2994
2995         if (!init_soc_bounding_box(dc, pool)) {
2996                 dm_error("DC: failed to initialize soc bounding box!\n");
2997                 BREAK_TO_DEBUGGER();
2998                 goto create_fail;
2999         }
3000
3001         dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
3002
3003         if (!dc->debug.disable_pplib_wm_range) {
3004                 struct pp_smu_wm_range_sets ranges = {0};
3005                 int i = 0;
3006
3007                 ranges.num_reader_wm_sets = 0;
3008
3009                 if (dcn2_0_soc.num_states == 1) {
3010                         ranges.reader_wm_sets[0].wm_inst = i;
3011                         ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3012                         ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3013                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3014                         ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3015
3016                         ranges.num_reader_wm_sets = 1;
3017                 } else if (dcn2_0_soc.num_states > 1) {
3018                         for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) {
3019                                 ranges.reader_wm_sets[i].wm_inst = i;
3020                                 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3021                                 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3022                                 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3023                                 ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
3024
3025                                 ranges.num_reader_wm_sets = i + 1;
3026                         }
3027
3028                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3029                         ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3030                 }
3031
3032                 ranges.num_writer_wm_sets = 1;
3033
3034                 ranges.writer_wm_sets[0].wm_inst = 0;
3035                 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3036                 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3037                 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3038                 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3039
3040                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3041                 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3042                         pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3043         }
3044
3045         init_data.ctx = dc->ctx;
3046         pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3047         if (!pool->base.irqs)
3048                 goto create_fail;
3049
3050         /* mem input -> ipp -> dpp -> opp -> TG */
3051         for (i = 0; i < pool->base.pipe_count; i++) {
3052                 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3053                 if (pool->base.hubps[i] == NULL) {
3054                         BREAK_TO_DEBUGGER();
3055                         dm_error(
3056                                 "DC: failed to create memory input!\n");
3057                         goto create_fail;
3058                 }
3059
3060                 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3061                 if (pool->base.ipps[i] == NULL) {
3062                         BREAK_TO_DEBUGGER();
3063                         dm_error(
3064                                 "DC: failed to create input pixel processor!\n");
3065                         goto create_fail;
3066                 }
3067
3068                 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3069                 if (pool->base.dpps[i] == NULL) {
3070                         BREAK_TO_DEBUGGER();
3071                         dm_error(
3072                                 "DC: failed to create dpps!\n");
3073                         goto create_fail;
3074                 }
3075         }
3076         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3077                 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3078                 if (pool->base.engines[i] == NULL) {
3079                         BREAK_TO_DEBUGGER();
3080                         dm_error(
3081                                 "DC:failed to create aux engine!!\n");
3082                         goto create_fail;
3083                 }
3084                 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3085                 if (pool->base.hw_i2cs[i] == NULL) {
3086                         BREAK_TO_DEBUGGER();
3087                         dm_error(
3088                                 "DC:failed to create hw i2c!!\n");
3089                         goto create_fail;
3090                 }
3091                 pool->base.sw_i2cs[i] = NULL;
3092         }
3093
3094         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3095                 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3096                 if (pool->base.opps[i] == NULL) {
3097                         BREAK_TO_DEBUGGER();
3098                         dm_error(
3099                                 "DC: failed to create output pixel processor!\n");
3100                         goto create_fail;
3101                 }
3102         }
3103
3104         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3105                 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3106                                 ctx, i);
3107                 if (pool->base.timing_generators[i] == NULL) {
3108                         BREAK_TO_DEBUGGER();
3109                         dm_error("DC: failed to create tg!\n");
3110                         goto create_fail;
3111                 }
3112         }
3113
3114         pool->base.timing_generator_count = i;
3115
3116         pool->base.mpc = dcn20_mpc_create(ctx);
3117         if (pool->base.mpc == NULL) {
3118                 BREAK_TO_DEBUGGER();
3119                 dm_error("DC: failed to create mpc!\n");
3120                 goto create_fail;
3121         }
3122
3123         pool->base.hubbub = dcn20_hubbub_create(ctx);
3124         if (pool->base.hubbub == NULL) {
3125                 BREAK_TO_DEBUGGER();
3126                 dm_error("DC: failed to create hubbub!\n");
3127                 goto create_fail;
3128         }
3129
3130 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3131         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3132                 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3133                 if (pool->base.dscs[i] == NULL) {
3134                         BREAK_TO_DEBUGGER();
3135                         dm_error("DC: failed to create display stream compressor %d!\n", i);
3136                         goto create_fail;
3137                 }
3138         }
3139 #endif
3140
3141         if (!dcn20_dwbc_create(ctx, &pool->base)) {
3142                 BREAK_TO_DEBUGGER();
3143                 dm_error("DC: failed to create dwbc!\n");
3144                 goto create_fail;
3145         }
3146         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3147                 BREAK_TO_DEBUGGER();
3148                 dm_error("DC: failed to create mcif_wb!\n");
3149                 goto create_fail;
3150         }
3151
3152         if (!resource_construct(num_virtual_links, dc, &pool->base,
3153                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3154                         &res_create_funcs : &res_create_maximus_funcs)))
3155                         goto create_fail;
3156
3157         dcn20_hw_sequencer_construct(dc);
3158
3159         dc->caps.max_planes =  pool->base.pipe_count;
3160
3161         for (i = 0; i < dc->caps.max_planes; ++i)
3162                 dc->caps.planes[i] = plane_cap;
3163
3164         dc->cap_funcs = cap_funcs;
3165
3166         return true;
3167
3168 create_fail:
3169
3170         destruct(pool);
3171
3172         return false;
3173 }
3174
3175 struct resource_pool *dcn20_create_resource_pool(
3176                 const struct dc_init_data *init_data,
3177                 struct dc *dc)
3178 {
3179         struct dcn20_resource_pool *pool =
3180                 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3181
3182         if (!pool)
3183                 return NULL;
3184
3185         if (construct(init_data->num_virtual_links, dc, pool))
3186                 return &pool->base;
3187
3188         BREAK_TO_DEBUGGER();
3189         kfree(pool);
3190         return NULL;
3191 }