2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
32 #include "include/irq_service_interface.h"
33 #include "dcn20/dcn20_resource.h"
35 #include "dcn10/dcn10_hubp.h"
36 #include "dcn10/dcn10_ipp.h"
37 #include "dcn20_hubbub.h"
38 #include "dcn20_mpc.h"
39 #include "dcn20_hubp.h"
40 #include "irq/dcn20/irq_service_dcn20.h"
41 #include "dcn20_dpp.h"
42 #include "dcn20_optc.h"
43 #include "dcn20_hwseq.h"
44 #include "dce110/dce110_hw_sequencer.h"
45 #include "dcn10/dcn10_resource.h"
46 #include "dcn20_opp.h"
48 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
49 #include "dcn20_dsc.h"
52 #include "dcn20_link_encoder.h"
53 #include "dcn20_stream_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn20_dccg.h"
61 #include "dcn20_vmid.h"
63 #include "navi10_ip_offset.h"
65 #include "dcn/dcn_2_0_0_offset.h"
66 #include "dcn/dcn_2_0_0_sh_mask.h"
68 #include "nbio/nbio_2_3_offset.h"
70 #include "dcn20/dcn20_dwb.h"
71 #include "dcn20/dcn20_mmhubbub.h"
73 #include "mmhub/mmhub_2_0_0_offset.h"
74 #include "mmhub/mmhub_2_0_0_sh_mask.h"
76 #include "reg_helper.h"
77 #include "dce/dce_abm.h"
78 #include "dce/dce_dmcu.h"
79 #include "dce/dce_aux.h"
80 #include "dce/dce_i2c.h"
81 #include "vm_helper.h"
83 #include "amdgpu_socbb.h"
85 /* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
86 #define SOC_BOUNDING_BOX_VALID false
87 #define DC_LOGGER_INIT(logger)
89 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
93 .gpuvm_max_page_table_levels = 4,
94 .hostvm_max_page_table_levels = 4,
95 .hostvm_cached_page_table_levels = 0,
96 .pte_group_size_bytes = 2048,
97 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
102 .rob_buffer_size_kbytes = 168,
103 .det_buffer_size_kbytes = 164,
104 .dpte_buffer_size_in_pte_reqs_luma = 84,
105 .pde_proc_buffer_size_64k_reqs = 48,
106 .dpp_output_buffer_pixels = 2560,
107 .opp_output_buffer_lines = 1,
108 .pixel_chunk_size_kbytes = 8,
109 .pte_chunk_size_kbytes = 2,
110 .meta_chunk_size_kbytes = 2,
111 .writeback_chunk_size_kbytes = 2,
112 .line_buffer_size_bits = 789504,
113 .is_line_buffer_bpp_fixed = 0,
114 .line_buffer_fixed_bpp = 0,
115 .dcc_supported = true,
116 .max_line_buffer_lines = 12,
117 .writeback_luma_buffer_size_kbytes = 12,
118 .writeback_chroma_buffer_size_kbytes = 8,
119 .writeback_chroma_line_buffer_width_pixels = 4,
120 .writeback_max_hscl_ratio = 1,
121 .writeback_max_vscl_ratio = 1,
122 .writeback_min_hscl_ratio = 1,
123 .writeback_min_vscl_ratio = 1,
124 .writeback_max_hscl_taps = 12,
125 .writeback_max_vscl_taps = 12,
126 .writeback_line_buffer_luma_buffer_size = 0,
127 .writeback_line_buffer_chroma_buffer_size = 14643,
128 .cursor_buffer_size = 8,
129 .cursor_chunk_size = 2,
133 .max_dchub_pscl_bw_pix_per_clk = 4,
134 .max_pscl_lb_bw_pix_per_clk = 2,
135 .max_lb_vscl_bw_pix_per_clk = 4,
136 .max_vscl_hscl_bw_pix_per_clk = 4,
143 .dispclk_ramp_margin_percent = 1,
144 .underscan_factor = 1.10,
145 .min_vblank_lines = 32, //
146 .dppclk_delay_subtotal = 77, //
147 .dppclk_delay_scl_lb_only = 16,
148 .dppclk_delay_scl = 50,
149 .dppclk_delay_cnvc_formatter = 8,
150 .dppclk_delay_cnvc_cursor = 6,
151 .dispclk_delay_subtotal = 87, //
152 .dcfclk_cstate_latency = 10, // SRExitTime
153 .max_inter_dcn_tile_repeaters = 8,
155 .xfc_supported = true,
156 .xfc_fill_bw_overhead_percent = 10.0,
157 .xfc_fill_constant_bytes = 0,
160 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
161 /* Defaults that get patched on driver load from firmware. */
166 .fabricclk_mhz = 560.0,
167 .dispclk_mhz = 513.0,
172 .dram_speed_mts = 8960.0,
177 .fabricclk_mhz = 694.0,
178 .dispclk_mhz = 642.0,
183 .dram_speed_mts = 11104.0,
188 .fabricclk_mhz = 875.0,
189 .dispclk_mhz = 734.0,
194 .dram_speed_mts = 14000.0,
198 .dcfclk_mhz = 1000.0,
199 .fabricclk_mhz = 1000.0,
200 .dispclk_mhz = 1100.0,
201 .dppclk_mhz = 1100.0,
203 .socclk_mhz = 1000.0,
205 .dram_speed_mts = 16000.0,
209 .dcfclk_mhz = 1200.0,
210 .fabricclk_mhz = 1200.0,
211 .dispclk_mhz = 1284.0,
212 .dppclk_mhz = 1284.0,
214 .socclk_mhz = 1200.0,
216 .dram_speed_mts = 16000.0,
218 /*Extra state, no dispclk ramping*/
221 .dcfclk_mhz = 1200.0,
222 .fabricclk_mhz = 1200.0,
223 .dispclk_mhz = 1284.0,
224 .dppclk_mhz = 1284.0,
226 .socclk_mhz = 1200.0,
228 .dram_speed_mts = 16000.0,
232 .sr_exit_time_us = 8.6,
233 .sr_enter_plus_exit_time_us = 10.9,
234 .urgent_latency_us = 4.0,
235 .urgent_latency_pixel_data_only_us = 4.0,
236 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
237 .urgent_latency_vm_data_only_us = 4.0,
238 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
239 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
240 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
241 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
242 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
243 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
244 .max_avg_sdp_bw_use_normal_percent = 40.0,
245 .max_avg_dram_bw_use_normal_percent = 40.0,
246 .writeback_latency_us = 12.0,
247 .ideal_dram_bw_after_urgent_percent = 40.0,
248 .max_request_size_bytes = 256,
249 .dram_channel_width_bytes = 2,
250 .fabric_datapath_to_dcn_data_return_bytes = 64,
251 .dcn_downspread_percent = 0.5,
252 .downspread_percent = 0.38,
253 .dram_page_open_time_ns = 50.0,
254 .dram_rw_turnaround_time_ns = 17.5,
255 .dram_return_buffer_per_channel_bytes = 8192,
256 .round_trip_ping_latency_dcfclk_cycles = 131,
257 .urgent_out_of_order_return_per_channel_bytes = 256,
258 .channel_interleave_bytes = 256,
261 .vmm_page_size_bytes = 4096,
262 .dram_clock_change_latency_us = 404.0,
263 .dummy_pstate_latency_us = 5.0,
264 .writeback_dram_clock_change_latency_us = 23.0,
265 .return_bus_width_bytes = 64,
266 .dispclk_dppclk_vco_speed_mhz = 3850,
267 .xfc_bus_transport_time_us = 20,
268 .xfc_xbuf_latency_tolerance_us = 4,
269 .use_urgent_burst_bw = 0
272 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
274 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
275 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
276 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
277 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
278 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
279 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
280 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
281 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
282 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
283 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
284 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
285 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
286 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
287 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
288 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
292 enum dcn20_clk_src_array_id {
302 /* begin *********************
303 * macros to expend register list macro defined in HW object header file */
306 /* TODO awful hack. fixup dcn20_dwb.h */
308 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
310 #define BASE(seg) BASE_INNER(seg)
312 #define SR(reg_name)\
313 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
316 #define SRI(reg_name, block, id)\
317 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
318 mm ## block ## id ## _ ## reg_name
320 #define SRIR(var_name, reg_name, block, id)\
321 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
322 mm ## block ## id ## _ ## reg_name
324 #define SRII(reg_name, block, id)\
325 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
326 mm ## block ## id ## _ ## reg_name
328 #define DCCG_SRII(reg_name, block, id)\
329 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
330 mm ## block ## id ## _ ## reg_name
333 #define NBIO_BASE_INNER(seg) \
334 NBIO_BASE__INST0_SEG ## seg
336 #define NBIO_BASE(seg) \
339 #define NBIO_SR(reg_name)\
340 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
344 #define MMHUB_BASE_INNER(seg) \
345 MMHUB_BASE__INST0_SEG ## seg
347 #define MMHUB_BASE(seg) \
348 MMHUB_BASE_INNER(seg)
350 #define MMHUB_SR(reg_name)\
351 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
354 static const struct bios_registers bios_regs = {
355 NBIO_SR(BIOS_SCRATCH_3),
356 NBIO_SR(BIOS_SCRATCH_6)
359 #define clk_src_regs(index, pllid)\
361 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
364 static const struct dce110_clk_src_regs clk_src_regs[] = {
373 static const struct dce110_clk_src_shift cs_shift = {
374 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
377 static const struct dce110_clk_src_mask cs_mask = {
378 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
381 static const struct dce_dmcu_registers dmcu_regs = {
382 DMCU_DCN10_REG_LIST()
385 static const struct dce_dmcu_shift dmcu_shift = {
386 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
389 static const struct dce_dmcu_mask dmcu_mask = {
390 DMCU_MASK_SH_LIST_DCN10(_MASK)
393 static const struct dce_abm_registers abm_regs = {
397 static const struct dce_abm_shift abm_shift = {
398 ABM_MASK_SH_LIST_DCN20(__SHIFT)
401 static const struct dce_abm_mask abm_mask = {
402 ABM_MASK_SH_LIST_DCN20(_MASK)
405 #define audio_regs(id)\
407 AUD_COMMON_REG_LIST(id)\
410 static const struct dce_audio_registers audio_regs[] = {
420 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
421 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
422 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
423 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
425 static const struct dce_audio_shift audio_shift = {
426 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
429 static const struct dce_audio_mask audio_mask = {
430 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
433 #define stream_enc_regs(id)\
435 SE_DCN2_REG_LIST(id)\
438 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
447 static const struct dcn10_stream_encoder_shift se_shift = {
448 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
451 static const struct dcn10_stream_encoder_mask se_mask = {
452 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
456 #define aux_regs(id)\
458 DCN2_AUX_REG_LIST(id)\
461 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
470 #define hpd_regs(id)\
475 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
484 #define link_regs(id, phyid)\
486 LE_DCN10_REG_LIST(id), \
487 UNIPHY_DCN2_REG_LIST(phyid), \
488 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
491 static const struct dcn10_link_enc_registers link_enc_regs[] = {
500 static const struct dcn10_link_enc_shift le_shift = {
501 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
504 static const struct dcn10_link_enc_mask le_mask = {
505 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
508 #define ipp_regs(id)\
510 IPP_REG_LIST_DCN20(id),\
513 static const struct dcn10_ipp_registers ipp_regs[] = {
522 static const struct dcn10_ipp_shift ipp_shift = {
523 IPP_MASK_SH_LIST_DCN20(__SHIFT)
526 static const struct dcn10_ipp_mask ipp_mask = {
527 IPP_MASK_SH_LIST_DCN20(_MASK),
530 #define opp_regs(id)\
532 OPP_REG_LIST_DCN20(id),\
535 static const struct dcn20_opp_registers opp_regs[] = {
544 static const struct dcn20_opp_shift opp_shift = {
545 OPP_MASK_SH_LIST_DCN20(__SHIFT)
548 static const struct dcn20_opp_mask opp_mask = {
549 OPP_MASK_SH_LIST_DCN20(_MASK)
552 #define aux_engine_regs(id)\
554 AUX_COMMON_REG_LIST0(id), \
557 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
560 static const struct dce110_aux_registers aux_engine_regs[] = {
571 TF_REG_LIST_DCN20(id),\
574 static const struct dcn2_dpp_registers tf_regs[] = {
583 static const struct dcn2_dpp_shift tf_shift = {
584 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
587 static const struct dcn2_dpp_mask tf_mask = {
588 TF_REG_LIST_SH_MASK_DCN20(_MASK)
591 #define dwbc_regs_dcn2(id)\
593 DWBC_COMMON_REG_LIST_DCN2_0(id),\
596 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
600 static const struct dcn20_dwbc_shift dwbc20_shift = {
601 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
604 static const struct dcn20_dwbc_mask dwbc20_mask = {
605 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
608 #define mcif_wb_regs_dcn2(id)\
610 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
613 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
614 mcif_wb_regs_dcn2(0),
617 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
618 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
621 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
622 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
625 static const struct dcn20_mpc_registers mpc_regs = {
626 MPC_REG_LIST_DCN2_0(0),
627 MPC_REG_LIST_DCN2_0(1),
628 MPC_REG_LIST_DCN2_0(2),
629 MPC_REG_LIST_DCN2_0(3),
630 MPC_REG_LIST_DCN2_0(4),
631 MPC_REG_LIST_DCN2_0(5),
632 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
633 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
634 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
635 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
636 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
637 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
640 static const struct dcn20_mpc_shift mpc_shift = {
641 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
644 static const struct dcn20_mpc_mask mpc_mask = {
645 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
649 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
652 static const struct dcn_optc_registers tg_regs[] = {
661 static const struct dcn_optc_shift tg_shift = {
662 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
665 static const struct dcn_optc_mask tg_mask = {
666 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
669 #define hubp_regs(id)\
671 HUBP_REG_LIST_DCN20(id)\
674 static const struct dcn_hubp2_registers hubp_regs[] = {
683 static const struct dcn_hubp2_shift hubp_shift = {
684 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
687 static const struct dcn_hubp2_mask hubp_mask = {
688 HUBP_MASK_SH_LIST_DCN20(_MASK)
691 static const struct dcn_hubbub_registers hubbub_reg = {
692 HUBBUB_REG_LIST_DCN20(0)
695 static const struct dcn_hubbub_shift hubbub_shift = {
696 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
699 static const struct dcn_hubbub_mask hubbub_mask = {
700 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
703 #define vmid_regs(id)\
705 DCN20_VMID_REG_LIST(id)\
708 static const struct dcn_vmid_registers vmid_regs[] = {
727 static const struct dcn20_vmid_shift vmid_shifts = {
728 DCN20_VMID_MASK_SH_LIST(__SHIFT)
731 static const struct dcn20_vmid_mask vmid_masks = {
732 DCN20_VMID_MASK_SH_LIST(_MASK)
735 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
736 #define dsc_regsDCN20(id)\
738 DSC_REG_LIST_DCN20(id)\
741 static const struct dcn20_dsc_registers dsc_regs[] = {
750 static const struct dcn20_dsc_shift dsc_shift = {
751 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
754 static const struct dcn20_dsc_mask dsc_mask = {
755 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
759 static const struct dccg_registers dccg_regs = {
763 static const struct dccg_shift dccg_shift = {
764 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
767 static const struct dccg_mask dccg_mask = {
768 DCCG_MASK_SH_LIST_DCN2(_MASK)
771 static const struct resource_caps res_cap_nv10 = {
772 .num_timing_generator = 6,
774 .num_video_plane = 6,
776 .num_stream_encoder = 6,
781 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
786 static const struct dc_plane_cap plane_cap = {
787 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
788 .blends_with_above = true,
789 .blends_with_below = true,
790 .per_pixel_alpha = true,
792 .pixel_format_support = {
798 .max_upscale_factor = {
804 .max_downscale_factor = {
810 static const struct resource_caps res_cap_nv14 = {
811 .num_timing_generator = 5,
813 .num_video_plane = 5,
815 .num_stream_encoder = 5,
821 static const struct dc_debug_options debug_defaults_drv = {
822 .disable_dmcu = true,
823 .force_abm_enable = false,
824 .timing_trace = false,
826 .disable_pplib_clock_request = true,
827 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
828 .force_single_disp_pipe_split = true,
829 .disable_dcc = DCC_ENABLE,
831 .performance_trace = false,
832 .max_downscale_src_width = 5120,/*upto 5K*/
833 .disable_pplib_wm_range = false,
834 .scl_reset_length10 = true,
835 .sanity_checks = false,
836 .disable_tri_buf = true,
837 .underflow_assert_delay_us = 0xFFFFFFFF,
840 static const struct dc_debug_options debug_defaults_diags = {
841 .disable_dmcu = true,
842 .force_abm_enable = false,
843 .timing_trace = true,
845 .disable_dpp_power_gate = true,
846 .disable_hubp_power_gate = true,
847 .disable_clock_gate = true,
848 .disable_pplib_clock_request = true,
849 .disable_pplib_wm_range = true,
850 .disable_stutter = true,
851 .scl_reset_length10 = true,
852 .underflow_assert_delay_us = 0xFFFFFFFF,
855 void dcn20_dpp_destroy(struct dpp **dpp)
857 kfree(TO_DCN20_DPP(*dpp));
861 struct dpp *dcn20_dpp_create(
862 struct dc_context *ctx,
865 struct dcn20_dpp *dpp =
866 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
871 if (dpp2_construct(dpp, ctx, inst,
872 &tf_regs[inst], &tf_shift, &tf_mask))
880 struct input_pixel_processor *dcn20_ipp_create(
881 struct dc_context *ctx, uint32_t inst)
883 struct dcn10_ipp *ipp =
884 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
891 dcn20_ipp_construct(ipp, ctx, inst,
892 &ipp_regs[inst], &ipp_shift, &ipp_mask);
897 struct output_pixel_processor *dcn20_opp_create(
898 struct dc_context *ctx, uint32_t inst)
900 struct dcn20_opp *opp =
901 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
908 dcn20_opp_construct(opp, ctx, inst,
909 &opp_regs[inst], &opp_shift, &opp_mask);
913 struct dce_aux *dcn20_aux_engine_create(
914 struct dc_context *ctx,
917 struct aux_engine_dce110 *aux_engine =
918 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
923 dce110_aux_engine_construct(aux_engine, ctx, inst,
924 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
925 &aux_engine_regs[inst]);
927 return &aux_engine->base;
929 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
931 static const struct dce_i2c_registers i2c_hw_regs[] = {
940 static const struct dce_i2c_shift i2c_shifts = {
941 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
944 static const struct dce_i2c_mask i2c_masks = {
945 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
948 struct dce_i2c_hw *dcn20_i2c_hw_create(
949 struct dc_context *ctx,
952 struct dce_i2c_hw *dce_i2c_hw =
953 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
958 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
959 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
963 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
965 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
971 dcn20_mpc_construct(mpc20, ctx,
980 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
983 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
989 hubbub2_construct(hubbub, ctx,
994 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
995 struct dcn20_vmid *vmid = &hubbub->vmid[i];
999 vmid->regs = &vmid_regs[i];
1000 vmid->shifts = &vmid_shifts;
1001 vmid->masks = &vmid_masks;
1004 return &hubbub->base;
1007 struct timing_generator *dcn20_timing_generator_create(
1008 struct dc_context *ctx,
1011 struct optc *tgn10 =
1012 kzalloc(sizeof(struct optc), GFP_KERNEL);
1017 tgn10->base.inst = instance;
1018 tgn10->base.ctx = ctx;
1020 tgn10->tg_regs = &tg_regs[instance];
1021 tgn10->tg_shift = &tg_shift;
1022 tgn10->tg_mask = &tg_mask;
1024 dcn20_timing_generator_init(tgn10);
1026 return &tgn10->base;
1029 static const struct encoder_feature_support link_enc_feature = {
1030 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1031 .max_hdmi_pixel_clock = 600000,
1032 .hdmi_ycbcr420_supported = true,
1033 .dp_ycbcr420_supported = true,
1034 .flags.bits.IS_HBR2_CAPABLE = true,
1035 .flags.bits.IS_HBR3_CAPABLE = true,
1036 .flags.bits.IS_TPS3_CAPABLE = true,
1037 .flags.bits.IS_TPS4_CAPABLE = true
1040 struct link_encoder *dcn20_link_encoder_create(
1041 const struct encoder_init_data *enc_init_data)
1043 struct dcn20_link_encoder *enc20 =
1044 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1049 dcn20_link_encoder_construct(enc20,
1052 &link_enc_regs[enc_init_data->transmitter],
1053 &link_enc_aux_regs[enc_init_data->channel - 1],
1054 &link_enc_hpd_regs[enc_init_data->hpd_source],
1058 return &enc20->enc10.base;
1061 struct clock_source *dcn20_clock_source_create(
1062 struct dc_context *ctx,
1063 struct dc_bios *bios,
1064 enum clock_source_id id,
1065 const struct dce110_clk_src_regs *regs,
1068 struct dce110_clk_src *clk_src =
1069 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1074 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1075 regs, &cs_shift, &cs_mask)) {
1076 clk_src->base.dp_clk_src = dp_clk_src;
1077 return &clk_src->base;
1080 BREAK_TO_DEBUGGER();
1084 static void read_dce_straps(
1085 struct dc_context *ctx,
1086 struct resource_straps *straps)
1088 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1089 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1092 static struct audio *dcn20_create_audio(
1093 struct dc_context *ctx, unsigned int inst)
1095 return dce_audio_create(ctx, inst,
1096 &audio_regs[inst], &audio_shift, &audio_mask);
1099 struct stream_encoder *dcn20_stream_encoder_create(
1100 enum engine_id eng_id,
1101 struct dc_context *ctx)
1103 struct dcn10_stream_encoder *enc1 =
1104 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1109 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1110 &stream_enc_regs[eng_id],
1111 &se_shift, &se_mask);
1116 static const struct dce_hwseq_registers hwseq_reg = {
1117 HWSEQ_DCN2_REG_LIST()
1120 static const struct dce_hwseq_shift hwseq_shift = {
1121 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1124 static const struct dce_hwseq_mask hwseq_mask = {
1125 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1128 struct dce_hwseq *dcn20_hwseq_create(
1129 struct dc_context *ctx)
1131 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1135 hws->regs = &hwseq_reg;
1136 hws->shifts = &hwseq_shift;
1137 hws->masks = &hwseq_mask;
1142 static const struct resource_create_funcs res_create_funcs = {
1143 .read_dce_straps = read_dce_straps,
1144 .create_audio = dcn20_create_audio,
1145 .create_stream_encoder = dcn20_stream_encoder_create,
1146 .create_hwseq = dcn20_hwseq_create,
1149 static const struct resource_create_funcs res_create_maximus_funcs = {
1150 .read_dce_straps = NULL,
1151 .create_audio = NULL,
1152 .create_stream_encoder = NULL,
1153 .create_hwseq = dcn20_hwseq_create,
1156 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1158 kfree(TO_DCE110_CLK_SRC(*clk_src));
1162 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1164 struct display_stream_compressor *dcn20_dsc_create(
1165 struct dc_context *ctx, uint32_t inst)
1167 struct dcn20_dsc *dsc =
1168 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1171 BREAK_TO_DEBUGGER();
1175 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1179 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1181 kfree(container_of(*dsc, struct dcn20_dsc, base));
1187 static void destruct(struct dcn20_resource_pool *pool)
1191 for (i = 0; i < pool->base.stream_enc_count; i++) {
1192 if (pool->base.stream_enc[i] != NULL) {
1193 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1194 pool->base.stream_enc[i] = NULL;
1198 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1199 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1200 if (pool->base.dscs[i] != NULL)
1201 dcn20_dsc_destroy(&pool->base.dscs[i]);
1205 if (pool->base.mpc != NULL) {
1206 kfree(TO_DCN20_MPC(pool->base.mpc));
1207 pool->base.mpc = NULL;
1209 if (pool->base.hubbub != NULL) {
1210 kfree(pool->base.hubbub);
1211 pool->base.hubbub = NULL;
1213 for (i = 0; i < pool->base.pipe_count; i++) {
1214 if (pool->base.dpps[i] != NULL)
1215 dcn20_dpp_destroy(&pool->base.dpps[i]);
1217 if (pool->base.ipps[i] != NULL)
1218 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1220 if (pool->base.hubps[i] != NULL) {
1221 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1222 pool->base.hubps[i] = NULL;
1225 if (pool->base.irqs != NULL) {
1226 dal_irq_service_destroy(&pool->base.irqs);
1230 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1231 if (pool->base.engines[i] != NULL)
1232 dce110_engine_destroy(&pool->base.engines[i]);
1233 if (pool->base.hw_i2cs[i] != NULL) {
1234 kfree(pool->base.hw_i2cs[i]);
1235 pool->base.hw_i2cs[i] = NULL;
1237 if (pool->base.sw_i2cs[i] != NULL) {
1238 kfree(pool->base.sw_i2cs[i]);
1239 pool->base.sw_i2cs[i] = NULL;
1243 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1244 if (pool->base.opps[i] != NULL)
1245 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1248 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1249 if (pool->base.timing_generators[i] != NULL) {
1250 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1251 pool->base.timing_generators[i] = NULL;
1255 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1256 if (pool->base.dwbc[i] != NULL) {
1257 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1258 pool->base.dwbc[i] = NULL;
1260 if (pool->base.mcif_wb[i] != NULL) {
1261 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1262 pool->base.mcif_wb[i] = NULL;
1266 for (i = 0; i < pool->base.audio_count; i++) {
1267 if (pool->base.audios[i])
1268 dce_aud_destroy(&pool->base.audios[i]);
1271 for (i = 0; i < pool->base.clk_src_count; i++) {
1272 if (pool->base.clock_sources[i] != NULL) {
1273 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1274 pool->base.clock_sources[i] = NULL;
1278 if (pool->base.dp_clock_source != NULL) {
1279 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1280 pool->base.dp_clock_source = NULL;
1284 if (pool->base.abm != NULL)
1285 dce_abm_destroy(&pool->base.abm);
1287 if (pool->base.dmcu != NULL)
1288 dce_dmcu_destroy(&pool->base.dmcu);
1290 if (pool->base.dccg != NULL)
1291 dcn_dccg_destroy(&pool->base.dccg);
1293 if (pool->base.pp_smu != NULL)
1294 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1298 struct hubp *dcn20_hubp_create(
1299 struct dc_context *ctx,
1302 struct dcn20_hubp *hubp2 =
1303 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1308 if (hubp2_construct(hubp2, ctx, inst,
1309 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1310 return &hubp2->base;
1312 BREAK_TO_DEBUGGER();
1317 static void get_pixel_clock_parameters(
1318 struct pipe_ctx *pipe_ctx,
1319 struct pixel_clk_params *pixel_clk_params)
1321 const struct dc_stream_state *stream = pipe_ctx->stream;
1322 struct pipe_ctx *odm_pipe;
1325 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1328 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1329 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1330 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1331 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1332 /* TODO: un-hardcode*/
1333 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1334 LINK_RATE_REF_FREQ_IN_KHZ;
1335 pixel_clk_params->flags.ENABLE_SS = 0;
1336 pixel_clk_params->color_depth =
1337 stream->timing.display_color_depth;
1338 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1339 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1341 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1342 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1345 pixel_clk_params->requested_pix_clk_100hz /= 4;
1346 else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1347 pixel_clk_params->requested_pix_clk_100hz /= 2;
1349 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1350 pixel_clk_params->requested_pix_clk_100hz *= 2;
1354 static void build_clamping_params(struct dc_stream_state *stream)
1356 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1357 stream->clamping.c_depth = stream->timing.display_color_depth;
1358 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1361 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1364 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1366 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1367 pipe_ctx->clock_source,
1368 &pipe_ctx->stream_res.pix_clk_params,
1369 &pipe_ctx->pll_settings);
1371 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1373 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1374 &pipe_ctx->stream->bit_depth_params);
1375 build_clamping_params(pipe_ctx->stream);
1380 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1382 enum dc_status status = DC_OK;
1383 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1385 /*TODO Seems unneeded anymore */
1386 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1387 if (stream != NULL && old_context->streams[i] != NULL) {
1388 todo: shouldn't have to copy missing parameter here
1389 resource_build_bit_depth_reduction_params(stream,
1390 &stream->bit_depth_params);
1391 stream->clamping.pixel_encoding =
1392 stream->timing.pixel_encoding;
1394 resource_build_bit_depth_reduction_params(stream,
1395 &stream->bit_depth_params);
1396 build_clamping_params(stream);
1404 return DC_ERROR_UNEXPECTED;
1407 status = build_pipe_hw_param(pipe_ctx);
1412 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1414 static void acquire_dsc(struct resource_context *res_ctx,
1415 const struct resource_pool *pool,
1416 struct display_stream_compressor **dsc)
1420 ASSERT(*dsc == NULL);
1423 /* Find first free DSC */
1424 for (i = 0; i < pool->res_cap->num_dsc; i++)
1425 if (!res_ctx->is_dsc_acquired[i]) {
1426 *dsc = pool->dscs[i];
1427 res_ctx->is_dsc_acquired[i] = true;
1432 static void release_dsc(struct resource_context *res_ctx,
1433 const struct resource_pool *pool,
1434 struct display_stream_compressor **dsc)
1438 for (i = 0; i < pool->res_cap->num_dsc; i++)
1439 if (pool->dscs[i] == *dsc) {
1440 res_ctx->is_dsc_acquired[i] = false;
1449 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1450 static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
1451 struct dc_state *dc_ctx,
1452 struct dc_stream_state *dc_stream)
1454 enum dc_status result = DC_OK;
1456 const struct resource_pool *pool = dc->res_pool;
1458 /* Get a DSC if required and available */
1459 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1460 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1462 if (pipe_ctx->stream != dc_stream)
1465 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
1467 /* The number of DSCs can be less than the number of pipes */
1468 if (!pipe_ctx->stream_res.dsc) {
1469 dm_output_to_console("No DSCs available\n");
1470 result = DC_NO_DSC_RESOURCE;
1480 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1481 struct dc_state *new_ctx,
1482 struct dc_stream_state *dc_stream)
1484 struct pipe_ctx *pipe_ctx = NULL;
1487 for (i = 0; i < MAX_PIPES; i++) {
1488 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1489 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1491 if (pipe_ctx->stream_res.dsc)
1492 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1497 return DC_ERROR_UNEXPECTED;
1504 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1506 enum dc_status result = DC_ERROR_UNEXPECTED;
1508 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1510 if (result == DC_OK)
1511 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1513 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1514 /* Get a DSC if required and available */
1515 if (result == DC_OK && dc_stream->timing.flags.DSC)
1516 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1519 if (result == DC_OK)
1520 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1526 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1528 enum dc_status result = DC_OK;
1530 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1531 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1538 static void swizzle_to_dml_params(
1539 enum swizzle_mode_values swizzle,
1540 unsigned int *sw_mode)
1544 *sw_mode = dm_sw_linear;
1547 *sw_mode = dm_sw_4kb_s;
1550 *sw_mode = dm_sw_4kb_s_x;
1553 *sw_mode = dm_sw_4kb_d;
1556 *sw_mode = dm_sw_4kb_d_x;
1559 *sw_mode = dm_sw_64kb_s;
1561 case DC_SW_64KB_S_X:
1562 *sw_mode = dm_sw_64kb_s_x;
1564 case DC_SW_64KB_S_T:
1565 *sw_mode = dm_sw_64kb_s_t;
1568 *sw_mode = dm_sw_64kb_d;
1570 case DC_SW_64KB_D_X:
1571 *sw_mode = dm_sw_64kb_d_x;
1573 case DC_SW_64KB_D_T:
1574 *sw_mode = dm_sw_64kb_d_t;
1576 case DC_SW_64KB_R_X:
1577 *sw_mode = dm_sw_64kb_r_x;
1580 *sw_mode = dm_sw_var_s;
1583 *sw_mode = dm_sw_var_s_x;
1586 *sw_mode = dm_sw_var_d;
1589 *sw_mode = dm_sw_var_d_x;
1593 ASSERT(0); /* Not supported */
1598 static bool dcn20_split_stream_for_odm(
1599 struct resource_context *res_ctx,
1600 const struct resource_pool *pool,
1601 struct pipe_ctx *prev_odm_pipe,
1602 struct pipe_ctx *next_odm_pipe)
1604 int pipe_idx = next_odm_pipe->pipe_idx;
1606 *next_odm_pipe = *prev_odm_pipe;
1608 next_odm_pipe->pipe_idx = pipe_idx;
1609 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1610 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1611 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1612 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1613 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1614 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1615 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1616 next_odm_pipe->stream_res.dsc = NULL;
1618 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1619 ASSERT(!next_odm_pipe->next_odm_pipe);
1620 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1621 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1623 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1624 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1625 ASSERT(next_odm_pipe->top_pipe == NULL);
1627 if (prev_odm_pipe->plane_state) {
1628 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1631 /* HACTIVE halved for odm combine */
1633 /* Calculate new vp and recout for left pipe */
1634 /* Need at least 16 pixels width per side */
1635 if (sd->recout.x + 16 >= sd->h_active)
1637 new_width = sd->h_active - sd->recout.x;
1638 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1639 sd->ratios.horz, sd->recout.width - new_width));
1640 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1641 sd->ratios.horz_c, sd->recout.width - new_width));
1642 sd->recout.width = new_width;
1644 /* Calculate new vp and recout for right pipe */
1645 sd = &next_odm_pipe->plane_res.scl_data;
1646 /* HACTIVE halved for odm combine */
1648 /* Need at least 16 pixels width per side */
1649 if (new_width <= 16)
1651 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1652 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1653 sd->ratios.horz, sd->recout.width - new_width));
1654 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1655 sd->ratios.horz_c, sd->recout.width - new_width));
1656 sd->recout.width = new_width;
1657 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1658 sd->ratios.horz, sd->h_active - sd->recout.x));
1659 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1660 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1663 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1664 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1665 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1666 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
1667 ASSERT(next_odm_pipe->stream_res.dsc);
1668 if (next_odm_pipe->stream_res.dsc == NULL)
1676 static void dcn20_split_stream_for_mpc(
1677 struct resource_context *res_ctx,
1678 const struct resource_pool *pool,
1679 struct pipe_ctx *primary_pipe,
1680 struct pipe_ctx *secondary_pipe)
1682 int pipe_idx = secondary_pipe->pipe_idx;
1683 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1685 *secondary_pipe = *primary_pipe;
1686 secondary_pipe->bottom_pipe = sec_bot_pipe;
1688 secondary_pipe->pipe_idx = pipe_idx;
1689 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1690 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1691 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1692 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1693 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1694 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1695 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1696 secondary_pipe->stream_res.dsc = NULL;
1698 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1699 ASSERT(!secondary_pipe->bottom_pipe);
1700 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1701 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1703 primary_pipe->bottom_pipe = secondary_pipe;
1704 secondary_pipe->top_pipe = primary_pipe;
1706 ASSERT(primary_pipe->plane_state);
1707 resource_build_scaling_params(primary_pipe);
1708 resource_build_scaling_params(secondary_pipe);
1711 void dcn20_populate_dml_writeback_from_context(
1712 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1716 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1717 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1719 if (!res_ctx->pipe_ctx[i].stream)
1722 /* Set writeback information */
1723 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1724 pipes[pipe_cnt].dout.num_active_wb++;
1725 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1726 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1727 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1728 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1729 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1730 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1731 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1732 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1733 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1734 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1735 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1736 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1737 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1739 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1741 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1748 int dcn20_populate_dml_pipes_from_context(
1749 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1752 bool synchronized_vblank = true;
1754 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1755 if (!res_ctx->pipe_ctx[i].stream)
1762 if (!resource_are_streams_timing_synchronizable(
1763 res_ctx->pipe_ctx[pipe_cnt].stream,
1764 res_ctx->pipe_ctx[i].stream)) {
1765 synchronized_vblank = false;
1770 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1771 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1774 if (!res_ctx->pipe_ctx[i].stream)
1777 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1778 pipes[pipe_cnt].pipe.src.dcc = 0;
1779 pipes[pipe_cnt].pipe.src.vm = 0;*/
1781 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1782 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1783 /* todo: rotation?*/
1784 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1786 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1787 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1789 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1790 (timing->v_total - timing->v_addressable
1791 - timing->v_border_top - timing->v_border_bottom) / 2;
1792 /* 36 bytes dp, 32 hdmi */
1793 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1794 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1796 pipes[pipe_cnt].pipe.src.dcc = false;
1797 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1798 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1799 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1800 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1801 - timing->h_addressable
1802 - timing->h_border_left
1803 - timing->h_border_right;
1804 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1805 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1806 - timing->v_addressable
1807 - timing->v_border_top
1808 - timing->v_border_bottom;
1809 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1810 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1811 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1812 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1813 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1814 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1815 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1816 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1817 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1818 pipes[pipe_cnt].dout.dp_lanes = 4;
1819 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1820 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1821 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
1822 || res_ctx->pipe_ctx[i].next_odm_pipe;
1823 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1824 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1825 == res_ctx->pipe_ctx[i].plane_state)
1826 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1827 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1828 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1830 while (first_pipe->prev_odm_pipe)
1831 first_pipe = first_pipe->prev_odm_pipe;
1832 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1835 switch (res_ctx->pipe_ctx[i].stream->signal) {
1836 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1837 case SIGNAL_TYPE_DISPLAY_PORT:
1838 pipes[pipe_cnt].dout.output_type = dm_dp;
1840 case SIGNAL_TYPE_EDP:
1841 pipes[pipe_cnt].dout.output_type = dm_edp;
1843 case SIGNAL_TYPE_HDMI_TYPE_A:
1844 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1845 case SIGNAL_TYPE_DVI_DUAL_LINK:
1846 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1849 /* In case there is no signal, set dp with 4 lanes to allow max config */
1850 pipes[pipe_cnt].dout.output_type = dm_dp;
1851 pipes[pipe_cnt].dout.dp_lanes = 4;
1854 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1855 case COLOR_DEPTH_666:
1858 case COLOR_DEPTH_888:
1861 case COLOR_DEPTH_101010:
1864 case COLOR_DEPTH_121212:
1867 case COLOR_DEPTH_141414:
1870 case COLOR_DEPTH_161616:
1873 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1874 case COLOR_DEPTH_999:
1877 case COLOR_DEPTH_111111:
1886 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1887 case PIXEL_ENCODING_RGB:
1888 case PIXEL_ENCODING_YCBCR444:
1889 pipes[pipe_cnt].dout.output_format = dm_444;
1890 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1892 case PIXEL_ENCODING_YCBCR420:
1893 pipes[pipe_cnt].dout.output_format = dm_420;
1894 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
1896 case PIXEL_ENCODING_YCBCR422:
1897 if (true) /* todo */
1898 pipes[pipe_cnt].dout.output_format = dm_s422;
1900 pipes[pipe_cnt].dout.output_format = dm_n422;
1901 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1904 pipes[pipe_cnt].dout.output_format = dm_444;
1905 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1908 /* todo: default max for now, until there is logic reflecting this in dc*/
1909 pipes[pipe_cnt].dout.output_bpc = 12;
1911 * Use max cursor settings for calculations to minimize
1912 * bw calculations due to cursor on/off
1914 pipes[pipe_cnt].pipe.src.num_cursors = 2;
1915 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1916 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1917 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
1918 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
1920 if (!res_ctx->pipe_ctx[i].plane_state) {
1921 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1922 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
1923 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1924 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1925 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1926 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1927 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1928 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1929 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1930 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
1931 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1932 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1933 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1934 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
1935 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1936 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1937 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1938 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1939 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1940 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1941 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1942 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
1943 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1944 pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
1945 pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
1947 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1948 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1950 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1951 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
1952 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1953 || (res_ctx->pipe_ctx[i].top_pipe
1954 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
1955 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1956 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1957 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1958 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1959 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1960 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1961 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1962 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1963 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1964 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1965 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1966 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1967 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1969 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1970 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1972 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1973 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1974 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1975 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1976 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1977 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
1978 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1979 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
1980 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1981 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
1982 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
1983 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1984 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
1985 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1986 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
1989 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1990 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1991 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1992 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1993 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1994 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1995 scl->ratios.vert.value != dc_fixpt_one.value
1996 || scl->ratios.horz.value != dc_fixpt_one.value
1997 || scl->ratios.vert_c.value != dc_fixpt_one.value
1998 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1999 || dc->debug.always_scale; /*support always scale*/
2000 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2001 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2002 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2003 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2005 pipes[pipe_cnt].pipe.src.macro_tile_size =
2006 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2007 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2008 &pipes[pipe_cnt].pipe.src.sw_mode);
2010 switch (pln->format) {
2011 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2012 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2013 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2015 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2016 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2017 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2019 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2020 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2021 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2022 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2024 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2025 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2026 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2028 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2029 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2032 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2040 /* populate writeback information */
2041 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2046 unsigned int dcn20_calc_max_scaled_time(
2047 unsigned int time_per_pixel,
2048 enum mmhubbub_wbif_mode mode,
2049 unsigned int urgent_watermark)
2051 unsigned int time_per_byte = 0;
2052 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2053 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2054 unsigned int small_free_entry, max_free_entry;
2055 unsigned int buf_lh_capability;
2056 unsigned int max_scaled_time;
2058 if (mode == PACKED_444) /* packed mode */
2059 time_per_byte = time_per_pixel/4;
2060 else if (mode == PLANAR_420_8BPC)
2061 time_per_byte = time_per_pixel;
2062 else if (mode == PLANAR_420_10BPC) /* p010 */
2063 time_per_byte = time_per_pixel * 819/1024;
2065 if (time_per_byte == 0)
2068 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2069 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2070 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2071 max_scaled_time = buf_lh_capability - urgent_watermark;
2072 return max_scaled_time;
2075 void dcn20_set_mcif_arb_params(
2077 struct dc_state *context,
2078 display_e2e_pipe_params_st *pipes,
2081 enum mmhubbub_wbif_mode wbif_mode;
2082 struct mcif_arb_params *wb_arb_params;
2083 int i, j, k, dwb_pipe;
2085 /* Writeback MCIF_WB arbitration parameters */
2087 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2089 if (!context->res_ctx.pipe_ctx[i].stream)
2092 for (j = 0; j < MAX_DWB_PIPES; j++) {
2093 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2096 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2097 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2099 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2100 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2101 wbif_mode = PLANAR_420_8BPC;
2103 wbif_mode = PLANAR_420_10BPC;
2105 wbif_mode = PACKED_444;
2107 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2108 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2109 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2111 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2112 wb_arb_params->slice_lines = 32;
2113 wb_arb_params->arbitration_slice = 2;
2114 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2116 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2120 if (dwb_pipe >= MAX_DWB_PIPES)
2123 if (dwb_pipe >= MAX_DWB_PIPES)
2128 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2129 static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2133 /* Validate DSC config, dsc count validation is already done */
2134 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2135 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2136 struct dc_stream_state *stream = pipe_ctx->stream;
2137 struct dsc_config dsc_cfg;
2138 struct pipe_ctx *odm_pipe;
2141 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2144 /* Only need to validate top pipe */
2145 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2148 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2149 + stream->timing.h_border_right) / opp_cnt;
2150 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2151 + stream->timing.v_border_bottom;
2152 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2153 dsc_cfg.color_depth = stream->timing.display_color_depth;
2154 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2155 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2157 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2164 static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2165 struct resource_context *res_ctx,
2166 const struct resource_pool *pool,
2167 const struct pipe_ctx *primary_pipe)
2169 struct pipe_ctx *secondary_pipe = NULL;
2171 if (dc && primary_pipe) {
2173 int preferred_pipe_idx = 0;
2175 /* first check the prev dc state:
2176 * if this primary pipe has a bottom pipe in prev. state
2177 * and if the bottom pipe is still available (which it should be),
2178 * pick that pipe as secondary
2179 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2180 * check in else case.
2182 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2183 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2184 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2185 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2186 secondary_pipe->pipe_idx = preferred_pipe_idx;
2188 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2189 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2190 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2191 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2192 secondary_pipe->pipe_idx = preferred_pipe_idx;
2197 * if this primary pipe does not have a bottom pipe in prev. state
2198 * start backward and find a pipe that did not used to be a bottom pipe in
2199 * prev. dc state. This way we make sure we keep the same assignment as
2200 * last state and will not have to reprogram every pipe
2202 if (secondary_pipe == NULL) {
2203 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2204 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) {
2205 preferred_pipe_idx = j;
2207 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2208 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2209 secondary_pipe->pipe_idx = preferred_pipe_idx;
2216 * We should never hit this assert unless assignments are shuffled around
2217 * if this happens we will prob. hit a vsync tdr
2219 ASSERT(secondary_pipe);
2221 * search backwards for the second pipe to keep pipe
2222 * assignment more consistent
2224 if (secondary_pipe == NULL) {
2225 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2226 preferred_pipe_idx = j;
2228 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2229 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2230 secondary_pipe->pipe_idx = preferred_pipe_idx;
2237 return secondary_pipe;
2240 bool dcn20_fast_validate_bw(
2242 struct dc_state *context,
2243 display_e2e_pipe_params_st *pipes,
2245 int *pipe_split_from,
2250 int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
2251 bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
2252 bool force_split = false;
2253 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2254 bool failed_non_odm_dsc = false;
2256 int split_threshold = dc->res_pool->pipe_count / 2;
2257 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
2264 /* merge previously split odm pipes since mode support needs to make the decision */
2265 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2266 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2267 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2269 if (pipe->prev_odm_pipe)
2272 pipe->next_odm_pipe = NULL;
2274 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2276 odm_pipe->plane_state = NULL;
2277 odm_pipe->stream = NULL;
2278 odm_pipe->top_pipe = NULL;
2279 odm_pipe->bottom_pipe = NULL;
2280 odm_pipe->prev_odm_pipe = NULL;
2281 odm_pipe->next_odm_pipe = NULL;
2282 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2283 if (odm_pipe->stream_res.dsc)
2284 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2286 /* Clear plane_res and stream_res */
2287 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2288 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2289 odm_pipe = next_odm_pipe;
2291 if (pipe->plane_state)
2292 resource_build_scaling_params(pipe);
2295 /* merge previously mpc split pipes since mode support needs to make the decision */
2296 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2297 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2298 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2300 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2303 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2304 if (hsplit_pipe->bottom_pipe)
2305 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2306 hsplit_pipe->plane_state = NULL;
2307 hsplit_pipe->stream = NULL;
2308 hsplit_pipe->top_pipe = NULL;
2309 hsplit_pipe->bottom_pipe = NULL;
2311 /* Clear plane_res and stream_res */
2312 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2313 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2314 if (pipe->plane_state)
2315 resource_build_scaling_params(pipe);
2318 if (dc->res_pool->funcs->populate_dml_pipes)
2319 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2320 &context->res_ctx, pipes);
2322 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2323 &context->res_ctx, pipes);
2325 *pipe_cnt_out = pipe_cnt;
2332 context->bw_ctx.dml.ip.odm_capable = 0;
2334 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2336 context->bw_ctx.dml.ip.odm_capable = odm_capable;
2338 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2339 /* 1 dsc per stream dsc validation */
2340 if (vlevel <= context->bw_ctx.dml.soc.num_states)
2341 if (!dcn20_validate_dsc(dc, context)) {
2342 failed_non_odm_dsc = true;
2343 vlevel = context->bw_ctx.dml.soc.num_states + 1;
2347 if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
2348 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2350 if (vlevel > context->bw_ctx.dml.soc.num_states)
2353 if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
2354 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
2355 context->commit_hints.full_update_needed = true;
2357 /*initialize pipe_just_split_from to invalid idx*/
2358 for (i = 0; i < MAX_PIPES; i++)
2359 pipe_split_from[i] = -1;
2361 /* Single display only conditionals get set here */
2362 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2363 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2364 bool exit_loop = false;
2366 if (!pipe->stream || pipe->top_pipe)
2369 if (dc->debug.force_single_disp_pipe_split) {
2373 force_split = false;
2377 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2379 avoid_split = false;
2389 if (context->stream_count > split_threshold)
2392 vlevel_unsplit = vlevel;
2393 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2394 if (!context->res_ctx.pipe_ctx[i].stream)
2396 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
2397 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
2402 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2403 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2404 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2405 bool need_split = true;
2408 if (!pipe->stream || pipe_split_from[i] >= 0)
2413 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2415 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
2416 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2418 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2419 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2420 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2421 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2422 ASSERT(hsplit_pipe);
2423 if (!dcn20_split_stream_for_odm(
2424 &context->res_ctx, dc->res_pool,
2427 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2428 dcn20_build_mapped_resource(dc, context, pipe->stream);
2431 if (!pipe->plane_state)
2433 /* Skip 2nd half of already split pipe */
2434 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2437 need_split3d = ((pipe->stream->view_format ==
2438 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2439 pipe->stream->view_format ==
2440 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2441 (pipe->stream->timing.timing_3d_format ==
2442 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2443 pipe->stream->timing.timing_3d_format ==
2444 TIMING_3D_FORMAT_SIDE_BY_SIDE));
2446 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
2448 vlevel = vlevel_unsplit;
2449 context->bw_ctx.dml.vba.maxMpcComb = 0;
2451 need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
2453 /* We do not support mpo + odm at the moment */
2454 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2455 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2458 if (need_split3d || need_split || force_split) {
2459 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2460 /* pipe not split previously needs split */
2461 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2462 ASSERT(hsplit_pipe || force_split);
2466 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2467 if (!dcn20_split_stream_for_odm(
2468 &context->res_ctx, dc->res_pool,
2472 dcn20_split_stream_for_mpc(
2473 &context->res_ctx, dc->res_pool,
2475 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2477 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2478 /* merge should already have been done */
2482 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2483 /* Actual dsc count per stream dsc validation*/
2484 if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
2485 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2486 DML_FAIL_DSC_VALIDATION_FAILURE;
2491 *vlevel_out = vlevel;
2503 void dcn20_calculate_wm(
2504 struct dc *dc, struct dc_state *context,
2505 display_e2e_pipe_params_st *pipes,
2507 int *pipe_split_from,
2510 int pipe_cnt, i, pipe_idx;
2512 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2513 if (!context->res_ctx.pipe_ctx[i].stream)
2516 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2517 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2519 if (pipe_split_from[i] < 0) {
2520 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2521 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2522 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2523 pipes[pipe_cnt].pipe.dest.odm_combine =
2524 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2526 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2529 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2530 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2531 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2532 pipes[pipe_cnt].pipe.dest.odm_combine =
2533 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
2535 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2538 if (dc->config.forced_clocks) {
2539 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2540 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2542 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2543 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2544 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2545 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2550 if (pipe_cnt != pipe_idx) {
2551 if (dc->res_pool->funcs->populate_dml_pipes)
2552 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2553 &context->res_ctx, pipes);
2555 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2556 &context->res_ctx, pipes);
2559 *out_pipe_cnt = pipe_cnt;
2561 pipes[0].clks_cfg.voltage = vlevel;
2562 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2563 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2565 /* only pipe 0 is read for voltage and dcf/soc clocks */
2567 pipes[0].clks_cfg.voltage = 1;
2568 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2569 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2571 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2572 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2573 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2574 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2575 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2578 pipes[0].clks_cfg.voltage = 2;
2579 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2580 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2582 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2583 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2584 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2585 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2586 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2589 pipes[0].clks_cfg.voltage = 3;
2590 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2591 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2593 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2594 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2595 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2596 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2597 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2599 pipes[0].clks_cfg.voltage = vlevel;
2600 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2601 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2602 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2603 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2604 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2605 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2606 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2609 void dcn20_calculate_dlg_params(
2610 struct dc *dc, struct dc_state *context,
2611 display_e2e_pipe_params_st *pipes,
2615 int i, j, pipe_idx, pipe_idx_unsplit;
2616 bool visited[MAX_PIPES] = { 0 };
2618 /* Writeback MCIF_WB arbitration parameters */
2619 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2621 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2622 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2623 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
2624 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
2625 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2626 context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
2627 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2628 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2629 != dm_dram_clock_change_unsupported;
2630 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2633 * An artifact of dml pipe split/odm is that pipes get merged back together for
2634 * calculation. Therefore we need to only extract for first pipe in ascending index order
2635 * and copy into the other split half.
2637 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2638 if (!context->res_ctx.pipe_ctx[i].stream)
2641 if (!visited[pipe_idx]) {
2642 display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;
2643 display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;
2645 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2646 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2647 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2648 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2650 * j iterates inside pipes array, unlike i which iterates inside
2654 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2655 display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2656 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2658 if (src_j->is_hsplit && !visited[j]
2659 && src->hsplit_grp == src_j->hsplit_grp) {
2660 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2661 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2662 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2663 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2667 visited[pipe_idx] = true;
2673 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2674 if (!context->res_ctx.pipe_ctx[i].stream)
2676 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2677 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2678 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2679 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2680 ASSERT(visited[pipe_idx]);
2681 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2684 /*save a original dppclock copy*/
2685 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2686 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
2687 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2688 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
2690 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2691 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2693 if (!context->res_ctx.pipe_ctx[i].stream)
2696 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2697 &context->res_ctx.pipe_ctx[i].dlg_regs,
2698 &context->res_ctx.pipe_ctx[i].ttu_regs,
2703 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2704 false, false, false);
2706 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2707 &context->res_ctx.pipe_ctx[i].rq_regs,
2708 pipes[pipe_idx].pipe);
2713 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
2718 BW_VAL_TRACE_SETUP();
2721 int pipe_split_from[MAX_PIPES];
2723 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2724 DC_LOGGER_INIT(dc->ctx->logger);
2726 BW_VAL_TRACE_COUNT();
2728 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2736 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2738 if (fast_validate) {
2739 BW_VAL_TRACE_SKIP(fast);
2743 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2744 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2746 BW_VAL_TRACE_END_WATERMARKS();
2751 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2752 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2754 BW_VAL_TRACE_SKIP(fail);
2760 BW_VAL_TRACE_FINISH();
2766 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2769 bool voltage_supported = false;
2770 bool full_pstate_supported = false;
2771 bool dummy_pstate_supported = false;
2772 double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2775 return dcn20_validate_bandwidth_internal(dc, context, true);
2778 // Best case, we support full UCLK switch latency
2779 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2780 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2782 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2783 (voltage_supported && full_pstate_supported)) {
2784 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2785 goto restore_dml_state;
2788 // Fallback: Try to only support G6 temperature read latency
2789 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2791 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2792 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2794 if (voltage_supported && dummy_pstate_supported) {
2795 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2796 goto restore_dml_state;
2799 // ERROR: fallback is supposed to always work.
2803 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2804 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2806 return voltage_supported;
2809 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2810 struct dc_state *state,
2811 const struct resource_pool *pool,
2812 struct dc_stream_state *stream)
2814 struct resource_context *res_ctx = &state->res_ctx;
2815 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2816 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2824 idle_pipe->stream = head_pipe->stream;
2825 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2826 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2828 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2829 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2830 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2831 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2836 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2837 const struct dc_dcc_surface_param *input,
2838 struct dc_surface_dcc_cap *output)
2840 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2841 dc->res_pool->hubbub,
2846 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2848 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2850 destruct(dcn20_pool);
2856 static struct dc_cap_funcs cap_funcs = {
2857 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2861 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2863 enum dc_status result = DC_OK;
2865 enum surface_pixel_format surf_pix_format = plane_state->format;
2866 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2868 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2871 swizzle = DC_SW_64KB_D;
2873 swizzle = DC_SW_64KB_S;
2875 plane_state->tiling_info.gfx9.swizzle = swizzle;
2879 static struct resource_funcs dcn20_res_pool_funcs = {
2880 .destroy = dcn20_destroy_resource_pool,
2881 .link_enc_create = dcn20_link_encoder_create,
2882 .validate_bandwidth = dcn20_validate_bandwidth,
2883 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2884 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2885 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2886 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2887 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
2888 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
2889 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
2892 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2895 uint32_t pipe_count = pool->res_cap->num_dwb;
2897 ASSERT(pipe_count > 0);
2899 for (i = 0; i < pipe_count; i++) {
2900 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2904 dm_error("DC: failed to create dwbc20!\n");
2907 dcn20_dwbc_construct(dwbc20, ctx,
2912 pool->dwbc[i] = &dwbc20->base;
2917 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2920 uint32_t pipe_count = pool->res_cap->num_dwb;
2922 ASSERT(pipe_count > 0);
2924 for (i = 0; i < pipe_count; i++) {
2925 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2929 dm_error("DC: failed to create mcif_wb20!\n");
2933 dcn20_mmhubbub_construct(mcif_wb20, ctx,
2939 pool->mcif_wb[i] = &mcif_wb20->base;
2944 struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2946 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
2951 dm_pp_get_funcs(ctx, pp_smu);
2953 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2954 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2959 void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2961 if (pp_smu && *pp_smu) {
2967 static void cap_soc_clocks(
2968 struct _vcs_dpi_soc_bounding_box_st *bb,
2969 struct pp_smu_nv_clock_table max_clocks)
2973 // First pass - cap all clocks higher than the reported max
2974 for (i = 0; i < bb->num_states; i++) {
2975 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
2976 && max_clocks.dcfClockInKhz != 0)
2977 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
2979 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
2980 && max_clocks.uClockInKhz != 0)
2981 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2983 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
2984 && max_clocks.fabricClockInKhz != 0)
2985 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
2987 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
2988 && max_clocks.displayClockInKhz != 0)
2989 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
2991 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
2992 && max_clocks.dppClockInKhz != 0)
2993 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
2995 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
2996 && max_clocks.phyClockInKhz != 0)
2997 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
2999 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3000 && max_clocks.socClockInKhz != 0)
3001 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3003 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3004 && max_clocks.dscClockInKhz != 0)
3005 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3008 // Second pass - remove all duplicate clock states
3009 for (i = bb->num_states - 1; i > 1; i--) {
3010 bool duplicate = true;
3012 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3014 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3016 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3018 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3020 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3022 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3024 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3026 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3034 static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3035 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3037 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
3039 int num_calculated_states = 0;
3042 if (num_states == 0)
3045 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3046 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3048 // Accounting for SOC/DCF relationship, we can go as high as
3049 // 506Mhz in Vmin. We need to code 507 since SMU will round down to 506.
3052 for (i = 0; i < num_states; i++) {
3053 int min_fclk_required_by_uclk;
3054 calculated_states[i].state = i;
3055 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3057 // FCLK:UCLK ratio is 1.08
3058 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
3060 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3061 min_dcfclk : min_fclk_required_by_uclk;
3063 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3064 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3066 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3067 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3069 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3070 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3071 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3073 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3075 num_calculated_states++;
3078 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3079 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3080 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3082 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3083 bb->num_states = num_calculated_states;
3085 // Duplicate the last state, DML always an extra state identical to max state to work
3086 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3087 bb->clock_limits[num_calculated_states].state = bb->num_states;
3090 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3093 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3094 && dc->bb_overrides.sr_exit_time_ns) {
3095 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3098 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3099 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3100 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3101 bb->sr_enter_plus_exit_time_us =
3102 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3105 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3106 && dc->bb_overrides.urgent_latency_ns) {
3107 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3110 if ((int)(bb->dram_clock_change_latency_us * 1000)
3111 != dc->bb_overrides.dram_clock_change_latency_ns
3112 && dc->bb_overrides.dram_clock_change_latency_ns) {
3113 bb->dram_clock_change_latency_us =
3114 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3119 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3120 uint32_t hw_internal_rev)
3122 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3123 return &dcn2_0_nv12_soc;
3128 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3129 uint32_t hw_internal_rev)
3135 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3137 return DML_PROJECT_NAVI10v2;
3140 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3141 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3143 static bool init_soc_bounding_box(struct dc *dc,
3144 struct dcn20_resource_pool *pool)
3146 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
3147 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3148 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3149 struct _vcs_dpi_ip_params_st *loaded_ip =
3150 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3152 DC_LOGGER_INIT(dc->ctx->logger);
3154 if (!bb && !SOC_BOUNDING_BOX_VALID) {
3155 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3159 if (bb && !SOC_BOUNDING_BOX_VALID) {
3162 dcn2_0_nv12_soc.sr_exit_time_us =
3163 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
3164 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
3165 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
3166 dcn2_0_nv12_soc.urgent_latency_us =
3167 fixed16_to_double_to_cpu(bb->urgent_latency_us);
3168 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
3169 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
3170 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
3171 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
3172 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
3173 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
3174 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
3175 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
3176 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
3177 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
3178 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
3179 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
3180 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
3181 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
3182 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
3183 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
3184 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
3185 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
3186 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
3187 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
3188 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
3189 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
3190 dcn2_0_nv12_soc.writeback_latency_us =
3191 fixed16_to_double_to_cpu(bb->writeback_latency_us);
3192 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
3193 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
3194 dcn2_0_nv12_soc.max_request_size_bytes =
3195 le32_to_cpu(bb->max_request_size_bytes);
3196 dcn2_0_nv12_soc.dram_channel_width_bytes =
3197 le32_to_cpu(bb->dram_channel_width_bytes);
3198 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
3199 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3200 dcn2_0_nv12_soc.dcn_downspread_percent =
3201 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3202 dcn2_0_nv12_soc.downspread_percent =
3203 fixed16_to_double_to_cpu(bb->downspread_percent);
3204 dcn2_0_nv12_soc.dram_page_open_time_ns =
3205 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3206 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
3207 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3208 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
3209 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3210 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
3211 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3212 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
3213 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3214 dcn2_0_nv12_soc.channel_interleave_bytes =
3215 le32_to_cpu(bb->channel_interleave_bytes);
3216 dcn2_0_nv12_soc.num_banks =
3217 le32_to_cpu(bb->num_banks);
3218 dcn2_0_nv12_soc.num_chans =
3219 le32_to_cpu(bb->num_chans);
3220 dcn2_0_nv12_soc.vmm_page_size_bytes =
3221 le32_to_cpu(bb->vmm_page_size_bytes);
3222 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3223 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3224 // HACK!! Lower uclock latency switch time so we don't switch
3225 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3226 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
3227 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3228 dcn2_0_nv12_soc.return_bus_width_bytes =
3229 le32_to_cpu(bb->return_bus_width_bytes);
3230 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
3231 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3232 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
3233 le32_to_cpu(bb->xfc_bus_transport_time_us);
3234 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
3235 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3236 dcn2_0_nv12_soc.use_urgent_burst_bw =
3237 le32_to_cpu(bb->use_urgent_burst_bw);
3238 dcn2_0_nv12_soc.num_states =
3239 le32_to_cpu(bb->num_states);
3241 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3242 dcn2_0_nv12_soc.clock_limits[i].state =
3243 le32_to_cpu(bb->clock_limits[i].state);
3244 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
3245 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3246 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
3247 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3248 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
3249 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3250 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
3251 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3252 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
3253 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3254 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
3255 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3256 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
3257 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3258 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
3259 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3263 if (pool->base.pp_smu) {
3264 struct pp_smu_nv_clock_table max_clocks = {0};
3265 unsigned int uclk_states[8] = {0};
3266 unsigned int num_states = 0;
3267 enum pp_smu_status status;
3268 bool clock_limits_available = false;
3269 bool uclk_states_available = false;
3271 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3272 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3273 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3275 uclk_states_available = (status == PP_SMU_RESULT_OK);
3278 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3279 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3280 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3281 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3283 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3284 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3285 clock_limits_available = (status == PP_SMU_RESULT_OK);
3288 if (clock_limits_available && uclk_states_available && num_states)
3289 update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3290 else if (clock_limits_available)
3291 cap_soc_clocks(loaded_bb, max_clocks);
3294 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3295 loaded_ip->max_num_dpp = pool->base.pipe_count;
3296 patch_bounding_box(dc, loaded_bb);
3301 static bool construct(
3302 uint8_t num_virtual_links,
3304 struct dcn20_resource_pool *pool)
3307 struct dc_context *ctx = dc->ctx;
3308 struct irq_service_init_data init_data;
3309 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3310 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3311 struct _vcs_dpi_ip_params_st *loaded_ip =
3312 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3313 enum dml_project dml_project_version =
3314 get_dml_project_version(ctx->asic_id.hw_internal_rev);
3316 ctx->dc_bios->regs = &bios_regs;
3317 pool->base.funcs = &dcn20_res_pool_funcs;
3319 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3320 pool->base.res_cap = &res_cap_nv14;
3321 pool->base.pipe_count = 5;
3322 pool->base.mpcc_count = 5;
3324 pool->base.res_cap = &res_cap_nv10;
3325 pool->base.pipe_count = 6;
3326 pool->base.mpcc_count = 6;
3328 /*************************************************
3329 * Resource + asic cap harcoding *
3330 *************************************************/
3331 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3333 dc->caps.max_downscale_ratio = 200;
3334 dc->caps.i2c_speed_in_khz = 100;
3335 dc->caps.max_cursor_size = 256;
3336 dc->caps.dmdata_alloc_size = 2048;
3338 dc->caps.max_slave_planes = 1;
3339 dc->caps.post_blend_color_processing = true;
3340 dc->caps.force_dp_tps4_for_cp2520 = true;
3341 dc->caps.hw_3d_lut = true;
3343 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3344 dc->debug = debug_defaults_drv;
3345 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3346 pool->base.pipe_count = 4;
3347 pool->base.mpcc_count = pool->base.pipe_count;
3348 dc->debug = debug_defaults_diags;
3350 dc->debug = debug_defaults_diags;
3353 dc->work_arounds.dedcn20_305_wa = true;
3355 // Init the vm_helper
3357 vm_helper_init(dc->vm_helper, 16);
3359 /*************************************************
3360 * Create resources *
3361 *************************************************/
3363 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3364 dcn20_clock_source_create(ctx, ctx->dc_bios,
3365 CLOCK_SOURCE_COMBO_PHY_PLL0,
3366 &clk_src_regs[0], false);
3367 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3368 dcn20_clock_source_create(ctx, ctx->dc_bios,
3369 CLOCK_SOURCE_COMBO_PHY_PLL1,
3370 &clk_src_regs[1], false);
3371 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3372 dcn20_clock_source_create(ctx, ctx->dc_bios,
3373 CLOCK_SOURCE_COMBO_PHY_PLL2,
3374 &clk_src_regs[2], false);
3375 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3376 dcn20_clock_source_create(ctx, ctx->dc_bios,
3377 CLOCK_SOURCE_COMBO_PHY_PLL3,
3378 &clk_src_regs[3], false);
3379 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3380 dcn20_clock_source_create(ctx, ctx->dc_bios,
3381 CLOCK_SOURCE_COMBO_PHY_PLL4,
3382 &clk_src_regs[4], false);
3383 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3384 dcn20_clock_source_create(ctx, ctx->dc_bios,
3385 CLOCK_SOURCE_COMBO_PHY_PLL5,
3386 &clk_src_regs[5], false);
3387 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3388 /* todo: not reuse phy_pll registers */
3389 pool->base.dp_clock_source =
3390 dcn20_clock_source_create(ctx, ctx->dc_bios,
3391 CLOCK_SOURCE_ID_DP_DTO,
3392 &clk_src_regs[0], true);
3394 for (i = 0; i < pool->base.clk_src_count; i++) {
3395 if (pool->base.clock_sources[i] == NULL) {
3396 dm_error("DC: failed to create clock sources!\n");
3397 BREAK_TO_DEBUGGER();
3402 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3403 if (pool->base.dccg == NULL) {
3404 dm_error("DC: failed to create dccg!\n");
3405 BREAK_TO_DEBUGGER();
3409 pool->base.dmcu = dcn20_dmcu_create(ctx,
3413 if (pool->base.dmcu == NULL) {
3414 dm_error("DC: failed to create dmcu!\n");
3415 BREAK_TO_DEBUGGER();
3419 pool->base.abm = dce_abm_create(ctx,
3423 if (pool->base.abm == NULL) {
3424 dm_error("DC: failed to create abm!\n");
3425 BREAK_TO_DEBUGGER();
3429 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3432 if (!init_soc_bounding_box(dc, pool)) {
3433 dm_error("DC: failed to initialize soc bounding box!\n");
3434 BREAK_TO_DEBUGGER();
3438 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3440 if (!dc->debug.disable_pplib_wm_range) {
3441 struct pp_smu_wm_range_sets ranges = {0};
3444 ranges.num_reader_wm_sets = 0;
3446 if (loaded_bb->num_states == 1) {
3447 ranges.reader_wm_sets[0].wm_inst = i;
3448 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3449 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3450 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3451 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3453 ranges.num_reader_wm_sets = 1;
3454 } else if (loaded_bb->num_states > 1) {
3455 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3456 ranges.reader_wm_sets[i].wm_inst = i;
3457 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3458 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3459 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3460 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3462 ranges.num_reader_wm_sets = i + 1;
3465 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3466 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3469 ranges.num_writer_wm_sets = 1;
3471 ranges.writer_wm_sets[0].wm_inst = 0;
3472 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3473 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3474 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3475 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3477 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3478 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3479 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3482 init_data.ctx = dc->ctx;
3483 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3484 if (!pool->base.irqs)
3487 /* mem input -> ipp -> dpp -> opp -> TG */
3488 for (i = 0; i < pool->base.pipe_count; i++) {
3489 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3490 if (pool->base.hubps[i] == NULL) {
3491 BREAK_TO_DEBUGGER();
3493 "DC: failed to create memory input!\n");
3497 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3498 if (pool->base.ipps[i] == NULL) {
3499 BREAK_TO_DEBUGGER();
3501 "DC: failed to create input pixel processor!\n");
3505 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3506 if (pool->base.dpps[i] == NULL) {
3507 BREAK_TO_DEBUGGER();
3509 "DC: failed to create dpps!\n");
3513 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3514 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3515 if (pool->base.engines[i] == NULL) {
3516 BREAK_TO_DEBUGGER();
3518 "DC:failed to create aux engine!!\n");
3521 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3522 if (pool->base.hw_i2cs[i] == NULL) {
3523 BREAK_TO_DEBUGGER();
3525 "DC:failed to create hw i2c!!\n");
3528 pool->base.sw_i2cs[i] = NULL;
3531 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3532 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3533 if (pool->base.opps[i] == NULL) {
3534 BREAK_TO_DEBUGGER();
3536 "DC: failed to create output pixel processor!\n");
3541 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3542 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3544 if (pool->base.timing_generators[i] == NULL) {
3545 BREAK_TO_DEBUGGER();
3546 dm_error("DC: failed to create tg!\n");
3551 pool->base.timing_generator_count = i;
3553 pool->base.mpc = dcn20_mpc_create(ctx);
3554 if (pool->base.mpc == NULL) {
3555 BREAK_TO_DEBUGGER();
3556 dm_error("DC: failed to create mpc!\n");
3560 pool->base.hubbub = dcn20_hubbub_create(ctx);
3561 if (pool->base.hubbub == NULL) {
3562 BREAK_TO_DEBUGGER();
3563 dm_error("DC: failed to create hubbub!\n");
3567 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3568 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3569 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3570 if (pool->base.dscs[i] == NULL) {
3571 BREAK_TO_DEBUGGER();
3572 dm_error("DC: failed to create display stream compressor %d!\n", i);
3578 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3579 BREAK_TO_DEBUGGER();
3580 dm_error("DC: failed to create dwbc!\n");
3583 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3584 BREAK_TO_DEBUGGER();
3585 dm_error("DC: failed to create mcif_wb!\n");
3589 if (!resource_construct(num_virtual_links, dc, &pool->base,
3590 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3591 &res_create_funcs : &res_create_maximus_funcs)))
3594 dcn20_hw_sequencer_construct(dc);
3596 dc->caps.max_planes = pool->base.pipe_count;
3598 for (i = 0; i < dc->caps.max_planes; ++i)
3599 dc->caps.planes[i] = plane_cap;
3601 dc->cap_funcs = cap_funcs;
3612 struct resource_pool *dcn20_create_resource_pool(
3613 const struct dc_init_data *init_data,
3616 struct dcn20_resource_pool *pool =
3617 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3622 if (construct(init_data->num_virtual_links, dc, pool))
3625 BREAK_TO_DEBUGGER();