drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dcn20/dcn20_resource.h"
  34
  35 #include "dcn10/dcn10_hubp.h"
  36 #include "dcn10/dcn10_ipp.h"
  37 #include "dcn20_hubbub.h"
  38 #include "dcn20_mpc.h"
  39 #include "dcn20_hubp.h"
  40 #include "irq/dcn20/irq_service_dcn20.h"
  41 #include "dcn20_dpp.h"
  42 #include "dcn20_optc.h"
  43 #include "dcn20_hwseq.h"
  44 #include "dce110/dce110_hw_sequencer.h"
  45 #include "dcn10/dcn10_resource.h"
  46 #include "dcn20_opp.h"
  47
  48 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  49 #include "dcn20_dsc.h"
  50 #endif
  51
  52 #include "dcn20_link_encoder.h"
  53 #include "dcn20_stream_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "virtual/virtual_stream_encoder.h"
  58 #include "dce110/dce110_resource.h"
  59 #include "dml/display_mode_vba.h"
  60 #include "dcn20_dccg.h"
  61 #include "dcn20_vmid.h"
  62
  63 #include "navi10_ip_offset.h"
  64
  65 #include "dcn/dcn_2_0_0_offset.h"
  66 #include "dcn/dcn_2_0_0_sh_mask.h"
  67
  68 #include "nbio/nbio_2_3_offset.h"
  69
  70 #include "dcn20/dcn20_dwb.h"
  71 #include "dcn20/dcn20_mmhubbub.h"
  72
  73 #include "mmhub/mmhub_2_0_0_offset.h"
  74 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  75
  76 #include "reg_helper.h"
  77 #include "dce/dce_abm.h"
  78 #include "dce/dce_dmcu.h"
  79 #include "dce/dce_aux.h"
  80 #include "dce/dce_i2c.h"
  81 #include "vm_helper.h"
  82
  83 #include "amdgpu_socbb.h"
  84
  85 /* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
  86 #define SOC_BOUNDING_BOX_VALID false
  87 #define DC_LOGGER_INIT(logger)
  88
  89 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  90         .odm_capable = 1,
  91         .gpuvm_enable = 0,
  92         .hostvm_enable = 0,
  93         .gpuvm_max_page_table_levels = 4,
  94         .hostvm_max_page_table_levels = 4,
  95         .hostvm_cached_page_table_levels = 0,
  96         .pte_group_size_bytes = 2048,
  97 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  98         .num_dsc = 6,
  99 #else
 100         .num_dsc = 0,
 101 #endif
 102         .rob_buffer_size_kbytes = 168,
 103         .det_buffer_size_kbytes = 164,
 104         .dpte_buffer_size_in_pte_reqs_luma = 84,
 105         .pde_proc_buffer_size_64k_reqs = 48,
 106         .dpp_output_buffer_pixels = 2560,
 107         .opp_output_buffer_lines = 1,
 108         .pixel_chunk_size_kbytes = 8,
 109         .pte_chunk_size_kbytes = 2,
 110         .meta_chunk_size_kbytes = 2,
 111         .writeback_chunk_size_kbytes = 2,
 112         .line_buffer_size_bits = 789504,
 113         .is_line_buffer_bpp_fixed = 0,
 114         .line_buffer_fixed_bpp = 0,
 115         .dcc_supported = true,
 116         .max_line_buffer_lines = 12,
 117         .writeback_luma_buffer_size_kbytes = 12,
 118         .writeback_chroma_buffer_size_kbytes = 8,
 119         .writeback_chroma_line_buffer_width_pixels = 4,
 120         .writeback_max_hscl_ratio = 1,
 121         .writeback_max_vscl_ratio = 1,
 122         .writeback_min_hscl_ratio = 1,
 123         .writeback_min_vscl_ratio = 1,
 124         .writeback_max_hscl_taps = 12,
 125         .writeback_max_vscl_taps = 12,
 126         .writeback_line_buffer_luma_buffer_size = 0,
 127         .writeback_line_buffer_chroma_buffer_size = 14643,
 128         .cursor_buffer_size = 8,
 129         .cursor_chunk_size = 2,
 130         .max_num_otg = 6,
 131         .max_num_dpp = 6,
 132         .max_num_wb = 1,
 133         .max_dchub_pscl_bw_pix_per_clk = 4,
 134         .max_pscl_lb_bw_pix_per_clk = 2,
 135         .max_lb_vscl_bw_pix_per_clk = 4,
 136         .max_vscl_hscl_bw_pix_per_clk = 4,
 137         .max_hscl_ratio = 8,
 138         .max_vscl_ratio = 8,
 139         .hscl_mults = 4,
 140         .vscl_mults = 4,
 141         .max_hscl_taps = 8,
 142         .max_vscl_taps = 8,
 143         .dispclk_ramp_margin_percent = 1,
 144         .underscan_factor = 1.10,
 145         .min_vblank_lines = 32, //
 146         .dppclk_delay_subtotal = 77, //
 147         .dppclk_delay_scl_lb_only = 16,
 148         .dppclk_delay_scl = 50,
 149         .dppclk_delay_cnvc_formatter = 8,
 150         .dppclk_delay_cnvc_cursor = 6,
 151         .dispclk_delay_subtotal = 87, //
 152         .dcfclk_cstate_latency = 10, // SRExitTime
 153         .max_inter_dcn_tile_repeaters = 8,
 154
 155         .xfc_supported = true,
 156         .xfc_fill_bw_overhead_percent = 10.0,
 157         .xfc_fill_constant_bytes = 0,
 158 };
 159
 160 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
 161         /* Defaults that get patched on driver load from firmware. */
 162         .clock_limits = {
 163                         {
 164                                 .state = 0,
 165                                 .dcfclk_mhz = 560.0,
 166                                 .fabricclk_mhz = 560.0,
 167                                 .dispclk_mhz = 513.0,
 168                                 .dppclk_mhz = 513.0,
 169                                 .phyclk_mhz = 540.0,
 170                                 .socclk_mhz = 560.0,
 171                                 .dscclk_mhz = 171.0,
 172                                 .dram_speed_mts = 8960.0,
 173                         },
 174                         {
 175                                 .state = 1,
 176                                 .dcfclk_mhz = 694.0,
 177                                 .fabricclk_mhz = 694.0,
 178                                 .dispclk_mhz = 642.0,
 179                                 .dppclk_mhz = 642.0,
 180                                 .phyclk_mhz = 600.0,
 181                                 .socclk_mhz = 694.0,
 182                                 .dscclk_mhz = 214.0,
 183                                 .dram_speed_mts = 11104.0,
 184                         },
 185                         {
 186                                 .state = 2,
 187                                 .dcfclk_mhz = 875.0,
 188                                 .fabricclk_mhz = 875.0,
 189                                 .dispclk_mhz = 734.0,
 190                                 .dppclk_mhz = 734.0,
 191                                 .phyclk_mhz = 810.0,
 192                                 .socclk_mhz = 875.0,
 193                                 .dscclk_mhz = 245.0,
 194                                 .dram_speed_mts = 14000.0,
 195                         },
 196                         {
 197                                 .state = 3,
 198                                 .dcfclk_mhz = 1000.0,
 199                                 .fabricclk_mhz = 1000.0,
 200                                 .dispclk_mhz = 1100.0,
 201                                 .dppclk_mhz = 1100.0,
 202                                 .phyclk_mhz = 810.0,
 203                                 .socclk_mhz = 1000.0,
 204                                 .dscclk_mhz = 367.0,
 205                                 .dram_speed_mts = 16000.0,
 206                         },
 207                         {
 208                                 .state = 4,
 209                                 .dcfclk_mhz = 1200.0,
 210                                 .fabricclk_mhz = 1200.0,
 211                                 .dispclk_mhz = 1284.0,
 212                                 .dppclk_mhz = 1284.0,
 213                                 .phyclk_mhz = 810.0,
 214                                 .socclk_mhz = 1200.0,
 215                                 .dscclk_mhz = 428.0,
 216                                 .dram_speed_mts = 16000.0,
 217                         },
 218                         /*Extra state, no dispclk ramping*/
 219                         {
 220                                 .state = 5,
 221                                 .dcfclk_mhz = 1200.0,
 222                                 .fabricclk_mhz = 1200.0,
 223                                 .dispclk_mhz = 1284.0,
 224                                 .dppclk_mhz = 1284.0,
 225                                 .phyclk_mhz = 810.0,
 226                                 .socclk_mhz = 1200.0,
 227                                 .dscclk_mhz = 428.0,
 228                                 .dram_speed_mts = 16000.0,
 229                         },
 230                 },
 231         .num_states = 5,
 232         .sr_exit_time_us = 8.6,
 233         .sr_enter_plus_exit_time_us = 10.9,
 234         .urgent_latency_us = 4.0,
 235         .urgent_latency_pixel_data_only_us = 4.0,
 236         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 237         .urgent_latency_vm_data_only_us = 4.0,
 238         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 239         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 240         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 241         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 242         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 243         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 244         .max_avg_sdp_bw_use_normal_percent = 40.0,
 245         .max_avg_dram_bw_use_normal_percent = 40.0,
 246         .writeback_latency_us = 12.0,
 247         .ideal_dram_bw_after_urgent_percent = 40.0,
 248         .max_request_size_bytes = 256,
 249         .dram_channel_width_bytes = 2,
 250         .fabric_datapath_to_dcn_data_return_bytes = 64,
 251         .dcn_downspread_percent = 0.5,
 252         .downspread_percent = 0.38,
 253         .dram_page_open_time_ns = 50.0,
 254         .dram_rw_turnaround_time_ns = 17.5,
 255         .dram_return_buffer_per_channel_bytes = 8192,
 256         .round_trip_ping_latency_dcfclk_cycles = 131,
 257         .urgent_out_of_order_return_per_channel_bytes = 256,
 258         .channel_interleave_bytes = 256,
 259         .num_banks = 8,
 260         .num_chans = 16,
 261         .vmm_page_size_bytes = 4096,
 262         .dram_clock_change_latency_us = 404.0,
 263         .dummy_pstate_latency_us = 5.0,
 264         .writeback_dram_clock_change_latency_us = 23.0,
 265         .return_bus_width_bytes = 64,
 266         .dispclk_dppclk_vco_speed_mhz = 3850,
 267         .xfc_bus_transport_time_us = 20,
 268         .xfc_xbuf_latency_tolerance_us = 4,
 269         .use_urgent_burst_bw = 0
 270 };
 271
 272 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
 273
 274 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 275         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 276         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 277         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 278         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 279         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 280         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 281         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 282         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 283         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 284         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 285         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 286         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 287         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 288         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 289 #endif
 290
 291
 292 enum dcn20_clk_src_array_id {
 293         DCN20_CLK_SRC_PLL0,
 294         DCN20_CLK_SRC_PLL1,
 295         DCN20_CLK_SRC_PLL2,
 296         DCN20_CLK_SRC_PLL3,
 297         DCN20_CLK_SRC_PLL4,
 298         DCN20_CLK_SRC_PLL5,
 299         DCN20_CLK_SRC_TOTAL
 300 };
 301
 302 /* begin *********************
 303  * macros to expend register list macro defined in HW object header file */
 304
 305 /* DCN */
 306 /* TODO awful hack. fixup dcn20_dwb.h */
 307 #undef BASE_INNER
 308 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 309
 310 #define BASE(seg) BASE_INNER(seg)
 311
 312 #define SR(reg_name)\
 313                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 314                                         mm ## reg_name
 315
 316 #define SRI(reg_name, block, id)\
 317         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 318                                         mm ## block ## id ## _ ## reg_name
 319
 320 #define SRIR(var_name, reg_name, block, id)\
 321         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 322                                         mm ## block ## id ## _ ## reg_name
 323
 324 #define SRII(reg_name, block, id)\
 325         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 326                                         mm ## block ## id ## _ ## reg_name
 327
 328 #define DCCG_SRII(reg_name, block, id)\
 329         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 330                                         mm ## block ## id ## _ ## reg_name
 331
 332 /* NBIO */
 333 #define NBIO_BASE_INNER(seg) \
 334         NBIO_BASE__INST0_SEG ## seg
 335
 336 #define NBIO_BASE(seg) \
 337         NBIO_BASE_INNER(seg)
 338
 339 #define NBIO_SR(reg_name)\
 340                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 341                                         mm ## reg_name
 342
 343 /* MMHUB */
 344 #define MMHUB_BASE_INNER(seg) \
 345         MMHUB_BASE__INST0_SEG ## seg
 346
 347 #define MMHUB_BASE(seg) \
 348         MMHUB_BASE_INNER(seg)
 349
 350 #define MMHUB_SR(reg_name)\
 351                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 352                                         mmMM ## reg_name
 353
 354 static const struct bios_registers bios_regs = {
 355                 NBIO_SR(BIOS_SCRATCH_3),
 356                 NBIO_SR(BIOS_SCRATCH_6)
 357 };
 358
 359 #define clk_src_regs(index, pllid)\
 360 [index] = {\
 361         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 362 }
 363
 364 static const struct dce110_clk_src_regs clk_src_regs[] = {
 365         clk_src_regs(0, A),
 366         clk_src_regs(1, B),
 367         clk_src_regs(2, C),
 368         clk_src_regs(3, D),
 369         clk_src_regs(4, E),
 370         clk_src_regs(5, F)
 371 };
 372
 373 static const struct dce110_clk_src_shift cs_shift = {
 374                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 375 };
 376
 377 static const struct dce110_clk_src_mask cs_mask = {
 378                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 379 };
 380
 381 static const struct dce_dmcu_registers dmcu_regs = {
 382                 DMCU_DCN10_REG_LIST()
 383 };
 384
 385 static const struct dce_dmcu_shift dmcu_shift = {
 386                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 387 };
 388
 389 static const struct dce_dmcu_mask dmcu_mask = {
 390                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 391 };
 392
 393 static const struct dce_abm_registers abm_regs = {
 394                 ABM_DCN20_REG_LIST()
 395 };
 396
 397 static const struct dce_abm_shift abm_shift = {
 398                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 399 };
 400
 401 static const struct dce_abm_mask abm_mask = {
 402                 ABM_MASK_SH_LIST_DCN20(_MASK)
 403 };
 404
 405 #define audio_regs(id)\
 406 [id] = {\
 407                 AUD_COMMON_REG_LIST(id)\
 408 }
 409
 410 static const struct dce_audio_registers audio_regs[] = {
 411         audio_regs(0),
 412         audio_regs(1),
 413         audio_regs(2),
 414         audio_regs(3),
 415         audio_regs(4),
 416         audio_regs(5),
 417         audio_regs(6),
 418 };
 419
 420 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 421                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 422                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 423                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 424
 425 static const struct dce_audio_shift audio_shift = {
 426                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 427 };
 428
 429 static const struct dce_audio_mask audio_mask = {
 430                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 431 };
 432
 433 #define stream_enc_regs(id)\
 434 [id] = {\
 435         SE_DCN2_REG_LIST(id)\
 436 }
 437
 438 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 439         stream_enc_regs(0),
 440         stream_enc_regs(1),
 441         stream_enc_regs(2),
 442         stream_enc_regs(3),
 443         stream_enc_regs(4),
 444         stream_enc_regs(5),
 445 };
 446
 447 static const struct dcn10_stream_encoder_shift se_shift = {
 448                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 449 };
 450
 451 static const struct dcn10_stream_encoder_mask se_mask = {
 452                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 453 };
 454
 455
 456 #define aux_regs(id)\
 457 [id] = {\
 458         DCN2_AUX_REG_LIST(id)\
 459 }
 460
 461 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 462                 aux_regs(0),
 463                 aux_regs(1),
 464                 aux_regs(2),
 465                 aux_regs(3),
 466                 aux_regs(4),
 467                 aux_regs(5)
 468 };
 469
 470 #define hpd_regs(id)\
 471 [id] = {\
 472         HPD_REG_LIST(id)\
 473 }
 474
 475 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 476                 hpd_regs(0),
 477                 hpd_regs(1),
 478                 hpd_regs(2),
 479                 hpd_regs(3),
 480                 hpd_regs(4),
 481                 hpd_regs(5)
 482 };
 483
 484 #define link_regs(id, phyid)\
 485 [id] = {\
 486         LE_DCN10_REG_LIST(id), \
 487         UNIPHY_DCN2_REG_LIST(phyid), \
 488         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 489 }
 490
 491 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 492         link_regs(0, A),
 493         link_regs(1, B),
 494         link_regs(2, C),
 495         link_regs(3, D),
 496         link_regs(4, E),
 497         link_regs(5, F)
 498 };
 499
 500 static const struct dcn10_link_enc_shift le_shift = {
 501         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
 502 };
 503
 504 static const struct dcn10_link_enc_mask le_mask = {
 505         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
 506 };
 507
 508 #define ipp_regs(id)\
 509 [id] = {\
 510         IPP_REG_LIST_DCN20(id),\
 511 }
 512
 513 static const struct dcn10_ipp_registers ipp_regs[] = {
 514         ipp_regs(0),
 515         ipp_regs(1),
 516         ipp_regs(2),
 517         ipp_regs(3),
 518         ipp_regs(4),
 519         ipp_regs(5),
 520 };
 521
 522 static const struct dcn10_ipp_shift ipp_shift = {
 523                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 524 };
 525
 526 static const struct dcn10_ipp_mask ipp_mask = {
 527                 IPP_MASK_SH_LIST_DCN20(_MASK),
 528 };
 529
 530 #define opp_regs(id)\
 531 [id] = {\
 532         OPP_REG_LIST_DCN20(id),\
 533 }
 534
 535 static const struct dcn20_opp_registers opp_regs[] = {
 536         opp_regs(0),
 537         opp_regs(1),
 538         opp_regs(2),
 539         opp_regs(3),
 540         opp_regs(4),
 541         opp_regs(5),
 542 };
 543
 544 static const struct dcn20_opp_shift opp_shift = {
 545                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 546 };
 547
 548 static const struct dcn20_opp_mask opp_mask = {
 549                 OPP_MASK_SH_LIST_DCN20(_MASK)
 550 };
 551
 552 #define aux_engine_regs(id)\
 553 [id] = {\
 554         AUX_COMMON_REG_LIST0(id), \
 555         .AUXN_IMPCAL = 0, \
 556         .AUXP_IMPCAL = 0, \
 557         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 558 }
 559
 560 static const struct dce110_aux_registers aux_engine_regs[] = {
 561                 aux_engine_regs(0),
 562                 aux_engine_regs(1),
 563                 aux_engine_regs(2),
 564                 aux_engine_regs(3),
 565                 aux_engine_regs(4),
 566                 aux_engine_regs(5)
 567 };
 568
 569 #define tf_regs(id)\
 570 [id] = {\
 571         TF_REG_LIST_DCN20(id),\
 572 }
 573
 574 static const struct dcn2_dpp_registers tf_regs[] = {
 575         tf_regs(0),
 576         tf_regs(1),
 577         tf_regs(2),
 578         tf_regs(3),
 579         tf_regs(4),
 580         tf_regs(5),
 581 };
 582
 583 static const struct dcn2_dpp_shift tf_shift = {
 584                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
 585 };
 586
 587 static const struct dcn2_dpp_mask tf_mask = {
 588                 TF_REG_LIST_SH_MASK_DCN20(_MASK)
 589 };
 590
 591 #define dwbc_regs_dcn2(id)\
 592 [id] = {\
 593         DWBC_COMMON_REG_LIST_DCN2_0(id),\
 594                 }
 595
 596 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
 597         dwbc_regs_dcn2(0),
 598 };
 599
 600 static const struct dcn20_dwbc_shift dwbc20_shift = {
 601         DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 602 };
 603
 604 static const struct dcn20_dwbc_mask dwbc20_mask = {
 605         DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 606 };
 607
 608 #define mcif_wb_regs_dcn2(id)\
 609 [id] = {\
 610         MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
 611                 }
 612
 613 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
 614         mcif_wb_regs_dcn2(0),
 615 };
 616
 617 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
 618         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 619 };
 620
 621 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
 622         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 623 };
 624
 625 static const struct dcn20_mpc_registers mpc_regs = {
 626                 MPC_REG_LIST_DCN2_0(0),
 627                 MPC_REG_LIST_DCN2_0(1),
 628                 MPC_REG_LIST_DCN2_0(2),
 629                 MPC_REG_LIST_DCN2_0(3),
 630                 MPC_REG_LIST_DCN2_0(4),
 631                 MPC_REG_LIST_DCN2_0(5),
 632                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 633                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 634                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 635                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 636                 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
 637                 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
 638 };
 639
 640 static const struct dcn20_mpc_shift mpc_shift = {
 641         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 642 };
 643
 644 static const struct dcn20_mpc_mask mpc_mask = {
 645         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 646 };
 647
 648 #define tg_regs(id)\
 649 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 650
 651
 652 static const struct dcn_optc_registers tg_regs[] = {
 653         tg_regs(0),
 654         tg_regs(1),
 655         tg_regs(2),
 656         tg_regs(3),
 657         tg_regs(4),
 658         tg_regs(5)
 659 };
 660
 661 static const struct dcn_optc_shift tg_shift = {
 662         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 663 };
 664
 665 static const struct dcn_optc_mask tg_mask = {
 666         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 667 };
 668
 669 #define hubp_regs(id)\
 670 [id] = {\
 671         HUBP_REG_LIST_DCN20(id)\
 672 }
 673
 674 static const struct dcn_hubp2_registers hubp_regs[] = {
 675                 hubp_regs(0),
 676                 hubp_regs(1),
 677                 hubp_regs(2),
 678                 hubp_regs(3),
 679                 hubp_regs(4),
 680                 hubp_regs(5)
 681 };
 682
 683 static const struct dcn_hubp2_shift hubp_shift = {
 684                 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
 685 };
 686
 687 static const struct dcn_hubp2_mask hubp_mask = {
 688                 HUBP_MASK_SH_LIST_DCN20(_MASK)
 689 };
 690
 691 static const struct dcn_hubbub_registers hubbub_reg = {
 692                 HUBBUB_REG_LIST_DCN20(0)
 693 };
 694
 695 static const struct dcn_hubbub_shift hubbub_shift = {
 696                 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
 697 };
 698
 699 static const struct dcn_hubbub_mask hubbub_mask = {
 700                 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
 701 };
 702
 703 #define vmid_regs(id)\
 704 [id] = {\
 705                 DCN20_VMID_REG_LIST(id)\
 706 }
 707
 708 static const struct dcn_vmid_registers vmid_regs[] = {
 709         vmid_regs(0),
 710         vmid_regs(1),
 711         vmid_regs(2),
 712         vmid_regs(3),
 713         vmid_regs(4),
 714         vmid_regs(5),
 715         vmid_regs(6),
 716         vmid_regs(7),
 717         vmid_regs(8),
 718         vmid_regs(9),
 719         vmid_regs(10),
 720         vmid_regs(11),
 721         vmid_regs(12),
 722         vmid_regs(13),
 723         vmid_regs(14),
 724         vmid_regs(15)
 725 };
 726
 727 static const struct dcn20_vmid_shift vmid_shifts = {
 728                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 729 };
 730
 731 static const struct dcn20_vmid_mask vmid_masks = {
 732                 DCN20_VMID_MASK_SH_LIST(_MASK)
 733 };
 734
 735 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 736 #define dsc_regsDCN20(id)\
 737 [id] = {\
 738         DSC_REG_LIST_DCN20(id)\
 739 }
 740
 741 static const struct dcn20_dsc_registers dsc_regs[] = {
 742         dsc_regsDCN20(0),
 743         dsc_regsDCN20(1),
 744         dsc_regsDCN20(2),
 745         dsc_regsDCN20(3),
 746         dsc_regsDCN20(4),
 747         dsc_regsDCN20(5)
 748 };
 749
 750 static const struct dcn20_dsc_shift dsc_shift = {
 751         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 752 };
 753
 754 static const struct dcn20_dsc_mask dsc_mask = {
 755         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 756 };
 757 #endif
 758
 759 static const struct dccg_registers dccg_regs = {
 760                 DCCG_REG_LIST_DCN2()
 761 };
 762
 763 static const struct dccg_shift dccg_shift = {
 764                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 765 };
 766
 767 static const struct dccg_mask dccg_mask = {
 768                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 769 };
 770
 771 static const struct resource_caps res_cap_nv10 = {
 772                 .num_timing_generator = 6,
 773                 .num_opp = 6,
 774                 .num_video_plane = 6,
 775                 .num_audio = 7,
 776                 .num_stream_encoder = 6,
 777                 .num_pll = 6,
 778                 .num_dwb = 1,
 779                 .num_ddc = 6,
 780                 .num_vmid = 16,
 781 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 782                 .num_dsc = 6,
 783 #endif
 784 };
 785
 786 static const struct dc_plane_cap plane_cap = {
 787         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 788         .blends_with_above = true,
 789         .blends_with_below = true,
 790         .per_pixel_alpha = true,
 791
 792         .pixel_format_support = {
 793                         .argb8888 = true,
 794                         .nv12 = true,
 795                         .fp16 = true
 796         },
 797
 798         .max_upscale_factor = {
 799                         .argb8888 = 16000,
 800                         .nv12 = 16000,
 801                         .fp16 = 1
 802         },
 803
 804         .max_downscale_factor = {
 805                         .argb8888 = 250,
 806                         .nv12 = 250,
 807                         .fp16 = 1
 808         }
 809 };
 810 static const struct resource_caps res_cap_nv14 = {
 811                 .num_timing_generator = 5,
 812                 .num_opp = 5,
 813                 .num_video_plane = 5,
 814                 .num_audio = 6,
 815                 .num_stream_encoder = 5,
 816                 .num_pll = 5,
 817                 .num_dwb = 0,
 818                 .num_ddc = 5,
 819 };
 820
 821 static const struct dc_debug_options debug_defaults_drv = {
 822                 .disable_dmcu = true,
 823                 .force_abm_enable = false,
 824                 .timing_trace = false,
 825                 .clock_trace = true,
 826                 .disable_pplib_clock_request = true,
 827                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 828                 .force_single_disp_pipe_split = true,
 829                 .disable_dcc = DCC_ENABLE,
 830                 .vsr_support = true,
 831                 .performance_trace = false,
 832                 .max_downscale_src_width = 5120,/*upto 5K*/
 833                 .disable_pplib_wm_range = false,
 834                 .scl_reset_length10 = true,
 835                 .sanity_checks = false,
 836                 .disable_tri_buf = true,
 837                 .underflow_assert_delay_us = 0xFFFFFFFF,
 838 };
 839
 840 static const struct dc_debug_options debug_defaults_diags = {
 841                 .disable_dmcu = true,
 842                 .force_abm_enable = false,
 843                 .timing_trace = true,
 844                 .clock_trace = true,
 845                 .disable_dpp_power_gate = true,
 846                 .disable_hubp_power_gate = true,
 847                 .disable_clock_gate = true,
 848                 .disable_pplib_clock_request = true,
 849                 .disable_pplib_wm_range = true,
 850                 .disable_stutter = true,
 851                 .scl_reset_length10 = true,
 852                 .underflow_assert_delay_us = 0xFFFFFFFF,
 853 };
 854
 855 void dcn20_dpp_destroy(struct dpp **dpp)
 856 {
 857         kfree(TO_DCN20_DPP(*dpp));
 858         *dpp = NULL;
 859 }
 860
 861 struct dpp *dcn20_dpp_create(
 862         struct dc_context *ctx,
 863         uint32_t inst)
 864 {
 865         struct dcn20_dpp *dpp =
 866                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 867
 868         if (!dpp)
 869                 return NULL;
 870
 871         if (dpp2_construct(dpp, ctx, inst,
 872                         &tf_regs[inst], &tf_shift, &tf_mask))
 873                 return &dpp->base;
 874
 875         BREAK_TO_DEBUGGER();
 876         kfree(dpp);
 877         return NULL;
 878 }
 879
 880 struct input_pixel_processor *dcn20_ipp_create(
 881         struct dc_context *ctx, uint32_t inst)
 882 {
 883         struct dcn10_ipp *ipp =
 884                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 885
 886         if (!ipp) {
 887                 BREAK_TO_DEBUGGER();
 888                 return NULL;
 889         }
 890
 891         dcn20_ipp_construct(ipp, ctx, inst,
 892                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 893         return &ipp->base;
 894 }
 895
 896
 897 struct output_pixel_processor *dcn20_opp_create(
 898         struct dc_context *ctx, uint32_t inst)
 899 {
 900         struct dcn20_opp *opp =
 901                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 902
 903         if (!opp) {
 904                 BREAK_TO_DEBUGGER();
 905                 return NULL;
 906         }
 907
 908         dcn20_opp_construct(opp, ctx, inst,
 909                         &opp_regs[inst], &opp_shift, &opp_mask);
 910         return &opp->base;
 911 }
 912
 913 struct dce_aux *dcn20_aux_engine_create(
 914         struct dc_context *ctx,
 915         uint32_t inst)
 916 {
 917         struct aux_engine_dce110 *aux_engine =
 918                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 919
 920         if (!aux_engine)
 921                 return NULL;
 922
 923         dce110_aux_engine_construct(aux_engine, ctx, inst,
 924                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 925                                     &aux_engine_regs[inst]);
 926
 927         return &aux_engine->base;
 928 }
 929 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 930
 931 static const struct dce_i2c_registers i2c_hw_regs[] = {
 932                 i2c_inst_regs(1),
 933                 i2c_inst_regs(2),
 934                 i2c_inst_regs(3),
 935                 i2c_inst_regs(4),
 936                 i2c_inst_regs(5),
 937                 i2c_inst_regs(6),
 938 };
 939
 940 static const struct dce_i2c_shift i2c_shifts = {
 941                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 942 };
 943
 944 static const struct dce_i2c_mask i2c_masks = {
 945                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 946 };
 947
 948 struct dce_i2c_hw *dcn20_i2c_hw_create(
 949         struct dc_context *ctx,
 950         uint32_t inst)
 951 {
 952         struct dce_i2c_hw *dce_i2c_hw =
 953                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 954
 955         if (!dce_i2c_hw)
 956                 return NULL;
 957
 958         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 959                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 960
 961         return dce_i2c_hw;
 962 }
 963 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
 964 {
 965         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
 966                                           GFP_KERNEL);
 967
 968         if (!mpc20)
 969                 return NULL;
 970
 971         dcn20_mpc_construct(mpc20, ctx,
 972                         &mpc_regs,
 973                         &mpc_shift,
 974                         &mpc_mask,
 975                         6);
 976
 977         return &mpc20->base;
 978 }
 979
 980 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
 981 {
 982         int i;
 983         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
 984                                           GFP_KERNEL);
 985
 986         if (!hubbub)
 987                 return NULL;
 988
 989         hubbub2_construct(hubbub, ctx,
 990                         &hubbub_reg,
 991                         &hubbub_shift,
 992                         &hubbub_mask);
 993
 994         for (i = 0; i < res_cap_nv10.num_vmid; i++) {
 995                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
 996
 997                 vmid->ctx = ctx;
 998
 999                 vmid->regs = &vmid_regs[i];
1000                 vmid->shifts = &vmid_shifts;
1001                 vmid->masks = &vmid_masks;
1002         }
1003
1004         return &hubbub->base;
1005 }
1006
1007 struct timing_generator *dcn20_timing_generator_create(
1008                 struct dc_context *ctx,
1009                 uint32_t instance)
1010 {
1011         struct optc *tgn10 =
1012                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1013
1014         if (!tgn10)
1015                 return NULL;
1016
1017         tgn10->base.inst = instance;
1018         tgn10->base.ctx = ctx;
1019
1020         tgn10->tg_regs = &tg_regs[instance];
1021         tgn10->tg_shift = &tg_shift;
1022         tgn10->tg_mask = &tg_mask;
1023
1024         dcn20_timing_generator_init(tgn10);
1025
1026         return &tgn10->base;
1027 }
1028
1029 static const struct encoder_feature_support link_enc_feature = {
1030                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1031                 .max_hdmi_pixel_clock = 600000,
1032                 .hdmi_ycbcr420_supported = true,
1033                 .dp_ycbcr420_supported = true,
1034                 .flags.bits.IS_HBR2_CAPABLE = true,
1035                 .flags.bits.IS_HBR3_CAPABLE = true,
1036                 .flags.bits.IS_TPS3_CAPABLE = true,
1037                 .flags.bits.IS_TPS4_CAPABLE = true
1038 };
1039
1040 struct link_encoder *dcn20_link_encoder_create(
1041         const struct encoder_init_data *enc_init_data)
1042 {
1043         struct dcn20_link_encoder *enc20 =
1044                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1045
1046         if (!enc20)
1047                 return NULL;
1048
1049         dcn20_link_encoder_construct(enc20,
1050                                       enc_init_data,
1051                                       &link_enc_feature,
1052                                       &link_enc_regs[enc_init_data->transmitter],
1053                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1054                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1055                                       &le_shift,
1056                                       &le_mask);
1057
1058         return &enc20->enc10.base;
1059 }
1060
1061 struct clock_source *dcn20_clock_source_create(
1062         struct dc_context *ctx,
1063         struct dc_bios *bios,
1064         enum clock_source_id id,
1065         const struct dce110_clk_src_regs *regs,
1066         bool dp_clk_src)
1067 {
1068         struct dce110_clk_src *clk_src =
1069                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1070
1071         if (!clk_src)
1072                 return NULL;
1073
1074         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1075                         regs, &cs_shift, &cs_mask)) {
1076                 clk_src->base.dp_clk_src = dp_clk_src;
1077                 return &clk_src->base;
1078         }
1079
1080         kfree(clk_src);
1081         BREAK_TO_DEBUGGER();
1082         return NULL;
1083 }
1084
1085 static void read_dce_straps(
1086         struct dc_context *ctx,
1087         struct resource_straps *straps)
1088 {
1089         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1090                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1091 }
1092
1093 static struct audio *dcn20_create_audio(
1094                 struct dc_context *ctx, unsigned int inst)
1095 {
1096         return dce_audio_create(ctx, inst,
1097                         &audio_regs[inst], &audio_shift, &audio_mask);
1098 }
1099
1100 struct stream_encoder *dcn20_stream_encoder_create(
1101         enum engine_id eng_id,
1102         struct dc_context *ctx)
1103 {
1104         struct dcn10_stream_encoder *enc1 =
1105                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1106
1107         if (!enc1)
1108                 return NULL;
1109
1110         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1111                                         &stream_enc_regs[eng_id],
1112                                         &se_shift, &se_mask);
1113
1114         return &enc1->base;
1115 }
1116
1117 static const struct dce_hwseq_registers hwseq_reg = {
1118                 HWSEQ_DCN2_REG_LIST()
1119 };
1120
1121 static const struct dce_hwseq_shift hwseq_shift = {
1122                 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1123 };
1124
1125 static const struct dce_hwseq_mask hwseq_mask = {
1126                 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1127 };
1128
1129 struct dce_hwseq *dcn20_hwseq_create(
1130         struct dc_context *ctx)
1131 {
1132         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1133
1134         if (hws) {
1135                 hws->ctx = ctx;
1136                 hws->regs = &hwseq_reg;
1137                 hws->shifts = &hwseq_shift;
1138                 hws->masks = &hwseq_mask;
1139         }
1140         return hws;
1141 }
1142
1143 static const struct resource_create_funcs res_create_funcs = {
1144         .read_dce_straps = read_dce_straps,
1145         .create_audio = dcn20_create_audio,
1146         .create_stream_encoder = dcn20_stream_encoder_create,
1147         .create_hwseq = dcn20_hwseq_create,
1148 };
1149
1150 static const struct resource_create_funcs res_create_maximus_funcs = {
1151         .read_dce_straps = NULL,
1152         .create_audio = NULL,
1153         .create_stream_encoder = NULL,
1154         .create_hwseq = dcn20_hwseq_create,
1155 };
1156
1157 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1158 {
1159         kfree(TO_DCE110_CLK_SRC(*clk_src));
1160         *clk_src = NULL;
1161 }
1162
1163 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1164
1165 struct display_stream_compressor *dcn20_dsc_create(
1166         struct dc_context *ctx, uint32_t inst)
1167 {
1168         struct dcn20_dsc *dsc =
1169                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1170
1171         if (!dsc) {
1172                 BREAK_TO_DEBUGGER();
1173                 return NULL;
1174         }
1175
1176         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1177         return &dsc->base;
1178 }
1179
1180 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1181 {
1182         kfree(container_of(*dsc, struct dcn20_dsc, base));
1183         *dsc = NULL;
1184 }
1185
1186 #endif
1187
1188 static void destruct(struct dcn20_resource_pool *pool)
1189 {
1190         unsigned int i;
1191
1192         for (i = 0; i < pool->base.stream_enc_count; i++) {
1193                 if (pool->base.stream_enc[i] != NULL) {
1194                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1195                         pool->base.stream_enc[i] = NULL;
1196                 }
1197         }
1198
1199 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1200         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1201                 if (pool->base.dscs[i] != NULL)
1202                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1203         }
1204 #endif
1205
1206         if (pool->base.mpc != NULL) {
1207                 kfree(TO_DCN20_MPC(pool->base.mpc));
1208                 pool->base.mpc = NULL;
1209         }
1210         if (pool->base.hubbub != NULL) {
1211                 kfree(pool->base.hubbub);
1212                 pool->base.hubbub = NULL;
1213         }
1214         for (i = 0; i < pool->base.pipe_count; i++) {
1215                 if (pool->base.dpps[i] != NULL)
1216                         dcn20_dpp_destroy(&pool->base.dpps[i]);
1217
1218                 if (pool->base.ipps[i] != NULL)
1219                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1220
1221                 if (pool->base.hubps[i] != NULL) {
1222                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1223                         pool->base.hubps[i] = NULL;
1224                 }
1225
1226                 if (pool->base.irqs != NULL) {
1227                         dal_irq_service_destroy(&pool->base.irqs);
1228                 }
1229         }
1230
1231         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1232                 if (pool->base.engines[i] != NULL)
1233                         dce110_engine_destroy(&pool->base.engines[i]);
1234                 if (pool->base.hw_i2cs[i] != NULL) {
1235                         kfree(pool->base.hw_i2cs[i]);
1236                         pool->base.hw_i2cs[i] = NULL;
1237                 }
1238                 if (pool->base.sw_i2cs[i] != NULL) {
1239                         kfree(pool->base.sw_i2cs[i]);
1240                         pool->base.sw_i2cs[i] = NULL;
1241                 }
1242         }
1243
1244         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1245                 if (pool->base.opps[i] != NULL)
1246                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1247         }
1248
1249         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1250                 if (pool->base.timing_generators[i] != NULL)    {
1251                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1252                         pool->base.timing_generators[i] = NULL;
1253                 }
1254         }
1255
1256         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1257                 if (pool->base.dwbc[i] != NULL) {
1258                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1259                         pool->base.dwbc[i] = NULL;
1260                 }
1261                 if (pool->base.mcif_wb[i] != NULL) {
1262                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1263                         pool->base.mcif_wb[i] = NULL;
1264                 }
1265         }
1266
1267         for (i = 0; i < pool->base.audio_count; i++) {
1268                 if (pool->base.audios[i])
1269                         dce_aud_destroy(&pool->base.audios[i]);
1270         }
1271
1272         for (i = 0; i < pool->base.clk_src_count; i++) {
1273                 if (pool->base.clock_sources[i] != NULL) {
1274                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1275                         pool->base.clock_sources[i] = NULL;
1276                 }
1277         }
1278
1279         if (pool->base.dp_clock_source != NULL) {
1280                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1281                 pool->base.dp_clock_source = NULL;
1282         }
1283
1284
1285         if (pool->base.abm != NULL)
1286                 dce_abm_destroy(&pool->base.abm);
1287
1288         if (pool->base.dmcu != NULL)
1289                 dce_dmcu_destroy(&pool->base.dmcu);
1290
1291         if (pool->base.dccg != NULL)
1292                 dcn_dccg_destroy(&pool->base.dccg);
1293
1294         if (pool->base.pp_smu != NULL)
1295                 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1296
1297 }
1298
1299 struct hubp *dcn20_hubp_create(
1300         struct dc_context *ctx,
1301         uint32_t inst)
1302 {
1303         struct dcn20_hubp *hubp2 =
1304                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1305
1306         if (!hubp2)
1307                 return NULL;
1308
1309         if (hubp2_construct(hubp2, ctx, inst,
1310                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1311                 return &hubp2->base;
1312
1313         BREAK_TO_DEBUGGER();
1314         kfree(hubp2);
1315         return NULL;
1316 }
1317
1318 static void get_pixel_clock_parameters(
1319         struct pipe_ctx *pipe_ctx,
1320         struct pixel_clk_params *pixel_clk_params)
1321 {
1322         const struct dc_stream_state *stream = pipe_ctx->stream;
1323         struct pipe_ctx *odm_pipe;
1324         int opp_cnt = 1;
1325
1326         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1327                 opp_cnt++;
1328
1329         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1330         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1331         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1332         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1333         /* TODO: un-hardcode*/
1334         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1335                 LINK_RATE_REF_FREQ_IN_KHZ;
1336         pixel_clk_params->flags.ENABLE_SS = 0;
1337         pixel_clk_params->color_depth =
1338                 stream->timing.display_color_depth;
1339         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1340         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1341
1342         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1343                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1344
1345         if (opp_cnt == 4)
1346                 pixel_clk_params->requested_pix_clk_100hz /= 4;
1347         else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1348                 pixel_clk_params->requested_pix_clk_100hz /= 2;
1349
1350         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1351                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1352
1353 }
1354
1355 static void build_clamping_params(struct dc_stream_state *stream)
1356 {
1357         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1358         stream->clamping.c_depth = stream->timing.display_color_depth;
1359         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1360 }
1361
1362 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1363 {
1364
1365         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1366
1367         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1368                 pipe_ctx->clock_source,
1369                 &pipe_ctx->stream_res.pix_clk_params,
1370                 &pipe_ctx->pll_settings);
1371
1372         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1373
1374         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1375                                         &pipe_ctx->stream->bit_depth_params);
1376         build_clamping_params(pipe_ctx->stream);
1377
1378         return DC_OK;
1379 }
1380
1381 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1382 {
1383         enum dc_status status = DC_OK;
1384         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1385
1386         /*TODO Seems unneeded anymore */
1387         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1388                         if (stream != NULL && old_context->streams[i] != NULL) {
1389                                  todo: shouldn't have to copy missing parameter here
1390                                 resource_build_bit_depth_reduction_params(stream,
1391                                                 &stream->bit_depth_params);
1392                                 stream->clamping.pixel_encoding =
1393                                                 stream->timing.pixel_encoding;
1394
1395                                 resource_build_bit_depth_reduction_params(stream,
1396                                                                 &stream->bit_depth_params);
1397                                 build_clamping_params(stream);
1398
1399                                 continue;
1400                         }
1401                 }
1402         */
1403
1404         if (!pipe_ctx)
1405                 return DC_ERROR_UNEXPECTED;
1406
1407
1408         status = build_pipe_hw_param(pipe_ctx);
1409
1410         return status;
1411 }
1412
1413 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1414
1415 static void acquire_dsc(struct resource_context *res_ctx,
1416                         const struct resource_pool *pool,
1417                         struct display_stream_compressor **dsc)
1418 {
1419         int i;
1420
1421         ASSERT(*dsc == NULL);
1422         *dsc = NULL;
1423
1424         /* Find first free DSC */
1425         for (i = 0; i < pool->res_cap->num_dsc; i++)
1426                 if (!res_ctx->is_dsc_acquired[i]) {
1427                         *dsc = pool->dscs[i];
1428                         res_ctx->is_dsc_acquired[i] = true;
1429                         break;
1430                 }
1431 }
1432
1433 static void release_dsc(struct resource_context *res_ctx,
1434                         const struct resource_pool *pool,
1435                         struct display_stream_compressor **dsc)
1436 {
1437         int i;
1438
1439         for (i = 0; i < pool->res_cap->num_dsc; i++)
1440                 if (pool->dscs[i] == *dsc) {
1441                         res_ctx->is_dsc_acquired[i] = false;
1442                         *dsc = NULL;
1443                         break;
1444                 }
1445 }
1446
1447 #endif
1448
1449
1450 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1451 static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
1452                 struct dc_state *dc_ctx,
1453                 struct dc_stream_state *dc_stream)
1454 {
1455         enum dc_status result = DC_OK;
1456         int i;
1457         const struct resource_pool *pool = dc->res_pool;
1458
1459         /* Get a DSC if required and available */
1460         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1461                 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1462
1463                 if (pipe_ctx->stream != dc_stream)
1464                         continue;
1465
1466                 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
1467
1468                 /* The number of DSCs can be less than the number of pipes */
1469                 if (!pipe_ctx->stream_res.dsc) {
1470                         dm_output_to_console("No DSCs available\n");
1471                         result = DC_NO_DSC_RESOURCE;
1472                 }
1473
1474                 break;
1475         }
1476
1477         return result;
1478 }
1479
1480
1481 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1482                 struct dc_state *new_ctx,
1483                 struct dc_stream_state *dc_stream)
1484 {
1485         struct pipe_ctx *pipe_ctx = NULL;
1486         int i;
1487
1488         for (i = 0; i < MAX_PIPES; i++) {
1489                 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1490                         pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1491
1492                         if (pipe_ctx->stream_res.dsc)
1493                                 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1494                 }
1495         }
1496
1497         if (!pipe_ctx)
1498                 return DC_ERROR_UNEXPECTED;
1499         else
1500                 return DC_OK;
1501 }
1502 #endif
1503
1504
1505 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1506 {
1507         enum dc_status result = DC_ERROR_UNEXPECTED;
1508
1509         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1510
1511         if (result == DC_OK)
1512                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1513
1514 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1515         /* Get a DSC if required and available */
1516         if (result == DC_OK && dc_stream->timing.flags.DSC)
1517                 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1518 #endif
1519
1520         if (result == DC_OK)
1521                 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1522
1523         return result;
1524 }
1525
1526
1527 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1528 {
1529         enum dc_status result = DC_OK;
1530
1531 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1532         result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1533 #endif
1534
1535         return result;
1536 }
1537
1538
1539 static void swizzle_to_dml_params(
1540                 enum swizzle_mode_values swizzle,
1541                 unsigned int *sw_mode)
1542 {
1543         switch (swizzle) {
1544         case DC_SW_LINEAR:
1545                 *sw_mode = dm_sw_linear;
1546                 break;
1547         case DC_SW_4KB_S:
1548                 *sw_mode = dm_sw_4kb_s;
1549                 break;
1550         case DC_SW_4KB_S_X:
1551                 *sw_mode = dm_sw_4kb_s_x;
1552                 break;
1553         case DC_SW_4KB_D:
1554                 *sw_mode = dm_sw_4kb_d;
1555                 break;
1556         case DC_SW_4KB_D_X:
1557                 *sw_mode = dm_sw_4kb_d_x;
1558                 break;
1559         case DC_SW_64KB_S:
1560                 *sw_mode = dm_sw_64kb_s;
1561                 break;
1562         case DC_SW_64KB_S_X:
1563                 *sw_mode = dm_sw_64kb_s_x;
1564                 break;
1565         case DC_SW_64KB_S_T:
1566                 *sw_mode = dm_sw_64kb_s_t;
1567                 break;
1568         case DC_SW_64KB_D:
1569                 *sw_mode = dm_sw_64kb_d;
1570                 break;
1571         case DC_SW_64KB_D_X:
1572                 *sw_mode = dm_sw_64kb_d_x;
1573                 break;
1574         case DC_SW_64KB_D_T:
1575                 *sw_mode = dm_sw_64kb_d_t;
1576                 break;
1577         case DC_SW_64KB_R_X:
1578                 *sw_mode = dm_sw_64kb_r_x;
1579                 break;
1580         case DC_SW_VAR_S:
1581                 *sw_mode = dm_sw_var_s;
1582                 break;
1583         case DC_SW_VAR_S_X:
1584                 *sw_mode = dm_sw_var_s_x;
1585                 break;
1586         case DC_SW_VAR_D:
1587                 *sw_mode = dm_sw_var_d;
1588                 break;
1589         case DC_SW_VAR_D_X:
1590                 *sw_mode = dm_sw_var_d_x;
1591                 break;
1592
1593         default:
1594                 ASSERT(0); /* Not supported */
1595                 break;
1596         }
1597 }
1598
1599 static bool dcn20_split_stream_for_odm(
1600                 struct resource_context *res_ctx,
1601                 const struct resource_pool *pool,
1602                 struct pipe_ctx *prev_odm_pipe,
1603                 struct pipe_ctx *next_odm_pipe)
1604 {
1605         int pipe_idx = next_odm_pipe->pipe_idx;
1606
1607         *next_odm_pipe = *prev_odm_pipe;
1608
1609         next_odm_pipe->pipe_idx = pipe_idx;
1610         next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1611         next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1612         next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1613         next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1614         next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1615         next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1616 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1617         next_odm_pipe->stream_res.dsc = NULL;
1618 #endif
1619         if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1620                 ASSERT(!next_odm_pipe->next_odm_pipe);
1621                 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1622                 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1623         }
1624         prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1625         next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1626         ASSERT(next_odm_pipe->top_pipe == NULL);
1627
1628         if (prev_odm_pipe->plane_state) {
1629                 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1630                 int new_width;
1631
1632                 /* HACTIVE halved for odm combine */
1633                 sd->h_active /= 2;
1634                 /* Calculate new vp and recout for left pipe */
1635                 /* Need at least 16 pixels width per side */
1636                 if (sd->recout.x + 16 >= sd->h_active)
1637                         return false;
1638                 new_width = sd->h_active - sd->recout.x;
1639                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1640                                 sd->ratios.horz, sd->recout.width - new_width));
1641                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1642                                 sd->ratios.horz_c, sd->recout.width - new_width));
1643                 sd->recout.width = new_width;
1644
1645                 /* Calculate new vp and recout for right pipe */
1646                 sd = &next_odm_pipe->plane_res.scl_data;
1647                 /* HACTIVE halved for odm combine */
1648                 sd->h_active /= 2;
1649                 /* Need at least 16 pixels width per side */
1650                 if (new_width <= 16)
1651                         return false;
1652                 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1653                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1654                                 sd->ratios.horz, sd->recout.width - new_width));
1655                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1656                                 sd->ratios.horz_c, sd->recout.width - new_width));
1657                 sd->recout.width = new_width;
1658                 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1659                                 sd->ratios.horz, sd->h_active - sd->recout.x));
1660                 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1661                                 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1662                 sd->recout.x = 0;
1663         }
1664         next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1665 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1666         if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1667                 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
1668                 ASSERT(next_odm_pipe->stream_res.dsc);
1669                 if (next_odm_pipe->stream_res.dsc == NULL)
1670                         return false;
1671         }
1672 #endif
1673
1674         return true;
1675 }
1676
1677 static void dcn20_split_stream_for_mpc(
1678                 struct resource_context *res_ctx,
1679                 const struct resource_pool *pool,
1680                 struct pipe_ctx *primary_pipe,
1681                 struct pipe_ctx *secondary_pipe)
1682 {
1683         int pipe_idx = secondary_pipe->pipe_idx;
1684         struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1685
1686         *secondary_pipe = *primary_pipe;
1687         secondary_pipe->bottom_pipe = sec_bot_pipe;
1688
1689         secondary_pipe->pipe_idx = pipe_idx;
1690         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1691         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1692         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1693         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1694         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1695         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1696 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1697         secondary_pipe->stream_res.dsc = NULL;
1698 #endif
1699         if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1700                 ASSERT(!secondary_pipe->bottom_pipe);
1701                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1702                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1703         }
1704         primary_pipe->bottom_pipe = secondary_pipe;
1705         secondary_pipe->top_pipe = primary_pipe;
1706
1707         ASSERT(primary_pipe->plane_state);
1708         resource_build_scaling_params(primary_pipe);
1709         resource_build_scaling_params(secondary_pipe);
1710 }
1711
1712 void dcn20_populate_dml_writeback_from_context(
1713                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1714 {
1715         int pipe_cnt, i;
1716
1717         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1718                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1719
1720                 if (!res_ctx->pipe_ctx[i].stream)
1721                         continue;
1722
1723                 /* Set writeback information */
1724                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1725                 pipes[pipe_cnt].dout.num_active_wb++;
1726                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1727                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1728                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1729                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1730                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1731                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1732                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1733                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1734                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1735                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1736                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1737                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1738                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1739                         else
1740                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1741                 } else
1742                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1743
1744                 pipe_cnt++;
1745         }
1746
1747 }
1748
1749 int dcn20_populate_dml_pipes_from_context(
1750                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1751 {
1752         int pipe_cnt, i;
1753         bool synchronized_vblank = true;
1754
1755         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1756                 if (!res_ctx->pipe_ctx[i].stream)
1757                         continue;
1758
1759                 if (pipe_cnt < 0) {
1760                         pipe_cnt = i;
1761                         continue;
1762                 }
1763                 if (!resource_are_streams_timing_synchronizable(
1764                                 res_ctx->pipe_ctx[pipe_cnt].stream,
1765                                 res_ctx->pipe_ctx[i].stream)) {
1766                         synchronized_vblank = false;
1767                         break;
1768                 }
1769         }
1770
1771         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1772                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1773                 int output_bpc;
1774
1775                 if (!res_ctx->pipe_ctx[i].stream)
1776                         continue;
1777                 /* todo:
1778                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1779                 pipes[pipe_cnt].pipe.src.dcc = 0;
1780                 pipes[pipe_cnt].pipe.src.vm = 0;*/
1781
1782 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1783                 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1784                 /* todo: rotation?*/
1785                 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1786 #endif
1787                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1788                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1789                         /* 1/2 vblank */
1790                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1791                                 (timing->v_total - timing->v_addressable
1792                                         - timing->v_border_top - timing->v_border_bottom) / 2;
1793                         /* 36 bytes dp, 32 hdmi */
1794                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1795                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1796                 }
1797                 pipes[pipe_cnt].pipe.src.dcc = false;
1798                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1799                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1800                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1801                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1802                                 - timing->h_addressable
1803                                 - timing->h_border_left
1804                                 - timing->h_border_right;
1805                 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1806                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1807                                 - timing->v_addressable
1808                                 - timing->v_border_top
1809                                 - timing->v_border_bottom;
1810                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1811                 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1812                 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1813                 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1814                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1815                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1816                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1817                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1818                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1819                 pipes[pipe_cnt].dout.dp_lanes = 4;
1820                 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1821                 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1822                 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
1823                                                         || res_ctx->pipe_ctx[i].next_odm_pipe;
1824                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1825                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1826                                 == res_ctx->pipe_ctx[i].plane_state)
1827                         pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1828                 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1829                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1830
1831                         while (first_pipe->prev_odm_pipe)
1832                                 first_pipe = first_pipe->prev_odm_pipe;
1833                         pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1834                 }
1835
1836                 switch (res_ctx->pipe_ctx[i].stream->signal) {
1837                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1838                 case SIGNAL_TYPE_DISPLAY_PORT:
1839                         pipes[pipe_cnt].dout.output_type = dm_dp;
1840                         break;
1841                 case SIGNAL_TYPE_EDP:
1842                         pipes[pipe_cnt].dout.output_type = dm_edp;
1843                         break;
1844                 case SIGNAL_TYPE_HDMI_TYPE_A:
1845                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1846                 case SIGNAL_TYPE_DVI_DUAL_LINK:
1847                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
1848                         break;
1849                 default:
1850                         /* In case there is no signal, set dp with 4 lanes to allow max config */
1851                         pipes[pipe_cnt].dout.output_type = dm_dp;
1852                         pipes[pipe_cnt].dout.dp_lanes = 4;
1853                 }
1854
1855                 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1856                 case COLOR_DEPTH_666:
1857                         output_bpc = 6;
1858                         break;
1859                 case COLOR_DEPTH_888:
1860                         output_bpc = 8;
1861                         break;
1862                 case COLOR_DEPTH_101010:
1863                         output_bpc = 10;
1864                         break;
1865                 case COLOR_DEPTH_121212:
1866                         output_bpc = 12;
1867                         break;
1868                 case COLOR_DEPTH_141414:
1869                         output_bpc = 14;
1870                         break;
1871                 case COLOR_DEPTH_161616:
1872                         output_bpc = 16;
1873                         break;
1874 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1875                 case COLOR_DEPTH_999:
1876                         output_bpc = 9;
1877                         break;
1878                 case COLOR_DEPTH_111111:
1879                         output_bpc = 11;
1880                         break;
1881 #endif
1882                 default:
1883                         output_bpc = 8;
1884                         break;
1885                 }
1886
1887                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1888                 case PIXEL_ENCODING_RGB:
1889                 case PIXEL_ENCODING_YCBCR444:
1890                         pipes[pipe_cnt].dout.output_format = dm_444;
1891                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1892                         break;
1893                 case PIXEL_ENCODING_YCBCR420:
1894                         pipes[pipe_cnt].dout.output_format = dm_420;
1895                         pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
1896                         break;
1897                 case PIXEL_ENCODING_YCBCR422:
1898                         if (true) /* todo */
1899                                 pipes[pipe_cnt].dout.output_format = dm_s422;
1900                         else
1901                                 pipes[pipe_cnt].dout.output_format = dm_n422;
1902                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1903                         break;
1904                 default:
1905                         pipes[pipe_cnt].dout.output_format = dm_444;
1906                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1907                 }
1908
1909                 /* todo: default max for now, until there is logic reflecting this in dc*/
1910                 pipes[pipe_cnt].dout.output_bpc = 12;
1911                 /*
1912                  * Use max cursor settings for calculations to minimize
1913                  * bw calculations due to cursor on/off
1914                  */
1915                 pipes[pipe_cnt].pipe.src.num_cursors = 2;
1916                 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1917                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1918                 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
1919                 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
1920
1921                 if (!res_ctx->pipe_ctx[i].plane_state) {
1922                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1923                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
1924                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1925                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1926                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1927                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1928                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1929                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1930                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1931                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
1932                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1933                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1934                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1935                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
1936                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1937                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1938                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1939                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1940                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1941                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1942                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1943                         pipes[pipe_cnt].pipe.src.is_hsplit = 0;
1944                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1945                         pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
1946                         pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
1947                 } else {
1948                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1949                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1950
1951                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1952                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
1953                                         && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1954                                         || (res_ctx->pipe_ctx[i].top_pipe
1955                                         && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
1956                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1957                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1958                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1959                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1960                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1961                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1962                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1963                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1964                         if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1965                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1966                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1967                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1968                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1969                         } else {
1970                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1971                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1972                         }
1973                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1974                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1975                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1976                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1977                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1978                         if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
1979                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1980                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
1981                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1982                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
1983                         } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
1984                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1985                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
1986                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1987                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
1988                         }
1989
1990                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1991                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1992                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1993                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1994                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1995                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1996                                         scl->ratios.vert.value != dc_fixpt_one.value
1997                                         || scl->ratios.horz.value != dc_fixpt_one.value
1998                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
1999                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2000                                         || dc->debug.always_scale; /*support always scale*/
2001                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2002                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2003                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2004                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2005
2006                         pipes[pipe_cnt].pipe.src.macro_tile_size =
2007                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2008                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2009                                         &pipes[pipe_cnt].pipe.src.sw_mode);
2010
2011                         switch (pln->format) {
2012                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2013                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2014                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2015                                 break;
2016                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2017                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2018                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2019                                 break;
2020                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2021                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2022                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2023                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2024                                 break;
2025                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2026                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2027                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2028                                 break;
2029                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2030                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2031                                 break;
2032                         default:
2033                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2034                                 break;
2035                         }
2036                 }
2037
2038                 pipe_cnt++;
2039         }
2040
2041         /* populate writeback information */
2042         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2043
2044         return pipe_cnt;
2045 }
2046
2047 unsigned int dcn20_calc_max_scaled_time(
2048                 unsigned int time_per_pixel,
2049                 enum mmhubbub_wbif_mode mode,
2050                 unsigned int urgent_watermark)
2051 {
2052         unsigned int time_per_byte = 0;
2053         unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2054         unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2055         unsigned int small_free_entry, max_free_entry;
2056         unsigned int buf_lh_capability;
2057         unsigned int max_scaled_time;
2058
2059         if (mode == PACKED_444) /* packed mode */
2060                 time_per_byte = time_per_pixel/4;
2061         else if (mode == PLANAR_420_8BPC)
2062                 time_per_byte  = time_per_pixel;
2063         else if (mode == PLANAR_420_10BPC) /* p010 */
2064                 time_per_byte  = time_per_pixel * 819/1024;
2065
2066         if (time_per_byte == 0)
2067                 time_per_byte = 1;
2068
2069         small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2070         max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2071         buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2072         max_scaled_time   = buf_lh_capability - urgent_watermark;
2073         return max_scaled_time;
2074 }
2075
2076 void dcn20_set_mcif_arb_params(
2077                 struct dc *dc,
2078                 struct dc_state *context,
2079                 display_e2e_pipe_params_st *pipes,
2080                 int pipe_cnt)
2081 {
2082         enum mmhubbub_wbif_mode wbif_mode;
2083         struct mcif_arb_params *wb_arb_params;
2084         int i, j, k, dwb_pipe;
2085
2086         /* Writeback MCIF_WB arbitration parameters */
2087         dwb_pipe = 0;
2088         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2089
2090                 if (!context->res_ctx.pipe_ctx[i].stream)
2091                         continue;
2092
2093                 for (j = 0; j < MAX_DWB_PIPES; j++) {
2094                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2095                                 continue;
2096
2097                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2098                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2099
2100                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2101                                 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2102                                         wbif_mode = PLANAR_420_8BPC;
2103                                 else
2104                                         wbif_mode = PLANAR_420_10BPC;
2105                         } else
2106                                 wbif_mode = PACKED_444;
2107
2108                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2109                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2110                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2111                         }
2112                         wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2113                         wb_arb_params->slice_lines = 32;
2114                         wb_arb_params->arbitration_slice = 2;
2115                         wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2116                                 wbif_mode,
2117                                 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2118
2119                         dwb_pipe++;
2120
2121                         if (dwb_pipe >= MAX_DWB_PIPES)
2122                                 return;
2123                 }
2124                 if (dwb_pipe >= MAX_DWB_PIPES)
2125                         return;
2126         }
2127 }
2128
2129 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2130 static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2131 {
2132         int i;
2133
2134         /* Validate DSC config, dsc count validation is already done */
2135         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2136                 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2137                 struct dc_stream_state *stream = pipe_ctx->stream;
2138                 struct dsc_config dsc_cfg;
2139                 struct pipe_ctx *odm_pipe;
2140                 int opp_cnt = 1;
2141
2142                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2143                         opp_cnt++;
2144
2145                 /* Only need to validate top pipe */
2146                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2147                         continue;
2148
2149                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2150                                 + stream->timing.h_border_right) / opp_cnt;
2151                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2152                                 + stream->timing.v_border_bottom;
2153                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2154                 dsc_cfg.color_depth = stream->timing.display_color_depth;
2155                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2156                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2157
2158                 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2159                         return false;
2160         }
2161         return true;
2162 }
2163 #endif
2164
2165 static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2166                 struct resource_context *res_ctx,
2167                 const struct resource_pool *pool,
2168                 const struct pipe_ctx *primary_pipe)
2169 {
2170         struct pipe_ctx *secondary_pipe = NULL;
2171
2172         if (dc && primary_pipe) {
2173                 int j;
2174                 int preferred_pipe_idx = 0;
2175
2176                 /* first check the prev dc state:
2177                  * if this primary pipe has a bottom pipe in prev. state
2178                  * and if the bottom pipe is still available (which it should be),
2179                  * pick that pipe as secondary
2180                  * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2181                  * check in else case.
2182                  */
2183                 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2184                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2185                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2186                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2187                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2188                         }
2189                 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2190                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2191                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2192                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2193                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2194                         }
2195                 }
2196
2197                 /*
2198                  * if this primary pipe does not have a bottom pipe in prev. state
2199                  * start backward and find a pipe that did not used to be a bottom pipe in
2200                  * prev. dc state. This way we make sure we keep the same assignment as
2201                  * last state and will not have to reprogram every pipe
2202                  */
2203                 if (secondary_pipe == NULL) {
2204                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2205                                 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) {
2206                                         preferred_pipe_idx = j;
2207
2208                                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2209                                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2210                                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2211                                                 break;
2212                                         }
2213                                 }
2214                         }
2215                 }
2216                 /*
2217                  * We should never hit this assert unless assignments are shuffled around
2218                  * if this happens we will prob. hit a vsync tdr
2219                  */
2220                 ASSERT(secondary_pipe);
2221                 /*
2222                  * search backwards for the second pipe to keep pipe
2223                  * assignment more consistent
2224                  */
2225                 if (secondary_pipe == NULL) {
2226                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2227                                 preferred_pipe_idx = j;
2228
2229                                 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2230                                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2231                                         secondary_pipe->pipe_idx = preferred_pipe_idx;
2232                                         break;
2233                                 }
2234                         }
2235                 }
2236         }
2237
2238         return secondary_pipe;
2239 }
2240
2241 bool dcn20_fast_validate_bw(
2242                 struct dc *dc,
2243                 struct dc_state *context,
2244                 display_e2e_pipe_params_st *pipes,
2245                 int *pipe_cnt_out,
2246                 int *pipe_split_from,
2247                 int *vlevel_out)
2248 {
2249         bool out = false;
2250
2251         int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
2252         bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
2253         bool force_split = false;
2254 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2255         bool failed_non_odm_dsc = false;
2256 #endif
2257         int split_threshold = dc->res_pool->pipe_count / 2;
2258         bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
2259
2260
2261         ASSERT(pipes);
2262         if (!pipes)
2263                 return false;
2264
2265         /* merge previously split odm pipes since mode support needs to make the decision */
2266         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2267                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2268                 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2269
2270                 if (pipe->prev_odm_pipe)
2271                         continue;
2272
2273                 pipe->next_odm_pipe = NULL;
2274                 while (odm_pipe) {
2275                         struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2276
2277                         odm_pipe->plane_state = NULL;
2278                         odm_pipe->stream = NULL;
2279                         odm_pipe->top_pipe = NULL;
2280                         odm_pipe->bottom_pipe = NULL;
2281                         odm_pipe->prev_odm_pipe = NULL;
2282                         odm_pipe->next_odm_pipe = NULL;
2283 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2284                         if (odm_pipe->stream_res.dsc)
2285                                 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2286 #endif
2287                         /* Clear plane_res and stream_res */
2288                         memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2289                         memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2290                         odm_pipe = next_odm_pipe;
2291                 }
2292                 if (pipe->plane_state)
2293                         resource_build_scaling_params(pipe);
2294         }
2295
2296         /* merge previously mpc split pipes since mode support needs to make the decision */
2297         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2298                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2299                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2300
2301                 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2302                         continue;
2303
2304                 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2305                 if (hsplit_pipe->bottom_pipe)
2306                         hsplit_pipe->bottom_pipe->top_pipe = pipe;
2307                 hsplit_pipe->plane_state = NULL;
2308                 hsplit_pipe->stream = NULL;
2309                 hsplit_pipe->top_pipe = NULL;
2310                 hsplit_pipe->bottom_pipe = NULL;
2311
2312                 /* Clear plane_res and stream_res */
2313                 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2314                 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2315                 if (pipe->plane_state)
2316                         resource_build_scaling_params(pipe);
2317         }
2318
2319         if (dc->res_pool->funcs->populate_dml_pipes)
2320                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2321                         &context->res_ctx, pipes);
2322         else
2323                 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2324                         &context->res_ctx, pipes);
2325
2326         *pipe_cnt_out = pipe_cnt;
2327
2328         if (!pipe_cnt) {
2329                 out = true;
2330                 goto validate_out;
2331         }
2332
2333         context->bw_ctx.dml.ip.odm_capable = 0;
2334
2335         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2336
2337         context->bw_ctx.dml.ip.odm_capable = odm_capable;
2338
2339 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2340         /* 1 dsc per stream dsc validation */
2341         if (vlevel <= context->bw_ctx.dml.soc.num_states)
2342                 if (!dcn20_validate_dsc(dc, context)) {
2343                         failed_non_odm_dsc = true;
2344                         vlevel = context->bw_ctx.dml.soc.num_states + 1;
2345                 }
2346 #endif
2347
2348         if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
2349                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2350
2351         if (vlevel > context->bw_ctx.dml.soc.num_states)
2352                 goto validate_fail;
2353
2354         if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
2355                 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
2356                 context->commit_hints.full_update_needed = true;
2357
2358         /*initialize pipe_just_split_from to invalid idx*/
2359         for (i = 0; i < MAX_PIPES; i++)
2360                 pipe_split_from[i] = -1;
2361
2362         /* Single display only conditionals get set here */
2363         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2364                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2365                 bool exit_loop = false;
2366
2367                 if (!pipe->stream || pipe->top_pipe)
2368                         continue;
2369
2370                 if (dc->debug.force_single_disp_pipe_split) {
2371                         if (!force_split)
2372                                 force_split = true;
2373                         else {
2374                                 force_split = false;
2375                                 exit_loop = true;
2376                         }
2377                 }
2378                 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2379                         if (avoid_split)
2380                                 avoid_split = false;
2381                         else {
2382                                 avoid_split = true;
2383                                 exit_loop = true;
2384                         }
2385                 }
2386                 if (exit_loop)
2387                         break;
2388         }
2389
2390         if (context->stream_count > split_threshold)
2391                 avoid_split = true;
2392
2393         vlevel_unsplit = vlevel;
2394         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2395                 if (!context->res_ctx.pipe_ctx[i].stream)
2396                         continue;
2397                 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
2398                         if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
2399                                 break;
2400                 pipe_idx++;
2401         }
2402
2403         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2404                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2405                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2406                 bool need_split = true;
2407                 bool need_split3d;
2408
2409                 if (!pipe->stream || pipe_split_from[i] >= 0)
2410                         continue;
2411
2412                 pipe_idx++;
2413
2414                 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2415                         force_split = true;
2416                         context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
2417                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2418                 }
2419                 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2420                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2421                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2422                         hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2423                         ASSERT(hsplit_pipe);
2424                         if (!dcn20_split_stream_for_odm(
2425                                         &context->res_ctx, dc->res_pool,
2426                                         pipe, hsplit_pipe))
2427                                 goto validate_fail;
2428                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2429                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2430                 }
2431
2432                 if (!pipe->plane_state)
2433                         continue;
2434                 /* Skip 2nd half of already split pipe */
2435                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2436                         continue;
2437
2438                 need_split3d = ((pipe->stream->view_format ==
2439                                 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2440                                 pipe->stream->view_format ==
2441                                 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2442                                 (pipe->stream->timing.timing_3d_format ==
2443                                 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2444                                  pipe->stream->timing.timing_3d_format ==
2445                                 TIMING_3D_FORMAT_SIDE_BY_SIDE));
2446
2447                 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
2448                         need_split = false;
2449                         vlevel = vlevel_unsplit;
2450                         context->bw_ctx.dml.vba.maxMpcComb = 0;
2451                 } else
2452                         need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
2453
2454                 /* We do not support mpo + odm at the moment */
2455                 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2456                                 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2457                         goto validate_fail;
2458
2459                 if (need_split3d || need_split || force_split) {
2460                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2461                                 /* pipe not split previously needs split */
2462                                 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2463                                 ASSERT(hsplit_pipe || force_split);
2464                                 if (!hsplit_pipe)
2465                                         continue;
2466
2467                                 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2468                                         if (!dcn20_split_stream_for_odm(
2469                                                         &context->res_ctx, dc->res_pool,
2470                                                         pipe, hsplit_pipe))
2471                                                 goto validate_fail;
2472                                 } else
2473                                         dcn20_split_stream_for_mpc(
2474                                                 &context->res_ctx, dc->res_pool,
2475                                                 pipe, hsplit_pipe);
2476                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2477                         }
2478                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2479                         /* merge should already have been done */
2480                         ASSERT(0);
2481                 }
2482         }
2483 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2484         /* Actual dsc count per stream dsc validation*/
2485         if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
2486                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2487                                 DML_FAIL_DSC_VALIDATION_FAILURE;
2488                 goto validate_fail;
2489         }
2490 #endif
2491
2492         *vlevel_out = vlevel;
2493
2494         out = true;
2495         goto validate_out;
2496
2497 validate_fail:
2498         out = false;
2499
2500 validate_out:
2501         return out;
2502 }
2503
2504 void dcn20_calculate_wm(
2505                 struct dc *dc, struct dc_state *context,
2506                 display_e2e_pipe_params_st *pipes,
2507                 int *out_pipe_cnt,
2508                 int *pipe_split_from,
2509                 int vlevel)
2510 {
2511         int pipe_cnt, i, pipe_idx;
2512
2513         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2514                 if (!context->res_ctx.pipe_ctx[i].stream)
2515                         continue;
2516
2517                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2518                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2519
2520                 if (pipe_split_from[i] < 0) {
2521                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2522                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2523                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2524                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2525                                                 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2526                         else
2527                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2528                         pipe_idx++;
2529                 } else {
2530                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2531                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2532                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2533                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2534                                                 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
2535                         else
2536                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2537                 }
2538
2539                 if (dc->config.forced_clocks) {
2540                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2541                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2542                 }
2543                 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2544                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2545                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2546                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2547
2548                 pipe_cnt++;
2549         }
2550
2551         if (pipe_cnt != pipe_idx) {
2552                 if (dc->res_pool->funcs->populate_dml_pipes)
2553                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2554                                 &context->res_ctx, pipes);
2555                 else
2556                         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2557                                 &context->res_ctx, pipes);
2558         }
2559
2560         *out_pipe_cnt = pipe_cnt;
2561
2562         pipes[0].clks_cfg.voltage = vlevel;
2563         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2564         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2565
2566         /* only pipe 0 is read for voltage and dcf/soc clocks */
2567         if (vlevel < 1) {
2568                 pipes[0].clks_cfg.voltage = 1;
2569                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2570                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2571         }
2572         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2573         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2574         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2575         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2576         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2577
2578         if (vlevel < 2) {
2579                 pipes[0].clks_cfg.voltage = 2;
2580                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2581                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2582         }
2583         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2584         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2585         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2586         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2587         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2588
2589         if (vlevel < 3) {
2590                 pipes[0].clks_cfg.voltage = 3;
2591                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2592                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2593         }
2594         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2595         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2596         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2597         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2598         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2599
2600         pipes[0].clks_cfg.voltage = vlevel;
2601         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2602         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2603         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2604         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2605         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2606         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2607         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2608 }
2609
2610 void dcn20_calculate_dlg_params(
2611                 struct dc *dc, struct dc_state *context,
2612                 display_e2e_pipe_params_st *pipes,
2613                 int pipe_cnt,
2614                 int vlevel)
2615 {
2616         int i, j, pipe_idx, pipe_idx_unsplit;
2617         bool visited[MAX_PIPES] = { 0 };
2618
2619         /* Writeback MCIF_WB arbitration parameters */
2620         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2621
2622         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2623         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2624         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
2625         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
2626         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2627         context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
2628         context->bw_ctx.bw.dcn.clk.p_state_change_support =
2629                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2630                                                         != dm_dram_clock_change_unsupported;
2631         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2632
2633         /*
2634          * An artifact of dml pipe split/odm is that pipes get merged back together for
2635          * calculation. Therefore we need to only extract for first pipe in ascending index order
2636          * and copy into the other split half.
2637          */
2638         for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2639                 if (!context->res_ctx.pipe_ctx[i].stream)
2640                         continue;
2641
2642                 if (!visited[pipe_idx]) {
2643                         display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;
2644                         display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;
2645
2646                         dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2647                         dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2648                         dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2649                         dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2650                         /*
2651                          * j iterates inside pipes array, unlike i which iterates inside
2652                          * pipe_ctx array
2653                          */
2654                         if (src->is_hsplit)
2655                                 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2656                                         display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2657                                         display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2658
2659                                         if (src_j->is_hsplit && !visited[j]
2660                                                         && src->hsplit_grp == src_j->hsplit_grp) {
2661                                                 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2662                                                 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2663                                                 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2664                                                 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2665                                                 visited[j] = true;
2666                                         }
2667                                 }
2668                         visited[pipe_idx] = true;
2669                         pipe_idx_unsplit++;
2670                 }
2671                 pipe_idx++;
2672         }
2673
2674         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2675                 if (!context->res_ctx.pipe_ctx[i].stream)
2676                         continue;
2677                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2678                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2679                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2680                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2681                 ASSERT(visited[pipe_idx]);
2682                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2683                 pipe_idx++;
2684         }
2685         /*save a original dppclock copy*/
2686         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2687         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
2688         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2689         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
2690
2691         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2692                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2693
2694                 if (!context->res_ctx.pipe_ctx[i].stream)
2695                         continue;
2696
2697                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2698                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2699                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
2700                                 pipes,
2701                                 pipe_cnt,
2702                                 pipe_idx,
2703                                 cstate_en,
2704                                 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2705                                 false, false, false);
2706
2707                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2708                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2709                                 pipes[pipe_idx].pipe);
2710                 pipe_idx++;
2711         }
2712 }
2713
2714 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
2715                 bool fast_validate)
2716 {
2717         bool out = false;
2718
2719         BW_VAL_TRACE_SETUP();
2720
2721         int vlevel = 0;
2722         int pipe_split_from[MAX_PIPES];
2723         int pipe_cnt = 0;
2724         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2725         DC_LOGGER_INIT(dc->ctx->logger);
2726
2727         BW_VAL_TRACE_COUNT();
2728
2729         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2730
2731         if (pipe_cnt == 0)
2732                 goto validate_out;
2733
2734         if (!out)
2735                 goto validate_fail;
2736
2737         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2738
2739         if (fast_validate) {
2740                 BW_VAL_TRACE_SKIP(fast);
2741                 goto validate_out;
2742         }
2743
2744         dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2745         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2746
2747         BW_VAL_TRACE_END_WATERMARKS();
2748
2749         goto validate_out;
2750
2751 validate_fail:
2752         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2753                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2754
2755         BW_VAL_TRACE_SKIP(fail);
2756         out = false;
2757
2758 validate_out:
2759         kfree(pipes);
2760
2761         BW_VAL_TRACE_FINISH();
2762
2763         return out;
2764 }
2765
2766
2767 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2768                 bool fast_validate)
2769 {
2770         bool voltage_supported = false;
2771         bool full_pstate_supported = false;
2772         bool dummy_pstate_supported = false;
2773         double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2774
2775         if (fast_validate)
2776                 return dcn20_validate_bandwidth_internal(dc, context, true);
2777
2778
2779         // Best case, we support full UCLK switch latency
2780         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2781         full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2782
2783         if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2784                 (voltage_supported && full_pstate_supported)) {
2785                 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2786                 goto restore_dml_state;
2787         }
2788
2789         // Fallback: Try to only support G6 temperature read latency
2790         context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2791
2792         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2793         dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2794
2795         if (voltage_supported && dummy_pstate_supported) {
2796                 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2797                 goto restore_dml_state;
2798         }
2799
2800         // ERROR: fallback is supposed to always work.
2801         ASSERT(false);
2802
2803 restore_dml_state:
2804         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2805         context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2806
2807         return voltage_supported;
2808 }
2809
2810 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2811                 struct dc_state *state,
2812                 const struct resource_pool *pool,
2813                 struct dc_stream_state *stream)
2814 {
2815         struct resource_context *res_ctx = &state->res_ctx;
2816         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2817         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2818
2819         if (!head_pipe)
2820                 ASSERT(0);
2821
2822         if (!idle_pipe)
2823                 return NULL;
2824
2825         idle_pipe->stream = head_pipe->stream;
2826         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2827         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2828
2829         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2830         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2831         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2832         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2833
2834         return idle_pipe;
2835 }
2836
2837 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2838                 const struct dc_dcc_surface_param *input,
2839                 struct dc_surface_dcc_cap *output)
2840 {
2841         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2842                         dc->res_pool->hubbub,
2843                         input,
2844                         output);
2845 }
2846
2847 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2848 {
2849         struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2850
2851         destruct(dcn20_pool);
2852         kfree(dcn20_pool);
2853         *pool = NULL;
2854 }
2855
2856
2857 static struct dc_cap_funcs cap_funcs = {
2858         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2859 };
2860
2861
2862 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2863 {
2864         enum dc_status result = DC_OK;
2865
2866         enum surface_pixel_format surf_pix_format = plane_state->format;
2867         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2868
2869         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2870
2871         if (bpp == 64)
2872                 swizzle = DC_SW_64KB_D;
2873         else
2874                 swizzle = DC_SW_64KB_S;
2875
2876         plane_state->tiling_info.gfx9.swizzle = swizzle;
2877         return result;
2878 }
2879
2880 static struct resource_funcs dcn20_res_pool_funcs = {
2881         .destroy = dcn20_destroy_resource_pool,
2882         .link_enc_create = dcn20_link_encoder_create,
2883         .validate_bandwidth = dcn20_validate_bandwidth,
2884         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2885         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2886         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2887         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2888         .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
2889         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
2890         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
2891 };
2892
2893 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2894 {
2895         int i;
2896         uint32_t pipe_count = pool->res_cap->num_dwb;
2897
2898         ASSERT(pipe_count > 0);
2899
2900         for (i = 0; i < pipe_count; i++) {
2901                 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2902                                                     GFP_KERNEL);
2903
2904                 if (!dwbc20) {
2905                         dm_error("DC: failed to create dwbc20!\n");
2906                         return false;
2907                 }
2908                 dcn20_dwbc_construct(dwbc20, ctx,
2909                                 &dwbc20_regs[i],
2910                                 &dwbc20_shift,
2911                                 &dwbc20_mask,
2912                                 i);
2913                 pool->dwbc[i] = &dwbc20->base;
2914         }
2915         return true;
2916 }
2917
2918 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2919 {
2920         int i;
2921         uint32_t pipe_count = pool->res_cap->num_dwb;
2922
2923         ASSERT(pipe_count > 0);
2924
2925         for (i = 0; i < pipe_count; i++) {
2926                 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2927                                                     GFP_KERNEL);
2928
2929                 if (!mcif_wb20) {
2930                         dm_error("DC: failed to create mcif_wb20!\n");
2931                         return false;
2932                 }
2933
2934                 dcn20_mmhubbub_construct(mcif_wb20, ctx,
2935                                 &mcif_wb20_regs[i],
2936                                 &mcif_wb20_shift,
2937                                 &mcif_wb20_mask,
2938                                 i);
2939
2940                 pool->mcif_wb[i] = &mcif_wb20->base;
2941         }
2942         return true;
2943 }
2944
2945 struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2946 {
2947         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
2948
2949         if (!pp_smu)
2950                 return pp_smu;
2951
2952         dm_pp_get_funcs(ctx, pp_smu);
2953
2954         if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2955                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2956
2957         return pp_smu;
2958 }
2959
2960 void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2961 {
2962         if (pp_smu && *pp_smu) {
2963                 kfree(*pp_smu);
2964                 *pp_smu = NULL;
2965         }
2966 }
2967
2968 static void cap_soc_clocks(
2969                 struct _vcs_dpi_soc_bounding_box_st *bb,
2970                 struct pp_smu_nv_clock_table max_clocks)
2971 {
2972         int i;
2973
2974         // First pass - cap all clocks higher than the reported max
2975         for (i = 0; i < bb->num_states; i++) {
2976                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
2977                                 && max_clocks.dcfClockInKhz != 0)
2978                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
2979
2980                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
2981                                                 && max_clocks.uClockInKhz != 0)
2982                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2983
2984                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
2985                                                 && max_clocks.fabricClockInKhz != 0)
2986                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
2987
2988                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
2989                                                 && max_clocks.displayClockInKhz != 0)
2990                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
2991
2992                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
2993                                                 && max_clocks.dppClockInKhz != 0)
2994                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
2995
2996                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
2997                                                 && max_clocks.phyClockInKhz != 0)
2998                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
2999
3000                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3001                                                 && max_clocks.socClockInKhz != 0)
3002                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3003
3004                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3005                                                 && max_clocks.dscClockInKhz != 0)
3006                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3007         }
3008
3009         // Second pass - remove all duplicate clock states
3010         for (i = bb->num_states - 1; i > 1; i--) {
3011                 bool duplicate = true;
3012
3013                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3014                         duplicate = false;
3015                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3016                         duplicate = false;
3017                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3018                         duplicate = false;
3019                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3020                         duplicate = false;
3021                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3022                         duplicate = false;
3023                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3024                         duplicate = false;
3025                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3026                         duplicate = false;
3027                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3028                         duplicate = false;
3029
3030                 if (duplicate)
3031                         bb->num_states--;
3032         }
3033 }
3034
3035 static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3036                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3037 {
3038         struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
3039         int i;
3040         int num_calculated_states = 0;
3041         int min_dcfclk = 0;
3042
3043         if (num_states == 0)
3044                 return;
3045
3046         if (dc->bb_overrides.min_dcfclk_mhz > 0)
3047                 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3048         else
3049                 // Accounting for SOC/DCF relationship, we can go as high as
3050                 // 506Mhz in Vmin.  We need to code 507 since SMU will round down to 506.
3051                 min_dcfclk = 507;
3052
3053         for (i = 0; i < num_states; i++) {
3054                 int min_fclk_required_by_uclk;
3055                 calculated_states[i].state = i;
3056                 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3057
3058                 // FCLK:UCLK ratio is 1.08
3059                 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
3060
3061                 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3062                                 min_dcfclk : min_fclk_required_by_uclk;
3063
3064                 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3065                                 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3066
3067                 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3068                                 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3069
3070                 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3071                 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3072                 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3073
3074                 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3075
3076                 num_calculated_states++;
3077         }
3078
3079         calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3080         calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3081         calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3082
3083         memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3084         bb->num_states = num_calculated_states;
3085
3086         // Duplicate the last state, DML always an extra state identical to max state to work
3087         memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3088         bb->clock_limits[num_calculated_states].state = bb->num_states;
3089 }
3090
3091 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3092 {
3093         kernel_fpu_begin();
3094         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3095                         && dc->bb_overrides.sr_exit_time_ns) {
3096                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3097         }
3098
3099         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3100                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3101                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3102                 bb->sr_enter_plus_exit_time_us =
3103                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3104         }
3105
3106         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3107                         && dc->bb_overrides.urgent_latency_ns) {
3108                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3109         }
3110
3111         if ((int)(bb->dram_clock_change_latency_us * 1000)
3112                                 != dc->bb_overrides.dram_clock_change_latency_ns
3113                         && dc->bb_overrides.dram_clock_change_latency_ns) {
3114                 bb->dram_clock_change_latency_us =
3115                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3116         }
3117         kernel_fpu_end();
3118 }
3119
3120 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3121         uint32_t hw_internal_rev)
3122 {
3123         if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3124                 return &dcn2_0_nv12_soc;
3125
3126         return &dcn2_0_soc;
3127 }
3128
3129 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3130         uint32_t hw_internal_rev)
3131 {
3132         /* NV12 and NV10 */
3133         return &dcn2_0_ip;
3134 }
3135
3136 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3137 {
3138         return DML_PROJECT_NAVI10v2;
3139 }
3140
3141 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3142 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3143
3144 static bool init_soc_bounding_box(struct dc *dc,
3145                                   struct dcn20_resource_pool *pool)
3146 {
3147         const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
3148         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3149                         get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3150         struct _vcs_dpi_ip_params_st *loaded_ip =
3151                         get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3152
3153         DC_LOGGER_INIT(dc->ctx->logger);
3154
3155         if (!bb && !SOC_BOUNDING_BOX_VALID) {
3156                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3157                 return false;
3158         }
3159
3160         if (bb && !SOC_BOUNDING_BOX_VALID) {
3161                 int i;
3162
3163                 dcn2_0_nv12_soc.sr_exit_time_us =
3164                                 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
3165                 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
3166                                 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
3167                 dcn2_0_nv12_soc.urgent_latency_us =
3168                                 fixed16_to_double_to_cpu(bb->urgent_latency_us);
3169                 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
3170                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
3171                 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
3172                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
3173                 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
3174                                 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
3175                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
3176                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
3177                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
3178                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
3179                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
3180                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
3181                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
3182                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
3183                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
3184                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
3185                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
3186                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
3187                 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
3188                                 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
3189                 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
3190                                 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
3191                 dcn2_0_nv12_soc.writeback_latency_us =
3192                                 fixed16_to_double_to_cpu(bb->writeback_latency_us);
3193                 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
3194                                 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
3195                 dcn2_0_nv12_soc.max_request_size_bytes =
3196                                 le32_to_cpu(bb->max_request_size_bytes);
3197                 dcn2_0_nv12_soc.dram_channel_width_bytes =
3198                                 le32_to_cpu(bb->dram_channel_width_bytes);
3199                 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
3200                                 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3201                 dcn2_0_nv12_soc.dcn_downspread_percent =
3202                                 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3203                 dcn2_0_nv12_soc.downspread_percent =
3204                                 fixed16_to_double_to_cpu(bb->downspread_percent);
3205                 dcn2_0_nv12_soc.dram_page_open_time_ns =
3206                                 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3207                 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
3208                                 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3209                 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
3210                                 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3211                 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
3212                                 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3213                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
3214                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3215                 dcn2_0_nv12_soc.channel_interleave_bytes =
3216                                 le32_to_cpu(bb->channel_interleave_bytes);
3217                 dcn2_0_nv12_soc.num_banks =
3218                                 le32_to_cpu(bb->num_banks);
3219                 dcn2_0_nv12_soc.num_chans =
3220                                 le32_to_cpu(bb->num_chans);
3221                 dcn2_0_nv12_soc.vmm_page_size_bytes =
3222                                 le32_to_cpu(bb->vmm_page_size_bytes);
3223                 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3224                                 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3225                 // HACK!! Lower uclock latency switch time so we don't switch
3226                 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3227                 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
3228                                 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3229                 dcn2_0_nv12_soc.return_bus_width_bytes =
3230                                 le32_to_cpu(bb->return_bus_width_bytes);
3231                 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
3232                                 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3233                 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
3234                                 le32_to_cpu(bb->xfc_bus_transport_time_us);
3235                 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
3236                                 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3237                 dcn2_0_nv12_soc.use_urgent_burst_bw =
3238                                 le32_to_cpu(bb->use_urgent_burst_bw);
3239                 dcn2_0_nv12_soc.num_states =
3240                                 le32_to_cpu(bb->num_states);
3241
3242                 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3243                         dcn2_0_nv12_soc.clock_limits[i].state =
3244                                         le32_to_cpu(bb->clock_limits[i].state);
3245                         dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
3246                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3247                         dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
3248                                         fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3249                         dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
3250                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3251                         dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
3252                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3253                         dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
3254                                         fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3255                         dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
3256                                         fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3257                         dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
3258                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3259                         dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
3260                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3261                 }
3262         }
3263
3264         if (pool->base.pp_smu) {
3265                 struct pp_smu_nv_clock_table max_clocks = {0};
3266                 unsigned int uclk_states[8] = {0};
3267                 unsigned int num_states = 0;
3268                 enum pp_smu_status status;
3269                 bool clock_limits_available = false;
3270                 bool uclk_states_available = false;
3271
3272                 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3273                         status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3274                                 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3275
3276                         uclk_states_available = (status == PP_SMU_RESULT_OK);
3277                 }
3278
3279                 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3280                         status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3281                                         (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3282                         /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3283                          */
3284                         if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3285                                 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3286                         clock_limits_available = (status == PP_SMU_RESULT_OK);
3287                 }
3288
3289                 if (clock_limits_available && uclk_states_available && num_states)
3290                         update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3291                 else if (clock_limits_available)
3292                         cap_soc_clocks(loaded_bb, max_clocks);
3293         }
3294
3295         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3296         loaded_ip->max_num_dpp = pool->base.pipe_count;
3297         patch_bounding_box(dc, loaded_bb);
3298
3299         return true;
3300 }
3301
3302 static bool construct(
3303         uint8_t num_virtual_links,
3304         struct dc *dc,
3305         struct dcn20_resource_pool *pool)
3306 {
3307         int i;
3308         struct dc_context *ctx = dc->ctx;
3309         struct irq_service_init_data init_data;
3310         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3311                         get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3312         struct _vcs_dpi_ip_params_st *loaded_ip =
3313                         get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3314         enum dml_project dml_project_version =
3315                         get_dml_project_version(ctx->asic_id.hw_internal_rev);
3316
3317         ctx->dc_bios->regs = &bios_regs;
3318         pool->base.funcs = &dcn20_res_pool_funcs;
3319
3320         if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3321                 pool->base.res_cap = &res_cap_nv14;
3322                 pool->base.pipe_count = 5;
3323                 pool->base.mpcc_count = 5;
3324         } else {
3325                 pool->base.res_cap = &res_cap_nv10;
3326                 pool->base.pipe_count = 6;
3327                 pool->base.mpcc_count = 6;
3328         }
3329         /*************************************************
3330          *  Resource + asic cap harcoding                *
3331          *************************************************/
3332         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3333
3334         dc->caps.max_downscale_ratio = 200;
3335         dc->caps.i2c_speed_in_khz = 100;
3336         dc->caps.max_cursor_size = 256;
3337         dc->caps.dmdata_alloc_size = 2048;
3338
3339         dc->caps.max_slave_planes = 1;
3340         dc->caps.post_blend_color_processing = true;
3341         dc->caps.force_dp_tps4_for_cp2520 = true;
3342         dc->caps.hw_3d_lut = true;
3343
3344         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3345                 dc->debug = debug_defaults_drv;
3346         } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3347                 pool->base.pipe_count = 4;
3348                 pool->base.mpcc_count = pool->base.pipe_count;
3349                 dc->debug = debug_defaults_diags;
3350         } else {
3351                 dc->debug = debug_defaults_diags;
3352         }
3353         //dcn2.0x
3354         dc->work_arounds.dedcn20_305_wa = true;
3355
3356         // Init the vm_helper
3357         if (dc->vm_helper)
3358                 vm_helper_init(dc->vm_helper, 16);
3359
3360         /*************************************************
3361          *  Create resources                             *
3362          *************************************************/
3363
3364         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3365                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3366                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
3367                                 &clk_src_regs[0], false);
3368         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3369                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3370                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
3371                                 &clk_src_regs[1], false);
3372         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3373                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3374                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
3375                                 &clk_src_regs[2], false);
3376         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3377                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3378                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
3379                                 &clk_src_regs[3], false);
3380         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3381                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3382                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
3383                                 &clk_src_regs[4], false);
3384         pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3385                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3386                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
3387                                 &clk_src_regs[5], false);
3388         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3389         /* todo: not reuse phy_pll registers */
3390         pool->base.dp_clock_source =
3391                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3392                                 CLOCK_SOURCE_ID_DP_DTO,
3393                                 &clk_src_regs[0], true);
3394
3395         for (i = 0; i < pool->base.clk_src_count; i++) {
3396                 if (pool->base.clock_sources[i] == NULL) {
3397                         dm_error("DC: failed to create clock sources!\n");
3398                         BREAK_TO_DEBUGGER();
3399                         goto create_fail;
3400                 }
3401         }
3402
3403         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3404         if (pool->base.dccg == NULL) {
3405                 dm_error("DC: failed to create dccg!\n");
3406                 BREAK_TO_DEBUGGER();
3407                 goto create_fail;
3408         }
3409
3410         pool->base.dmcu = dcn20_dmcu_create(ctx,
3411                         &dmcu_regs,
3412                         &dmcu_shift,
3413                         &dmcu_mask);
3414         if (pool->base.dmcu == NULL) {
3415                 dm_error("DC: failed to create dmcu!\n");
3416                 BREAK_TO_DEBUGGER();
3417                 goto create_fail;
3418         }
3419
3420         pool->base.abm = dce_abm_create(ctx,
3421                         &abm_regs,
3422                         &abm_shift,
3423                         &abm_mask);
3424         if (pool->base.abm == NULL) {
3425                 dm_error("DC: failed to create abm!\n");
3426                 BREAK_TO_DEBUGGER();
3427                 goto create_fail;
3428         }
3429
3430         pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3431
3432
3433         if (!init_soc_bounding_box(dc, pool)) {
3434                 dm_error("DC: failed to initialize soc bounding box!\n");
3435                 BREAK_TO_DEBUGGER();
3436                 goto create_fail;
3437         }
3438
3439         dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3440
3441         if (!dc->debug.disable_pplib_wm_range) {
3442                 struct pp_smu_wm_range_sets ranges = {0};
3443                 int i = 0;
3444
3445                 ranges.num_reader_wm_sets = 0;
3446
3447                 if (loaded_bb->num_states == 1) {
3448                         ranges.reader_wm_sets[0].wm_inst = i;
3449                         ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3450                         ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3451                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3452                         ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3453
3454                         ranges.num_reader_wm_sets = 1;
3455                 } else if (loaded_bb->num_states > 1) {
3456                         for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3457                                 ranges.reader_wm_sets[i].wm_inst = i;
3458                                 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3459                                 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3460                                 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3461                                 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3462
3463                                 ranges.num_reader_wm_sets = i + 1;
3464                         }
3465
3466                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3467                         ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3468                 }
3469
3470                 ranges.num_writer_wm_sets = 1;
3471
3472                 ranges.writer_wm_sets[0].wm_inst = 0;
3473                 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3474                 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3475                 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3476                 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3477
3478                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3479                 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3480                         pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3481         }
3482
3483         init_data.ctx = dc->ctx;
3484         pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3485         if (!pool->base.irqs)
3486                 goto create_fail;
3487
3488         /* mem input -> ipp -> dpp -> opp -> TG */
3489         for (i = 0; i < pool->base.pipe_count; i++) {
3490                 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3491                 if (pool->base.hubps[i] == NULL) {
3492                         BREAK_TO_DEBUGGER();
3493                         dm_error(
3494                                 "DC: failed to create memory input!\n");
3495                         goto create_fail;
3496                 }
3497
3498                 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3499                 if (pool->base.ipps[i] == NULL) {
3500                         BREAK_TO_DEBUGGER();
3501                         dm_error(
3502                                 "DC: failed to create input pixel processor!\n");
3503                         goto create_fail;
3504                 }
3505
3506                 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3507                 if (pool->base.dpps[i] == NULL) {
3508                         BREAK_TO_DEBUGGER();
3509                         dm_error(
3510                                 "DC: failed to create dpps!\n");
3511                         goto create_fail;
3512                 }
3513         }
3514         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3515                 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3516                 if (pool->base.engines[i] == NULL) {
3517                         BREAK_TO_DEBUGGER();
3518                         dm_error(
3519                                 "DC:failed to create aux engine!!\n");
3520                         goto create_fail;
3521                 }
3522                 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3523                 if (pool->base.hw_i2cs[i] == NULL) {
3524                         BREAK_TO_DEBUGGER();
3525                         dm_error(
3526                                 "DC:failed to create hw i2c!!\n");
3527                         goto create_fail;
3528                 }
3529                 pool->base.sw_i2cs[i] = NULL;
3530         }
3531
3532         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3533                 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3534                 if (pool->base.opps[i] == NULL) {
3535                         BREAK_TO_DEBUGGER();
3536                         dm_error(
3537                                 "DC: failed to create output pixel processor!\n");
3538                         goto create_fail;
3539                 }
3540         }
3541
3542         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3543                 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3544                                 ctx, i);
3545                 if (pool->base.timing_generators[i] == NULL) {
3546                         BREAK_TO_DEBUGGER();
3547                         dm_error("DC: failed to create tg!\n");
3548                         goto create_fail;
3549                 }
3550         }
3551
3552         pool->base.timing_generator_count = i;
3553
3554         pool->base.mpc = dcn20_mpc_create(ctx);
3555         if (pool->base.mpc == NULL) {
3556                 BREAK_TO_DEBUGGER();
3557                 dm_error("DC: failed to create mpc!\n");
3558                 goto create_fail;
3559         }
3560
3561         pool->base.hubbub = dcn20_hubbub_create(ctx);
3562         if (pool->base.hubbub == NULL) {
3563                 BREAK_TO_DEBUGGER();
3564                 dm_error("DC: failed to create hubbub!\n");
3565                 goto create_fail;
3566         }
3567
3568 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3569         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3570                 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3571                 if (pool->base.dscs[i] == NULL) {
3572                         BREAK_TO_DEBUGGER();
3573                         dm_error("DC: failed to create display stream compressor %d!\n", i);
3574                         goto create_fail;
3575                 }
3576         }
3577 #endif
3578
3579         if (!dcn20_dwbc_create(ctx, &pool->base)) {
3580                 BREAK_TO_DEBUGGER();
3581                 dm_error("DC: failed to create dwbc!\n");
3582                 goto create_fail;
3583         }
3584         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3585                 BREAK_TO_DEBUGGER();
3586                 dm_error("DC: failed to create mcif_wb!\n");
3587                 goto create_fail;
3588         }
3589
3590         if (!resource_construct(num_virtual_links, dc, &pool->base,
3591                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3592                         &res_create_funcs : &res_create_maximus_funcs)))
3593                         goto create_fail;
3594
3595         dcn20_hw_sequencer_construct(dc);
3596
3597         dc->caps.max_planes =  pool->base.pipe_count;
3598
3599         for (i = 0; i < dc->caps.max_planes; ++i)
3600                 dc->caps.planes[i] = plane_cap;
3601
3602         dc->cap_funcs = cap_funcs;
3603
3604         return true;
3605
3606 create_fail:
3607
3608         destruct(pool);
3609
3610         return false;
3611 }
3612
3613 struct resource_pool *dcn20_create_resource_pool(
3614                 const struct dc_init_data *init_data,
3615                 struct dc *dc)
3616 {
3617         struct dcn20_resource_pool *pool =
3618                 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3619
3620         if (!pool)
3621                 return NULL;
3622
3623         if (construct(init_data->num_virtual_links, dc, pool))
3624                 return &pool->base;
3625
3626         BREAK_TO_DEBUGGER();
3627         kfree(pool);
3628         return NULL;
3629 }