drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "vm_helper.h"
  50 #include "dccg.h"
  51 #include "dc_dmub_srv.h"
  52 #include "dce/dmub_hw_lock_mgr.h"
  53 #include "hw_sequencer.h"
  54 #include "dpcd_defs.h"
  55 #include "inc/link_enc_cfg.h"
  56 #include "link_hwss.h"
  57 #include "link.h"
  58
  59 #define DC_LOGGER_INIT(logger)
  60
  61 #define CTX \
  62         hws->ctx
  63 #define REG(reg)\
  64         hws->regs->reg
  65
  66 #undef FN
  67 #define FN(reg_name, field_name) \
  68         hws->shifts->field_name, hws->masks->field_name
  69
  70 static int find_free_gsl_group(const struct dc *dc)
  71 {
  72         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  73                 return 1;
  74         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  75                 return 2;
  76         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  77                 return 3;
  78
  79         return 0;
  80 }
  81
  82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  83  * This is only used to lock pipes in pipe splitting case with immediate flip
  84  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  85  * so we get tearing with freesync since we cannot flip multiple pipes
  86  * atomically.
  87  * We use GSL for this:
  88  * - immediate flip: find first available GSL group if not already assigned
  89  *                   program gsl with that group, set current OTG as master
  90  *                   and always us 0x4 = AND of flip_ready from all pipes
  91  * - vsync flip: disable GSL if used
  92  *
  93  * Groups in stream_res are stored as +1 from HW registers, i.e.
  94  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  95  * Using a magic value like -1 would require tracking all inits/resets
  96  */
  97 static void dcn20_setup_gsl_group_as_lock(
  98                 const struct dc *dc,
  99                 struct pipe_ctx *pipe_ctx,
 100                 bool enable)
 101 {
 102         struct gsl_params gsl;
 103         int group_idx;
 104
 105         memset(&gsl, 0, sizeof(struct gsl_params));
 106
 107         if (enable) {
 108                 /* return if group already assigned since GSL was set up
 109                  * for vsync flip, we would unassign so it can't be "left over"
 110                  */
 111                 if (pipe_ctx->stream_res.gsl_group > 0)
 112                         return;
 113
 114                 group_idx = find_free_gsl_group(dc);
 115                 ASSERT(group_idx != 0);
 116                 pipe_ctx->stream_res.gsl_group = group_idx;
 117
 118                 /* set gsl group reg field and mark resource used */
 119                 switch (group_idx) {
 120                 case 1:
 121                         gsl.gsl0_en = 1;
 122                         dc->res_pool->gsl_groups.gsl_0 = 1;
 123                         break;
 124                 case 2:
 125                         gsl.gsl1_en = 1;
 126                         dc->res_pool->gsl_groups.gsl_1 = 1;
 127                         break;
 128                 case 3:
 129                         gsl.gsl2_en = 1;
 130                         dc->res_pool->gsl_groups.gsl_2 = 1;
 131                         break;
 132                 default:
 133                         BREAK_TO_DEBUGGER();
 134                         return; // invalid case
 135                 }
 136                 gsl.gsl_master_en = 1;
 137         } else {
 138                 group_idx = pipe_ctx->stream_res.gsl_group;
 139                 if (group_idx == 0)
 140                         return; // if not in use, just return
 141
 142                 pipe_ctx->stream_res.gsl_group = 0;
 143
 144                 /* unset gsl group reg field and mark resource free */
 145                 switch (group_idx) {
 146                 case 1:
 147                         gsl.gsl0_en = 0;
 148                         dc->res_pool->gsl_groups.gsl_0 = 0;
 149                         break;
 150                 case 2:
 151                         gsl.gsl1_en = 0;
 152                         dc->res_pool->gsl_groups.gsl_1 = 0;
 153                         break;
 154                 case 3:
 155                         gsl.gsl2_en = 0;
 156                         dc->res_pool->gsl_groups.gsl_2 = 0;
 157                         break;
 158                 default:
 159                         BREAK_TO_DEBUGGER();
 160                         return;
 161                 }
 162                 gsl.gsl_master_en = 0;
 163         }
 164
 165         /* at this point we want to program whether it's to enable or disable */
 166         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 167                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 168                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 169                         pipe_ctx->stream_res.tg,
 170                         &gsl);
 171
 172                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 173                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 174         } else
 175                 BREAK_TO_DEBUGGER();
 176 }
 177
 178 void dcn20_set_flip_control_gsl(
 179                 struct pipe_ctx *pipe_ctx,
 180                 bool flip_immediate)
 181 {
 182         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 183                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 184                                 pipe_ctx->plane_res.hubp, flip_immediate);
 185
 186 }
 187
 188 void dcn20_enable_power_gating_plane(
 189         struct dce_hwseq *hws,
 190         bool enable)
 191 {
 192         bool force_on = true; /* disable power gating */
 193         uint32_t org_ip_request_cntl = 0;
 194
 195         if (enable)
 196                 force_on = false;
 197
 198         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 199         if (org_ip_request_cntl == 0)
 200                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 201
 202         /* DCHUBP0/1/2/3/4/5 */
 203         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 204         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 205         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 206         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 207         if (REG(DOMAIN8_PG_CONFIG))
 208                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 209         if (REG(DOMAIN10_PG_CONFIG))
 210                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 211
 212         /* DPP0/1/2/3/4/5 */
 213         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 214         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 215         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 216         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 217         if (REG(DOMAIN9_PG_CONFIG))
 218                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 219         if (REG(DOMAIN11_PG_CONFIG))
 220                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 221
 222         /* DCS0/1/2/3/4/5 */
 223         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 224         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 225         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 226         if (REG(DOMAIN19_PG_CONFIG))
 227                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 228         if (REG(DOMAIN20_PG_CONFIG))
 229                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 230         if (REG(DOMAIN21_PG_CONFIG))
 231                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 232
 233         if (org_ip_request_cntl == 0)
 234                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 235
 236 }
 237
 238 void dcn20_dccg_init(struct dce_hwseq *hws)
 239 {
 240         /*
 241          * set MICROSECOND_TIME_BASE_DIV
 242          * 100Mhz refclk -> 0x120264
 243          * 27Mhz refclk -> 0x12021b
 244          * 48Mhz refclk -> 0x120230
 245          *
 246          */
 247         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 248
 249         /*
 250          * set MILLISECOND_TIME_BASE_DIV
 251          * 100Mhz refclk -> 0x1186a0
 252          * 27Mhz refclk -> 0x106978
 253          * 48Mhz refclk -> 0x10bb80
 254          *
 255          */
 256         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 257
 258         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 259         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 260 }
 261
 262 void dcn20_disable_vga(
 263         struct dce_hwseq *hws)
 264 {
 265         REG_WRITE(D1VGA_CONTROL, 0);
 266         REG_WRITE(D2VGA_CONTROL, 0);
 267         REG_WRITE(D3VGA_CONTROL, 0);
 268         REG_WRITE(D4VGA_CONTROL, 0);
 269         REG_WRITE(D5VGA_CONTROL, 0);
 270         REG_WRITE(D6VGA_CONTROL, 0);
 271 }
 272
 273 void dcn20_program_triple_buffer(
 274         const struct dc *dc,
 275         struct pipe_ctx *pipe_ctx,
 276         bool enable_triple_buffer)
 277 {
 278         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 279                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 280                         pipe_ctx->plane_res.hubp,
 281                         enable_triple_buffer);
 282         }
 283 }
 284
 285 /* Blank pixel data during initialization */
 286 void dcn20_init_blank(
 287                 struct dc *dc,
 288                 struct timing_generator *tg)
 289 {
 290         struct dce_hwseq *hws = dc->hwseq;
 291         enum dc_color_space color_space;
 292         struct tg_color black_color = {0};
 293         struct output_pixel_processor *opp = NULL;
 294         struct output_pixel_processor *bottom_opp = NULL;
 295         uint32_t num_opps, opp_id_src0, opp_id_src1;
 296         uint32_t otg_active_width, otg_active_height;
 297
 298         /* program opp dpg blank color */
 299         color_space = COLOR_SPACE_SRGB;
 300         color_space_to_black_color(dc, color_space, &black_color);
 301
 302         /* get the OTG active size */
 303         tg->funcs->get_otg_active_size(tg,
 304                         &otg_active_width,
 305                         &otg_active_height);
 306
 307         /* get the OPTC source */
 308         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 309
 310         if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
 311                 ASSERT(false);
 312                 return;
 313         }
 314         opp = dc->res_pool->opps[opp_id_src0];
 315
 316         /* don't override the blank pattern if already enabled with the correct one. */
 317         if (opp->funcs->dpg_is_blanked && opp->funcs->dpg_is_blanked(opp))
 318                 return;
 319
 320         if (num_opps == 2) {
 321                 otg_active_width = otg_active_width / 2;
 322
 323                 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
 324                         ASSERT(false);
 325                         return;
 326                 }
 327                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 328         }
 329
 330         opp->funcs->opp_set_disp_pattern_generator(
 331                         opp,
 332                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 333                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 334                         COLOR_DEPTH_UNDEFINED,
 335                         &black_color,
 336                         otg_active_width,
 337                         otg_active_height,
 338                         0);
 339
 340         if (num_opps == 2) {
 341                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 342                                 bottom_opp,
 343                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 344                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 345                                 COLOR_DEPTH_UNDEFINED,
 346                                 &black_color,
 347                                 otg_active_width,
 348                                 otg_active_height,
 349                                 0);
 350         }
 351
 352         hws->funcs.wait_for_blank_complete(opp);
 353 }
 354
 355 void dcn20_dsc_pg_control(
 356                 struct dce_hwseq *hws,
 357                 unsigned int dsc_inst,
 358                 bool power_on)
 359 {
 360         uint32_t power_gate = power_on ? 0 : 1;
 361         uint32_t pwr_status = power_on ? 0 : 2;
 362         uint32_t org_ip_request_cntl = 0;
 363
 364         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 365                 return;
 366
 367         if (REG(DOMAIN16_PG_CONFIG) == 0)
 368                 return;
 369
 370         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 371         if (org_ip_request_cntl == 0)
 372                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 373
 374         switch (dsc_inst) {
 375         case 0: /* DSC0 */
 376                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 377                                 DOMAIN16_POWER_GATE, power_gate);
 378
 379                 REG_WAIT(DOMAIN16_PG_STATUS,
 380                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 381                                 1, 1000);
 382                 break;
 383         case 1: /* DSC1 */
 384                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 385                                 DOMAIN17_POWER_GATE, power_gate);
 386
 387                 REG_WAIT(DOMAIN17_PG_STATUS,
 388                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 389                                 1, 1000);
 390                 break;
 391         case 2: /* DSC2 */
 392                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 393                                 DOMAIN18_POWER_GATE, power_gate);
 394
 395                 REG_WAIT(DOMAIN18_PG_STATUS,
 396                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 397                                 1, 1000);
 398                 break;
 399         case 3: /* DSC3 */
 400                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 401                                 DOMAIN19_POWER_GATE, power_gate);
 402
 403                 REG_WAIT(DOMAIN19_PG_STATUS,
 404                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 405                                 1, 1000);
 406                 break;
 407         case 4: /* DSC4 */
 408                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 409                                 DOMAIN20_POWER_GATE, power_gate);
 410
 411                 REG_WAIT(DOMAIN20_PG_STATUS,
 412                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 413                                 1, 1000);
 414                 break;
 415         case 5: /* DSC5 */
 416                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 417                                 DOMAIN21_POWER_GATE, power_gate);
 418
 419                 REG_WAIT(DOMAIN21_PG_STATUS,
 420                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 421                                 1, 1000);
 422                 break;
 423         default:
 424                 BREAK_TO_DEBUGGER();
 425                 break;
 426         }
 427
 428         if (org_ip_request_cntl == 0)
 429                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 430 }
 431
 432 void dcn20_dpp_pg_control(
 433                 struct dce_hwseq *hws,
 434                 unsigned int dpp_inst,
 435                 bool power_on)
 436 {
 437         uint32_t power_gate = power_on ? 0 : 1;
 438         uint32_t pwr_status = power_on ? 0 : 2;
 439
 440         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 441                 return;
 442         if (REG(DOMAIN1_PG_CONFIG) == 0)
 443                 return;
 444
 445         switch (dpp_inst) {
 446         case 0: /* DPP0 */
 447                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 448                                 DOMAIN1_POWER_GATE, power_gate);
 449
 450                 REG_WAIT(DOMAIN1_PG_STATUS,
 451                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 452                                 1, 1000);
 453                 break;
 454         case 1: /* DPP1 */
 455                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 456                                 DOMAIN3_POWER_GATE, power_gate);
 457
 458                 REG_WAIT(DOMAIN3_PG_STATUS,
 459                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 460                                 1, 1000);
 461                 break;
 462         case 2: /* DPP2 */
 463                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 464                                 DOMAIN5_POWER_GATE, power_gate);
 465
 466                 REG_WAIT(DOMAIN5_PG_STATUS,
 467                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 468                                 1, 1000);
 469                 break;
 470         case 3: /* DPP3 */
 471                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 472                                 DOMAIN7_POWER_GATE, power_gate);
 473
 474                 REG_WAIT(DOMAIN7_PG_STATUS,
 475                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 476                                 1, 1000);
 477                 break;
 478         case 4: /* DPP4 */
 479                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 480                                 DOMAIN9_POWER_GATE, power_gate);
 481
 482                 REG_WAIT(DOMAIN9_PG_STATUS,
 483                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 484                                 1, 1000);
 485                 break;
 486         case 5: /* DPP5 */
 487                 /*
 488                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 489                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 490                  * reset.
 491                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 492                  *              DOMAIN11_POWER_GATE, power_gate);
 493                  *
 494                  * REG_WAIT(DOMAIN11_PG_STATUS,
 495                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 496                  *              1, 1000);
 497                  */
 498                 break;
 499         default:
 500                 BREAK_TO_DEBUGGER();
 501                 break;
 502         }
 503 }
 504
 505
 506 void dcn20_hubp_pg_control(
 507                 struct dce_hwseq *hws,
 508                 unsigned int hubp_inst,
 509                 bool power_on)
 510 {
 511         uint32_t power_gate = power_on ? 0 : 1;
 512         uint32_t pwr_status = power_on ? 0 : 2;
 513
 514         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 515                 return;
 516         if (REG(DOMAIN0_PG_CONFIG) == 0)
 517                 return;
 518
 519         switch (hubp_inst) {
 520         case 0: /* DCHUBP0 */
 521                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 522                                 DOMAIN0_POWER_GATE, power_gate);
 523
 524                 REG_WAIT(DOMAIN0_PG_STATUS,
 525                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 526                                 1, 1000);
 527                 break;
 528         case 1: /* DCHUBP1 */
 529                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 530                                 DOMAIN2_POWER_GATE, power_gate);
 531
 532                 REG_WAIT(DOMAIN2_PG_STATUS,
 533                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 534                                 1, 1000);
 535                 break;
 536         case 2: /* DCHUBP2 */
 537                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 538                                 DOMAIN4_POWER_GATE, power_gate);
 539
 540                 REG_WAIT(DOMAIN4_PG_STATUS,
 541                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 542                                 1, 1000);
 543                 break;
 544         case 3: /* DCHUBP3 */
 545                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 546                                 DOMAIN6_POWER_GATE, power_gate);
 547
 548                 REG_WAIT(DOMAIN6_PG_STATUS,
 549                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 550                                 1, 1000);
 551                 break;
 552         case 4: /* DCHUBP4 */
 553                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 554                                 DOMAIN8_POWER_GATE, power_gate);
 555
 556                 REG_WAIT(DOMAIN8_PG_STATUS,
 557                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 558                                 1, 1000);
 559                 break;
 560         case 5: /* DCHUBP5 */
 561                 /*
 562                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 563                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 564                  * reset.
 565                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 566                  *              DOMAIN10_POWER_GATE, power_gate);
 567                  *
 568                  * REG_WAIT(DOMAIN10_PG_STATUS,
 569                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 570                  *              1, 1000);
 571                  */
 572                 break;
 573         default:
 574                 BREAK_TO_DEBUGGER();
 575                 break;
 576         }
 577 }
 578
 579
 580 /* disable HW used by plane.
 581  * note:  cannot disable until disconnect is complete
 582  */
 583 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 584 {
 585         struct dce_hwseq *hws = dc->hwseq;
 586         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 587         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 588
 589         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 590
 591         /* In flip immediate with pipe splitting case GSL is used for
 592          * synchronization so we must disable it when the plane is disabled.
 593          */
 594         if (pipe_ctx->stream_res.gsl_group != 0)
 595                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 596
 597         if (hubp->funcs->hubp_update_mall_sel)
 598                 hubp->funcs->hubp_update_mall_sel(hubp, 0, false);
 599
 600         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 601
 602         hubp->funcs->hubp_clk_cntl(hubp, false);
 603
 604         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 605
 606         hubp->power_gated = true;
 607
 608         hws->funcs.plane_atomic_power_down(dc,
 609                         pipe_ctx->plane_res.dpp,
 610                         pipe_ctx->plane_res.hubp);
 611
 612         pipe_ctx->stream = NULL;
 613         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 614         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 615         pipe_ctx->top_pipe = NULL;
 616         pipe_ctx->bottom_pipe = NULL;
 617         pipe_ctx->prev_odm_pipe = NULL;
 618         pipe_ctx->next_odm_pipe = NULL;
 619         pipe_ctx->plane_state = NULL;
 620 }
 621
 622
 623 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 624 {
 625         bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom;
 626         struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;
 627
 628         DC_LOGGER_INIT(dc->ctx->logger);
 629
 630         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 631                 return;
 632
 633         dcn20_plane_atomic_disable(dc, pipe_ctx);
 634
 635         /* Turn back off the phantom OTG after the phantom plane is fully disabled
 636          */
 637         if (is_phantom)
 638                 if (tg && tg->funcs->disable_phantom_crtc)
 639                         tg->funcs->disable_phantom_crtc(tg);
 640
 641         DC_LOG_DC("Power down front end %d\n",
 642                                         pipe_ctx->pipe_idx);
 643 }
 644
 645 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
 646 {
 647         dcn20_blank_pixel_data(dc, pipe_ctx, blank);
 648 }
 649
 650 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 651                 int opp_cnt)
 652 {
 653         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 654         int flow_ctrl_cnt;
 655
 656         if (opp_cnt >= 2)
 657                 hblank_halved = true;
 658
 659         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 660                         stream->timing.h_border_left -
 661                         stream->timing.h_border_right;
 662
 663         if (hblank_halved)
 664                 flow_ctrl_cnt /= 2;
 665
 666         /* ODM combine 4:1 case */
 667         if (opp_cnt == 4)
 668                 flow_ctrl_cnt /= 2;
 669
 670         return flow_ctrl_cnt;
 671 }
 672
 673 enum dc_status dcn20_enable_stream_timing(
 674                 struct pipe_ctx *pipe_ctx,
 675                 struct dc_state *context,
 676                 struct dc *dc)
 677 {
 678         struct dce_hwseq *hws = dc->hwseq;
 679         struct dc_stream_state *stream = pipe_ctx->stream;
 680         struct drr_params params = {0};
 681         unsigned int event_triggers = 0;
 682         struct pipe_ctx *odm_pipe;
 683         int opp_cnt = 1;
 684         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 685         bool interlace = stream->timing.flags.INTERLACE;
 686         int i;
 687         struct mpc_dwb_flow_control flow_control;
 688         struct mpc *mpc = dc->res_pool->mpc;
 689         bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
 690         unsigned int k1_div = PIXEL_RATE_DIV_NA;
 691         unsigned int k2_div = PIXEL_RATE_DIV_NA;
 692
 693         if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
 694                 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
 695
 696                 dc->res_pool->dccg->funcs->set_pixel_rate_div(
 697                         dc->res_pool->dccg,
 698                         pipe_ctx->stream_res.tg->inst,
 699                         k1_div, k2_div);
 700         }
 701         /* by upper caller loop, pipe0 is parent pipe and be called first.
 702          * back end is set up by for pipe0. Other children pipe share back end
 703          * with pipe 0. No program is needed.
 704          */
 705         if (pipe_ctx->top_pipe != NULL)
 706                 return DC_OK;
 707
 708         /* TODO check if timing_changed, disable stream if timing changed */
 709
 710         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 711                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 712                 opp_cnt++;
 713         }
 714
 715         if (opp_cnt > 1)
 716                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 717                                 pipe_ctx->stream_res.tg,
 718                                 opp_inst, opp_cnt,
 719                                 &pipe_ctx->stream->timing);
 720
 721         /* HW program guide assume display already disable
 722          * by unplug sequence. OTG assume stop.
 723          */
 724         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 725
 726         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 727                         pipe_ctx->clock_source,
 728                         &pipe_ctx->stream_res.pix_clk_params,
 729                         dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
 730                         &pipe_ctx->pll_settings)) {
 731                 BREAK_TO_DEBUGGER();
 732                 return DC_ERROR_UNEXPECTED;
 733         }
 734
 735         if (dc_is_hdmi_tmds_signal(stream->signal)) {
 736                 stream->link->phy_state.symclk_ref_cnts.otg = 1;
 737                 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
 738                         stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
 739                 else
 740                         stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
 741         }
 742
 743         if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
 744                 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
 745
 746         pipe_ctx->stream_res.tg->funcs->program_timing(
 747                         pipe_ctx->stream_res.tg,
 748                         &stream->timing,
 749                         pipe_ctx->pipe_dlg_param.vready_offset,
 750                         pipe_ctx->pipe_dlg_param.vstartup_start,
 751                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 752                         pipe_ctx->pipe_dlg_param.vupdate_width,
 753                         pipe_ctx->stream->signal,
 754                         true);
 755
 756         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
 757         flow_control.flow_ctrl_mode = 0;
 758         flow_control.flow_ctrl_cnt0 = 0x80;
 759         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
 760         if (mpc->funcs->set_out_rate_control) {
 761                 for (i = 0; i < opp_cnt; ++i) {
 762                         mpc->funcs->set_out_rate_control(
 763                                         mpc, opp_inst[i],
 764                                         true,
 765                                         rate_control_2x_pclk,
 766                                         &flow_control);
 767                 }
 768         }
 769
 770         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 771                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 772                                 odm_pipe->stream_res.opp,
 773                                 true);
 774
 775         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 776                         pipe_ctx->stream_res.opp,
 777                         true);
 778
 779         hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
 780
 781         /* VTG is  within DCHUB command block. DCFCLK is always on */
 782         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 783                 BREAK_TO_DEBUGGER();
 784                 return DC_ERROR_UNEXPECTED;
 785         }
 786
 787         hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 788
 789         params.vertical_total_min = stream->adjust.v_total_min;
 790         params.vertical_total_max = stream->adjust.v_total_max;
 791         params.vertical_total_mid = stream->adjust.v_total_mid;
 792         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 793         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 794                 pipe_ctx->stream_res.tg->funcs->set_drr(
 795                         pipe_ctx->stream_res.tg, &params);
 796
 797         // DRR should set trigger event to monitor surface update event
 798         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 799                 event_triggers = 0x80;
 800         /* Event triggers and num frames initialized for DRR, but can be
 801          * later updated for PSR use. Note DRR trigger events are generated
 802          * regardless of whether num frames met.
 803          */
 804         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 805                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 806                                 pipe_ctx->stream_res.tg, event_triggers, 2);
 807
 808         /* TODO program crtc source select for non-virtual signal*/
 809         /* TODO program FMT */
 810         /* TODO setup link_enc */
 811         /* TODO set stream attributes */
 812         /* TODO program audio */
 813         /* TODO enable stream if timing changed */
 814         /* TODO unblank stream if DP */
 815
 816         if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 817                 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
 818                         pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
 819         }
 820         return DC_OK;
 821 }
 822
 823 void dcn20_program_output_csc(struct dc *dc,
 824                 struct pipe_ctx *pipe_ctx,
 825                 enum dc_color_space colorspace,
 826                 uint16_t *matrix,
 827                 int opp_id)
 828 {
 829         struct mpc *mpc = dc->res_pool->mpc;
 830         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 831         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 832
 833         if (mpc->funcs->power_on_mpc_mem_pwr)
 834                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 835
 836         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 837                 if (mpc->funcs->set_output_csc != NULL)
 838                         mpc->funcs->set_output_csc(mpc,
 839                                         opp_id,
 840                                         matrix,
 841                                         ocsc_mode);
 842         } else {
 843                 if (mpc->funcs->set_ocsc_default != NULL)
 844                         mpc->funcs->set_ocsc_default(mpc,
 845                                         opp_id,
 846                                         colorspace,
 847                                         ocsc_mode);
 848         }
 849 }
 850
 851 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 852                                 const struct dc_stream_state *stream)
 853 {
 854         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 855         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 856         struct pwl_params *params = NULL;
 857         /*
 858          * program OGAM only for the top pipe
 859          * if there is a pipe split then fix diagnostic is required:
 860          * how to pass OGAM parameter for stream.
 861          * if programming for all pipes is required then remove condition
 862          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 863          */
 864         if (mpc->funcs->power_on_mpc_mem_pwr)
 865                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 866         if (pipe_ctx->top_pipe == NULL
 867                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 868                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 869                         params = &stream->out_transfer_func->pwl;
 870                 else if (pipe_ctx->stream->out_transfer_func->type ==
 871                         TF_TYPE_DISTRIBUTED_POINTS &&
 872                         cm_helper_translate_curve_to_hw_format(dc->ctx,
 873                         stream->out_transfer_func,
 874                         &mpc->blender_params, false))
 875                         params = &mpc->blender_params;
 876                 /*
 877                  * there is no ROM
 878                  */
 879                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 880                         BREAK_TO_DEBUGGER();
 881         }
 882         /*
 883          * if above if is not executed then 'params' equal to 0 and set in bypass
 884          */
 885         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 886
 887         return true;
 888 }
 889
 890 bool dcn20_set_blend_lut(
 891         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 892 {
 893         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 894         bool result = true;
 895         struct pwl_params *blend_lut = NULL;
 896
 897         if (plane_state->blend_tf) {
 898                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 899                         blend_lut = &plane_state->blend_tf->pwl;
 900                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 901                         cm_helper_translate_curve_to_hw_format(plane_state->ctx,
 902                                         plane_state->blend_tf,
 903                                         &dpp_base->regamma_params, false);
 904                         blend_lut = &dpp_base->regamma_params;
 905                 }
 906         }
 907         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 908
 909         return result;
 910 }
 911
 912 bool dcn20_set_shaper_3dlut(
 913         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 914 {
 915         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 916         bool result = true;
 917         struct pwl_params *shaper_lut = NULL;
 918
 919         if (plane_state->in_shaper_func) {
 920                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 921                         shaper_lut = &plane_state->in_shaper_func->pwl;
 922                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 923                         cm_helper_translate_curve_to_hw_format(plane_state->ctx,
 924                                         plane_state->in_shaper_func,
 925                                         &dpp_base->shaper_params, true);
 926                         shaper_lut = &dpp_base->shaper_params;
 927                 }
 928         }
 929
 930         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 931         if (plane_state->lut3d_func &&
 932                 plane_state->lut3d_func->state.bits.initialized == 1)
 933                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 934                                                                 &plane_state->lut3d_func->lut_3d);
 935         else
 936                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 937
 938         return result;
 939 }
 940
 941 bool dcn20_set_input_transfer_func(struct dc *dc,
 942                                 struct pipe_ctx *pipe_ctx,
 943                                 const struct dc_plane_state *plane_state)
 944 {
 945         struct dce_hwseq *hws = dc->hwseq;
 946         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 947         const struct dc_transfer_func *tf = NULL;
 948         bool result = true;
 949         bool use_degamma_ram = false;
 950
 951         if (dpp_base == NULL || plane_state == NULL)
 952                 return false;
 953
 954         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 955         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 956
 957         if (plane_state->in_transfer_func)
 958                 tf = plane_state->in_transfer_func;
 959
 960
 961         if (tf == NULL) {
 962                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 963                                 IPP_DEGAMMA_MODE_BYPASS);
 964                 return true;
 965         }
 966
 967         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 968                 use_degamma_ram = true;
 969
 970         if (use_degamma_ram == true) {
 971                 if (tf->type == TF_TYPE_HWPWL)
 972                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 973                                         &tf->pwl);
 974                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 975                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 976                                         &dpp_base->degamma_params);
 977                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 978                                 &dpp_base->degamma_params);
 979                 }
 980                 return true;
 981         }
 982         /* handle here the optimized cases when de-gamma ROM could be used.
 983          *
 984          */
 985         if (tf->type == TF_TYPE_PREDEFINED) {
 986                 switch (tf->tf) {
 987                 case TRANSFER_FUNCTION_SRGB:
 988                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 989                                         IPP_DEGAMMA_MODE_HW_sRGB);
 990                         break;
 991                 case TRANSFER_FUNCTION_BT709:
 992                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 993                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 994                         break;
 995                 case TRANSFER_FUNCTION_LINEAR:
 996                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 997                                         IPP_DEGAMMA_MODE_BYPASS);
 998                         break;
 999                 case TRANSFER_FUNCTION_PQ:
1000                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
1001                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
1002                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
1003                         result = true;
1004                         break;
1005                 default:
1006                         result = false;
1007                         break;
1008                 }
1009         } else if (tf->type == TF_TYPE_BYPASS)
1010                 dpp_base->funcs->dpp_set_degamma(dpp_base,
1011                                 IPP_DEGAMMA_MODE_BYPASS);
1012         else {
1013                 /*
1014                  * if we are here, we did not handle correctly.
1015                  * fix is required for this use case
1016                  */
1017                 BREAK_TO_DEBUGGER();
1018                 dpp_base->funcs->dpp_set_degamma(dpp_base,
1019                                 IPP_DEGAMMA_MODE_BYPASS);
1020         }
1021
1022         return result;
1023 }
1024
1025 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1026 {
1027         struct pipe_ctx *odm_pipe;
1028         int opp_cnt = 1;
1029         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
1030
1031         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1032                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
1033                 opp_cnt++;
1034         }
1035
1036         if (opp_cnt > 1)
1037                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1038                                 pipe_ctx->stream_res.tg,
1039                                 opp_inst, opp_cnt,
1040                                 &pipe_ctx->stream->timing);
1041         else
1042                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1043                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1044 }
1045
1046 void dcn20_blank_pixel_data(
1047                 struct dc *dc,
1048                 struct pipe_ctx *pipe_ctx,
1049                 bool blank)
1050 {
1051         struct tg_color black_color = {0};
1052         struct stream_resource *stream_res = &pipe_ctx->stream_res;
1053         struct dc_stream_state *stream = pipe_ctx->stream;
1054         enum dc_color_space color_space = stream->output_color_space;
1055         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1056         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1057         struct pipe_ctx *odm_pipe;
1058         int odm_cnt = 1;
1059         int h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1060         int v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1061         int odm_slice_width, last_odm_slice_width, offset = 0;
1062
1063         if (stream->link->test_pattern_enabled)
1064                 return;
1065
1066         /* get opp dpg blank color */
1067         color_space_to_black_color(dc, color_space, &black_color);
1068
1069         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1070                 odm_cnt++;
1071         odm_slice_width = h_active / odm_cnt;
1072         last_odm_slice_width = h_active - odm_slice_width * (odm_cnt - 1);
1073
1074         if (blank) {
1075                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1076
1077                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1078                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1079                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1080                 }
1081         } else {
1082                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1083         }
1084
1085         odm_pipe = pipe_ctx;
1086
1087         while (odm_pipe->next_odm_pipe) {
1088                 dc->hwss.set_disp_pattern_generator(dc,
1089                                 odm_pipe,
1090                                 test_pattern,
1091                                 test_pattern_color_space,
1092                                 stream->timing.display_color_depth,
1093                                 &black_color,
1094                                 odm_slice_width,
1095                                 v_active,
1096                                 offset);
1097                 offset += odm_slice_width;
1098                 odm_pipe = odm_pipe->next_odm_pipe;
1099         }
1100
1101         dc->hwss.set_disp_pattern_generator(dc,
1102                         odm_pipe,
1103                         test_pattern,
1104                         test_pattern_color_space,
1105                         stream->timing.display_color_depth,
1106                         &black_color,
1107                         last_odm_slice_width,
1108                         v_active,
1109                         offset);
1110
1111         if (!blank)
1112                 if (stream_res->abm) {
1113                         dc->hwss.set_pipe(pipe_ctx);
1114                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1115                 }
1116 }
1117
1118
1119 static void dcn20_power_on_plane_resources(
1120         struct dce_hwseq *hws,
1121         struct pipe_ctx *pipe_ctx)
1122 {
1123         DC_LOGGER_INIT(hws->ctx->logger);
1124
1125         if (hws->funcs.dpp_root_clock_control)
1126                 hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1127
1128         if (REG(DC_IP_REQUEST_CNTL)) {
1129                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1130                                 IP_REQUEST_EN, 1);
1131
1132                 if (hws->funcs.dpp_pg_control)
1133                         hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1134
1135                 if (hws->funcs.hubp_pg_control)
1136                         hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1137
1138                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1139                                 IP_REQUEST_EN, 0);
1140                 DC_LOG_DEBUG(
1141                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1142         }
1143 }
1144
1145 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1146                                struct dc_state *context)
1147 {
1148         //if (dc->debug.sanity_checks) {
1149         //      dcn10_verify_allow_pstate_change_high(dc);
1150         //}
1151         dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);
1152
1153         /* enable DCFCLK current DCHUB */
1154         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1155
1156         /* initialize HUBP on power up */
1157         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1158
1159         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1160         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1161                         pipe_ctx->stream_res.opp,
1162                         true);
1163
1164 /* TODO: enable/disable in dm as per update type.
1165         if (plane_state) {
1166                 DC_LOG_DC(dc->ctx->logger,
1167                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1168                                 "addr low:0x%x, "
1169                                 "src: %d, %d, %d,"
1170                                 " %d; dst: %d, %d, %d, %d;\n",
1171                                 pipe_ctx->pipe_idx,
1172                                 plane_state,
1173                                 plane_state->address.grph.addr.high_part,
1174                                 plane_state->address.grph.addr.low_part,
1175                                 plane_state->src_rect.x,
1176                                 plane_state->src_rect.y,
1177                                 plane_state->src_rect.width,
1178                                 plane_state->src_rect.height,
1179                                 plane_state->dst_rect.x,
1180                                 plane_state->dst_rect.y,
1181                                 plane_state->dst_rect.width,
1182                                 plane_state->dst_rect.height);
1183
1184                 DC_LOG_DC(dc->ctx->logger,
1185                                 "Pipe %d: width, height, x, y         format:%d\n"
1186                                 "viewport:%d, %d, %d, %d\n"
1187                                 "recout:  %d, %d, %d, %d\n",
1188                                 pipe_ctx->pipe_idx,
1189                                 plane_state->format,
1190                                 pipe_ctx->plane_res.scl_data.viewport.width,
1191                                 pipe_ctx->plane_res.scl_data.viewport.height,
1192                                 pipe_ctx->plane_res.scl_data.viewport.x,
1193                                 pipe_ctx->plane_res.scl_data.viewport.y,
1194                                 pipe_ctx->plane_res.scl_data.recout.width,
1195                                 pipe_ctx->plane_res.scl_data.recout.height,
1196                                 pipe_ctx->plane_res.scl_data.recout.x,
1197                                 pipe_ctx->plane_res.scl_data.recout.y);
1198                 print_rq_dlg_ttu(dc, pipe_ctx);
1199         }
1200 */
1201         if (dc->vm_pa_config.valid) {
1202                 struct vm_system_aperture_param apt;
1203
1204                 apt.sys_default.quad_part = 0;
1205
1206                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1207                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1208
1209                 // Program system aperture settings
1210                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1211         }
1212
1213         if (!pipe_ctx->top_pipe
1214                 && pipe_ctx->plane_state
1215                 && pipe_ctx->plane_state->flip_int_enabled
1216                 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1217                         pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1218
1219 //      if (dc->debug.sanity_checks) {
1220 //              dcn10_verify_allow_pstate_change_high(dc);
1221 //      }
1222 }
1223
1224 void dcn20_pipe_control_lock(
1225         struct dc *dc,
1226         struct pipe_ctx *pipe,
1227         bool lock)
1228 {
1229         struct pipe_ctx *temp_pipe;
1230         bool flip_immediate = false;
1231
1232         /* use TG master update lock to lock everything on the TG
1233          * therefore only top pipe need to lock
1234          */
1235         if (!pipe || pipe->top_pipe)
1236                 return;
1237
1238         if (pipe->plane_state != NULL)
1239                 flip_immediate = pipe->plane_state->flip_immediate;
1240
1241         if  (pipe->stream_res.gsl_group > 0) {
1242             temp_pipe = pipe->bottom_pipe;
1243             while (!flip_immediate && temp_pipe) {
1244                     if (temp_pipe->plane_state != NULL)
1245                             flip_immediate = temp_pipe->plane_state->flip_immediate;
1246                     temp_pipe = temp_pipe->bottom_pipe;
1247             }
1248         }
1249
1250         if (flip_immediate && lock) {
1251                 const int TIMEOUT_FOR_FLIP_PENDING_US = 100000;
1252                 unsigned int polling_interval_us = 1;
1253                 int i;
1254
1255                 temp_pipe = pipe;
1256                 while (temp_pipe) {
1257                         if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1258                                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING_US / polling_interval_us; ++i) {
1259                                         if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1260                                                 break;
1261                                         udelay(polling_interval_us);
1262                                 }
1263
1264                                 /* no reason it should take this long for immediate flips */
1265                                 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING_US);
1266                         }
1267                         temp_pipe = temp_pipe->bottom_pipe;
1268                 }
1269         }
1270
1271         /* In flip immediate and pipe splitting case, we need to use GSL
1272          * for synchronization. Only do setup on locking and on flip type change.
1273          */
1274         if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
1275                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1276                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1277                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1278
1279         if (pipe->plane_state != NULL)
1280                 flip_immediate = pipe->plane_state->flip_immediate;
1281
1282         temp_pipe = pipe->bottom_pipe;
1283         while (flip_immediate && temp_pipe) {
1284             if (temp_pipe->plane_state != NULL)
1285                 flip_immediate = temp_pipe->plane_state->flip_immediate;
1286             temp_pipe = temp_pipe->bottom_pipe;
1287         }
1288
1289         if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1290                 !flip_immediate)
1291             dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1292
1293         if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1294                 union dmub_hw_lock_flags hw_locks = { 0 };
1295                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1296
1297                 hw_locks.bits.lock_pipe = 1;
1298                 inst_flags.otg_inst =  pipe->stream_res.tg->inst;
1299
1300                 if (pipe->plane_state != NULL)
1301                         hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1302
1303                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1304                                         lock,
1305                                         &hw_locks,
1306                                         &inst_flags);
1307         } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1308                 if (lock)
1309                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1310                 else
1311                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1312         } else {
1313                 if (lock)
1314                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1315                 else
1316                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1317         }
1318 }
1319
1320 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1321 {
1322         new_pipe->update_flags.raw = 0;
1323
1324         /* If non-phantom pipe is being transitioned to a phantom pipe,
1325          * set disable and return immediately. This is because the pipe
1326          * that was previously in use must be fully disabled before we
1327          * can "enable" it as a phantom pipe (since the OTG will certainly
1328          * be different). The post_unlock sequence will set the correct
1329          * update flags to enable the phantom pipe.
1330          */
1331         if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom &&
1332                         new_pipe->plane_state && new_pipe->plane_state->is_phantom) {
1333                 new_pipe->update_flags.bits.disable = 1;
1334                 return;
1335         }
1336
1337         /* Exit on unchanged, unused pipe */
1338         if (!old_pipe->plane_state && !new_pipe->plane_state)
1339                 return;
1340         /* Detect pipe enable/disable */
1341         if (!old_pipe->plane_state && new_pipe->plane_state) {
1342                 new_pipe->update_flags.bits.enable = 1;
1343                 new_pipe->update_flags.bits.mpcc = 1;
1344                 new_pipe->update_flags.bits.dppclk = 1;
1345                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1346                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1347                 new_pipe->update_flags.bits.unbounded_req = 1;
1348                 new_pipe->update_flags.bits.gamut_remap = 1;
1349                 new_pipe->update_flags.bits.scaler = 1;
1350                 new_pipe->update_flags.bits.viewport = 1;
1351                 new_pipe->update_flags.bits.det_size = 1;
1352                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1353                         new_pipe->update_flags.bits.odm = 1;
1354                         new_pipe->update_flags.bits.global_sync = 1;
1355                 }
1356                 return;
1357         }
1358
1359         /* For SubVP we need to unconditionally enable because any phantom pipes are
1360          * always removed then newly added for every full updates whenever SubVP is in use.
1361          * The remove-add sequence of the phantom pipe always results in the pipe
1362          * being blanked in enable_stream_timing (DPG).
1363          */
1364         if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1365                 new_pipe->update_flags.bits.enable = 1;
1366
1367         /* Phantom pipes are effectively disabled, if the pipe was previously phantom
1368          * we have to enable
1369          */
1370         if (old_pipe->plane_state && old_pipe->plane_state->is_phantom &&
1371                         new_pipe->plane_state && !new_pipe->plane_state->is_phantom)
1372                 new_pipe->update_flags.bits.enable = 1;
1373
1374         if (old_pipe->plane_state && !new_pipe->plane_state) {
1375                 new_pipe->update_flags.bits.disable = 1;
1376                 return;
1377         }
1378
1379         /* Detect plane change */
1380         if (old_pipe->plane_state != new_pipe->plane_state) {
1381                 new_pipe->update_flags.bits.plane_changed = true;
1382         }
1383
1384         /* Detect top pipe only changes */
1385         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1386                 /* Detect odm changes */
1387                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1388                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1389                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1390                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1391                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1392                         new_pipe->update_flags.bits.odm = 1;
1393
1394                 /* Detect global sync changes */
1395                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1396                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1397                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1398                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1399                         new_pipe->update_flags.bits.global_sync = 1;
1400         }
1401
1402         if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1403                 new_pipe->update_flags.bits.det_size = 1;
1404
1405         /*
1406          * Detect opp / tg change, only set on change, not on enable
1407          * Assume mpcc inst = pipe index, if not this code needs to be updated
1408          * since mpcc is what is affected by these. In fact all of our sequence
1409          * makes this assumption at the moment with how hubp reset is matched to
1410          * same index mpcc reset.
1411          */
1412         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1413                 new_pipe->update_flags.bits.opp_changed = 1;
1414         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1415                 new_pipe->update_flags.bits.tg_changed = 1;
1416
1417         /*
1418          * Detect mpcc blending changes, only dpp inst and opp matter here,
1419          * mpccs getting removed/inserted update connected ones during their own
1420          * programming
1421          */
1422         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1423                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1424                 new_pipe->update_flags.bits.mpcc = 1;
1425
1426         /* Detect dppclk change */
1427         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1428                 new_pipe->update_flags.bits.dppclk = 1;
1429
1430         /* Check for scl update */
1431         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1432                         new_pipe->update_flags.bits.scaler = 1;
1433         /* Check for vp update */
1434         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1435                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1436                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1437                 new_pipe->update_flags.bits.viewport = 1;
1438
1439         /* Detect dlg/ttu/rq updates */
1440         {
1441                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1442                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1443                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1444                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1445
1446                 /* Detect pipe interdependent updates */
1447                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1448                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1449                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1450                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1451                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1452                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1453                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1454                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1455                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1456                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1457                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1458                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1459                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1460                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1461                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1462                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1463                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1464                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1465                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1466                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1467                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1468                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1469                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1470                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1471                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1472                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1473                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1474                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1475                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1476                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1477                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1478                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1479                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1480                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1481                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1482                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1483                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1484                 }
1485                 /* Detect any other updates to ttu/rq/dlg */
1486                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1487                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1488                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1489                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1490         }
1491
1492         if (old_pipe->unbounded_req != new_pipe->unbounded_req)
1493                 new_pipe->update_flags.bits.unbounded_req = 1;
1494 }
1495
1496 static void dcn20_update_dchubp_dpp(
1497         struct dc *dc,
1498         struct pipe_ctx *pipe_ctx,
1499         struct dc_state *context)
1500 {
1501         struct dce_hwseq *hws = dc->hwseq;
1502         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1503         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1504         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1505         struct dccg *dccg = dc->res_pool->dccg;
1506         bool viewport_changed = false;
1507
1508         if (pipe_ctx->update_flags.bits.dppclk)
1509                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1510
1511         if (pipe_ctx->update_flags.bits.enable)
1512                 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
1513
1514         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1515          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1516          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1517          */
1518         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1519                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1520
1521                 hubp->funcs->hubp_setup(
1522                         hubp,
1523                         &pipe_ctx->dlg_regs,
1524                         &pipe_ctx->ttu_regs,
1525                         &pipe_ctx->rq_regs,
1526                         &pipe_ctx->pipe_dlg_param);
1527         }
1528
1529         if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)
1530                 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
1531
1532         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1533                 hubp->funcs->hubp_setup_interdependent(
1534                         hubp,
1535                         &pipe_ctx->dlg_regs,
1536                         &pipe_ctx->ttu_regs);
1537
1538         if (pipe_ctx->update_flags.bits.enable ||
1539                         pipe_ctx->update_flags.bits.plane_changed ||
1540                         plane_state->update_flags.bits.bpp_change ||
1541                         plane_state->update_flags.bits.input_csc_change ||
1542                         plane_state->update_flags.bits.color_space_change ||
1543                         plane_state->update_flags.bits.coeff_reduction_change) {
1544                 struct dc_bias_and_scale bns_params = {0};
1545
1546                 // program the input csc
1547                 dpp->funcs->dpp_setup(dpp,
1548                                 plane_state->format,
1549                                 EXPANSION_MODE_ZERO,
1550                                 plane_state->input_csc_color_matrix,
1551                                 plane_state->color_space,
1552                                 NULL);
1553
1554                 if (dpp->funcs->dpp_program_bias_and_scale) {
1555                         //TODO :for CNVC set scale and bias registers if necessary
1556                         build_prescale_params(&bns_params, plane_state);
1557                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1558                 }
1559         }
1560
1561         if (pipe_ctx->update_flags.bits.mpcc
1562                         || pipe_ctx->update_flags.bits.plane_changed
1563                         || plane_state->update_flags.bits.global_alpha_change
1564                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1565                 // MPCC inst is equal to pipe index in practice
1566                 int mpcc_inst = hubp->inst;
1567                 int opp_inst;
1568                 int opp_count = dc->res_pool->pipe_count;
1569
1570                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1571                         if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1572                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1573                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1574                                 break;
1575                         }
1576                 }
1577                 hws->funcs.update_mpcc(dc, pipe_ctx);
1578         }
1579
1580         if (pipe_ctx->update_flags.bits.scaler ||
1581                         plane_state->update_flags.bits.scaling_change ||
1582                         plane_state->update_flags.bits.position_change ||
1583                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1584                         pipe_ctx->stream->update_flags.bits.scaling) {
1585                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1586                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
1587                 /* scaler configuration */
1588                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1589                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1590         }
1591
1592         if (pipe_ctx->update_flags.bits.viewport ||
1593                         (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1594                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1595                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1596
1597                 hubp->funcs->mem_program_viewport(
1598                         hubp,
1599                         &pipe_ctx->plane_res.scl_data.viewport,
1600                         &pipe_ctx->plane_res.scl_data.viewport_c);
1601                 viewport_changed = true;
1602         }
1603
1604         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1605         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1606                         pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1607                         pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1608                 dc->hwss.set_cursor_position(pipe_ctx);
1609                 dc->hwss.set_cursor_attribute(pipe_ctx);
1610
1611                 if (dc->hwss.set_cursor_sdr_white_level)
1612                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1613         }
1614
1615         /* Any updates are handled in dc interface, just need
1616          * to apply existing for plane enable / opp change */
1617         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1618                         || pipe_ctx->update_flags.bits.plane_changed
1619                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1620                         || plane_state->update_flags.bits.gamut_remap_change
1621                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1622                 /* dpp/cm gamut remap*/
1623                 dc->hwss.program_gamut_remap(pipe_ctx);
1624
1625                 /*call the dcn2 method which uses mpc csc*/
1626                 dc->hwss.program_output_csc(dc,
1627                                 pipe_ctx,
1628                                 pipe_ctx->stream->output_color_space,
1629                                 pipe_ctx->stream->csc_color_matrix.matrix,
1630                                 hubp->opp_id);
1631         }
1632
1633         if (pipe_ctx->update_flags.bits.enable ||
1634                         pipe_ctx->update_flags.bits.plane_changed ||
1635                         pipe_ctx->update_flags.bits.opp_changed ||
1636                         plane_state->update_flags.bits.pixel_format_change ||
1637                         plane_state->update_flags.bits.horizontal_mirror_change ||
1638                         plane_state->update_flags.bits.rotation_change ||
1639                         plane_state->update_flags.bits.swizzle_change ||
1640                         plane_state->update_flags.bits.dcc_change ||
1641                         plane_state->update_flags.bits.bpp_change ||
1642                         plane_state->update_flags.bits.scaling_change ||
1643                         plane_state->update_flags.bits.plane_size_change) {
1644                 struct plane_size size = plane_state->plane_size;
1645
1646                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1647                 hubp->funcs->hubp_program_surface_config(
1648                         hubp,
1649                         plane_state->format,
1650                         &plane_state->tiling_info,
1651                         &size,
1652                         plane_state->rotation,
1653                         &plane_state->dcc,
1654                         plane_state->horizontal_mirror,
1655                         0);
1656                 hubp->power_gated = false;
1657         }
1658
1659         if (pipe_ctx->update_flags.bits.enable ||
1660                 pipe_ctx->update_flags.bits.plane_changed ||
1661                 plane_state->update_flags.bits.addr_update) {
1662                 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&
1663                                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
1664                         union block_sequence_params params;
1665
1666                         params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
1667                         params.subvp_save_surf_addr.addr = &pipe_ctx->plane_state->address;
1668                         params.subvp_save_surf_addr.subvp_index = pipe_ctx->subvp_index;
1669                         hwss_subvp_save_surf_addr(&params);
1670                 }
1671                 hws->funcs.update_plane_addr(dc, pipe_ctx);
1672         }
1673
1674         if (pipe_ctx->update_flags.bits.enable)
1675                 hubp->funcs->set_blank(hubp, false);
1676         /* If the stream paired with this plane is phantom, the plane is also phantom */
1677         if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
1678                         && hubp->funcs->phantom_hubp_post_enable)
1679                 hubp->funcs->phantom_hubp_post_enable(hubp);
1680 }
1681
1682 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)
1683 {
1684         struct pipe_ctx *other_pipe;
1685         int vready_offset = pipe->pipe_dlg_param.vready_offset;
1686
1687         /* Always use the largest vready_offset of all connected pipes */
1688         for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {
1689                 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1690                         vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1691         }
1692         for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {
1693                 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1694                         vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1695         }
1696         for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {
1697                 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1698                         vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1699         }
1700         for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {
1701                 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1702                         vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1703         }
1704
1705         return vready_offset;
1706 }
1707
1708 static void dcn20_program_pipe(
1709                 struct dc *dc,
1710                 struct pipe_ctx *pipe_ctx,
1711                 struct dc_state *context)
1712 {
1713         struct dce_hwseq *hws = dc->hwseq;
1714
1715         /* Only need to unblank on top pipe */
1716         if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {
1717                 if (pipe_ctx->update_flags.bits.enable ||
1718                                 pipe_ctx->update_flags.bits.odm ||
1719                                 pipe_ctx->stream->update_flags.bits.abm_level)
1720                         hws->funcs.blank_pixel_data(dc, pipe_ctx,
1721                                         !pipe_ctx->plane_state ||
1722                                         !pipe_ctx->plane_state->visible);
1723         }
1724
1725         /* Only update TG on top pipe */
1726         if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1727                         && !pipe_ctx->prev_odm_pipe) {
1728                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1729                                 pipe_ctx->stream_res.tg,
1730                                 calculate_vready_offset_for_group(pipe_ctx),
1731                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1732                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1733                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1734
1735                 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM)
1736                         pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1737
1738                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1739                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1740
1741                 if (hws->funcs.setup_vupdate_interrupt)
1742                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1743         }
1744
1745         if (pipe_ctx->update_flags.bits.odm)
1746                 hws->funcs.update_odm(dc, context, pipe_ctx);
1747
1748         if (pipe_ctx->update_flags.bits.enable) {
1749                 dcn20_enable_plane(dc, pipe_ctx, context);
1750                 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1751                         dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1752         }
1753
1754         if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1755                 dc->res_pool->hubbub->funcs->program_det_size(
1756                         dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
1757
1758         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1759                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1760
1761         if (pipe_ctx->update_flags.bits.enable
1762                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1763                 hws->funcs.set_hdr_multiplier(pipe_ctx);
1764
1765         if (pipe_ctx->update_flags.bits.enable ||
1766             pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1767             pipe_ctx->plane_state->update_flags.bits.gamma_change ||
1768             pipe_ctx->plane_state->update_flags.bits.lut_3d)
1769                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1770
1771         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1772          * only do gamma programming for powering on, internal memcmp to avoid
1773          * updating on slave planes
1774          */
1775         if (pipe_ctx->update_flags.bits.enable ||
1776                         pipe_ctx->update_flags.bits.plane_changed ||
1777                         pipe_ctx->stream->update_flags.bits.out_tf ||
1778                         pipe_ctx->plane_state->update_flags.bits.output_tf_change)
1779                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1780
1781         /* If the pipe has been enabled or has a different opp, we
1782          * should reprogram the fmt. This deals with cases where
1783          * interation between mpc and odm combine on different streams
1784          * causes a different pipe to be chosen to odm combine with.
1785          */
1786         if (pipe_ctx->update_flags.bits.enable
1787             || pipe_ctx->update_flags.bits.opp_changed) {
1788
1789                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1790                         pipe_ctx->stream_res.opp,
1791                         COLOR_SPACE_YCBCR601,
1792                         pipe_ctx->stream->timing.display_color_depth,
1793                         pipe_ctx->stream->signal);
1794
1795                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1796                         pipe_ctx->stream_res.opp,
1797                         &pipe_ctx->stream->bit_depth_params,
1798                         &pipe_ctx->stream->clamping);
1799         }
1800
1801         /* Set ABM pipe after other pipe configurations done */
1802         if (pipe_ctx->plane_state->visible) {
1803                 if (pipe_ctx->stream_res.abm) {
1804                         dc->hwss.set_pipe(pipe_ctx);
1805                         pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,
1806                                 pipe_ctx->stream->abm_level);
1807                 }
1808         }
1809 }
1810
1811 void dcn20_program_front_end_for_ctx(
1812                 struct dc *dc,
1813                 struct dc_state *context)
1814 {
1815         int i;
1816         struct dce_hwseq *hws = dc->hwseq;
1817         DC_LOGGER_INIT(dc->ctx->logger);
1818
1819         /* Carry over GSL groups in case the context is changing. */
1820         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1821                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1822                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1823
1824                 if (pipe_ctx->stream == old_pipe_ctx->stream)
1825                         pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
1826         }
1827
1828         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1829                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1830                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1831
1832                         if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1833                                 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1834                                 /*turn off triple buffer for full update*/
1835                                 dc->hwss.program_triplebuffer(
1836                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1837                         }
1838                 }
1839         }
1840
1841         /* Set pipe update flags and lock pipes */
1842         for (i = 0; i < dc->res_pool->pipe_count; i++)
1843                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1844                                 &context->res_ctx.pipe_ctx[i]);
1845
1846         /* When disabling phantom pipes, turn on phantom OTG first (so we can get double
1847          * buffer updates properly)
1848          */
1849         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1850                 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
1851
1852                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&
1853                         dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1854                         struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
1855
1856                         if (tg->funcs->enable_crtc)
1857                                 tg->funcs->enable_crtc(tg);
1858                 }
1859         }
1860         /* OTG blank before disabling all front ends */
1861         for (i = 0; i < dc->res_pool->pipe_count; i++)
1862                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1863                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1864                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1865                                 && context->res_ctx.pipe_ctx[i].stream)
1866                         hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1867
1868
1869         /* Disconnect mpcc */
1870         for (i = 0; i < dc->res_pool->pipe_count; i++)
1871                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1872                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1873                         struct hubbub *hubbub = dc->res_pool->hubbub;
1874
1875                         /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom
1876                          * then we want to do the programming here (effectively it's being disabled). If we do
1877                          * the programming later the DET won't be updated until the OTG for the phantom pipe is
1878                          * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with
1879                          * DET allocation.
1880                          */
1881                         if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||
1882                                         (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom)))
1883                                 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
1884                         hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1885                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1886                 }
1887
1888         /*
1889          * Program all updated pipes, order matters for mpcc setup. Start with
1890          * top pipe and program all pipes that follow in order
1891          */
1892         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1893                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1894
1895                 if (pipe->plane_state && !pipe->top_pipe) {
1896                         while (pipe) {
1897                                 if (hws->funcs.program_pipe)
1898                                         hws->funcs.program_pipe(dc, pipe, context);
1899                                 else {
1900                                         /* Don't program phantom pipes in the regular front end programming sequence.
1901                                          * There is an MPO transition case where a pipe being used by a video plane is
1902                                          * transitioned directly to be a phantom pipe when closing the MPO video. However
1903                                          * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away),
1904                                          * but the MPO still exists until the double buffered update of the main pipe so we
1905                                          * will get a frame of underflow if the phantom pipe is programmed here.
1906                                          */
1907                                         if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM)
1908                                                 dcn20_program_pipe(dc, pipe, context);
1909                                 }
1910
1911                                 pipe = pipe->bottom_pipe;
1912                         }
1913                 }
1914                 /* Program secondary blending tree and writeback pipes */
1915                 pipe = &context->res_ctx.pipe_ctx[i];
1916                 if (!pipe->top_pipe && !pipe->prev_odm_pipe
1917                                 && pipe->stream && pipe->stream->num_wb_info > 0
1918                                 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1919                                         || pipe->stream->update_flags.raw)
1920                                 && hws->funcs.program_all_writeback_pipes_in_tree)
1921                         hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1922
1923                 /* Avoid underflow by check of pipe line read when adding 2nd plane. */
1924                 if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1925                         !pipe->top_pipe &&
1926                         pipe->stream &&
1927                         pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1928                         dc->current_state->stream_status[0].plane_count == 1 &&
1929                         context->stream_status[0].plane_count > 1) {
1930                         pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1931                 }
1932
1933                 /* when dynamic ODM is active, pipes must be reconfigured when all planes are
1934                  * disabled, as some transitions will leave software and hardware state
1935                  * mismatched.
1936                  */
1937                 if (dc->debug.enable_single_display_2to1_odm_policy &&
1938                         pipe->stream &&
1939                         pipe->update_flags.bits.disable &&
1940                         !pipe->prev_odm_pipe &&
1941                         hws->funcs.update_odm)
1942                         hws->funcs.update_odm(dc, context, pipe);
1943         }
1944 }
1945
1946 void dcn20_post_unlock_program_front_end(
1947                 struct dc *dc,
1948                 struct dc_state *context)
1949 {
1950         int i;
1951         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_US = 100000;
1952         unsigned int polling_interval_us = 1;
1953         struct dce_hwseq *hwseq = dc->hwseq;
1954
1955         DC_LOGGER_INIT(dc->ctx->logger);
1956
1957         for (i = 0; i < dc->res_pool->pipe_count; i++)
1958                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1959                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1960
1961         /*
1962          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1963          * part of the enable operation otherwise, DM may request an immediate flip which
1964          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1965          * is unsupported on DCN.
1966          */
1967         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1968                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1969                 // Don't check flip pending on phantom pipes
1970                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&
1971                                 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1972                         struct hubp *hubp = pipe->plane_res.hubp;
1973                         int j = 0;
1974                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us
1975                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1976                                 udelay(polling_interval_us);
1977                 }
1978         }
1979
1980         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1981                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1982
1983                 if (pipe->plane_state && !pipe->top_pipe) {
1984                         /* Program phantom pipe here to prevent a frame of underflow in the MPO transition
1985                          * case (if a pipe being used for a video plane transitions to a phantom pipe, it
1986                          * can underflow due to HUBP_VTG_SEL programming if done in the regular front end
1987                          * programming sequence).
1988                          */
1989                         while (pipe) {
1990                                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1991                                         /* When turning on the phantom pipe we want to run through the
1992                                          * entire enable sequence, so apply all the "enable" flags.
1993                                          */
1994                                         if (dc->hwss.apply_update_flags_for_phantom)
1995                                                 dc->hwss.apply_update_flags_for_phantom(pipe);
1996                                         if (dc->hwss.update_phantom_vp_position)
1997                                                 dc->hwss.update_phantom_vp_position(dc, context, pipe);
1998                                         dcn20_program_pipe(dc, pipe, context);
1999                                 }
2000                                 pipe = pipe->bottom_pipe;
2001                         }
2002                 }
2003         }
2004
2005         /* P-State support transitions:
2006          * Natural -> FPO:              P-State disabled in prepare, force disallow anytime is safe
2007          * FPO -> Natural:              Unforce anytime after FW disable is safe (P-State will assert naturally)
2008          * Unsupported -> FPO:  P-State enabled in optimize, force disallow anytime is safe
2009          * FPO -> Unsupported:  P-State disabled in prepare, unforce disallow anytime is safe
2010          * FPO <-> SubVP:               Force disallow is maintained on the FPO / SubVP pipes
2011          */
2012         if (hwseq && hwseq->funcs.update_force_pstate)
2013                 dc->hwseq->funcs.update_force_pstate(dc, context);
2014
2015         /* Only program the MALL registers after all the main and phantom pipes
2016          * are done programming.
2017          */
2018         if (hwseq->funcs.program_mall_pipe_config)
2019                 hwseq->funcs.program_mall_pipe_config(dc, context);
2020
2021         /* WA to apply WM setting*/
2022         if (hwseq->wa.DEGVIDCN21)
2023                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
2024
2025
2026         /* WA for stutter underflow during MPO transitions when adding 2nd plane */
2027         if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
2028
2029                 if (dc->current_state->stream_status[0].plane_count == 1 &&
2030                                 context->stream_status[0].plane_count > 1) {
2031
2032                         struct timing_generator *tg = dc->res_pool->timing_generators[0];
2033
2034                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
2035
2036                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
2037                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
2038                 }
2039         }
2040 }
2041
2042 void dcn20_prepare_bandwidth(
2043                 struct dc *dc,
2044                 struct dc_state *context)
2045 {
2046         struct hubbub *hubbub = dc->res_pool->hubbub;
2047         unsigned int compbuf_size_kb = 0;
2048         unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;
2049         unsigned int i;
2050
2051         dc->clk_mgr->funcs->update_clocks(
2052                         dc->clk_mgr,
2053                         context,
2054                         false);
2055
2056         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2057                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2058
2059                 // At optimize don't restore the original watermark value
2060                 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2061                         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2062                         break;
2063                 }
2064         }
2065
2066         /* program dchubbub watermarks:
2067          * For assigning wm_optimized_required, use |= operator since we don't want
2068          * to clear the value if the optimize has not happened yet
2069          */
2070         dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub,
2071                                         &context->bw_ctx.bw.dcn.watermarks,
2072                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2073                                         false);
2074
2075         // Restore the real watermark so we can commit the value to DMCUB
2076         // DMCUB uses the "original" watermark value in SubVP MCLK switch
2077         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;
2078
2079         /* decrease compbuf size */
2080         if (hubbub->funcs->program_compbuf_size) {
2081                 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {
2082                         compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
2083                         dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);
2084                 } else {
2085                         compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
2086                         dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
2087                 }
2088
2089                 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
2090         }
2091 }
2092
2093 void dcn20_optimize_bandwidth(
2094                 struct dc *dc,
2095                 struct dc_state *context)
2096 {
2097         struct hubbub *hubbub = dc->res_pool->hubbub;
2098         int i;
2099
2100         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2101                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2102
2103                 // At optimize don't need  to restore the original watermark value
2104                 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2105                         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2106                         break;
2107                 }
2108         }
2109
2110         /* program dchubbub watermarks */
2111         hubbub->funcs->program_watermarks(hubbub,
2112                                         &context->bw_ctx.bw.dcn.watermarks,
2113                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2114                                         true);
2115
2116         if (dc->clk_mgr->dc_mode_softmax_enabled)
2117                 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
2118                                 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
2119                         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
2120
2121         /* increase compbuf size */
2122         if (hubbub->funcs->program_compbuf_size)
2123                 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
2124
2125         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2126                 dc_dmub_srv_p_state_delegate(dc,
2127                         true, context);
2128                 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2129                 dc->clk_mgr->clks.fw_based_mclk_switching = true;
2130         } else {
2131                 dc->clk_mgr->clks.fw_based_mclk_switching = false;
2132         }
2133
2134         dc->clk_mgr->funcs->update_clocks(
2135                         dc->clk_mgr,
2136                         context,
2137                         true);
2138         if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
2139                 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
2140                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2141
2142                         if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank
2143                                 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max
2144                                 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
2145                                         pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,
2146                                                 pipe_ctx->dlg_regs.min_dst_y_next_start);
2147                 }
2148         }
2149 }
2150
2151 bool dcn20_update_bandwidth(
2152                 struct dc *dc,
2153                 struct dc_state *context)
2154 {
2155         int i;
2156         struct dce_hwseq *hws = dc->hwseq;
2157
2158         /* recalculate DML parameters */
2159         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
2160                 return false;
2161
2162         /* apply updated bandwidth parameters */
2163         dc->hwss.prepare_bandwidth(dc, context);
2164
2165         /* update hubp configs for all pipes */
2166         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2167                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2168
2169                 if (pipe_ctx->plane_state == NULL)
2170                         continue;
2171
2172                 if (pipe_ctx->top_pipe == NULL) {
2173                         bool blank = !is_pipe_tree_visible(pipe_ctx);
2174
2175                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
2176                                         pipe_ctx->stream_res.tg,
2177                                         calculate_vready_offset_for_group(pipe_ctx),
2178                                         pipe_ctx->pipe_dlg_param.vstartup_start,
2179                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
2180                                         pipe_ctx->pipe_dlg_param.vupdate_width);
2181
2182                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2183                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
2184
2185                         if (pipe_ctx->prev_odm_pipe == NULL)
2186                                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
2187
2188                         if (hws->funcs.setup_vupdate_interrupt)
2189                                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
2190                 }
2191
2192                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
2193                                 pipe_ctx->plane_res.hubp,
2194                                         &pipe_ctx->dlg_regs,
2195                                         &pipe_ctx->ttu_regs,
2196                                         &pipe_ctx->rq_regs,
2197                                         &pipe_ctx->pipe_dlg_param);
2198         }
2199
2200         return true;
2201 }
2202
2203 void dcn20_enable_writeback(
2204                 struct dc *dc,
2205                 struct dc_writeback_info *wb_info,
2206                 struct dc_state *context)
2207 {
2208         struct dwbc *dwb;
2209         struct mcif_wb *mcif_wb;
2210         struct timing_generator *optc;
2211
2212         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
2213         ASSERT(wb_info->wb_enabled);
2214         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
2215         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
2216
2217         /* set the OPTC source mux */
2218         optc = dc->res_pool->timing_generators[dwb->otg_inst];
2219         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
2220         /* set MCIF_WB buffer and arbitration configuration */
2221         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
2222         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
2223         /* Enable MCIF_WB */
2224         mcif_wb->funcs->enable_mcif(mcif_wb);
2225         /* Enable DWB */
2226         dwb->funcs->enable(dwb, &wb_info->dwb_params);
2227         /* TODO: add sequence to enable/disable warmup */
2228 }
2229
2230 void dcn20_disable_writeback(
2231                 struct dc *dc,
2232                 unsigned int dwb_pipe_inst)
2233 {
2234         struct dwbc *dwb;
2235         struct mcif_wb *mcif_wb;
2236
2237         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
2238         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
2239         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
2240
2241         dwb->funcs->disable(dwb);
2242         mcif_wb->funcs->disable_mcif(mcif_wb);
2243 }
2244
2245 bool dcn20_wait_for_blank_complete(
2246                 struct output_pixel_processor *opp)
2247 {
2248         int counter;
2249
2250         for (counter = 0; counter < 1000; counter++) {
2251                 if (opp->funcs->dpg_is_blanked(opp))
2252                         break;
2253
2254                 udelay(100);
2255         }
2256
2257         if (counter == 1000) {
2258                 dm_error("DC: failed to blank crtc!\n");
2259                 return false;
2260         }
2261
2262         return true;
2263 }
2264
2265 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
2266 {
2267         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2268
2269         if (!hubp)
2270                 return false;
2271         return hubp->funcs->dmdata_status_done(hubp);
2272 }
2273
2274 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2275 {
2276         struct dce_hwseq *hws = dc->hwseq;
2277
2278         if (pipe_ctx->stream_res.dsc) {
2279                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2280
2281                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
2282                 while (odm_pipe) {
2283                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
2284                         odm_pipe = odm_pipe->next_odm_pipe;
2285                 }
2286         }
2287 }
2288
2289 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2290 {
2291         struct dce_hwseq *hws = dc->hwseq;
2292
2293         if (pipe_ctx->stream_res.dsc) {
2294                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2295
2296                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
2297                 while (odm_pipe) {
2298                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
2299                         odm_pipe = odm_pipe->next_odm_pipe;
2300                 }
2301         }
2302 }
2303
2304 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2305 {
2306         struct dc_dmdata_attributes attr = { 0 };
2307         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2308
2309         attr.dmdata_mode = DMDATA_HW_MODE;
2310         attr.dmdata_size =
2311                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2312         attr.address.quad_part =
2313                         pipe_ctx->stream->dmdata_address.quad_part;
2314         attr.dmdata_dl_delta = 0;
2315         attr.dmdata_qos_mode = 0;
2316         attr.dmdata_qos_level = 0;
2317         attr.dmdata_repeat = 1; /* always repeat */
2318         attr.dmdata_updated = 1;
2319         attr.dmdata_sw_data = NULL;
2320
2321         hubp->funcs->dmdata_set_attributes(hubp, &attr);
2322 }
2323
2324 void dcn20_init_vm_ctx(
2325                 struct dce_hwseq *hws,
2326                 struct dc *dc,
2327                 struct dc_virtual_addr_space_config *va_config,
2328                 int vmid)
2329 {
2330         struct dcn_hubbub_virt_addr_config config;
2331
2332         if (vmid == 0) {
2333                 ASSERT(0); /* VMID cannot be 0 for vm context */
2334                 return;
2335         }
2336
2337         config.page_table_start_addr = va_config->page_table_start_addr;
2338         config.page_table_end_addr = va_config->page_table_end_addr;
2339         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2340         config.page_table_depth = va_config->page_table_depth;
2341         config.page_table_base_addr = va_config->page_table_base_addr;
2342
2343         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2344 }
2345
2346 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
2347 {
2348         struct dcn_hubbub_phys_addr_config config;
2349
2350         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2351         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2352         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2353         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2354         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2355         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2356         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2357         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2358         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
2359         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
2360
2361         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
2362 }
2363
2364 static bool patch_address_for_sbs_tb_stereo(
2365                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2366 {
2367         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2368         bool sec_split = pipe_ctx->top_pipe &&
2369                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2370         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2371                         (pipe_ctx->stream->timing.timing_3d_format ==
2372                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2373                         pipe_ctx->stream->timing.timing_3d_format ==
2374                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2375                 *addr = plane_state->address.grph_stereo.left_addr;
2376                 plane_state->address.grph_stereo.left_addr =
2377                                 plane_state->address.grph_stereo.right_addr;
2378                 return true;
2379         }
2380
2381         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2382                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2383                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2384                 plane_state->address.grph_stereo.right_addr =
2385                                 plane_state->address.grph_stereo.left_addr;
2386                 plane_state->address.grph_stereo.right_meta_addr =
2387                                 plane_state->address.grph_stereo.left_meta_addr;
2388         }
2389         return false;
2390 }
2391
2392 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2393 {
2394         bool addr_patched = false;
2395         PHYSICAL_ADDRESS_LOC addr;
2396         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2397
2398         if (plane_state == NULL)
2399                 return;
2400
2401         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2402
2403         // Call Helper to track VMID use
2404         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2405
2406         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2407                         pipe_ctx->plane_res.hubp,
2408                         &plane_state->address,
2409                         plane_state->flip_immediate);
2410
2411         plane_state->status.requested_address = plane_state->address;
2412
2413         if (plane_state->flip_immediate)
2414                 plane_state->status.current_address = plane_state->address;
2415
2416         if (addr_patched)
2417                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2418 }
2419
2420 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2421                 struct dc_link_settings *link_settings)
2422 {
2423         struct encoder_unblank_param params = {0};
2424         struct dc_stream_state *stream = pipe_ctx->stream;
2425         struct dc_link *link = stream->link;
2426         struct dce_hwseq *hws = link->dc->hwseq;
2427         struct pipe_ctx *odm_pipe;
2428
2429         params.opp_cnt = 1;
2430         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2431                 params.opp_cnt++;
2432         }
2433         /* only 3 items below are used by unblank */
2434         params.timing = pipe_ctx->stream->timing;
2435
2436         params.link_settings.link_rate = link_settings->link_rate;
2437
2438         if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
2439                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2440                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2441                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
2442                                 pipe_ctx->stream_res.tg->inst);
2443         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2444                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2445                         params.timing.pix_clk_100hz /= 2;
2446                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2447                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2448                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
2449         }
2450
2451         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2452                 hws->funcs.edp_backlight_control(link, true);
2453         }
2454 }
2455
2456 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2457 {
2458         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2459         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2460
2461         if (start_line < 0)
2462                 start_line = 0;
2463
2464         if (tg->funcs->setup_vertical_interrupt2)
2465                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2466 }
2467
2468 static void dcn20_reset_back_end_for_pipe(
2469                 struct dc *dc,
2470                 struct pipe_ctx *pipe_ctx,
2471                 struct dc_state *context)
2472 {
2473         int i;
2474         struct dc_link *link = pipe_ctx->stream->link;
2475         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2476
2477         DC_LOGGER_INIT(dc->ctx->logger);
2478         if (pipe_ctx->stream_res.stream_enc == NULL) {
2479                 pipe_ctx->stream = NULL;
2480                 return;
2481         }
2482
2483         /* DPMS may already disable or */
2484         /* dpms_off status is incorrect due to fastboot
2485          * feature. When system resume from S4 with second
2486          * screen only, the dpms_off would be true but
2487          * VBIOS lit up eDP, so check link status too.
2488          */
2489         if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2490                 dc->link_srv->set_dpms_off(pipe_ctx);
2491         else if (pipe_ctx->stream_res.audio)
2492                 dc->hwss.disable_audio_stream(pipe_ctx);
2493
2494         /* free acquired resources */
2495         if (pipe_ctx->stream_res.audio) {
2496                 /*disable az_endpoint*/
2497                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2498
2499                 /*free audio*/
2500                 if (dc->caps.dynamic_audio == true) {
2501                         /*we have to dynamic arbitrate the audio endpoints*/
2502                         /*we free the resource, need reset is_audio_acquired*/
2503                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2504                                         pipe_ctx->stream_res.audio, false);
2505                         pipe_ctx->stream_res.audio = NULL;
2506                 }
2507         }
2508
2509         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2510          * back end share by all pipes and will be disable only when disable
2511          * parent pipe.
2512          */
2513         if (pipe_ctx->top_pipe == NULL) {
2514
2515                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2516
2517                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2518
2519                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2520                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2521                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2522                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2523
2524                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2525                         pipe_ctx->stream_res.tg->funcs->set_drr(
2526                                         pipe_ctx->stream_res.tg, NULL);
2527                 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve
2528                  * the case where the same symclk is shared across multiple otg
2529                  * instances
2530                  */
2531                 link->phy_state.symclk_ref_cnts.otg = 0;
2532                 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
2533                         link_hwss->disable_link_output(link,
2534                                         &pipe_ctx->link_res, pipe_ctx->stream->signal);
2535                         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
2536                 }
2537         }
2538
2539         for (i = 0; i < dc->res_pool->pipe_count; i++)
2540                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2541                         break;
2542
2543         if (i == dc->res_pool->pipe_count)
2544                 return;
2545
2546         pipe_ctx->stream = NULL;
2547         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2548                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2549 }
2550
2551 void dcn20_reset_hw_ctx_wrap(
2552                 struct dc *dc,
2553                 struct dc_state *context)
2554 {
2555         int i;
2556         struct dce_hwseq *hws = dc->hwseq;
2557
2558         /* Reset Back End*/
2559         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2560                 struct pipe_ctx *pipe_ctx_old =
2561                         &dc->current_state->res_ctx.pipe_ctx[i];
2562                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2563
2564                 if (!pipe_ctx_old->stream)
2565                         continue;
2566
2567                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2568                         continue;
2569
2570                 if (!pipe_ctx->stream ||
2571                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2572                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2573
2574                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2575                         if (hws->funcs.enable_stream_gating)
2576                                 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
2577                         if (old_clk)
2578                                 old_clk->funcs->cs_power_down(old_clk);
2579                 }
2580         }
2581 }
2582
2583 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2584 {
2585         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2586         struct mpcc_blnd_cfg blnd_cfg = {0};
2587         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2588         int mpcc_id;
2589         struct mpcc *new_mpcc;
2590         struct mpc *mpc = dc->res_pool->mpc;
2591         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2592
2593         blnd_cfg.overlap_only = false;
2594         blnd_cfg.global_gain = 0xff;
2595
2596         if (per_pixel_alpha) {
2597                 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;
2598                 if (pipe_ctx->plane_state->global_alpha) {
2599                         blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2600                         blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2601                 } else {
2602                         blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2603                 }
2604         } else {
2605                 blnd_cfg.pre_multiplied_alpha = false;
2606                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2607         }
2608
2609         if (pipe_ctx->plane_state->global_alpha)
2610                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2611         else
2612                 blnd_cfg.global_alpha = 0xff;
2613
2614         blnd_cfg.background_color_bpc = 4;
2615         blnd_cfg.bottom_gain_mode = 0;
2616         blnd_cfg.top_gain = 0x1f000;
2617         blnd_cfg.bottom_inside_gain = 0x1f000;
2618         blnd_cfg.bottom_outside_gain = 0x1f000;
2619
2620         if (pipe_ctx->plane_state->format
2621                         == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2622                 blnd_cfg.pre_multiplied_alpha = false;
2623
2624         /*
2625          * TODO: remove hack
2626          * Note: currently there is a bug in init_hw such that
2627          * on resume from hibernate, BIOS sets up MPCC0, and
2628          * we do mpcc_remove but the mpcc cannot go to idle
2629          * after remove. This cause us to pick mpcc1 here,
2630          * which causes a pstate hang for yet unknown reason.
2631          */
2632         mpcc_id = hubp->inst;
2633
2634         /* If there is no full update, don't need to touch MPC tree*/
2635         if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2636                 !pipe_ctx->update_flags.bits.mpcc) {
2637                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2638                 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
2639                 return;
2640         }
2641
2642         /* check if this MPCC is already being used */
2643         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2644         /* remove MPCC if being used */
2645         if (new_mpcc != NULL)
2646                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2647         else
2648                 if (dc->debug.sanity_checks)
2649                         mpc->funcs->assert_mpcc_idle_before_connect(
2650                                         dc->res_pool->mpc, mpcc_id);
2651
2652         /* Call MPC to insert new plane */
2653         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2654                         mpc_tree_params,
2655                         &blnd_cfg,
2656                         NULL,
2657                         NULL,
2658                         hubp->inst,
2659                         mpcc_id);
2660         dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
2661
2662         ASSERT(new_mpcc != NULL);
2663         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2664         hubp->mpcc_id = mpcc_id;
2665 }
2666
2667 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
2668 {
2669         switch (link->link_enc->transmitter) {
2670         case TRANSMITTER_UNIPHY_A:
2671                 return PHYD32CLKA;
2672         case TRANSMITTER_UNIPHY_B:
2673                 return PHYD32CLKB;
2674         case TRANSMITTER_UNIPHY_C:
2675                 return PHYD32CLKC;
2676         case TRANSMITTER_UNIPHY_D:
2677                 return PHYD32CLKD;
2678         case TRANSMITTER_UNIPHY_E:
2679                 return PHYD32CLKE;
2680         default:
2681                 return PHYD32CLKA;
2682         }
2683 }
2684
2685 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
2686 {
2687         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2688         int count = 1;
2689
2690         while (odm_pipe != NULL) {
2691                 count++;
2692                 odm_pipe = odm_pipe->next_odm_pipe;
2693         }
2694
2695         return count;
2696 }
2697
2698 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2699 {
2700         enum dc_lane_count lane_count =
2701                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2702
2703         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2704         struct dc_link *link = pipe_ctx->stream->link;
2705
2706         uint32_t active_total_with_borders;
2707         uint32_t early_control = 0;
2708         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2709         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2710         struct dc *dc = pipe_ctx->stream->ctx->dc;
2711         struct dtbclk_dto_params dto_params = {0};
2712         struct dccg *dccg = dc->res_pool->dccg;
2713         enum phyd32clk_clock_source phyd32clk;
2714         int dp_hpo_inst;
2715         struct dce_hwseq *hws = dc->hwseq;
2716         unsigned int k1_div = PIXEL_RATE_DIV_NA;
2717         unsigned int k2_div = PIXEL_RATE_DIV_NA;
2718         struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
2719         struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2720
2721         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
2722                 if (dc->hwseq->funcs.setup_hpo_hw_control)
2723                         dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
2724         }
2725
2726         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
2727                 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
2728                 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
2729
2730                 phyd32clk = get_phyd32clk_src(link);
2731                 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
2732
2733                 dto_params.otg_inst = tg->inst;
2734                 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
2735                 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
2736                 dto_params.timing = &pipe_ctx->stream->timing;
2737                 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
2738                 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
2739         } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se)
2740                 dccg->funcs->enable_symclk_se(dccg,
2741                         stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);
2742
2743         if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
2744                 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
2745
2746                 dc->res_pool->dccg->funcs->set_pixel_rate_div(
2747                         dc->res_pool->dccg,
2748                         pipe_ctx->stream_res.tg->inst,
2749                         k1_div, k2_div);
2750         }
2751
2752         link_hwss->setup_stream_encoder(pipe_ctx);
2753
2754         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2755                 if (dc->hwss.program_dmdata_engine)
2756                         dc->hwss.program_dmdata_engine(pipe_ctx);
2757         }
2758
2759         dc->hwss.update_info_frame(pipe_ctx);
2760
2761         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2762                 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2763
2764         /* enable early control to avoid corruption on DP monitor*/
2765         active_total_with_borders =
2766                         timing->h_addressable
2767                                 + timing->h_border_left
2768                                 + timing->h_border_right;
2769
2770         if (lane_count != 0)
2771                 early_control = active_total_with_borders % lane_count;
2772
2773         if (early_control == 0)
2774                 early_control = lane_count;
2775
2776         tg->funcs->set_early_control(tg, early_control);
2777
2778         if (dc->hwseq->funcs.set_pixels_per_cycle)
2779                 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
2780 }
2781
2782 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2783 {
2784         struct dc_stream_state    *stream     = pipe_ctx->stream;
2785         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2786         bool                       enable     = false;
2787         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2788         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2789                                                         ? dmdata_dp
2790                                                         : dmdata_hdmi;
2791
2792         /* if using dynamic meta, don't set up generic infopackets */
2793         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2794                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2795                 enable = true;
2796         }
2797
2798         if (!hubp)
2799                 return;
2800
2801         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2802                 return;
2803
2804         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2805                                                 hubp->inst, mode);
2806 }
2807
2808 void dcn20_fpga_init_hw(struct dc *dc)
2809 {
2810         int i, j;
2811         struct dce_hwseq *hws = dc->hwseq;
2812         struct resource_pool *res_pool = dc->res_pool;
2813         struct dc_state  *context = dc->current_state;
2814
2815         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2816                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2817
2818         // Initialize the dccg
2819         if (res_pool->dccg->funcs->dccg_init)
2820                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2821
2822         //Enable ability to power gate / don't force power on permanently
2823         hws->funcs.enable_power_gating_plane(hws, true);
2824
2825         // Specific to FPGA dccg and registers
2826         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2827         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2828
2829         hws->funcs.dccg_init(hws);
2830
2831         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2832         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2833         if (REG(REFCLK_CNTL))
2834                 REG_WRITE(REFCLK_CNTL, 0);
2835         //
2836
2837
2838         /* Blank pixel data with OPP DPG */
2839         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2840                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2841
2842                 if (tg->funcs->is_tg_enabled(tg))
2843                         dcn20_init_blank(dc, tg);
2844         }
2845
2846         for (i = 0; i < res_pool->timing_generator_count; i++) {
2847                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2848
2849                 if (tg->funcs->is_tg_enabled(tg))
2850                         tg->funcs->lock(tg);
2851         }
2852
2853         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2854                 struct dpp *dpp = res_pool->dpps[i];
2855
2856                 dpp->funcs->dpp_reset(dpp);
2857         }
2858
2859         /* Reset all MPCC muxes */
2860         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2861
2862         /* initialize OPP mpc_tree parameter */
2863         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2864                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2865                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2866                 for (j = 0; j < MAX_PIPES; j++)
2867                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2868         }
2869
2870         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2871                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2872                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2873                 struct hubp *hubp = dc->res_pool->hubps[i];
2874                 struct dpp *dpp = dc->res_pool->dpps[i];
2875
2876                 pipe_ctx->stream_res.tg = tg;
2877                 pipe_ctx->pipe_idx = i;
2878
2879                 pipe_ctx->plane_res.hubp = hubp;
2880                 pipe_ctx->plane_res.dpp = dpp;
2881                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2882                 hubp->mpcc_id = dpp->inst;
2883                 hubp->opp_id = OPP_ID_INVALID;
2884                 hubp->power_gated = false;
2885                 pipe_ctx->stream_res.opp = NULL;
2886
2887                 hubp->funcs->hubp_init(hubp);
2888
2889                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2890                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2891                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2892                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2893                 /*to do*/
2894                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2895         }
2896
2897         /* initialize DWB pointer to MCIF_WB */
2898         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2899                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2900
2901         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2902                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2903
2904                 if (tg->funcs->is_tg_enabled(tg))
2905                         tg->funcs->unlock(tg);
2906         }
2907
2908         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2909                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2910
2911                 dc->hwss.disable_plane(dc, pipe_ctx);
2912
2913                 pipe_ctx->stream_res.tg = NULL;
2914                 pipe_ctx->plane_res.hubp = NULL;
2915         }
2916
2917         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2918                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2919
2920                 tg->funcs->tg_init(tg);
2921         }
2922
2923         if (dc->res_pool->hubbub->funcs->init_crb)
2924                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
2925 }
2926 #ifndef TRIM_FSFT
2927 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2928                 struct dc_crtc_timing *timing,
2929                 unsigned int max_input_rate_in_khz)
2930 {
2931         unsigned int old_v_front_porch;
2932         unsigned int old_v_total;
2933         unsigned int max_input_rate_in_100hz;
2934         unsigned long long new_v_total;
2935
2936         max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2937         if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2938                 return false;
2939
2940         old_v_total = timing->v_total;
2941         old_v_front_porch = timing->v_front_porch;
2942
2943         timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2944         timing->pix_clk_100hz = max_input_rate_in_100hz;
2945
2946         new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2947
2948         timing->v_total = new_v_total;
2949         timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2950         return true;
2951 }
2952 #endif
2953
2954 void dcn20_set_disp_pattern_generator(const struct dc *dc,
2955                 struct pipe_ctx *pipe_ctx,
2956                 enum controller_dp_test_pattern test_pattern,
2957                 enum controller_dp_color_space color_space,
2958                 enum dc_color_depth color_depth,
2959                 const struct tg_color *solid_color,
2960                 int width, int height, int offset)
2961 {
2962         pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2963                         color_space, color_depth, solid_color, width, height, offset);
2964 }