drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dm_helpers.h"
  28 #include "core_types.h"
  29 #include "resource.h"
  30 #include "dcn20/dcn20_resource.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dcn10/dcn10_hw_sequencer.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  36 #include "dcn20/dcn20_dsc.h"
  37 #endif
  38 #include "abm.h"
  39 #include "clk_mgr.h"
  40 #include "dmcu.h"
  41 #include "hubp.h"
  42 #include "timing_generator.h"
  43 #include "opp.h"
  44 #include "ipp.h"
  45 #include "mpc.h"
  46 #include "mcif_wb.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dcn10/dcn10_hubbub.h"
  50 #include "dcn10/dcn10_optc.h"
  51 #include "dc_link_dp.h"
  52 #include "vm_helper.h"
  53 #include "dccg.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61
  62 #undef FN
  63 #define FN(reg_name, field_name) \
  64         hws->shifts->field_name, hws->masks->field_name
  65
  66 static void bios_golden_init(struct dc *dc)
  67 {
  68         struct dc_bios *bp = dc->ctx->dc_bios;
  69         int i;
  70
  71         /* initialize dcn global */
  72         bp->funcs->enable_disp_power_gating(bp,
  73                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
  74
  75         for (i = 0; i < dc->res_pool->pipe_count; i++) {
  76                 /* initialize dcn per pipe */
  77                 bp->funcs->enable_disp_power_gating(bp,
  78                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
  79         }
  80 }
  81
  82 static void enable_power_gating_plane(
  83         struct dce_hwseq *hws,
  84         bool enable)
  85 {
  86         bool force_on = 1; /* disable power gating */
  87
  88         if (enable)
  89                 force_on = 0;
  90
  91         /* DCHUBP0/1/2/3/4/5 */
  92         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
  93         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
  94         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
  95         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
  96         REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
  97         /*Do not power gate DCHUB5, should be left at HW default, power on permanently*/
  98         /*REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, force_on);*/
  99
 100         /* DPP0/1/2/3/4/5 */
 101         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 102         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 103         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 104         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 105         REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 106         /*Do not power gate DPP5, should be left at HW default, power on permanently*/
 107         /*REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, force_on);*/
 108
 109         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 110         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 111         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 112         REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 113         REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 114         REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 115 }
 116
 117 static void dcn20_dccg_init(struct dce_hwseq *hws)
 118 {
 119         /*
 120          * set MICROSECOND_TIME_BASE_DIV
 121          * 100Mhz refclk -> 0x120264
 122          * 27Mhz refclk -> 0x12021b
 123          * 48Mhz refclk -> 0x120230
 124          *
 125          */
 126         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 127
 128         /*
 129          * set MILLISECOND_TIME_BASE_DIV
 130          * 100Mhz refclk -> 0x1186a0
 131          * 27Mhz refclk -> 0x106978
 132          * 48Mhz refclk -> 0x10bb80
 133          *
 134          */
 135         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 136
 137         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 138         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
 139 }
 140
 141 static void disable_vga(
 142         struct dce_hwseq *hws)
 143 {
 144         REG_WRITE(D1VGA_CONTROL, 0);
 145         REG_WRITE(D2VGA_CONTROL, 0);
 146         REG_WRITE(D3VGA_CONTROL, 0);
 147         REG_WRITE(D4VGA_CONTROL, 0);
 148         REG_WRITE(D5VGA_CONTROL, 0);
 149         REG_WRITE(D6VGA_CONTROL, 0);
 150 }
 151
 152 void dcn20_program_tripleBuffer(
 153         const struct dc *dc,
 154         struct pipe_ctx *pipe_ctx,
 155         bool enableTripleBuffer)
 156 {
 157         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 158                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 159                         pipe_ctx->plane_res.hubp,
 160                         enableTripleBuffer);
 161         }
 162 }
 163
 164 /* Blank pixel data during initialization */
 165 static void dcn20_init_blank(
 166                 struct dc *dc,
 167                 struct timing_generator *tg)
 168 {
 169         enum dc_color_space color_space;
 170         struct tg_color black_color = {0};
 171         struct output_pixel_processor *opp = NULL;
 172         struct output_pixel_processor *bottom_opp = NULL;
 173         uint32_t num_opps, opp_id_src0, opp_id_src1;
 174         uint32_t otg_active_width, otg_active_height;
 175
 176         /* program opp dpg blank color */
 177         color_space = COLOR_SPACE_SRGB;
 178         color_space_to_black_color(dc, color_space, &black_color);
 179
 180         /* get the OTG active size */
 181         tg->funcs->get_otg_active_size(tg,
 182                         &otg_active_width,
 183                         &otg_active_height);
 184
 185         /* get the OPTC source */
 186         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 187         ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
 188         opp = dc->res_pool->opps[opp_id_src0];
 189
 190         if (num_opps == 2) {
 191                 otg_active_width = otg_active_width / 2;
 192                 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
 193                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 194         }
 195
 196         opp->funcs->opp_set_disp_pattern_generator(
 197                         opp,
 198                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 199                         COLOR_DEPTH_UNDEFINED,
 200                         &black_color,
 201                         otg_active_width,
 202                         otg_active_height);
 203
 204         if (num_opps == 2) {
 205                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 206                                 bottom_opp,
 207                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 208                                 COLOR_DEPTH_UNDEFINED,
 209                                 &black_color,
 210                                 otg_active_width,
 211                                 otg_active_height);
 212         }
 213
 214         dcn20_hwss_wait_for_blank_complete(opp);
 215 }
 216
 217 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 218 static void dcn20_dsc_pg_control(
 219                 struct dce_hwseq *hws,
 220                 unsigned int dsc_inst,
 221                 bool power_on)
 222 {
 223         uint32_t power_gate = power_on ? 0 : 1;
 224         uint32_t pwr_status = power_on ? 0 : 2;
 225
 226         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 227                 return;
 228
 229         if (REG(DOMAIN16_PG_CONFIG) == 0)
 230                 return;
 231
 232         switch (dsc_inst) {
 233         case 0: /* DSC0 */
 234                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 235                                 DOMAIN16_POWER_GATE, power_gate);
 236
 237                 REG_WAIT(DOMAIN16_PG_STATUS,
 238                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 239                                 1, 1000);
 240                 break;
 241         case 1: /* DSC1 */
 242                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 243                                 DOMAIN17_POWER_GATE, power_gate);
 244
 245                 REG_WAIT(DOMAIN17_PG_STATUS,
 246                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 247                                 1, 1000);
 248                 break;
 249         case 2: /* DSC2 */
 250                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 251                                 DOMAIN18_POWER_GATE, power_gate);
 252
 253                 REG_WAIT(DOMAIN18_PG_STATUS,
 254                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 255                                 1, 1000);
 256                 break;
 257         case 3: /* DSC3 */
 258                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 259                                 DOMAIN19_POWER_GATE, power_gate);
 260
 261                 REG_WAIT(DOMAIN19_PG_STATUS,
 262                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 263                                 1, 1000);
 264                 break;
 265         case 4: /* DSC4 */
 266                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 267                                 DOMAIN20_POWER_GATE, power_gate);
 268
 269                 REG_WAIT(DOMAIN20_PG_STATUS,
 270                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 271                                 1, 1000);
 272                 break;
 273         case 5: /* DSC5 */
 274                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 275                                 DOMAIN21_POWER_GATE, power_gate);
 276
 277                 REG_WAIT(DOMAIN21_PG_STATUS,
 278                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 279                                 1, 1000);
 280                 break;
 281         default:
 282                 BREAK_TO_DEBUGGER();
 283                 break;
 284         }
 285 }
 286 #endif
 287
 288 static void dcn20_dpp_pg_control(
 289                 struct dce_hwseq *hws,
 290                 unsigned int dpp_inst,
 291                 bool power_on)
 292 {
 293         uint32_t power_gate = power_on ? 0 : 1;
 294         uint32_t pwr_status = power_on ? 0 : 2;
 295
 296         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 297                 return;
 298         if (REG(DOMAIN1_PG_CONFIG) == 0)
 299                 return;
 300
 301         switch (dpp_inst) {
 302         case 0: /* DPP0 */
 303                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 304                                 DOMAIN1_POWER_GATE, power_gate);
 305
 306                 REG_WAIT(DOMAIN1_PG_STATUS,
 307                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 308                                 1, 1000);
 309                 break;
 310         case 1: /* DPP1 */
 311                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 312                                 DOMAIN3_POWER_GATE, power_gate);
 313
 314                 REG_WAIT(DOMAIN3_PG_STATUS,
 315                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 316                                 1, 1000);
 317                 break;
 318         case 2: /* DPP2 */
 319                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 320                                 DOMAIN5_POWER_GATE, power_gate);
 321
 322                 REG_WAIT(DOMAIN5_PG_STATUS,
 323                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 324                                 1, 1000);
 325                 break;
 326         case 3: /* DPP3 */
 327                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 328                                 DOMAIN7_POWER_GATE, power_gate);
 329
 330                 REG_WAIT(DOMAIN7_PG_STATUS,
 331                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 332                                 1, 1000);
 333                 break;
 334         case 4: /* DPP4 */
 335                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 336                                 DOMAIN9_POWER_GATE, power_gate);
 337
 338                 REG_WAIT(DOMAIN9_PG_STATUS,
 339                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 340                                 1, 1000);
 341                 break;
 342         case 5: /* DPP5 */
 343                 /*
 344                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 345                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 346                  * reset.
 347                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 348                  *              DOMAIN11_POWER_GATE, power_gate);
 349                  *
 350                  * REG_WAIT(DOMAIN11_PG_STATUS,
 351                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 352                  *              1, 1000);
 353                  */
 354                 break;
 355         default:
 356                 BREAK_TO_DEBUGGER();
 357                 break;
 358         }
 359 }
 360
 361
 362 static void dcn20_hubp_pg_control(
 363                 struct dce_hwseq *hws,
 364                 unsigned int hubp_inst,
 365                 bool power_on)
 366 {
 367         uint32_t power_gate = power_on ? 0 : 1;
 368         uint32_t pwr_status = power_on ? 0 : 2;
 369
 370         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 371                 return;
 372         if (REG(DOMAIN0_PG_CONFIG) == 0)
 373                 return;
 374
 375         switch (hubp_inst) {
 376         case 0: /* DCHUBP0 */
 377                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 378                                 DOMAIN0_POWER_GATE, power_gate);
 379
 380                 REG_WAIT(DOMAIN0_PG_STATUS,
 381                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 382                                 1, 1000);
 383                 break;
 384         case 1: /* DCHUBP1 */
 385                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 386                                 DOMAIN2_POWER_GATE, power_gate);
 387
 388                 REG_WAIT(DOMAIN2_PG_STATUS,
 389                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 390                                 1, 1000);
 391                 break;
 392         case 2: /* DCHUBP2 */
 393                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 394                                 DOMAIN4_POWER_GATE, power_gate);
 395
 396                 REG_WAIT(DOMAIN4_PG_STATUS,
 397                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 398                                 1, 1000);
 399                 break;
 400         case 3: /* DCHUBP3 */
 401                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 402                                 DOMAIN6_POWER_GATE, power_gate);
 403
 404                 REG_WAIT(DOMAIN6_PG_STATUS,
 405                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 406                                 1, 1000);
 407                 break;
 408         case 4: /* DCHUBP4 */
 409                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 410                                 DOMAIN8_POWER_GATE, power_gate);
 411
 412                 REG_WAIT(DOMAIN8_PG_STATUS,
 413                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 414                                 1, 1000);
 415                 break;
 416         case 5: /* DCHUBP5 */
 417                 /*
 418                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 419                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 420                  * reset.
 421                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 422                  *              DOMAIN10_POWER_GATE, power_gate);
 423                  *
 424                  * REG_WAIT(DOMAIN10_PG_STATUS,
 425                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 426                  *              1, 1000);
 427                  */
 428                 break;
 429         default:
 430                 BREAK_TO_DEBUGGER();
 431                 break;
 432         }
 433 }
 434
 435
 436
 437 static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
 438 {
 439         struct dce_hwseq *hws = dc->hwseq;
 440         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 441
 442         DC_LOGGER_INIT(dc->ctx->logger);
 443
 444         if (REG(DC_IP_REQUEST_CNTL)) {
 445                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 446                                 IP_REQUEST_EN, 1);
 447                 dcn20_dpp_pg_control(hws, dpp->inst, false);
 448                 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
 449                 dpp->funcs->dpp_reset(dpp);
 450                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 451                                 IP_REQUEST_EN, 0);
 452                 DC_LOG_DEBUG(
 453                                 "Power gated front end %d\n", pipe_ctx->pipe_idx);
 454         }
 455 }
 456
 457
 458
 459 /* disable HW used by plane.
 460  * note:  cannot disable until disconnect is complete
 461  */
 462 static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 463 {
 464         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 465         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 466
 467         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 468
 469         /* In flip immediate with pipe splitting case GSL is used for
 470          * synchronization so we must disable it when the plane is disabled.
 471          */
 472         if (pipe_ctx->stream_res.gsl_group != 0)
 473                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 474
 475         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 476
 477         hubp->funcs->hubp_clk_cntl(hubp, false);
 478
 479         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 480
 481         hubp->power_gated = true;
 482         dc->optimized_required = false; /* We're powering off, no need to optimize */
 483
 484         dcn20_plane_atomic_power_down(dc, pipe_ctx);
 485
 486         pipe_ctx->stream = NULL;
 487         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 488         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 489         pipe_ctx->top_pipe = NULL;
 490         pipe_ctx->bottom_pipe = NULL;
 491         pipe_ctx->plane_state = NULL;
 492 }
 493
 494
 495 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 496 {
 497         DC_LOGGER_INIT(dc->ctx->logger);
 498
 499         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 500                 return;
 501
 502         dcn20_plane_atomic_disable(dc, pipe_ctx);
 503
 504         DC_LOG_DC("Power down front end %d\n",
 505                                         pipe_ctx->pipe_idx);
 506 }
 507
 508 static void dcn20_init_hw(struct dc *dc)
 509 {
 510         int i, j;
 511         struct abm *abm = dc->res_pool->abm;
 512         struct dmcu *dmcu = dc->res_pool->dmcu;
 513         struct dce_hwseq *hws = dc->hwseq;
 514         struct dc_bios *dcb = dc->ctx->dc_bios;
 515         struct resource_pool *res_pool = dc->res_pool;
 516         struct dc_state  *context = dc->current_state;
 517
 518         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 519                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 520
 521         // Initialize the dccg
 522         if (res_pool->dccg->funcs->dccg_init)
 523                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 524
 525         //Enable ability to power gate / don't force power on permanently
 526         enable_power_gating_plane(dc->hwseq, true);
 527
 528         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 529                 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
 530                 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
 531
 532                 dcn20_dccg_init(hws);
 533
 534                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
 535                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 536                 REG_WRITE(REFCLK_CNTL, 0);
 537         } else {
 538                 if (!dcb->funcs->is_accelerated_mode(dcb)) {
 539                         bios_golden_init(dc);
 540                         disable_vga(dc->hwseq);
 541                 }
 542
 543                 for (i = 0; i < dc->link_count; i++) {
 544                         /* Power up AND update implementation according to the
 545                          * required signal (which may be different from the
 546                          * default signal on connector).
 547                          */
 548                         struct dc_link *link = dc->links[i];
 549
 550                         link->link_enc->funcs->hw_init(link->link_enc);
 551                 }
 552         }
 553
 554         /* Blank pixel data with OPP DPG */
 555         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
 556                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 557
 558                 if (tg->funcs->is_tg_enabled(tg)) {
 559                         dcn20_init_blank(dc, tg);
 560                 }
 561         }
 562
 563         for (i = 0; i < res_pool->timing_generator_count; i++) {
 564                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 565
 566                 if (tg->funcs->is_tg_enabled(tg))
 567                         tg->funcs->lock(tg);
 568         }
 569
 570         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 571                 struct dpp *dpp = res_pool->dpps[i];
 572
 573                 dpp->funcs->dpp_reset(dpp);
 574         }
 575
 576         /* Reset all MPCC muxes */
 577         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
 578
 579         /* initialize OPP mpc_tree parameter */
 580         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
 581                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
 582                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 583                 for (j = 0; j < MAX_PIPES; j++)
 584                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
 585         }
 586
 587         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 588                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 589                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 590                 struct hubp *hubp = dc->res_pool->hubps[i];
 591                 struct dpp *dpp = dc->res_pool->dpps[i];
 592
 593                 pipe_ctx->stream_res.tg = tg;
 594                 pipe_ctx->pipe_idx = i;
 595
 596                 pipe_ctx->plane_res.hubp = hubp;
 597                 pipe_ctx->plane_res.dpp = dpp;
 598                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
 599                 hubp->mpcc_id = dpp->inst;
 600                 hubp->opp_id = 0xf;
 601                 hubp->power_gated = false;
 602                 pipe_ctx->stream_res.opp = NULL;
 603
 604                 hubp->funcs->hubp_init(hubp);
 605
 606                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 607                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 608                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 609                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 610                 /*to do*/
 611                 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
 612         }
 613
 614         /* initialize DWB pointer to MCIF_WB */
 615         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
 616                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
 617
 618         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
 619                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 620
 621                 if (tg->funcs->is_tg_enabled(tg))
 622                         tg->funcs->unlock(tg);
 623         }
 624
 625         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 626                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 627
 628                 dc->hwss.disable_plane(dc, pipe_ctx);
 629
 630                 pipe_ctx->stream_res.tg = NULL;
 631                 pipe_ctx->plane_res.hubp = NULL;
 632         }
 633
 634         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
 635                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 636
 637                 tg->funcs->tg_init(tg);
 638         }
 639
 640         /* end of FPGA. Below if real ASIC */
 641         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 642                 return;
 643
 644
 645         for (i = 0; i < res_pool->audio_count; i++) {
 646                 struct audio *audio = res_pool->audios[i];
 647
 648                 audio->funcs->hw_init(audio);
 649         }
 650
 651         if (abm != NULL) {
 652                 abm->funcs->init_backlight(abm);
 653                 abm->funcs->abm_init(abm);
 654         }
 655
 656         if (dmcu != NULL)
 657                 dmcu->funcs->dmcu_init(dmcu);
 658
 659         if (abm != NULL && dmcu != NULL)
 660                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
 661
 662         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 663         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 664
 665         if (!dc->debug.disable_clock_gate) {
 666                 /* enable all DCN clock gating */
 667                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 668
 669                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 670
 671                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 672         }
 673
 674 }
 675
 676 enum dc_status dcn20_enable_stream_timing(
 677                 struct pipe_ctx *pipe_ctx,
 678                 struct dc_state *context,
 679                 struct dc *dc)
 680 {
 681         struct dc_stream_state *stream = pipe_ctx->stream;
 682         enum dc_color_space color_space;
 683         struct tg_color black_color = {0};
 684         struct drr_params params = {0};
 685         unsigned int event_triggers = 0;
 686         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 687         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
 688         enum controller_dp_test_pattern dpg_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
 689
 690
 691 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 692         struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
 693 #endif
 694
 695         /* by upper caller loop, pipe0 is parent pipe and be called first.
 696          * back end is set up by for pipe0. Other children pipe share back end
 697          * with pipe 0. No program is needed.
 698          */
 699         if (pipe_ctx->top_pipe != NULL)
 700                 return DC_OK;
 701
 702         /* TODO check if timing_changed, disable stream if timing changed */
 703
 704         if (odm_pipe)
 705                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 706                                 pipe_ctx->stream_res.tg,
 707                                 odm_pipe->stream_res.opp->inst,
 708                                 pipe_ctx->stream->timing.h_addressable/2,
 709                                 pipe_ctx->stream->timing.pixel_encoding);
 710         /* HW program guide assume display already disable
 711          * by unplug sequence. OTG assume stop.
 712          */
 713         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 714
 715         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 716                         pipe_ctx->clock_source,
 717                         &pipe_ctx->stream_res.pix_clk_params,
 718                         &pipe_ctx->pll_settings)) {
 719                 BREAK_TO_DEBUGGER();
 720                 return DC_ERROR_UNEXPECTED;
 721         }
 722
 723         pipe_ctx->stream_res.tg->funcs->program_timing(
 724                         pipe_ctx->stream_res.tg,
 725                         &stream->timing,
 726                         pipe_ctx->pipe_dlg_param.vready_offset,
 727                         pipe_ctx->pipe_dlg_param.vstartup_start,
 728                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 729                         pipe_ctx->pipe_dlg_param.vupdate_width,
 730                         pipe_ctx->stream->signal,
 731                         true);
 732
 733         if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
 734                 pipe_ctx->stream_res.tg->funcs->setup_global_lock(
 735                                 pipe_ctx->stream_res.tg);
 736
 737         /* program otg blank color */
 738         color_space = stream->output_color_space;
 739         color_space_to_black_color(dc, color_space, &black_color);
 740
 741         if (odm_pipe) {
 742
 743                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
 744                         dpg_pattern = CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
 745
 746                 width /= 2;
 747
 748                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 749                                 odm_pipe->stream_res.opp,
 750                                 true);
 751
 752                 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
 753                                 odm_pipe->stream_res.opp,
 754                                 dpg_pattern,
 755                                 stream->timing.display_color_depth,
 756                                 &black_color,
 757                                 width,
 758                                 height);
 759         }
 760
 761         if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
 762                 dpg_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
 763
 764         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 765                         pipe_ctx->stream_res.opp,
 766                         true);
 767
 768         pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(
 769                         pipe_ctx->stream_res.opp,
 770                         dpg_pattern,
 771                         stream->timing.display_color_depth,
 772                         &black_color,
 773                         width,
 774                         height);
 775
 776         /* VTG is  within DCHUB command block. DCFCLK is always on */
 777         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 778                 BREAK_TO_DEBUGGER();
 779                 return DC_ERROR_UNEXPECTED;
 780         }
 781
 782         dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp);
 783
 784         params.vertical_total_min = stream->adjust.v_total_min;
 785         params.vertical_total_max = stream->adjust.v_total_max;
 786         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 787                 pipe_ctx->stream_res.tg->funcs->set_drr(
 788                         pipe_ctx->stream_res.tg, &params);
 789
 790         // DRR should set trigger event to monitor surface update event
 791         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 792                 event_triggers = 0x80;
 793         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 794                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 795                                 pipe_ctx->stream_res.tg, event_triggers);
 796
 797         /* TODO program crtc source select for non-virtual signal*/
 798         /* TODO program FMT */
 799         /* TODO setup link_enc */
 800         /* TODO set stream attributes */
 801         /* TODO program audio */
 802         /* TODO enable stream if timing changed */
 803         /* TODO unblank stream if DP */
 804
 805         return DC_OK;
 806 }
 807
 808 void dcn20_program_output_csc(struct dc *dc,
 809                 struct pipe_ctx *pipe_ctx,
 810                 enum dc_color_space colorspace,
 811                 uint16_t *matrix,
 812                 int opp_id)
 813 {
 814         struct mpc *mpc = dc->res_pool->mpc;
 815         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 816
 817         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 818                 if (mpc->funcs->set_output_csc != NULL)
 819                         mpc->funcs->set_output_csc(mpc,
 820                                         opp_id,
 821                                         matrix,
 822                                         ocsc_mode);
 823         } else {
 824                 if (mpc->funcs->set_ocsc_default != NULL)
 825                         mpc->funcs->set_ocsc_default(mpc,
 826                                         opp_id,
 827                                         colorspace,
 828                                         ocsc_mode);
 829         }
 830 }
 831
 832 bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 833                                 const struct dc_stream_state *stream)
 834 {
 835         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 836         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 837         struct pwl_params *params = NULL;
 838         /*
 839          * program OGAM only for the top pipe
 840          * if there is a pipe split then fix diagnostic is required:
 841          * how to pass OGAM parameter for stream.
 842          * if programming for all pipes is required then remove condition
 843          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 844          */
 845         if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx))
 846                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 847                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 848                         params = &stream->out_transfer_func->pwl;
 849                 else if (pipe_ctx->stream->out_transfer_func->type ==
 850                         TF_TYPE_DISTRIBUTED_POINTS &&
 851                         cm_helper_translate_curve_to_hw_format(
 852                         stream->out_transfer_func,
 853                         &mpc->blender_params, false))
 854                         params = &mpc->blender_params;
 855                 /*
 856                  * there is no ROM
 857                  */
 858                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 859                         BREAK_TO_DEBUGGER();
 860         }
 861         /*
 862          * if above if is not executed then 'params' equal to 0 and set in bypass
 863          */
 864         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 865
 866         return true;
 867 }
 868
 869 static bool dcn20_set_blend_lut(
 870         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 871 {
 872         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 873         bool result = true;
 874         struct pwl_params *blend_lut = NULL;
 875
 876         if (plane_state->blend_tf) {
 877                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 878                         blend_lut = &plane_state->blend_tf->pwl;
 879                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 880                         cm_helper_translate_curve_to_hw_format(
 881                                         plane_state->blend_tf,
 882                                         &dpp_base->regamma_params, false);
 883                         blend_lut = &dpp_base->regamma_params;
 884                 }
 885         }
 886         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 887
 888         return result;
 889 }
 890
 891 static bool dcn20_set_shaper_3dlut(
 892         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 893 {
 894         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 895         bool result = true;
 896         struct pwl_params *shaper_lut = NULL;
 897
 898         if (plane_state->in_shaper_func) {
 899                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 900                         shaper_lut = &plane_state->in_shaper_func->pwl;
 901                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 902                         cm_helper_translate_curve_to_hw_format(
 903                                         plane_state->in_shaper_func,
 904                                         &dpp_base->shaper_params, true);
 905                         shaper_lut = &dpp_base->shaper_params;
 906                 }
 907         }
 908
 909         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 910         if (plane_state->lut3d_func &&
 911                 plane_state->lut3d_func->initialized == true)
 912                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 913                                                                 &plane_state->lut3d_func->lut_3d);
 914         else
 915                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 916
 917         if (plane_state->lut3d_func &&
 918                 plane_state->lut3d_func->initialized == true &&
 919                 plane_state->lut3d_func->hdr_multiplier != 0)
 920                 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
 921                                 plane_state->lut3d_func->hdr_multiplier);
 922         else
 923                 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000);
 924
 925         return result;
 926 }
 927
 928 bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 929                                           const struct dc_plane_state *plane_state)
 930 {
 931         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 932         const struct dc_transfer_func *tf = NULL;
 933         bool result = true;
 934         bool use_degamma_ram = false;
 935
 936         if (dpp_base == NULL || plane_state == NULL)
 937                 return false;
 938
 939         dcn20_set_shaper_3dlut(pipe_ctx, plane_state);
 940         dcn20_set_blend_lut(pipe_ctx, plane_state);
 941
 942         if (plane_state->in_transfer_func)
 943                 tf = plane_state->in_transfer_func;
 944
 945
 946         if (tf == NULL) {
 947                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 948                                 IPP_DEGAMMA_MODE_BYPASS);
 949                 return true;
 950         }
 951
 952         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 953                 use_degamma_ram = true;
 954
 955         if (use_degamma_ram == true) {
 956                 if (tf->type == TF_TYPE_HWPWL)
 957                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 958                                         &tf->pwl);
 959                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 960                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 961                                         &dpp_base->degamma_params);
 962                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 963                                 &dpp_base->degamma_params);
 964                 }
 965                 return true;
 966         }
 967         /* handle here the optimized cases when de-gamma ROM could be used.
 968          *
 969          */
 970         if (tf->type == TF_TYPE_PREDEFINED) {
 971                 switch (tf->tf) {
 972                 case TRANSFER_FUNCTION_SRGB:
 973                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 974                                         IPP_DEGAMMA_MODE_HW_sRGB);
 975                         break;
 976                 case TRANSFER_FUNCTION_BT709:
 977                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 978                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 979                         break;
 980                 case TRANSFER_FUNCTION_LINEAR:
 981                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 982                                         IPP_DEGAMMA_MODE_BYPASS);
 983                         break;
 984                 case TRANSFER_FUNCTION_PQ:
 985                 default:
 986                         result = false;
 987                         break;
 988                 }
 989         } else if (tf->type == TF_TYPE_BYPASS)
 990                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 991                                 IPP_DEGAMMA_MODE_BYPASS);
 992         else {
 993                 /*
 994                  * if we are here, we did not handle correctly.
 995                  * fix is required for this use case
 996                  */
 997                 BREAK_TO_DEBUGGER();
 998                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 999                                 IPP_DEGAMMA_MODE_BYPASS);
1000         }
1001
1002         return result;
1003 }
1004
1005 static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1006 {
1007         struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1008
1009         if (combine_pipe)
1010                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1011                                 pipe_ctx->stream_res.tg,
1012                                 combine_pipe->stream_res.opp->inst,
1013                                 pipe_ctx->plane_res.scl_data.h_active,
1014                                 pipe_ctx->stream->timing.pixel_encoding);
1015         else
1016                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1017                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1018 }
1019
1020 void dcn20_blank_pixel_data(
1021                 struct dc *dc,
1022                 struct pipe_ctx *pipe_ctx,
1023                 bool blank)
1024 {
1025         enum dc_color_space color_space;
1026         struct tg_color black_color = {0};
1027         struct stream_resource *stream_res = &pipe_ctx->stream_res;
1028         struct dc_stream_state *stream = pipe_ctx->stream;
1029         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1030         struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1031
1032
1033         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1034         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1035
1036         /* program opp dpg blank color */
1037         color_space = stream->output_color_space;
1038         color_space_to_black_color(dc, color_space, &black_color);
1039
1040         if (bot_odm_pipe)
1041                 width = width / 2;
1042
1043         if (blank) {
1044                 if (stream_res->abm)
1045                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
1046         } else
1047                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1048
1049
1050         stream_res->opp->funcs->opp_set_disp_pattern_generator(
1051                         stream_res->opp,
1052                         test_pattern,
1053                         stream->timing.display_color_depth,
1054                         &black_color,
1055                         width,
1056                         height);
1057
1058         if (bot_odm_pipe) {
1059                 bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
1060                                 bot_odm_pipe->stream_res.opp,
1061                                 test_pattern,
1062                                 stream->timing.display_color_depth,
1063                                 &black_color,
1064                                 width,
1065                                 height);
1066         }
1067
1068         if (!blank)
1069                 if (stream_res->abm) {
1070                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
1071                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1072                 }
1073 }
1074
1075
1076 static void dcn20_power_on_plane(
1077         struct dce_hwseq *hws,
1078         struct pipe_ctx *pipe_ctx)
1079 {
1080         DC_LOGGER_INIT(hws->ctx->logger);
1081         if (REG(DC_IP_REQUEST_CNTL)) {
1082                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1083                                 IP_REQUEST_EN, 1);
1084                 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1085                 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1086                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1087                                 IP_REQUEST_EN, 0);
1088                 DC_LOG_DEBUG(
1089                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1090         }
1091 }
1092
1093 void dcn20_enable_plane(
1094         struct dc *dc,
1095         struct pipe_ctx *pipe_ctx,
1096         struct dc_state *context)
1097 {
1098         //if (dc->debug.sanity_checks) {
1099         //      dcn10_verify_allow_pstate_change_high(dc);
1100         //}
1101         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1102
1103         /* enable DCFCLK current DCHUB */
1104         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1105
1106         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1107         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1108                         pipe_ctx->stream_res.opp,
1109                         true);
1110
1111 /* TODO: enable/disable in dm as per update type.
1112         if (plane_state) {
1113                 DC_LOG_DC(dc->ctx->logger,
1114                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1115                                 "addr low:0x%x, "
1116                                 "src: %d, %d, %d,"
1117                                 " %d; dst: %d, %d, %d, %d;\n",
1118                                 pipe_ctx->pipe_idx,
1119                                 plane_state,
1120                                 plane_state->address.grph.addr.high_part,
1121                                 plane_state->address.grph.addr.low_part,
1122                                 plane_state->src_rect.x,
1123                                 plane_state->src_rect.y,
1124                                 plane_state->src_rect.width,
1125                                 plane_state->src_rect.height,
1126                                 plane_state->dst_rect.x,
1127                                 plane_state->dst_rect.y,
1128                                 plane_state->dst_rect.width,
1129                                 plane_state->dst_rect.height);
1130
1131                 DC_LOG_DC(dc->ctx->logger,
1132                                 "Pipe %d: width, height, x, y         format:%d\n"
1133                                 "viewport:%d, %d, %d, %d\n"
1134                                 "recout:  %d, %d, %d, %d\n",
1135                                 pipe_ctx->pipe_idx,
1136                                 plane_state->format,
1137                                 pipe_ctx->plane_res.scl_data.viewport.width,
1138                                 pipe_ctx->plane_res.scl_data.viewport.height,
1139                                 pipe_ctx->plane_res.scl_data.viewport.x,
1140                                 pipe_ctx->plane_res.scl_data.viewport.y,
1141                                 pipe_ctx->plane_res.scl_data.recout.width,
1142                                 pipe_ctx->plane_res.scl_data.recout.height,
1143                                 pipe_ctx->plane_res.scl_data.recout.x,
1144                                 pipe_ctx->plane_res.scl_data.recout.y);
1145                 print_rq_dlg_ttu(dc, pipe_ctx);
1146         }
1147 */
1148         if (dc->vm_config.valid) {
1149                 struct vm_system_aperture_param apt;
1150
1151                 apt.sys_default.quad_part = 0;
1152                 apt.sys_high.quad_part = 0;
1153                 apt.sys_low.quad_part = 0;
1154
1155                 apt.sys_high.quad_part = dc->vm_config.pa_config.system_aperture.start_addr;
1156                 apt.sys_low.quad_part = dc->vm_config.pa_config.system_aperture.end_addr;
1157
1158                 // Program system aperture settings
1159                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1160         }
1161
1162 //      if (dc->debug.sanity_checks) {
1163 //              dcn10_verify_allow_pstate_change_high(dc);
1164 //      }
1165 }
1166
1167
1168 static void dcn20_program_pipe(
1169                 struct dc *dc,
1170                 struct pipe_ctx *pipe_ctx,
1171                 struct dc_state *context)
1172 {
1173         pipe_ctx->plane_state->update_flags.bits.full_update =
1174                         context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update;
1175
1176         if (pipe_ctx->plane_state->update_flags.bits.full_update)
1177                 dcn20_enable_plane(dc, pipe_ctx, context);
1178
1179         update_dchubp_dpp(dc, pipe_ctx, context);
1180
1181         set_hdr_multiplier(pipe_ctx);
1182
1183         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
1184                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1185                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1186                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1187
1188         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1189          * only do gamma programming for full update.
1190          * TODO: This can be further optimized/cleaned up
1191          * Always call this for now since it does memcmp inside before
1192          * doing heavy calculation and programming
1193          */
1194         if (pipe_ctx->plane_state->update_flags.bits.full_update)
1195                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1196 }
1197
1198 static void dcn20_program_all_pipe_in_tree(
1199                 struct dc *dc,
1200                 struct pipe_ctx *pipe_ctx,
1201                 struct dc_state *context)
1202 {
1203         if (pipe_ctx->top_pipe == NULL) {
1204                 bool blank = !is_pipe_tree_visible(pipe_ctx);
1205
1206                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1207                                 pipe_ctx->stream_res.tg,
1208                                 pipe_ctx->pipe_dlg_param.vready_offset,
1209                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1210                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1211                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1212
1213                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1214                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1215
1216                 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
1217
1218                 if (dc->hwss.update_odm)
1219                         dc->hwss.update_odm(dc, context, pipe_ctx);
1220         }
1221
1222         if (pipe_ctx->plane_state != NULL)
1223                 dcn20_program_pipe(dc, pipe_ctx, context);
1224
1225         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
1226                 dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1227 }
1228
1229 void dcn20_pipe_control_lock_global(
1230                 struct dc *dc,
1231                 struct pipe_ctx *pipe,
1232                 bool lock)
1233 {
1234         if (lock) {
1235                 pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
1236                                 pipe->stream_res.tg);
1237                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1238         } else {
1239                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1240                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1241                                 CRTC_STATE_VACTIVE);
1242                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1243                                 CRTC_STATE_VBLANK);
1244                 pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
1245                                 pipe->stream_res.tg);
1246         }
1247 }
1248
1249 void dcn20_pipe_control_lock(
1250         struct dc *dc,
1251         struct pipe_ctx *pipe,
1252         bool lock)
1253 {
1254         bool flip_immediate = false;
1255
1256         /* use TG master update lock to lock everything on the TG
1257          * therefore only top pipe need to lock
1258          */
1259         if (pipe->top_pipe)
1260                 return;
1261
1262         if (pipe->plane_state != NULL)
1263                 flip_immediate = pipe->plane_state->flip_immediate;
1264
1265         /* In flip immediate and pipe splitting case, we need to use GSL
1266          * for synchronization. Only do setup on locking and on flip type change.
1267          */
1268         if (lock && pipe->bottom_pipe != NULL)
1269                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1270                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1271                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1272
1273         if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1274                 if (lock)
1275                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1276                 else
1277                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1278         } else {
1279                 if (lock)
1280                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1281                 else
1282                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1283         }
1284 }
1285
1286 static void dcn20_apply_ctx_for_surface(
1287                 struct dc *dc,
1288                 const struct dc_stream_state *stream,
1289                 int num_planes,
1290                 struct dc_state *context)
1291 {
1292
1293         int i;
1294         struct timing_generator *tg;
1295         bool removed_pipe[6] = { false };
1296         bool interdependent_update = false;
1297         struct pipe_ctx *top_pipe_to_program =
1298                         find_top_pipe_for_stream(dc, context, stream);
1299         DC_LOGGER_INIT(dc->ctx->logger);
1300
1301         if (!top_pipe_to_program)
1302                 return;
1303
1304         tg = top_pipe_to_program->stream_res.tg;
1305
1306         interdependent_update = top_pipe_to_program->plane_state &&
1307                 top_pipe_to_program->plane_state->update_flags.bits.full_update;
1308
1309         if (interdependent_update)
1310                 lock_all_pipes(dc, context, true);
1311         else
1312                 dcn20_pipe_control_lock(dc, top_pipe_to_program, true);
1313
1314         if (num_planes == 0) {
1315                 /* OTG blank before remove all front end */
1316                 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
1317         }
1318
1319         /* Disconnect unused mpcc */
1320         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1321                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1322                 struct pipe_ctx *old_pipe_ctx =
1323                                 &dc->current_state->res_ctx.pipe_ctx[i];
1324                 /*
1325                  * Powergate reused pipes that are not powergated
1326                  * fairly hacky right now, using opp_id as indicator
1327                  * TODO: After move dc_post to dc_update, this will
1328                  * be removed.
1329                  */
1330                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1331                         if (old_pipe_ctx->stream_res.tg == tg &&
1332                             old_pipe_ctx->plane_res.hubp &&
1333                             old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
1334                                 dcn20_disable_plane(dc, old_pipe_ctx);
1335                 }
1336
1337                 if ((!pipe_ctx->plane_state ||
1338                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
1339                      old_pipe_ctx->plane_state &&
1340                      old_pipe_ctx->stream_res.tg == tg) {
1341
1342                         dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
1343                         removed_pipe[i] = true;
1344
1345                         DC_LOG_DC("Reset mpcc for pipe %d\n",
1346                                         old_pipe_ctx->pipe_idx);
1347                 }
1348         }
1349
1350         if (num_planes > 0)
1351                 dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
1352
1353         /* Program secondary blending tree and writeback pipes */
1354         if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
1355                 dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
1356
1357         if (interdependent_update)
1358                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1359                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1360
1361                         /* Skip inactive pipes and ones already updated */
1362                         if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
1363                             !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
1364                                 continue;
1365
1366                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
1367                                 pipe_ctx->plane_res.hubp,
1368                                 &pipe_ctx->dlg_regs,
1369                                 &pipe_ctx->ttu_regs);
1370                 }
1371
1372         if (interdependent_update)
1373                 lock_all_pipes(dc, context, false);
1374         else
1375                 dcn20_pipe_control_lock(dc, top_pipe_to_program, false);
1376
1377         for (i = 0; i < dc->res_pool->pipe_count; i++)
1378                 if (removed_pipe[i])
1379                         dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1380 }
1381
1382
1383 void dcn20_prepare_bandwidth(
1384                 struct dc *dc,
1385                 struct dc_state *context)
1386 {
1387         struct hubbub *hubbub = dc->res_pool->hubbub;
1388
1389         /* program dchubbub watermarks */
1390         hubbub->funcs->program_watermarks(hubbub,
1391                                         &context->bw_ctx.bw.dcn.watermarks,
1392                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1393                                         false);
1394
1395         dc->clk_mgr->funcs->update_clocks(
1396                         dc->clk_mgr,
1397                         context,
1398                         false);
1399 }
1400
1401 void dcn20_optimize_bandwidth(
1402                 struct dc *dc,
1403                 struct dc_state *context)
1404 {
1405         struct hubbub *hubbub = dc->res_pool->hubbub;
1406
1407         /* program dchubbub watermarks */
1408         hubbub->funcs->program_watermarks(hubbub,
1409                                         &context->bw_ctx.bw.dcn.watermarks,
1410                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1411                                         true);
1412
1413         dc->clk_mgr->funcs->update_clocks(
1414                         dc->clk_mgr,
1415                         context,
1416                         true);
1417 }
1418
1419 bool dcn20_update_bandwidth(
1420                 struct dc *dc,
1421                 struct dc_state *context)
1422 {
1423         int i;
1424
1425         /* recalculate DML parameters */
1426         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1427                 return false;
1428
1429         /* apply updated bandwidth parameters */
1430         dc->hwss.prepare_bandwidth(dc, context);
1431
1432         /* update hubp configs for all pipes */
1433         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1434                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1435
1436                 if (pipe_ctx->plane_state == NULL)
1437                         continue;
1438
1439                 if (pipe_ctx->top_pipe == NULL) {
1440                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1441
1442                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1443                                         pipe_ctx->stream_res.tg,
1444                                         pipe_ctx->pipe_dlg_param.vready_offset,
1445                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1446                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1447                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1448
1449                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1450                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1451
1452                         dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
1453                 }
1454
1455                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1456                                 pipe_ctx->plane_res.hubp,
1457                                         &pipe_ctx->dlg_regs,
1458                                         &pipe_ctx->ttu_regs,
1459                                         &pipe_ctx->rq_regs,
1460                                         &pipe_ctx->pipe_dlg_param);
1461         }
1462
1463         return true;
1464 }
1465
1466 static void dcn20_enable_writeback(
1467                 struct dc *dc,
1468                 const struct dc_stream_status *stream_status,
1469                 struct dc_writeback_info *wb_info)
1470 {
1471         struct dwbc *dwb;
1472         struct mcif_wb *mcif_wb;
1473         struct timing_generator *optc;
1474
1475         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1476         ASSERT(wb_info->wb_enabled);
1477         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1478         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1479
1480         /* set the OPTC source mux */
1481         ASSERT(stream_status->primary_otg_inst < MAX_PIPES);
1482         optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst];
1483         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1484         /* set MCIF_WB buffer and arbitration configuration */
1485         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1486         mcif_wb->funcs->config_mcif_arb(mcif_wb, &dc->current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1487         /* Enable MCIF_WB */
1488         mcif_wb->funcs->enable_mcif(mcif_wb);
1489         /* Enable DWB */
1490         dwb->funcs->enable(dwb, &wb_info->dwb_params);
1491         /* TODO: add sequence to enable/disable warmup */
1492 }
1493
1494 void dcn20_disable_writeback(
1495                 struct dc *dc,
1496                 unsigned int dwb_pipe_inst)
1497 {
1498         struct dwbc *dwb;
1499         struct mcif_wb *mcif_wb;
1500
1501         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1502         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1503         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1504
1505         dwb->funcs->disable(dwb);
1506         mcif_wb->funcs->disable_mcif(mcif_wb);
1507 }
1508
1509 bool dcn20_hwss_wait_for_blank_complete(
1510                 struct output_pixel_processor *opp)
1511 {
1512         int counter;
1513
1514         for (counter = 0; counter < 1000; counter++) {
1515                 if (opp->funcs->dpg_is_blanked(opp))
1516                         break;
1517
1518                 udelay(100);
1519         }
1520
1521         if (counter == 1000) {
1522                 dm_error("DC: failed to blank crtc!\n");
1523                 return false;
1524         }
1525
1526         return true;
1527 }
1528
1529 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1530 {
1531         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1532
1533         if (!hubp)
1534                 return false;
1535         return hubp->funcs->dmdata_status_done(hubp);
1536 }
1537
1538 static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1539 {
1540 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1541         struct dce_hwseq *hws = dc->hwseq;
1542         struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1543
1544         if (pipe_ctx->stream_res.dsc) {
1545                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1546                 if (bot_odm_pipe)
1547                         dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true);
1548         }
1549 #endif
1550 }
1551
1552 static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1553 {
1554 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1555         struct dce_hwseq *hws = dc->hwseq;
1556         struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1557
1558         if (pipe_ctx->stream_res.dsc) {
1559                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1560                 if (bot_odm_pipe)
1561                         dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false);
1562         }
1563 #endif
1564 }
1565
1566 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1567 {
1568         struct dc_dmdata_attributes attr = { 0 };
1569         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1570
1571         attr.dmdata_mode = DMDATA_HW_MODE;
1572         attr.dmdata_size =
1573                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1574         attr.address.quad_part =
1575                         pipe_ctx->stream->dmdata_address.quad_part;
1576         attr.dmdata_dl_delta = 0;
1577         attr.dmdata_qos_mode = 0;
1578         attr.dmdata_qos_level = 0;
1579         attr.dmdata_repeat = 1; /* always repeat */
1580         attr.dmdata_updated = 1;
1581         attr.dmdata_sw_data = NULL;
1582
1583         hubp->funcs->dmdata_set_attributes(hubp, &attr);
1584 }
1585
1586 void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option)
1587 {
1588         dce110_disable_stream(pipe_ctx, option);
1589 }
1590
1591 static void dcn20_init_dchub(struct dce_hwseq *hws, struct dc *dc, struct dc_addr_space_config *config)
1592 {
1593         struct hubbub_addr_config hubbub_config;
1594
1595         hubbub_config.pa_config.system_aperture.fb_top = config->pa_config.system_aperture.fb_top;
1596         hubbub_config.pa_config.system_aperture.fb_offset = config->pa_config.system_aperture.fb_offset;
1597         hubbub_config.pa_config.system_aperture.fb_base = config->pa_config.system_aperture.fb_base;
1598         hubbub_config.pa_config.system_aperture.agp_top = config->pa_config.system_aperture.agp_top;
1599         hubbub_config.pa_config.system_aperture.agp_bot = config->pa_config.system_aperture.agp_bot;
1600         hubbub_config.pa_config.system_aperture.agp_base = config->pa_config.system_aperture.agp_base;
1601         hubbub_config.pa_config.gart_config.page_table_start_addr = config->pa_config.gart_config.page_table_start_addr;
1602         hubbub_config.pa_config.gart_config.page_table_end_addr = config->pa_config.gart_config.page_table_end_addr;
1603         hubbub_config.pa_config.gart_config.page_table_base_addr = config->pa_config.gart_config.page_table_base_addr;
1604
1605         hubbub_config.va_config.page_table_start_addr = config->va_config.page_table_start_addr;
1606         hubbub_config.va_config.page_table_end_addr = config->va_config.page_table_end_addr;
1607         hubbub_config.va_config.page_table_block_size = config->va_config.page_table_block_size_in_bytes;
1608         hubbub_config.va_config.page_table_depth = config->va_config.page_table_depth;
1609
1610         dc->res_pool->hubbub->funcs->init_dchub(dc->res_pool->hubbub, &hubbub_config);
1611 }
1612
1613 static bool patch_address_for_sbs_tb_stereo(
1614                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1615 {
1616         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1617         bool sec_split = pipe_ctx->top_pipe &&
1618                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1619         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1620                         (pipe_ctx->stream->timing.timing_3d_format ==
1621                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1622                         pipe_ctx->stream->timing.timing_3d_format ==
1623                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1624                 *addr = plane_state->address.grph_stereo.left_addr;
1625                 plane_state->address.grph_stereo.left_addr =
1626                                 plane_state->address.grph_stereo.right_addr;
1627                 return true;
1628         }
1629
1630         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1631                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1632                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1633                 plane_state->address.grph_stereo.right_addr =
1634                                 plane_state->address.grph_stereo.left_addr;
1635         }
1636         return false;
1637 }
1638
1639
1640 static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1641 {
1642         bool addr_patched = false;
1643         PHYSICAL_ADDRESS_LOC addr;
1644         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1645         uint8_t vmid;
1646
1647         if (plane_state == NULL)
1648                 return;
1649
1650         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1651
1652         // Call Helper to assign correct VMID to this PTB
1653         vmid = get_vmid_for_ptb(dc->vm_helper,
1654                         plane_state->address.page_table_base.quad_part,
1655                         pipe_ctx->pipe_idx);
1656
1657         // Call hubbub to program PTB of VMID
1658         if (dc->res_pool->hubbub->funcs->setup_vmid_ptb)
1659                 dc->res_pool->hubbub->funcs->setup_vmid_ptb(dc->res_pool->hubbub,
1660                                 plane_state->address.page_table_base.quad_part,
1661                                 vmid);
1662
1663         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1664                         pipe_ctx->plane_res.hubp,
1665                         &plane_state->address,
1666                         plane_state->flip_immediate,
1667                         vmid);
1668
1669         plane_state->status.requested_address = plane_state->address;
1670
1671         if (plane_state->flip_immediate)
1672                 plane_state->status.current_address = plane_state->address;
1673
1674         if (addr_patched)
1675                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1676 }
1677
1678 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
1679                 struct dc_link_settings *link_settings)
1680 {
1681         struct encoder_unblank_param params = { { 0 } };
1682         struct dc_stream_state *stream = pipe_ctx->stream;
1683         struct dc_link *link = stream->link;
1684         params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx);
1685
1686         /* only 3 items below are used by unblank */
1687         params.timing = pipe_ctx->stream->timing;
1688
1689         params.link_settings.link_rate = link_settings->link_rate;
1690
1691         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1692                 if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm)
1693                         params.timing.pix_clk_100hz /= 2;
1694                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1695                                 pipe_ctx->stream_res.stream_enc, params.odm);
1696                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1697         }
1698
1699         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1700                 link->dc->hwss.edp_backlight_control(link, true);
1701         }
1702 }
1703
1704 void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
1705 {
1706         struct timing_generator *tg = pipe_ctx->stream_res.tg;
1707         int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
1708
1709         if (start_line < 0)
1710                 start_line = 0;
1711
1712         if (tg->funcs->setup_vertical_interrupt2)
1713                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
1714 }
1715
1716 static void dcn20_reset_back_end_for_pipe(
1717                 struct dc *dc,
1718                 struct pipe_ctx *pipe_ctx,
1719                 struct dc_state *context)
1720 {
1721         int i;
1722         DC_LOGGER_INIT(dc->ctx->logger);
1723         if (pipe_ctx->stream_res.stream_enc == NULL) {
1724                 pipe_ctx->stream = NULL;
1725                 return;
1726         }
1727
1728         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1729                 /* DPMS may already disable */
1730                 if (!pipe_ctx->stream->dpms_off)
1731                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
1732                 else if (pipe_ctx->stream_res.audio) {
1733                         dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
1734                 }
1735
1736         }
1737
1738         /* by upper caller loop, parent pipe: pipe0, will be reset last.
1739          * back end share by all pipes and will be disable only when disable
1740          * parent pipe.
1741          */
1742         if (pipe_ctx->top_pipe == NULL) {
1743                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
1744
1745                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
1746                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
1747                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1748                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1749         }
1750
1751         for (i = 0; i < dc->res_pool->pipe_count; i++)
1752                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
1753                         break;
1754
1755         if (i == dc->res_pool->pipe_count)
1756                 return;
1757
1758         pipe_ctx->stream = NULL;
1759         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
1760                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
1761 }
1762
1763 static void dcn20_reset_hw_ctx_wrap(
1764                 struct dc *dc,
1765                 struct dc_state *context)
1766 {
1767         int i;
1768
1769         /* Reset Back End*/
1770         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1771                 struct pipe_ctx *pipe_ctx_old =
1772                         &dc->current_state->res_ctx.pipe_ctx[i];
1773                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1774
1775                 if (!pipe_ctx_old->stream)
1776                         continue;
1777
1778                 if (pipe_ctx_old->top_pipe)
1779                         continue;
1780
1781                 if (!pipe_ctx->stream ||
1782                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1783                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1784
1785                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1786                         if (dc->hwss.enable_stream_gating)
1787                                 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1788                         if (old_clk)
1789                                 old_clk->funcs->cs_power_down(old_clk);
1790                 }
1791         }
1792 }
1793
1794 static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1795 {
1796         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1797         struct mpcc_blnd_cfg blnd_cfg = { {0} };
1798         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1799         int mpcc_id;
1800         struct mpcc *new_mpcc;
1801         struct mpc *mpc = dc->res_pool->mpc;
1802         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1803
1804         // input to MPCC is always RGB, by default leave black_color at 0
1805         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1806                 dcn10_get_hdr_visual_confirm_color(
1807                                 pipe_ctx, &blnd_cfg.black_color);
1808         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1809                 dcn10_get_surface_visual_confirm_color(
1810                                 pipe_ctx, &blnd_cfg.black_color);
1811         }
1812
1813         if (per_pixel_alpha)
1814                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1815         else
1816                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1817
1818         blnd_cfg.overlap_only = false;
1819         blnd_cfg.global_gain = 0xff;
1820
1821         if (pipe_ctx->plane_state->global_alpha)
1822                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
1823         else
1824                 blnd_cfg.global_alpha = 0xff;
1825
1826         blnd_cfg.background_color_bpc = 4;
1827         blnd_cfg.bottom_gain_mode = 0;
1828         blnd_cfg.top_gain = 0x1f000;
1829         blnd_cfg.bottom_inside_gain = 0x1f000;
1830         blnd_cfg.bottom_outside_gain = 0x1f000;
1831         blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
1832
1833         /*
1834          * TODO: remove hack
1835          * Note: currently there is a bug in init_hw such that
1836          * on resume from hibernate, BIOS sets up MPCC0, and
1837          * we do mpcc_remove but the mpcc cannot go to idle
1838          * after remove. This cause us to pick mpcc1 here,
1839          * which causes a pstate hang for yet unknown reason.
1840          */
1841         mpcc_id = hubp->inst;
1842
1843         /* If there is no full update, don't need to touch MPC tree*/
1844         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
1845                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
1846                 return;
1847         }
1848
1849         /* check if this MPCC is already being used */
1850         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1851         /* remove MPCC if being used */
1852         if (new_mpcc != NULL)
1853                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1854         else
1855                 if (dc->debug.sanity_checks)
1856                         mpc->funcs->assert_mpcc_idle_before_connect(
1857                                         dc->res_pool->mpc, mpcc_id);
1858
1859         /* Call MPC to insert new plane */
1860         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1861                         mpc_tree_params,
1862                         &blnd_cfg,
1863                         NULL,
1864                         NULL,
1865                         hubp->inst,
1866                         mpcc_id);
1867
1868         ASSERT(new_mpcc != NULL);
1869         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1870         hubp->mpcc_id = mpcc_id;
1871 }
1872
1873 static int find_free_gsl_group(const struct dc *dc)
1874 {
1875         if (dc->res_pool->gsl_groups.gsl_0 == 0)
1876                 return 1;
1877         if (dc->res_pool->gsl_groups.gsl_1 == 0)
1878                 return 2;
1879         if (dc->res_pool->gsl_groups.gsl_2 == 0)
1880                 return 3;
1881
1882         return 0;
1883 }
1884
1885 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
1886  * This is only used to lock pipes in pipe splitting case with immediate flip
1887  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
1888  * so we get tearing with freesync since we cannot flip multiple pipes
1889  * atomically.
1890  * We use GSL for this:
1891  * - immediate flip: find first available GSL group if not already assigned
1892  *                   program gsl with that group, set current OTG as master
1893  *                   and always us 0x4 = AND of flip_ready from all pipes
1894  * - vsync flip: disable GSL if used
1895  *
1896  * Groups in stream_res are stored as +1 from HW registers, i.e.
1897  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
1898  * Using a magic value like -1 would require tracking all inits/resets
1899  */
1900 void dcn20_setup_gsl_group_as_lock(
1901                 const struct dc *dc,
1902                 struct pipe_ctx *pipe_ctx,
1903                 bool enable)
1904 {
1905         struct gsl_params gsl;
1906         int group_idx;
1907
1908         memset(&gsl, 0, sizeof(struct gsl_params));
1909
1910         if (enable) {
1911                 /* return if group already assigned since GSL was set up
1912                  * for vsync flip, we would unassign so it can't be "left over"
1913                  */
1914                 if (pipe_ctx->stream_res.gsl_group > 0)
1915                         return;
1916
1917                 group_idx = find_free_gsl_group(dc);
1918                 ASSERT(group_idx != 0);
1919                 pipe_ctx->stream_res.gsl_group = group_idx;
1920
1921                 /* set gsl group reg field and mark resource used */
1922                 switch (group_idx) {
1923                 case 1:
1924                         gsl.gsl0_en = 1;
1925                         dc->res_pool->gsl_groups.gsl_0 = 1;
1926                         break;
1927                 case 2:
1928                         gsl.gsl1_en = 1;
1929                         dc->res_pool->gsl_groups.gsl_1 = 1;
1930                         break;
1931                 case 3:
1932                         gsl.gsl2_en = 1;
1933                         dc->res_pool->gsl_groups.gsl_2 = 1;
1934                         break;
1935                 default:
1936                         BREAK_TO_DEBUGGER();
1937                         return; // invalid case
1938                 }
1939                 gsl.gsl_master_en = 1;
1940         } else {
1941                 group_idx = pipe_ctx->stream_res.gsl_group;
1942                 if (group_idx == 0)
1943                         return; // if not in use, just return
1944
1945                 pipe_ctx->stream_res.gsl_group = 0;
1946
1947                 /* unset gsl group reg field and mark resource free */
1948                 switch (group_idx) {
1949                 case 1:
1950                         gsl.gsl0_en = 0;
1951                         dc->res_pool->gsl_groups.gsl_0 = 0;
1952                         break;
1953                 case 2:
1954                         gsl.gsl1_en = 0;
1955                         dc->res_pool->gsl_groups.gsl_1 = 0;
1956                         break;
1957                 case 3:
1958                         gsl.gsl2_en = 0;
1959                         dc->res_pool->gsl_groups.gsl_2 = 0;
1960                         break;
1961                 default:
1962                         BREAK_TO_DEBUGGER();
1963                         return;
1964                 }
1965                 gsl.gsl_master_en = 0;
1966         }
1967
1968         /* at this point we want to program whether it's to enable or disable */
1969         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
1970                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
1971                 pipe_ctx->stream_res.tg->funcs->set_gsl(
1972                         pipe_ctx->stream_res.tg,
1973                         &gsl);
1974
1975                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
1976                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
1977         } else
1978                 BREAK_TO_DEBUGGER();
1979 }
1980
1981 static void dcn20_set_flip_control_gsl(
1982                 struct pipe_ctx *pipe_ctx,
1983                 bool flip_immediate)
1984 {
1985         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
1986                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
1987                                 pipe_ctx->plane_res.hubp, flip_immediate);
1988
1989 }
1990
1991 void dcn20_hw_sequencer_construct(struct dc *dc)
1992 {
1993         dcn10_hw_sequencer_construct(dc);
1994         dc->hwss.init_hw = dcn20_init_hw;
1995         dc->hwss.init_pipes = NULL;
1996         dc->hwss.unblank_stream = dcn20_unblank_stream;
1997         dc->hwss.update_plane_addr = dcn20_update_plane_addr;
1998         dc->hwss.disable_plane = dcn20_disable_plane,
1999         dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
2000         dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
2001         dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
2002         dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func;
2003         dc->hwss.apply_ctx_for_surface = dcn20_apply_ctx_for_surface;
2004         dc->hwss.pipe_control_lock = dcn20_pipe_control_lock;
2005         dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global;
2006         dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth;
2007         dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth;
2008         dc->hwss.update_bandwidth = dcn20_update_bandwidth;
2009         dc->hwss.enable_writeback = dcn20_enable_writeback;
2010         dc->hwss.disable_writeback = dcn20_disable_writeback;
2011         dc->hwss.program_output_csc = dcn20_program_output_csc;
2012         dc->hwss.update_odm = dcn20_update_odm;
2013         dc->hwss.blank_pixel_data = dcn20_blank_pixel_data;
2014         dc->hwss.dmdata_status_done = dcn20_dmdata_status_done;
2015         dc->hwss.disable_stream = dcn20_disable_stream;
2016         dc->hwss.init_dchub = dcn20_init_dchub;
2017         dc->hwss.disable_stream_gating = dcn20_disable_stream_gating;
2018         dc->hwss.enable_stream_gating = dcn20_enable_stream_gating;
2019         dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt;
2020         dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
2021         dc->hwss.update_mpcc = dcn20_update_mpcc;
2022         dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
2023 }