2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/delay.h>
27 #include "dm_services.h"
28 #include "basics/dc_common.h"
29 #include "dm_helpers.h"
30 #include "core_types.h"
32 #include "dcn20_resource.h"
33 #include "dcn20_hwseq.h"
34 #include "dce/dce_hwseq.h"
35 #include "dcn20_dsc.h"
36 #include "dcn20_optc.h"
41 #include "timing_generator.h"
47 #include "reg_helper.h"
48 #include "dcn10/dcn10_cm_common.h"
49 #include "dc_link_dp.h"
50 #include "vm_helper.h"
52 #include "dc_dmub_srv.h"
53 #include "dce/dmub_hw_lock_mgr.h"
54 #include "hw_sequencer.h"
55 #include "inc/link_dpcd.h"
56 #include "dpcd_defs.h"
57 #include "inc/link_enc_cfg.h"
58 #include "link_hwss.h"
60 #define DC_LOGGER_INIT(logger)
68 #define FN(reg_name, field_name) \
69 hws->shifts->field_name, hws->masks->field_name
71 static int find_free_gsl_group(const struct dc *dc)
73 if (dc->res_pool->gsl_groups.gsl_0 == 0)
75 if (dc->res_pool->gsl_groups.gsl_1 == 0)
77 if (dc->res_pool->gsl_groups.gsl_2 == 0)
83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
84 * This is only used to lock pipes in pipe splitting case with immediate flip
85 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
86 * so we get tearing with freesync since we cannot flip multiple pipes
88 * We use GSL for this:
89 * - immediate flip: find first available GSL group if not already assigned
90 * program gsl with that group, set current OTG as master
91 * and always us 0x4 = AND of flip_ready from all pipes
92 * - vsync flip: disable GSL if used
94 * Groups in stream_res are stored as +1 from HW registers, i.e.
95 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
96 * Using a magic value like -1 would require tracking all inits/resets
98 static void dcn20_setup_gsl_group_as_lock(
100 struct pipe_ctx *pipe_ctx,
103 struct gsl_params gsl;
106 memset(&gsl, 0, sizeof(struct gsl_params));
109 /* return if group already assigned since GSL was set up
110 * for vsync flip, we would unassign so it can't be "left over"
112 if (pipe_ctx->stream_res.gsl_group > 0)
115 group_idx = find_free_gsl_group(dc);
116 ASSERT(group_idx != 0);
117 pipe_ctx->stream_res.gsl_group = group_idx;
119 /* set gsl group reg field and mark resource used */
123 dc->res_pool->gsl_groups.gsl_0 = 1;
127 dc->res_pool->gsl_groups.gsl_1 = 1;
131 dc->res_pool->gsl_groups.gsl_2 = 1;
135 return; // invalid case
137 gsl.gsl_master_en = 1;
139 group_idx = pipe_ctx->stream_res.gsl_group;
141 return; // if not in use, just return
143 pipe_ctx->stream_res.gsl_group = 0;
145 /* unset gsl group reg field and mark resource free */
149 dc->res_pool->gsl_groups.gsl_0 = 0;
153 dc->res_pool->gsl_groups.gsl_1 = 0;
157 dc->res_pool->gsl_groups.gsl_2 = 0;
163 gsl.gsl_master_en = 0;
166 /* at this point we want to program whether it's to enable or disable */
167 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
169 pipe_ctx->stream_res.tg->funcs->set_gsl(
170 pipe_ctx->stream_res.tg,
173 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
174 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
179 void dcn20_set_flip_control_gsl(
180 struct pipe_ctx *pipe_ctx,
183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
185 pipe_ctx->plane_res.hubp, flip_immediate);
189 void dcn20_enable_power_gating_plane(
190 struct dce_hwseq *hws,
193 bool force_on = true; /* disable power gating */
198 /* DCHUBP0/1/2/3/4/5 */
199 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
200 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
201 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
202 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
203 if (REG(DOMAIN8_PG_CONFIG))
204 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
205 if (REG(DOMAIN10_PG_CONFIG))
206 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
209 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
210 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
211 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
212 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
213 if (REG(DOMAIN9_PG_CONFIG))
214 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
215 if (REG(DOMAIN11_PG_CONFIG))
216 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
219 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
220 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
221 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
222 if (REG(DOMAIN19_PG_CONFIG))
223 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
224 if (REG(DOMAIN20_PG_CONFIG))
225 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
226 if (REG(DOMAIN21_PG_CONFIG))
227 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
230 void dcn20_dccg_init(struct dce_hwseq *hws)
233 * set MICROSECOND_TIME_BASE_DIV
234 * 100Mhz refclk -> 0x120264
235 * 27Mhz refclk -> 0x12021b
236 * 48Mhz refclk -> 0x120230
239 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
242 * set MILLISECOND_TIME_BASE_DIV
243 * 100Mhz refclk -> 0x1186a0
244 * 27Mhz refclk -> 0x106978
245 * 48Mhz refclk -> 0x10bb80
248 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
250 /* This value is dependent on the hardware pipeline delay so set once per SOC */
251 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
254 void dcn20_disable_vga(
255 struct dce_hwseq *hws)
257 REG_WRITE(D1VGA_CONTROL, 0);
258 REG_WRITE(D2VGA_CONTROL, 0);
259 REG_WRITE(D3VGA_CONTROL, 0);
260 REG_WRITE(D4VGA_CONTROL, 0);
261 REG_WRITE(D5VGA_CONTROL, 0);
262 REG_WRITE(D6VGA_CONTROL, 0);
265 void dcn20_program_triple_buffer(
267 struct pipe_ctx *pipe_ctx,
268 bool enable_triple_buffer)
270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
272 pipe_ctx->plane_res.hubp,
273 enable_triple_buffer);
277 /* Blank pixel data during initialization */
278 void dcn20_init_blank(
280 struct timing_generator *tg)
282 struct dce_hwseq *hws = dc->hwseq;
283 enum dc_color_space color_space;
284 struct tg_color black_color = {0};
285 struct output_pixel_processor *opp = NULL;
286 struct output_pixel_processor *bottom_opp = NULL;
287 uint32_t num_opps, opp_id_src0, opp_id_src1;
288 uint32_t otg_active_width, otg_active_height;
290 /* program opp dpg blank color */
291 color_space = COLOR_SPACE_SRGB;
292 color_space_to_black_color(dc, color_space, &black_color);
294 /* get the OTG active size */
295 tg->funcs->get_otg_active_size(tg,
299 /* get the OPTC source */
300 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
302 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
306 opp = dc->res_pool->opps[opp_id_src0];
309 otg_active_width = otg_active_width / 2;
311 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
315 bottom_opp = dc->res_pool->opps[opp_id_src1];
318 opp->funcs->opp_set_disp_pattern_generator(
320 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
321 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
322 COLOR_DEPTH_UNDEFINED,
329 bottom_opp->funcs->opp_set_disp_pattern_generator(
331 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
332 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
333 COLOR_DEPTH_UNDEFINED,
340 hws->funcs.wait_for_blank_complete(opp);
343 void dcn20_dsc_pg_control(
344 struct dce_hwseq *hws,
345 unsigned int dsc_inst,
348 uint32_t power_gate = power_on ? 0 : 1;
349 uint32_t pwr_status = power_on ? 0 : 2;
350 uint32_t org_ip_request_cntl = 0;
352 if (hws->ctx->dc->debug.disable_dsc_power_gate)
355 if (REG(DOMAIN16_PG_CONFIG) == 0)
358 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
359 if (org_ip_request_cntl == 0)
360 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
364 REG_UPDATE(DOMAIN16_PG_CONFIG,
365 DOMAIN16_POWER_GATE, power_gate);
367 REG_WAIT(DOMAIN16_PG_STATUS,
368 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
372 REG_UPDATE(DOMAIN17_PG_CONFIG,
373 DOMAIN17_POWER_GATE, power_gate);
375 REG_WAIT(DOMAIN17_PG_STATUS,
376 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
380 REG_UPDATE(DOMAIN18_PG_CONFIG,
381 DOMAIN18_POWER_GATE, power_gate);
383 REG_WAIT(DOMAIN18_PG_STATUS,
384 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
388 REG_UPDATE(DOMAIN19_PG_CONFIG,
389 DOMAIN19_POWER_GATE, power_gate);
391 REG_WAIT(DOMAIN19_PG_STATUS,
392 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
396 REG_UPDATE(DOMAIN20_PG_CONFIG,
397 DOMAIN20_POWER_GATE, power_gate);
399 REG_WAIT(DOMAIN20_PG_STATUS,
400 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
404 REG_UPDATE(DOMAIN21_PG_CONFIG,
405 DOMAIN21_POWER_GATE, power_gate);
407 REG_WAIT(DOMAIN21_PG_STATUS,
408 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
416 if (org_ip_request_cntl == 0)
417 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
420 void dcn20_dpp_pg_control(
421 struct dce_hwseq *hws,
422 unsigned int dpp_inst,
425 uint32_t power_gate = power_on ? 0 : 1;
426 uint32_t pwr_status = power_on ? 0 : 2;
428 if (hws->ctx->dc->debug.disable_dpp_power_gate)
430 if (REG(DOMAIN1_PG_CONFIG) == 0)
435 REG_UPDATE(DOMAIN1_PG_CONFIG,
436 DOMAIN1_POWER_GATE, power_gate);
438 REG_WAIT(DOMAIN1_PG_STATUS,
439 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
443 REG_UPDATE(DOMAIN3_PG_CONFIG,
444 DOMAIN3_POWER_GATE, power_gate);
446 REG_WAIT(DOMAIN3_PG_STATUS,
447 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
451 REG_UPDATE(DOMAIN5_PG_CONFIG,
452 DOMAIN5_POWER_GATE, power_gate);
454 REG_WAIT(DOMAIN5_PG_STATUS,
455 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
459 REG_UPDATE(DOMAIN7_PG_CONFIG,
460 DOMAIN7_POWER_GATE, power_gate);
462 REG_WAIT(DOMAIN7_PG_STATUS,
463 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
467 REG_UPDATE(DOMAIN9_PG_CONFIG,
468 DOMAIN9_POWER_GATE, power_gate);
470 REG_WAIT(DOMAIN9_PG_STATUS,
471 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
476 * Do not power gate DPP5, should be left at HW default, power on permanently.
477 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
479 * REG_UPDATE(DOMAIN11_PG_CONFIG,
480 * DOMAIN11_POWER_GATE, power_gate);
482 * REG_WAIT(DOMAIN11_PG_STATUS,
483 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
494 void dcn20_hubp_pg_control(
495 struct dce_hwseq *hws,
496 unsigned int hubp_inst,
499 uint32_t power_gate = power_on ? 0 : 1;
500 uint32_t pwr_status = power_on ? 0 : 2;
502 if (hws->ctx->dc->debug.disable_hubp_power_gate)
504 if (REG(DOMAIN0_PG_CONFIG) == 0)
508 case 0: /* DCHUBP0 */
509 REG_UPDATE(DOMAIN0_PG_CONFIG,
510 DOMAIN0_POWER_GATE, power_gate);
512 REG_WAIT(DOMAIN0_PG_STATUS,
513 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
516 case 1: /* DCHUBP1 */
517 REG_UPDATE(DOMAIN2_PG_CONFIG,
518 DOMAIN2_POWER_GATE, power_gate);
520 REG_WAIT(DOMAIN2_PG_STATUS,
521 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
524 case 2: /* DCHUBP2 */
525 REG_UPDATE(DOMAIN4_PG_CONFIG,
526 DOMAIN4_POWER_GATE, power_gate);
528 REG_WAIT(DOMAIN4_PG_STATUS,
529 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
532 case 3: /* DCHUBP3 */
533 REG_UPDATE(DOMAIN6_PG_CONFIG,
534 DOMAIN6_POWER_GATE, power_gate);
536 REG_WAIT(DOMAIN6_PG_STATUS,
537 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
540 case 4: /* DCHUBP4 */
541 REG_UPDATE(DOMAIN8_PG_CONFIG,
542 DOMAIN8_POWER_GATE, power_gate);
544 REG_WAIT(DOMAIN8_PG_STATUS,
545 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
548 case 5: /* DCHUBP5 */
550 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
551 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
553 * REG_UPDATE(DOMAIN10_PG_CONFIG,
554 * DOMAIN10_POWER_GATE, power_gate);
556 * REG_WAIT(DOMAIN10_PG_STATUS,
557 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
568 /* disable HW used by plane.
569 * note: cannot disable until disconnect is complete
571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
573 struct dce_hwseq *hws = dc->hwseq;
574 struct hubp *hubp = pipe_ctx->plane_res.hubp;
575 struct dpp *dpp = pipe_ctx->plane_res.dpp;
577 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
579 /* In flip immediate with pipe splitting case GSL is used for
580 * synchronization so we must disable it when the plane is disabled.
582 if (pipe_ctx->stream_res.gsl_group != 0)
583 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
585 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
587 hubp->funcs->hubp_clk_cntl(hubp, false);
589 dpp->funcs->dpp_dppclk_control(dpp, false, false);
591 hubp->power_gated = true;
593 hws->funcs.plane_atomic_power_down(dc,
594 pipe_ctx->plane_res.dpp,
595 pipe_ctx->plane_res.hubp);
597 pipe_ctx->stream = NULL;
598 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
599 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
600 pipe_ctx->top_pipe = NULL;
601 pipe_ctx->bottom_pipe = NULL;
602 pipe_ctx->plane_state = NULL;
606 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
608 DC_LOGGER_INIT(dc->ctx->logger);
610 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
613 dcn20_plane_atomic_disable(dc, pipe_ctx);
615 DC_LOG_DC("Power down front end %d\n",
619 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
621 dcn20_blank_pixel_data(dc, pipe_ctx, blank);
624 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
627 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
631 hblank_halved = true;
633 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
634 stream->timing.h_border_left -
635 stream->timing.h_border_right;
640 /* ODM combine 4:1 case */
644 return flow_ctrl_cnt;
647 enum dc_status dcn20_enable_stream_timing(
648 struct pipe_ctx *pipe_ctx,
649 struct dc_state *context,
652 struct dce_hwseq *hws = dc->hwseq;
653 struct dc_stream_state *stream = pipe_ctx->stream;
654 struct drr_params params = {0};
655 unsigned int event_triggers = 0;
656 struct pipe_ctx *odm_pipe;
658 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
659 bool interlace = stream->timing.flags.INTERLACE;
661 struct mpc_dwb_flow_control flow_control;
662 struct mpc *mpc = dc->res_pool->mpc;
663 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
665 /* by upper caller loop, pipe0 is parent pipe and be called first.
666 * back end is set up by for pipe0. Other children pipe share back end
667 * with pipe 0. No program is needed.
669 if (pipe_ctx->top_pipe != NULL)
672 /* TODO check if timing_changed, disable stream if timing changed */
674 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
675 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
680 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
681 pipe_ctx->stream_res.tg,
683 &pipe_ctx->stream->timing);
685 /* HW program guide assume display already disable
686 * by unplug sequence. OTG assume stop.
688 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
690 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
691 pipe_ctx->clock_source,
692 &pipe_ctx->stream_res.pix_clk_params,
693 &pipe_ctx->pll_settings)) {
695 return DC_ERROR_UNEXPECTED;
698 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
699 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
701 pipe_ctx->stream_res.tg->funcs->program_timing(
702 pipe_ctx->stream_res.tg,
704 pipe_ctx->pipe_dlg_param.vready_offset,
705 pipe_ctx->pipe_dlg_param.vstartup_start,
706 pipe_ctx->pipe_dlg_param.vupdate_offset,
707 pipe_ctx->pipe_dlg_param.vupdate_width,
708 pipe_ctx->stream->signal,
711 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
712 flow_control.flow_ctrl_mode = 0;
713 flow_control.flow_ctrl_cnt0 = 0x80;
714 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
715 if (mpc->funcs->set_out_rate_control) {
716 for (i = 0; i < opp_cnt; ++i) {
717 mpc->funcs->set_out_rate_control(
720 rate_control_2x_pclk,
725 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
726 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
727 odm_pipe->stream_res.opp,
730 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
731 pipe_ctx->stream_res.opp,
734 hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
736 /* VTG is within DCHUB command block. DCFCLK is always on */
737 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
739 return DC_ERROR_UNEXPECTED;
742 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
744 params.vertical_total_min = stream->adjust.v_total_min;
745 params.vertical_total_max = stream->adjust.v_total_max;
746 params.vertical_total_mid = stream->adjust.v_total_mid;
747 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
748 if (pipe_ctx->stream_res.tg->funcs->set_drr)
749 pipe_ctx->stream_res.tg->funcs->set_drr(
750 pipe_ctx->stream_res.tg, ¶ms);
752 // DRR should set trigger event to monitor surface update event
753 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
754 event_triggers = 0x80;
755 /* Event triggers and num frames initialized for DRR, but can be
756 * later updated for PSR use. Note DRR trigger events are generated
757 * regardless of whether num frames met.
759 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
760 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
761 pipe_ctx->stream_res.tg, event_triggers, 2);
763 /* TODO program crtc source select for non-virtual signal*/
764 /* TODO program FMT */
765 /* TODO setup link_enc */
766 /* TODO set stream attributes */
767 /* TODO program audio */
768 /* TODO enable stream if timing changed */
769 /* TODO unblank stream if DP */
774 void dcn20_program_output_csc(struct dc *dc,
775 struct pipe_ctx *pipe_ctx,
776 enum dc_color_space colorspace,
780 struct mpc *mpc = dc->res_pool->mpc;
781 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
782 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
784 if (mpc->funcs->power_on_mpc_mem_pwr)
785 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
787 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
788 if (mpc->funcs->set_output_csc != NULL)
789 mpc->funcs->set_output_csc(mpc,
794 if (mpc->funcs->set_ocsc_default != NULL)
795 mpc->funcs->set_ocsc_default(mpc,
802 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
803 const struct dc_stream_state *stream)
805 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
806 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
807 struct pwl_params *params = NULL;
809 * program OGAM only for the top pipe
810 * if there is a pipe split then fix diagnostic is required:
811 * how to pass OGAM parameter for stream.
812 * if programming for all pipes is required then remove condition
813 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
815 if (mpc->funcs->power_on_mpc_mem_pwr)
816 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
817 if (pipe_ctx->top_pipe == NULL
818 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
819 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
820 params = &stream->out_transfer_func->pwl;
821 else if (pipe_ctx->stream->out_transfer_func->type ==
822 TF_TYPE_DISTRIBUTED_POINTS &&
823 cm_helper_translate_curve_to_hw_format(
824 stream->out_transfer_func,
825 &mpc->blender_params, false))
826 params = &mpc->blender_params;
830 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
834 * if above if is not executed then 'params' equal to 0 and set in bypass
836 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
841 bool dcn20_set_blend_lut(
842 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
844 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
846 struct pwl_params *blend_lut = NULL;
848 if (plane_state->blend_tf) {
849 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
850 blend_lut = &plane_state->blend_tf->pwl;
851 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
852 cm_helper_translate_curve_to_hw_format(
853 plane_state->blend_tf,
854 &dpp_base->regamma_params, false);
855 blend_lut = &dpp_base->regamma_params;
858 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
863 bool dcn20_set_shaper_3dlut(
864 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
866 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
868 struct pwl_params *shaper_lut = NULL;
870 if (plane_state->in_shaper_func) {
871 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
872 shaper_lut = &plane_state->in_shaper_func->pwl;
873 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
874 cm_helper_translate_curve_to_hw_format(
875 plane_state->in_shaper_func,
876 &dpp_base->shaper_params, true);
877 shaper_lut = &dpp_base->shaper_params;
881 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
882 if (plane_state->lut3d_func &&
883 plane_state->lut3d_func->state.bits.initialized == 1)
884 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
885 &plane_state->lut3d_func->lut_3d);
887 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
892 bool dcn20_set_input_transfer_func(struct dc *dc,
893 struct pipe_ctx *pipe_ctx,
894 const struct dc_plane_state *plane_state)
896 struct dce_hwseq *hws = dc->hwseq;
897 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
898 const struct dc_transfer_func *tf = NULL;
900 bool use_degamma_ram = false;
902 if (dpp_base == NULL || plane_state == NULL)
905 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
906 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
908 if (plane_state->in_transfer_func)
909 tf = plane_state->in_transfer_func;
913 dpp_base->funcs->dpp_set_degamma(dpp_base,
914 IPP_DEGAMMA_MODE_BYPASS);
918 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
919 use_degamma_ram = true;
921 if (use_degamma_ram == true) {
922 if (tf->type == TF_TYPE_HWPWL)
923 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
925 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
926 cm_helper_translate_curve_to_degamma_hw_format(tf,
927 &dpp_base->degamma_params);
928 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
929 &dpp_base->degamma_params);
933 /* handle here the optimized cases when de-gamma ROM could be used.
936 if (tf->type == TF_TYPE_PREDEFINED) {
938 case TRANSFER_FUNCTION_SRGB:
939 dpp_base->funcs->dpp_set_degamma(dpp_base,
940 IPP_DEGAMMA_MODE_HW_sRGB);
942 case TRANSFER_FUNCTION_BT709:
943 dpp_base->funcs->dpp_set_degamma(dpp_base,
944 IPP_DEGAMMA_MODE_HW_xvYCC);
946 case TRANSFER_FUNCTION_LINEAR:
947 dpp_base->funcs->dpp_set_degamma(dpp_base,
948 IPP_DEGAMMA_MODE_BYPASS);
950 case TRANSFER_FUNCTION_PQ:
951 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
952 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
953 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
960 } else if (tf->type == TF_TYPE_BYPASS)
961 dpp_base->funcs->dpp_set_degamma(dpp_base,
962 IPP_DEGAMMA_MODE_BYPASS);
965 * if we are here, we did not handle correctly.
966 * fix is required for this use case
969 dpp_base->funcs->dpp_set_degamma(dpp_base,
970 IPP_DEGAMMA_MODE_BYPASS);
976 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
978 struct pipe_ctx *odm_pipe;
980 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
982 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
983 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
988 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
989 pipe_ctx->stream_res.tg,
991 &pipe_ctx->stream->timing);
993 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
994 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
997 void dcn20_blank_pixel_data(
999 struct pipe_ctx *pipe_ctx,
1002 struct tg_color black_color = {0};
1003 struct stream_resource *stream_res = &pipe_ctx->stream_res;
1004 struct dc_stream_state *stream = pipe_ctx->stream;
1005 enum dc_color_space color_space = stream->output_color_space;
1006 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1007 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1008 struct pipe_ctx *odm_pipe;
1011 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1012 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1014 if (stream->link->test_pattern_enabled)
1017 /* get opp dpg blank color */
1018 color_space_to_black_color(dc, color_space, &black_color);
1020 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1023 width = width / odm_cnt;
1026 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1028 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1029 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1030 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1033 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1036 dc->hwss.set_disp_pattern_generator(dc,
1039 test_pattern_color_space,
1040 stream->timing.display_color_depth,
1046 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1047 dc->hwss.set_disp_pattern_generator(dc,
1049 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
1050 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
1051 test_pattern_color_space,
1052 stream->timing.display_color_depth,
1060 if (stream_res->abm) {
1061 dc->hwss.set_pipe(pipe_ctx);
1062 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1067 static void dcn20_power_on_plane(
1068 struct dce_hwseq *hws,
1069 struct pipe_ctx *pipe_ctx)
1071 DC_LOGGER_INIT(hws->ctx->logger);
1072 if (REG(DC_IP_REQUEST_CNTL)) {
1073 REG_SET(DC_IP_REQUEST_CNTL, 0,
1076 if (hws->funcs.dpp_pg_control)
1077 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1079 if (hws->funcs.hubp_pg_control)
1080 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1082 REG_SET(DC_IP_REQUEST_CNTL, 0,
1085 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1089 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1090 struct dc_state *context)
1092 //if (dc->debug.sanity_checks) {
1093 // dcn10_verify_allow_pstate_change_high(dc);
1095 dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1097 /* enable DCFCLK current DCHUB */
1098 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1100 /* initialize HUBP on power up */
1101 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1103 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1104 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1105 pipe_ctx->stream_res.opp,
1108 /* TODO: enable/disable in dm as per update type.
1110 DC_LOG_DC(dc->ctx->logger,
1111 "Pipe:%d 0x%x: addr hi:0x%x, "
1114 " %d; dst: %d, %d, %d, %d;\n",
1117 plane_state->address.grph.addr.high_part,
1118 plane_state->address.grph.addr.low_part,
1119 plane_state->src_rect.x,
1120 plane_state->src_rect.y,
1121 plane_state->src_rect.width,
1122 plane_state->src_rect.height,
1123 plane_state->dst_rect.x,
1124 plane_state->dst_rect.y,
1125 plane_state->dst_rect.width,
1126 plane_state->dst_rect.height);
1128 DC_LOG_DC(dc->ctx->logger,
1129 "Pipe %d: width, height, x, y format:%d\n"
1130 "viewport:%d, %d, %d, %d\n"
1131 "recout: %d, %d, %d, %d\n",
1133 plane_state->format,
1134 pipe_ctx->plane_res.scl_data.viewport.width,
1135 pipe_ctx->plane_res.scl_data.viewport.height,
1136 pipe_ctx->plane_res.scl_data.viewport.x,
1137 pipe_ctx->plane_res.scl_data.viewport.y,
1138 pipe_ctx->plane_res.scl_data.recout.width,
1139 pipe_ctx->plane_res.scl_data.recout.height,
1140 pipe_ctx->plane_res.scl_data.recout.x,
1141 pipe_ctx->plane_res.scl_data.recout.y);
1142 print_rq_dlg_ttu(dc, pipe_ctx);
1145 if (dc->vm_pa_config.valid) {
1146 struct vm_system_aperture_param apt;
1148 apt.sys_default.quad_part = 0;
1150 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1151 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1153 // Program system aperture settings
1154 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1157 if (!pipe_ctx->top_pipe
1158 && pipe_ctx->plane_state
1159 && pipe_ctx->plane_state->flip_int_enabled
1160 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1161 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1163 // if (dc->debug.sanity_checks) {
1164 // dcn10_verify_allow_pstate_change_high(dc);
1168 void dcn20_pipe_control_lock(
1170 struct pipe_ctx *pipe,
1173 struct pipe_ctx *temp_pipe;
1174 bool flip_immediate = false;
1176 /* use TG master update lock to lock everything on the TG
1177 * therefore only top pipe need to lock
1179 if (!pipe || pipe->top_pipe)
1182 if (pipe->plane_state != NULL)
1183 flip_immediate = pipe->plane_state->flip_immediate;
1185 if (pipe->stream_res.gsl_group > 0) {
1186 temp_pipe = pipe->bottom_pipe;
1187 while (!flip_immediate && temp_pipe) {
1188 if (temp_pipe->plane_state != NULL)
1189 flip_immediate = temp_pipe->plane_state->flip_immediate;
1190 temp_pipe = temp_pipe->bottom_pipe;
1194 if (flip_immediate && lock) {
1195 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1200 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1201 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1202 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1207 /* no reason it should take this long for immediate flips */
1208 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
1210 temp_pipe = temp_pipe->bottom_pipe;
1214 /* In flip immediate and pipe splitting case, we need to use GSL
1215 * for synchronization. Only do setup on locking and on flip type change.
1217 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
1218 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1219 (!flip_immediate && pipe->stream_res.gsl_group > 0))
1220 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1222 if (pipe->plane_state != NULL)
1223 flip_immediate = pipe->plane_state->flip_immediate;
1225 temp_pipe = pipe->bottom_pipe;
1226 while (flip_immediate && temp_pipe) {
1227 if (temp_pipe->plane_state != NULL)
1228 flip_immediate = temp_pipe->plane_state->flip_immediate;
1229 temp_pipe = temp_pipe->bottom_pipe;
1232 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1234 dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1236 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1237 union dmub_hw_lock_flags hw_locks = { 0 };
1238 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1240 hw_locks.bits.lock_pipe = 1;
1241 inst_flags.otg_inst = pipe->stream_res.tg->inst;
1243 if (pipe->plane_state != NULL)
1244 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1246 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1250 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1252 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1254 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1257 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1259 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1263 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1265 new_pipe->update_flags.raw = 0;
1267 /* Exit on unchanged, unused pipe */
1268 if (!old_pipe->plane_state && !new_pipe->plane_state)
1270 /* Detect pipe enable/disable */
1271 if (!old_pipe->plane_state && new_pipe->plane_state) {
1272 new_pipe->update_flags.bits.enable = 1;
1273 new_pipe->update_flags.bits.mpcc = 1;
1274 new_pipe->update_flags.bits.dppclk = 1;
1275 new_pipe->update_flags.bits.hubp_interdependent = 1;
1276 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1277 new_pipe->update_flags.bits.gamut_remap = 1;
1278 new_pipe->update_flags.bits.scaler = 1;
1279 new_pipe->update_flags.bits.viewport = 1;
1280 new_pipe->update_flags.bits.det_size = 1;
1281 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1282 new_pipe->update_flags.bits.odm = 1;
1283 new_pipe->update_flags.bits.global_sync = 1;
1287 if (old_pipe->plane_state && !new_pipe->plane_state) {
1288 new_pipe->update_flags.bits.disable = 1;
1292 /* Detect plane change */
1293 if (old_pipe->plane_state != new_pipe->plane_state) {
1294 new_pipe->update_flags.bits.plane_changed = true;
1297 /* Detect top pipe only changes */
1298 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1299 /* Detect odm changes */
1300 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1301 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1302 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1303 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1304 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1305 new_pipe->update_flags.bits.odm = 1;
1307 /* Detect global sync changes */
1308 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1309 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1310 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1311 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1312 new_pipe->update_flags.bits.global_sync = 1;
1315 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1316 new_pipe->update_flags.bits.det_size = 1;
1319 * Detect opp / tg change, only set on change, not on enable
1320 * Assume mpcc inst = pipe index, if not this code needs to be updated
1321 * since mpcc is what is affected by these. In fact all of our sequence
1322 * makes this assumption at the moment with how hubp reset is matched to
1323 * same index mpcc reset.
1325 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1326 new_pipe->update_flags.bits.opp_changed = 1;
1327 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1328 new_pipe->update_flags.bits.tg_changed = 1;
1331 * Detect mpcc blending changes, only dpp inst and opp matter here,
1332 * mpccs getting removed/inserted update connected ones during their own
1335 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1336 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1337 new_pipe->update_flags.bits.mpcc = 1;
1339 /* Detect dppclk change */
1340 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1341 new_pipe->update_flags.bits.dppclk = 1;
1343 /* Check for scl update */
1344 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1345 new_pipe->update_flags.bits.scaler = 1;
1346 /* Check for vp update */
1347 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1348 || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1349 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1350 new_pipe->update_flags.bits.viewport = 1;
1352 /* Detect dlg/ttu/rq updates */
1354 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1355 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1356 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1357 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1359 /* Detect pipe interdependent updates */
1360 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1361 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1362 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1363 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1364 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1365 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1366 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1367 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1368 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1369 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1370 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1371 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1372 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1373 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1374 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1375 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1376 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1377 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1378 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1379 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1380 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1381 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1382 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1383 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1384 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1385 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1386 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1387 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1388 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1389 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1390 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1391 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1392 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1393 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1394 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1395 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1396 new_pipe->update_flags.bits.hubp_interdependent = 1;
1398 /* Detect any other updates to ttu/rq/dlg */
1399 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1400 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1401 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1402 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1406 static void dcn20_update_dchubp_dpp(
1408 struct pipe_ctx *pipe_ctx,
1409 struct dc_state *context)
1411 struct dce_hwseq *hws = dc->hwseq;
1412 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1413 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1414 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1415 bool viewport_changed = false;
1417 if (pipe_ctx->update_flags.bits.dppclk)
1418 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1420 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1421 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1422 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1424 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1425 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1427 hubp->funcs->hubp_setup(
1429 &pipe_ctx->dlg_regs,
1430 &pipe_ctx->ttu_regs,
1432 &pipe_ctx->pipe_dlg_param);
1434 if (hubp->funcs->set_unbounded_requesting)
1435 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
1437 if (pipe_ctx->update_flags.bits.hubp_interdependent)
1438 hubp->funcs->hubp_setup_interdependent(
1440 &pipe_ctx->dlg_regs,
1441 &pipe_ctx->ttu_regs);
1443 if (pipe_ctx->update_flags.bits.enable ||
1444 pipe_ctx->update_flags.bits.plane_changed ||
1445 plane_state->update_flags.bits.bpp_change ||
1446 plane_state->update_flags.bits.input_csc_change ||
1447 plane_state->update_flags.bits.color_space_change ||
1448 plane_state->update_flags.bits.coeff_reduction_change) {
1449 struct dc_bias_and_scale bns_params = {0};
1451 // program the input csc
1452 dpp->funcs->dpp_setup(dpp,
1453 plane_state->format,
1454 EXPANSION_MODE_ZERO,
1455 plane_state->input_csc_color_matrix,
1456 plane_state->color_space,
1459 if (dpp->funcs->dpp_program_bias_and_scale) {
1460 //TODO :for CNVC set scale and bias registers if necessary
1461 build_prescale_params(&bns_params, plane_state);
1462 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1466 if (pipe_ctx->update_flags.bits.mpcc
1467 || pipe_ctx->update_flags.bits.plane_changed
1468 || plane_state->update_flags.bits.global_alpha_change
1469 || plane_state->update_flags.bits.per_pixel_alpha_change) {
1470 // MPCC inst is equal to pipe index in practice
1471 int mpcc_inst = hubp->inst;
1473 int opp_count = dc->res_pool->pipe_count;
1475 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1476 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1477 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1478 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1482 hws->funcs.update_mpcc(dc, pipe_ctx);
1485 if (pipe_ctx->update_flags.bits.scaler ||
1486 plane_state->update_flags.bits.scaling_change ||
1487 plane_state->update_flags.bits.position_change ||
1488 plane_state->update_flags.bits.per_pixel_alpha_change ||
1489 pipe_ctx->stream->update_flags.bits.scaling) {
1490 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1491 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
1492 /* scaler configuration */
1493 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1494 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1497 if (pipe_ctx->update_flags.bits.viewport ||
1498 (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1499 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1500 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1502 hubp->funcs->mem_program_viewport(
1504 &pipe_ctx->plane_res.scl_data.viewport,
1505 &pipe_ctx->plane_res.scl_data.viewport_c);
1506 viewport_changed = true;
1509 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1510 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1511 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1512 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1513 dc->hwss.set_cursor_position(pipe_ctx);
1514 dc->hwss.set_cursor_attribute(pipe_ctx);
1516 if (dc->hwss.set_cursor_sdr_white_level)
1517 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1520 /* Any updates are handled in dc interface, just need
1521 * to apply existing for plane enable / opp change */
1522 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1523 || pipe_ctx->stream->update_flags.bits.gamut_remap
1524 || pipe_ctx->stream->update_flags.bits.out_csc) {
1525 /* dpp/cm gamut remap*/
1526 dc->hwss.program_gamut_remap(pipe_ctx);
1528 /*call the dcn2 method which uses mpc csc*/
1529 dc->hwss.program_output_csc(dc,
1531 pipe_ctx->stream->output_color_space,
1532 pipe_ctx->stream->csc_color_matrix.matrix,
1536 if (pipe_ctx->update_flags.bits.enable ||
1537 pipe_ctx->update_flags.bits.plane_changed ||
1538 pipe_ctx->update_flags.bits.opp_changed ||
1539 plane_state->update_flags.bits.pixel_format_change ||
1540 plane_state->update_flags.bits.horizontal_mirror_change ||
1541 plane_state->update_flags.bits.rotation_change ||
1542 plane_state->update_flags.bits.swizzle_change ||
1543 plane_state->update_flags.bits.dcc_change ||
1544 plane_state->update_flags.bits.bpp_change ||
1545 plane_state->update_flags.bits.scaling_change ||
1546 plane_state->update_flags.bits.plane_size_change) {
1547 struct plane_size size = plane_state->plane_size;
1549 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1550 hubp->funcs->hubp_program_surface_config(
1552 plane_state->format,
1553 &plane_state->tiling_info,
1555 plane_state->rotation,
1557 plane_state->horizontal_mirror,
1559 hubp->power_gated = false;
1562 if (pipe_ctx->update_flags.bits.enable ||
1563 pipe_ctx->update_flags.bits.plane_changed ||
1564 plane_state->update_flags.bits.addr_update)
1565 hws->funcs.update_plane_addr(dc, pipe_ctx);
1569 if (pipe_ctx->update_flags.bits.enable)
1570 hubp->funcs->set_blank(hubp, false);
1574 static void dcn20_program_pipe(
1576 struct pipe_ctx *pipe_ctx,
1577 struct dc_state *context)
1579 struct dce_hwseq *hws = dc->hwseq;
1580 /* Only need to unblank on top pipe */
1581 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1582 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1583 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1585 /* Only update TG on top pipe */
1586 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1587 && !pipe_ctx->prev_odm_pipe) {
1589 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1590 pipe_ctx->stream_res.tg,
1591 pipe_ctx->pipe_dlg_param.vready_offset,
1592 pipe_ctx->pipe_dlg_param.vstartup_start,
1593 pipe_ctx->pipe_dlg_param.vupdate_offset,
1594 pipe_ctx->pipe_dlg_param.vupdate_width);
1596 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
1597 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1599 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1600 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1602 if (hws->funcs.setup_vupdate_interrupt)
1603 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1606 if (pipe_ctx->update_flags.bits.odm)
1607 hws->funcs.update_odm(dc, context, pipe_ctx);
1609 if (pipe_ctx->update_flags.bits.enable) {
1610 dcn20_enable_plane(dc, pipe_ctx, context);
1611 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1612 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1615 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1616 dc->res_pool->hubbub->funcs->program_det_size(
1617 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
1619 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1620 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1622 if (pipe_ctx->update_flags.bits.enable
1623 || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1624 hws->funcs.set_hdr_multiplier(pipe_ctx);
1626 if (pipe_ctx->update_flags.bits.enable ||
1627 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1628 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1629 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1631 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1632 * only do gamma programming for powering on, internal memcmp to avoid
1633 * updating on slave planes
1635 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1636 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1638 /* If the pipe has been enabled or has a different opp, we
1639 * should reprogram the fmt. This deals with cases where
1640 * interation between mpc and odm combine on different streams
1641 * causes a different pipe to be chosen to odm combine with.
1643 if (pipe_ctx->update_flags.bits.enable
1644 || pipe_ctx->update_flags.bits.opp_changed) {
1646 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1647 pipe_ctx->stream_res.opp,
1648 COLOR_SPACE_YCBCR601,
1649 pipe_ctx->stream->timing.display_color_depth,
1650 pipe_ctx->stream->signal);
1652 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1653 pipe_ctx->stream_res.opp,
1654 &pipe_ctx->stream->bit_depth_params,
1655 &pipe_ctx->stream->clamping);
1659 void dcn20_program_front_end_for_ctx(
1661 struct dc_state *context)
1664 struct dce_hwseq *hws = dc->hwseq;
1665 DC_LOGGER_INIT(dc->ctx->logger);
1667 /* Carry over GSL groups in case the context is changing. */
1668 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1669 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1670 struct pipe_ctx *old_pipe_ctx =
1671 &dc->current_state->res_ctx.pipe_ctx[i];
1673 if (pipe_ctx->stream == old_pipe_ctx->stream)
1674 pipe_ctx->stream_res.gsl_group =
1675 old_pipe_ctx->stream_res.gsl_group;
1678 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1679 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1680 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1682 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1683 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1684 /*turn off triple buffer for full update*/
1685 dc->hwss.program_triplebuffer(
1686 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1691 /* Set pipe update flags and lock pipes */
1692 for (i = 0; i < dc->res_pool->pipe_count; i++)
1693 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1694 &context->res_ctx.pipe_ctx[i]);
1696 /* OTG blank before disabling all front ends */
1697 for (i = 0; i < dc->res_pool->pipe_count; i++)
1698 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1699 && !context->res_ctx.pipe_ctx[i].top_pipe
1700 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1701 && context->res_ctx.pipe_ctx[i].stream)
1702 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1705 /* Disconnect mpcc */
1706 for (i = 0; i < dc->res_pool->pipe_count; i++)
1707 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1708 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1709 struct hubbub *hubbub = dc->res_pool->hubbub;
1711 if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1712 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
1713 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1714 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1718 * Program all updated pipes, order matters for mpcc setup. Start with
1719 * top pipe and program all pipes that follow in order
1721 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1722 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1724 if (pipe->plane_state && !pipe->top_pipe) {
1726 if (hws->funcs.program_pipe)
1727 hws->funcs.program_pipe(dc, pipe, context);
1729 dcn20_program_pipe(dc, pipe, context);
1731 pipe = pipe->bottom_pipe;
1734 /* Program secondary blending tree and writeback pipes */
1735 pipe = &context->res_ctx.pipe_ctx[i];
1736 if (!pipe->top_pipe && !pipe->prev_odm_pipe
1737 && pipe->stream && pipe->stream->num_wb_info > 0
1738 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1739 || pipe->stream->update_flags.raw)
1740 && hws->funcs.program_all_writeback_pipes_in_tree)
1741 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1743 /* Avoid underflow by check of pipe line read when adding 2nd plane. */
1744 if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1747 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1748 dc->current_state->stream_status[0].plane_count == 1 &&
1749 context->stream_status[0].plane_count > 1) {
1750 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1755 void dcn20_post_unlock_program_front_end(
1757 struct dc_state *context)
1760 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1761 struct dce_hwseq *hwseq = dc->hwseq;
1763 DC_LOGGER_INIT(dc->ctx->logger);
1765 for (i = 0; i < dc->res_pool->pipe_count; i++)
1766 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1767 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1770 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1771 * part of the enable operation otherwise, DM may request an immediate flip which
1772 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1773 * is unsupported on DCN.
1775 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1776 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1778 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1779 struct hubp *hubp = pipe->plane_res.hubp;
1782 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1783 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1788 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1789 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1790 struct pipe_ctx *mpcc_pipe;
1792 if (pipe->vtp_locked) {
1793 dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp);
1794 pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true);
1795 pipe->vtp_locked = false;
1797 for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
1798 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
1800 for (i = 0; i < dc->res_pool->pipe_count; i++)
1801 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1802 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1805 /* WA to apply WM setting*/
1806 if (hwseq->wa.DEGVIDCN21)
1807 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1810 /* WA for stutter underflow during MPO transitions when adding 2nd plane */
1811 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1813 if (dc->current_state->stream_status[0].plane_count == 1 &&
1814 context->stream_status[0].plane_count > 1) {
1816 struct timing_generator *tg = dc->res_pool->timing_generators[0];
1818 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1820 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1821 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1826 void dcn20_prepare_bandwidth(
1828 struct dc_state *context)
1830 struct hubbub *hubbub = dc->res_pool->hubbub;
1831 unsigned int compbuf_size_kb = 0;
1833 dc->clk_mgr->funcs->update_clocks(
1838 /* program dchubbub watermarks */
1839 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
1840 &context->bw_ctx.bw.dcn.watermarks,
1841 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1844 /* decrease compbuf size */
1845 if (hubbub->funcs->program_compbuf_size) {
1846 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
1847 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
1849 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
1851 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
1855 void dcn20_optimize_bandwidth(
1857 struct dc_state *context)
1859 struct hubbub *hubbub = dc->res_pool->hubbub;
1861 /* program dchubbub watermarks */
1862 hubbub->funcs->program_watermarks(hubbub,
1863 &context->bw_ctx.bw.dcn.watermarks,
1864 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1867 if (dc->clk_mgr->dc_mode_softmax_enabled)
1868 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1869 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1870 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
1872 dc->clk_mgr->funcs->update_clocks(
1876 /* increase compbuf size */
1877 if (hubbub->funcs->program_compbuf_size)
1878 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
1881 bool dcn20_update_bandwidth(
1883 struct dc_state *context)
1886 struct dce_hwseq *hws = dc->hwseq;
1888 /* recalculate DML parameters */
1889 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1892 /* apply updated bandwidth parameters */
1893 dc->hwss.prepare_bandwidth(dc, context);
1895 /* update hubp configs for all pipes */
1896 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1897 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1899 if (pipe_ctx->plane_state == NULL)
1902 if (pipe_ctx->top_pipe == NULL) {
1903 bool blank = !is_pipe_tree_visible(pipe_ctx);
1905 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1906 pipe_ctx->stream_res.tg,
1907 pipe_ctx->pipe_dlg_param.vready_offset,
1908 pipe_ctx->pipe_dlg_param.vstartup_start,
1909 pipe_ctx->pipe_dlg_param.vupdate_offset,
1910 pipe_ctx->pipe_dlg_param.vupdate_width);
1912 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1913 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
1915 if (pipe_ctx->prev_odm_pipe == NULL)
1916 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1918 if (hws->funcs.setup_vupdate_interrupt)
1919 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1922 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1923 pipe_ctx->plane_res.hubp,
1924 &pipe_ctx->dlg_regs,
1925 &pipe_ctx->ttu_regs,
1927 &pipe_ctx->pipe_dlg_param);
1933 void dcn20_enable_writeback(
1935 struct dc_writeback_info *wb_info,
1936 struct dc_state *context)
1939 struct mcif_wb *mcif_wb;
1940 struct timing_generator *optc;
1942 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1943 ASSERT(wb_info->wb_enabled);
1944 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1945 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1947 /* set the OPTC source mux */
1948 optc = dc->res_pool->timing_generators[dwb->otg_inst];
1949 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1950 /* set MCIF_WB buffer and arbitration configuration */
1951 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1952 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1953 /* Enable MCIF_WB */
1954 mcif_wb->funcs->enable_mcif(mcif_wb);
1956 dwb->funcs->enable(dwb, &wb_info->dwb_params);
1957 /* TODO: add sequence to enable/disable warmup */
1960 void dcn20_disable_writeback(
1962 unsigned int dwb_pipe_inst)
1965 struct mcif_wb *mcif_wb;
1967 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1968 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1969 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1971 dwb->funcs->disable(dwb);
1972 mcif_wb->funcs->disable_mcif(mcif_wb);
1975 bool dcn20_wait_for_blank_complete(
1976 struct output_pixel_processor *opp)
1980 for (counter = 0; counter < 1000; counter++) {
1981 if (opp->funcs->dpg_is_blanked(opp))
1987 if (counter == 1000) {
1988 dm_error("DC: failed to blank crtc!\n");
1995 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1997 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2001 return hubp->funcs->dmdata_status_done(hubp);
2004 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2006 struct dce_hwseq *hws = dc->hwseq;
2008 if (pipe_ctx->stream_res.dsc) {
2009 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2011 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
2013 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
2014 odm_pipe = odm_pipe->next_odm_pipe;
2019 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2021 struct dce_hwseq *hws = dc->hwseq;
2023 if (pipe_ctx->stream_res.dsc) {
2024 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2026 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
2028 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
2029 odm_pipe = odm_pipe->next_odm_pipe;
2034 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2036 struct dc_dmdata_attributes attr = { 0 };
2037 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2039 attr.dmdata_mode = DMDATA_HW_MODE;
2041 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2042 attr.address.quad_part =
2043 pipe_ctx->stream->dmdata_address.quad_part;
2044 attr.dmdata_dl_delta = 0;
2045 attr.dmdata_qos_mode = 0;
2046 attr.dmdata_qos_level = 0;
2047 attr.dmdata_repeat = 1; /* always repeat */
2048 attr.dmdata_updated = 1;
2049 attr.dmdata_sw_data = NULL;
2051 hubp->funcs->dmdata_set_attributes(hubp, &attr);
2054 void dcn20_init_vm_ctx(
2055 struct dce_hwseq *hws,
2057 struct dc_virtual_addr_space_config *va_config,
2060 struct dcn_hubbub_virt_addr_config config;
2063 ASSERT(0); /* VMID cannot be 0 for vm context */
2067 config.page_table_start_addr = va_config->page_table_start_addr;
2068 config.page_table_end_addr = va_config->page_table_end_addr;
2069 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2070 config.page_table_depth = va_config->page_table_depth;
2071 config.page_table_base_addr = va_config->page_table_base_addr;
2073 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2076 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
2078 struct dcn_hubbub_phys_addr_config config;
2080 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2081 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2082 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2083 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2084 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2085 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2086 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2087 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2088 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
2089 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
2091 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
2094 static bool patch_address_for_sbs_tb_stereo(
2095 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2097 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2098 bool sec_split = pipe_ctx->top_pipe &&
2099 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2100 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2101 (pipe_ctx->stream->timing.timing_3d_format ==
2102 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2103 pipe_ctx->stream->timing.timing_3d_format ==
2104 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2105 *addr = plane_state->address.grph_stereo.left_addr;
2106 plane_state->address.grph_stereo.left_addr =
2107 plane_state->address.grph_stereo.right_addr;
2111 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2112 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2113 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2114 plane_state->address.grph_stereo.right_addr =
2115 plane_state->address.grph_stereo.left_addr;
2116 plane_state->address.grph_stereo.right_meta_addr =
2117 plane_state->address.grph_stereo.left_meta_addr;
2122 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2124 bool addr_patched = false;
2125 PHYSICAL_ADDRESS_LOC addr;
2126 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2128 if (plane_state == NULL)
2131 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2133 // Call Helper to track VMID use
2134 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2136 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2137 pipe_ctx->plane_res.hubp,
2138 &plane_state->address,
2139 plane_state->flip_immediate);
2141 plane_state->status.requested_address = plane_state->address;
2143 if (plane_state->flip_immediate)
2144 plane_state->status.current_address = plane_state->address;
2147 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2150 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2151 struct dc_link_settings *link_settings)
2153 struct encoder_unblank_param params = {0};
2154 struct dc_stream_state *stream = pipe_ctx->stream;
2155 struct dc_link *link = stream->link;
2156 struct dce_hwseq *hws = link->dc->hwseq;
2157 struct pipe_ctx *odm_pipe;
2160 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2163 /* only 3 items below are used by unblank */
2164 params.timing = pipe_ctx->stream->timing;
2166 params.link_settings.link_rate = link_settings->link_rate;
2168 if (is_dp_128b_132b_signal(pipe_ctx)) {
2169 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2170 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2171 pipe_ctx->stream_res.hpo_dp_stream_enc,
2172 pipe_ctx->stream_res.tg->inst);
2173 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2174 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2175 params.timing.pix_clk_100hz /= 2;
2176 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2177 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2178 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
2181 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2182 hws->funcs.edp_backlight_control(link, true);
2186 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2188 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2189 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2194 if (tg->funcs->setup_vertical_interrupt2)
2195 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2198 static void dcn20_reset_back_end_for_pipe(
2200 struct pipe_ctx *pipe_ctx,
2201 struct dc_state *context)
2204 struct dc_link *link;
2205 DC_LOGGER_INIT(dc->ctx->logger);
2206 if (pipe_ctx->stream_res.stream_enc == NULL) {
2207 pipe_ctx->stream = NULL;
2211 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2212 link = pipe_ctx->stream->link;
2213 /* DPMS may already disable or */
2214 /* dpms_off status is incorrect due to fastboot
2215 * feature. When system resume from S4 with second
2216 * screen only, the dpms_off would be true but
2217 * VBIOS lit up eDP, so check link status too.
2219 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2220 core_link_disable_stream(pipe_ctx);
2221 else if (pipe_ctx->stream_res.audio)
2222 dc->hwss.disable_audio_stream(pipe_ctx);
2224 /* free acquired resources */
2225 if (pipe_ctx->stream_res.audio) {
2226 /*disable az_endpoint*/
2227 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2230 if (dc->caps.dynamic_audio == true) {
2231 /*we have to dynamic arbitrate the audio endpoints*/
2232 /*we free the resource, need reset is_audio_acquired*/
2233 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2234 pipe_ctx->stream_res.audio, false);
2235 pipe_ctx->stream_res.audio = NULL;
2239 else if (pipe_ctx->stream_res.dsc) {
2240 dp_set_dsc_enable(pipe_ctx, false);
2243 /* by upper caller loop, parent pipe: pipe0, will be reset last.
2244 * back end share by all pipes and will be disable only when disable
2247 if (pipe_ctx->top_pipe == NULL) {
2249 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2251 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2253 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2254 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2255 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2256 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2258 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2259 pipe_ctx->stream_res.tg->funcs->set_drr(
2260 pipe_ctx->stream_res.tg, NULL);
2263 for (i = 0; i < dc->res_pool->pipe_count; i++)
2264 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2267 if (i == dc->res_pool->pipe_count)
2270 pipe_ctx->stream = NULL;
2271 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2272 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2275 void dcn20_reset_hw_ctx_wrap(
2277 struct dc_state *context)
2280 struct dce_hwseq *hws = dc->hwseq;
2283 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2284 struct pipe_ctx *pipe_ctx_old =
2285 &dc->current_state->res_ctx.pipe_ctx[i];
2286 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2288 if (!pipe_ctx_old->stream)
2291 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2294 if (!pipe_ctx->stream ||
2295 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2296 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2298 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2299 if (hws->funcs.enable_stream_gating)
2300 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
2302 old_clk->funcs->cs_power_down(old_clk);
2307 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
2309 struct mpc *mpc = dc->res_pool->mpc;
2311 // input to MPCC is always RGB, by default leave black_color at 0
2312 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
2313 get_hdr_visual_confirm_color(pipe_ctx, color);
2314 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
2315 get_surface_visual_confirm_color(pipe_ctx, color);
2316 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
2317 get_mpctree_visual_confirm_color(pipe_ctx, color);
2318 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
2319 get_surface_tile_visual_confirm_color(pipe_ctx, color);
2321 if (mpc->funcs->set_bg_color)
2322 mpc->funcs->set_bg_color(mpc, color, mpcc_id);
2325 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2327 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2328 struct mpcc_blnd_cfg blnd_cfg = {0};
2329 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2331 struct mpcc *new_mpcc;
2332 struct mpc *mpc = dc->res_pool->mpc;
2333 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2335 if (per_pixel_alpha)
2336 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2338 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2340 blnd_cfg.overlap_only = false;
2341 blnd_cfg.global_gain = 0xff;
2343 if (pipe_ctx->plane_state->global_alpha)
2344 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2346 blnd_cfg.global_alpha = 0xff;
2348 blnd_cfg.background_color_bpc = 4;
2349 blnd_cfg.bottom_gain_mode = 0;
2350 blnd_cfg.top_gain = 0x1f000;
2351 blnd_cfg.bottom_inside_gain = 0x1f000;
2352 blnd_cfg.bottom_outside_gain = 0x1f000;
2353 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2354 if (pipe_ctx->plane_state->format
2355 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2356 blnd_cfg.pre_multiplied_alpha = false;
2360 * Note: currently there is a bug in init_hw such that
2361 * on resume from hibernate, BIOS sets up MPCC0, and
2362 * we do mpcc_remove but the mpcc cannot go to idle
2363 * after remove. This cause us to pick mpcc1 here,
2364 * which causes a pstate hang for yet unknown reason.
2366 mpcc_id = hubp->inst;
2368 /* If there is no full update, don't need to touch MPC tree*/
2369 if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2370 !pipe_ctx->update_flags.bits.mpcc) {
2371 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2372 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2376 /* check if this MPCC is already being used */
2377 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2378 /* remove MPCC if being used */
2379 if (new_mpcc != NULL)
2380 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2382 if (dc->debug.sanity_checks)
2383 mpc->funcs->assert_mpcc_idle_before_connect(
2384 dc->res_pool->mpc, mpcc_id);
2386 /* Call MPC to insert new plane */
2387 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2394 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2396 ASSERT(new_mpcc != NULL);
2397 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2398 hubp->mpcc_id = mpcc_id;
2401 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2403 enum dc_lane_count lane_count =
2404 pipe_ctx->stream->link->cur_link_settings.lane_count;
2406 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2407 struct dc_link *link = pipe_ctx->stream->link;
2409 uint32_t active_total_with_borders;
2410 uint32_t early_control = 0;
2411 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2412 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2413 struct dc *dc = pipe_ctx->stream->ctx->dc;
2415 if (is_dp_128b_132b_signal(pipe_ctx)) {
2416 if (dc->hwseq->funcs.setup_hpo_hw_control)
2417 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
2420 link_hwss->setup_stream_encoder(pipe_ctx);
2422 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2423 if (dc->hwss.program_dmdata_engine)
2424 dc->hwss.program_dmdata_engine(pipe_ctx);
2427 dc->hwss.update_info_frame(pipe_ctx);
2429 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2430 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2432 /* enable early control to avoid corruption on DP monitor*/
2433 active_total_with_borders =
2434 timing->h_addressable
2435 + timing->h_border_left
2436 + timing->h_border_right;
2438 if (lane_count != 0)
2439 early_control = active_total_with_borders % lane_count;
2441 if (early_control == 0)
2442 early_control = lane_count;
2444 tg->funcs->set_early_control(tg, early_control);
2446 /* enable audio only within mode set */
2447 if (pipe_ctx->stream_res.audio != NULL) {
2448 if (is_dp_128b_132b_signal(pipe_ctx))
2449 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc);
2450 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
2451 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2455 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2457 struct dc_stream_state *stream = pipe_ctx->stream;
2458 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2459 bool enable = false;
2460 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2461 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
2465 /* if using dynamic meta, don't set up generic infopackets */
2466 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2467 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2474 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2477 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2481 void dcn20_fpga_init_hw(struct dc *dc)
2484 struct dce_hwseq *hws = dc->hwseq;
2485 struct resource_pool *res_pool = dc->res_pool;
2486 struct dc_state *context = dc->current_state;
2488 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2489 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2491 // Initialize the dccg
2492 if (res_pool->dccg->funcs->dccg_init)
2493 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2495 //Enable ability to power gate / don't force power on permanently
2496 hws->funcs.enable_power_gating_plane(hws, true);
2498 // Specific to FPGA dccg and registers
2499 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2500 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2502 hws->funcs.dccg_init(hws);
2504 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2505 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2506 if (REG(REFCLK_CNTL))
2507 REG_WRITE(REFCLK_CNTL, 0);
2511 /* Blank pixel data with OPP DPG */
2512 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2513 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2515 if (tg->funcs->is_tg_enabled(tg))
2516 dcn20_init_blank(dc, tg);
2519 for (i = 0; i < res_pool->timing_generator_count; i++) {
2520 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2522 if (tg->funcs->is_tg_enabled(tg))
2523 tg->funcs->lock(tg);
2526 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2527 struct dpp *dpp = res_pool->dpps[i];
2529 dpp->funcs->dpp_reset(dpp);
2532 /* Reset all MPCC muxes */
2533 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2535 /* initialize OPP mpc_tree parameter */
2536 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2537 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2538 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2539 for (j = 0; j < MAX_PIPES; j++)
2540 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2543 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2544 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2545 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2546 struct hubp *hubp = dc->res_pool->hubps[i];
2547 struct dpp *dpp = dc->res_pool->dpps[i];
2549 pipe_ctx->stream_res.tg = tg;
2550 pipe_ctx->pipe_idx = i;
2552 pipe_ctx->plane_res.hubp = hubp;
2553 pipe_ctx->plane_res.dpp = dpp;
2554 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2555 hubp->mpcc_id = dpp->inst;
2556 hubp->opp_id = OPP_ID_INVALID;
2557 hubp->power_gated = false;
2558 pipe_ctx->stream_res.opp = NULL;
2560 hubp->funcs->hubp_init(hubp);
2562 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2563 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2564 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2565 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2567 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2570 /* initialize DWB pointer to MCIF_WB */
2571 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2572 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2574 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2575 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2577 if (tg->funcs->is_tg_enabled(tg))
2578 tg->funcs->unlock(tg);
2581 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2582 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2584 dc->hwss.disable_plane(dc, pipe_ctx);
2586 pipe_ctx->stream_res.tg = NULL;
2587 pipe_ctx->plane_res.hubp = NULL;
2590 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2591 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2593 tg->funcs->tg_init(tg);
2596 if (dc->res_pool->hubbub->funcs->init_crb)
2597 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
2600 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2601 struct dc_crtc_timing *timing,
2602 unsigned int max_input_rate_in_khz)
2604 unsigned int old_v_front_porch;
2605 unsigned int old_v_total;
2606 unsigned int max_input_rate_in_100hz;
2607 unsigned long long new_v_total;
2609 max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2610 if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2613 old_v_total = timing->v_total;
2614 old_v_front_porch = timing->v_front_porch;
2616 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2617 timing->pix_clk_100hz = max_input_rate_in_100hz;
2619 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2621 timing->v_total = new_v_total;
2622 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2627 void dcn20_set_disp_pattern_generator(const struct dc *dc,
2628 struct pipe_ctx *pipe_ctx,
2629 enum controller_dp_test_pattern test_pattern,
2630 enum controller_dp_color_space color_space,
2631 enum dc_color_depth color_depth,
2632 const struct tg_color *solid_color,
2633 int width, int height, int offset)
2635 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2636 color_space, color_depth, solid_color, width, height, offset);