drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dc_link_dp.h"
  50 #include "vm_helper.h"
  51 #include "dccg.h"
  52 #include "dc_dmub_srv.h"
  53 #include "dce/dmub_hw_lock_mgr.h"
  54 #include "hw_sequencer.h"
  55 #include "inc/link_dpcd.h"
  56 #include "dpcd_defs.h"
  57 #include "inc/link_enc_cfg.h"
  58 #include "link_hwss.h"
  59
  60 #define DC_LOGGER_INIT(logger)
  61
  62 #define CTX \
  63         hws->ctx
  64 #define REG(reg)\
  65         hws->regs->reg
  66
  67 #undef FN
  68 #define FN(reg_name, field_name) \
  69         hws->shifts->field_name, hws->masks->field_name
  70
  71 static int find_free_gsl_group(const struct dc *dc)
  72 {
  73         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  74                 return 1;
  75         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  76                 return 2;
  77         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  78                 return 3;
  79
  80         return 0;
  81 }
  82
  83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  84  * This is only used to lock pipes in pipe splitting case with immediate flip
  85  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  86  * so we get tearing with freesync since we cannot flip multiple pipes
  87  * atomically.
  88  * We use GSL for this:
  89  * - immediate flip: find first available GSL group if not already assigned
  90  *                   program gsl with that group, set current OTG as master
  91  *                   and always us 0x4 = AND of flip_ready from all pipes
  92  * - vsync flip: disable GSL if used
  93  *
  94  * Groups in stream_res are stored as +1 from HW registers, i.e.
  95  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  96  * Using a magic value like -1 would require tracking all inits/resets
  97  */
  98 static void dcn20_setup_gsl_group_as_lock(
  99                 const struct dc *dc,
 100                 struct pipe_ctx *pipe_ctx,
 101                 bool enable)
 102 {
 103         struct gsl_params gsl;
 104         int group_idx;
 105
 106         memset(&gsl, 0, sizeof(struct gsl_params));
 107
 108         if (enable) {
 109                 /* return if group already assigned since GSL was set up
 110                  * for vsync flip, we would unassign so it can't be "left over"
 111                  */
 112                 if (pipe_ctx->stream_res.gsl_group > 0)
 113                         return;
 114
 115                 group_idx = find_free_gsl_group(dc);
 116                 ASSERT(group_idx != 0);
 117                 pipe_ctx->stream_res.gsl_group = group_idx;
 118
 119                 /* set gsl group reg field and mark resource used */
 120                 switch (group_idx) {
 121                 case 1:
 122                         gsl.gsl0_en = 1;
 123                         dc->res_pool->gsl_groups.gsl_0 = 1;
 124                         break;
 125                 case 2:
 126                         gsl.gsl1_en = 1;
 127                         dc->res_pool->gsl_groups.gsl_1 = 1;
 128                         break;
 129                 case 3:
 130                         gsl.gsl2_en = 1;
 131                         dc->res_pool->gsl_groups.gsl_2 = 1;
 132                         break;
 133                 default:
 134                         BREAK_TO_DEBUGGER();
 135                         return; // invalid case
 136                 }
 137                 gsl.gsl_master_en = 1;
 138         } else {
 139                 group_idx = pipe_ctx->stream_res.gsl_group;
 140                 if (group_idx == 0)
 141                         return; // if not in use, just return
 142
 143                 pipe_ctx->stream_res.gsl_group = 0;
 144
 145                 /* unset gsl group reg field and mark resource free */
 146                 switch (group_idx) {
 147                 case 1:
 148                         gsl.gsl0_en = 0;
 149                         dc->res_pool->gsl_groups.gsl_0 = 0;
 150                         break;
 151                 case 2:
 152                         gsl.gsl1_en = 0;
 153                         dc->res_pool->gsl_groups.gsl_1 = 0;
 154                         break;
 155                 case 3:
 156                         gsl.gsl2_en = 0;
 157                         dc->res_pool->gsl_groups.gsl_2 = 0;
 158                         break;
 159                 default:
 160                         BREAK_TO_DEBUGGER();
 161                         return;
 162                 }
 163                 gsl.gsl_master_en = 0;
 164         }
 165
 166         /* at this point we want to program whether it's to enable or disable */
 167         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 168                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 169                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 170                         pipe_ctx->stream_res.tg,
 171                         &gsl);
 172
 173                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 174                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 175         } else
 176                 BREAK_TO_DEBUGGER();
 177 }
 178
 179 void dcn20_set_flip_control_gsl(
 180                 struct pipe_ctx *pipe_ctx,
 181                 bool flip_immediate)
 182 {
 183         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 184                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 185                                 pipe_ctx->plane_res.hubp, flip_immediate);
 186
 187 }
 188
 189 void dcn20_enable_power_gating_plane(
 190         struct dce_hwseq *hws,
 191         bool enable)
 192 {
 193         bool force_on = true; /* disable power gating */
 194
 195         if (enable)
 196                 force_on = false;
 197
 198         /* DCHUBP0/1/2/3/4/5 */
 199         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 200         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 201         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 202         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 203         if (REG(DOMAIN8_PG_CONFIG))
 204                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 205         if (REG(DOMAIN10_PG_CONFIG))
 206                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 207
 208         /* DPP0/1/2/3/4/5 */
 209         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 210         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 211         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 212         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 213         if (REG(DOMAIN9_PG_CONFIG))
 214                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 215         if (REG(DOMAIN11_PG_CONFIG))
 216                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 217
 218         /* DCS0/1/2/3/4/5 */
 219         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 220         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 221         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 222         if (REG(DOMAIN19_PG_CONFIG))
 223                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 224         if (REG(DOMAIN20_PG_CONFIG))
 225                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 226         if (REG(DOMAIN21_PG_CONFIG))
 227                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 228 }
 229
 230 void dcn20_dccg_init(struct dce_hwseq *hws)
 231 {
 232         /*
 233          * set MICROSECOND_TIME_BASE_DIV
 234          * 100Mhz refclk -> 0x120264
 235          * 27Mhz refclk -> 0x12021b
 236          * 48Mhz refclk -> 0x120230
 237          *
 238          */
 239         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 240
 241         /*
 242          * set MILLISECOND_TIME_BASE_DIV
 243          * 100Mhz refclk -> 0x1186a0
 244          * 27Mhz refclk -> 0x106978
 245          * 48Mhz refclk -> 0x10bb80
 246          *
 247          */
 248         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 249
 250         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 251         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 252 }
 253
 254 void dcn20_disable_vga(
 255         struct dce_hwseq *hws)
 256 {
 257         REG_WRITE(D1VGA_CONTROL, 0);
 258         REG_WRITE(D2VGA_CONTROL, 0);
 259         REG_WRITE(D3VGA_CONTROL, 0);
 260         REG_WRITE(D4VGA_CONTROL, 0);
 261         REG_WRITE(D5VGA_CONTROL, 0);
 262         REG_WRITE(D6VGA_CONTROL, 0);
 263 }
 264
 265 void dcn20_program_triple_buffer(
 266         const struct dc *dc,
 267         struct pipe_ctx *pipe_ctx,
 268         bool enable_triple_buffer)
 269 {
 270         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 271                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 272                         pipe_ctx->plane_res.hubp,
 273                         enable_triple_buffer);
 274         }
 275 }
 276
 277 /* Blank pixel data during initialization */
 278 void dcn20_init_blank(
 279                 struct dc *dc,
 280                 struct timing_generator *tg)
 281 {
 282         struct dce_hwseq *hws = dc->hwseq;
 283         enum dc_color_space color_space;
 284         struct tg_color black_color = {0};
 285         struct output_pixel_processor *opp = NULL;
 286         struct output_pixel_processor *bottom_opp = NULL;
 287         uint32_t num_opps, opp_id_src0, opp_id_src1;
 288         uint32_t otg_active_width, otg_active_height;
 289
 290         /* program opp dpg blank color */
 291         color_space = COLOR_SPACE_SRGB;
 292         color_space_to_black_color(dc, color_space, &black_color);
 293
 294         /* get the OTG active size */
 295         tg->funcs->get_otg_active_size(tg,
 296                         &otg_active_width,
 297                         &otg_active_height);
 298
 299         /* get the OPTC source */
 300         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 301
 302         if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
 303                 ASSERT(false);
 304                 return;
 305         }
 306         opp = dc->res_pool->opps[opp_id_src0];
 307
 308         if (num_opps == 2) {
 309                 otg_active_width = otg_active_width / 2;
 310
 311                 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
 312                         ASSERT(false);
 313                         return;
 314                 }
 315                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 316         }
 317
 318         opp->funcs->opp_set_disp_pattern_generator(
 319                         opp,
 320                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 321                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 322                         COLOR_DEPTH_UNDEFINED,
 323                         &black_color,
 324                         otg_active_width,
 325                         otg_active_height,
 326                         0);
 327
 328         if (num_opps == 2) {
 329                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 330                                 bottom_opp,
 331                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 332                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 333                                 COLOR_DEPTH_UNDEFINED,
 334                                 &black_color,
 335                                 otg_active_width,
 336                                 otg_active_height,
 337                                 0);
 338         }
 339
 340         hws->funcs.wait_for_blank_complete(opp);
 341 }
 342
 343 void dcn20_dsc_pg_control(
 344                 struct dce_hwseq *hws,
 345                 unsigned int dsc_inst,
 346                 bool power_on)
 347 {
 348         uint32_t power_gate = power_on ? 0 : 1;
 349         uint32_t pwr_status = power_on ? 0 : 2;
 350         uint32_t org_ip_request_cntl = 0;
 351
 352         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 353                 return;
 354
 355         if (REG(DOMAIN16_PG_CONFIG) == 0)
 356                 return;
 357
 358         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 359         if (org_ip_request_cntl == 0)
 360                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 361
 362         switch (dsc_inst) {
 363         case 0: /* DSC0 */
 364                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 365                                 DOMAIN16_POWER_GATE, power_gate);
 366
 367                 REG_WAIT(DOMAIN16_PG_STATUS,
 368                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 369                                 1, 1000);
 370                 break;
 371         case 1: /* DSC1 */
 372                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 373                                 DOMAIN17_POWER_GATE, power_gate);
 374
 375                 REG_WAIT(DOMAIN17_PG_STATUS,
 376                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 377                                 1, 1000);
 378                 break;
 379         case 2: /* DSC2 */
 380                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 381                                 DOMAIN18_POWER_GATE, power_gate);
 382
 383                 REG_WAIT(DOMAIN18_PG_STATUS,
 384                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 385                                 1, 1000);
 386                 break;
 387         case 3: /* DSC3 */
 388                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 389                                 DOMAIN19_POWER_GATE, power_gate);
 390
 391                 REG_WAIT(DOMAIN19_PG_STATUS,
 392                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 393                                 1, 1000);
 394                 break;
 395         case 4: /* DSC4 */
 396                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 397                                 DOMAIN20_POWER_GATE, power_gate);
 398
 399                 REG_WAIT(DOMAIN20_PG_STATUS,
 400                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 401                                 1, 1000);
 402                 break;
 403         case 5: /* DSC5 */
 404                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 405                                 DOMAIN21_POWER_GATE, power_gate);
 406
 407                 REG_WAIT(DOMAIN21_PG_STATUS,
 408                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 409                                 1, 1000);
 410                 break;
 411         default:
 412                 BREAK_TO_DEBUGGER();
 413                 break;
 414         }
 415
 416         if (org_ip_request_cntl == 0)
 417                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 418 }
 419
 420 void dcn20_dpp_pg_control(
 421                 struct dce_hwseq *hws,
 422                 unsigned int dpp_inst,
 423                 bool power_on)
 424 {
 425         uint32_t power_gate = power_on ? 0 : 1;
 426         uint32_t pwr_status = power_on ? 0 : 2;
 427
 428         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 429                 return;
 430         if (REG(DOMAIN1_PG_CONFIG) == 0)
 431                 return;
 432
 433         switch (dpp_inst) {
 434         case 0: /* DPP0 */
 435                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 436                                 DOMAIN1_POWER_GATE, power_gate);
 437
 438                 REG_WAIT(DOMAIN1_PG_STATUS,
 439                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 440                                 1, 1000);
 441                 break;
 442         case 1: /* DPP1 */
 443                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 444                                 DOMAIN3_POWER_GATE, power_gate);
 445
 446                 REG_WAIT(DOMAIN3_PG_STATUS,
 447                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 448                                 1, 1000);
 449                 break;
 450         case 2: /* DPP2 */
 451                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 452                                 DOMAIN5_POWER_GATE, power_gate);
 453
 454                 REG_WAIT(DOMAIN5_PG_STATUS,
 455                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 456                                 1, 1000);
 457                 break;
 458         case 3: /* DPP3 */
 459                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 460                                 DOMAIN7_POWER_GATE, power_gate);
 461
 462                 REG_WAIT(DOMAIN7_PG_STATUS,
 463                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 464                                 1, 1000);
 465                 break;
 466         case 4: /* DPP4 */
 467                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 468                                 DOMAIN9_POWER_GATE, power_gate);
 469
 470                 REG_WAIT(DOMAIN9_PG_STATUS,
 471                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 472                                 1, 1000);
 473                 break;
 474         case 5: /* DPP5 */
 475                 /*
 476                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 477                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 478                  * reset.
 479                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 480                  *              DOMAIN11_POWER_GATE, power_gate);
 481                  *
 482                  * REG_WAIT(DOMAIN11_PG_STATUS,
 483                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 484                  *              1, 1000);
 485                  */
 486                 break;
 487         default:
 488                 BREAK_TO_DEBUGGER();
 489                 break;
 490         }
 491 }
 492
 493
 494 void dcn20_hubp_pg_control(
 495                 struct dce_hwseq *hws,
 496                 unsigned int hubp_inst,
 497                 bool power_on)
 498 {
 499         uint32_t power_gate = power_on ? 0 : 1;
 500         uint32_t pwr_status = power_on ? 0 : 2;
 501
 502         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 503                 return;
 504         if (REG(DOMAIN0_PG_CONFIG) == 0)
 505                 return;
 506
 507         switch (hubp_inst) {
 508         case 0: /* DCHUBP0 */
 509                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 510                                 DOMAIN0_POWER_GATE, power_gate);
 511
 512                 REG_WAIT(DOMAIN0_PG_STATUS,
 513                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 514                                 1, 1000);
 515                 break;
 516         case 1: /* DCHUBP1 */
 517                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 518                                 DOMAIN2_POWER_GATE, power_gate);
 519
 520                 REG_WAIT(DOMAIN2_PG_STATUS,
 521                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 522                                 1, 1000);
 523                 break;
 524         case 2: /* DCHUBP2 */
 525                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 526                                 DOMAIN4_POWER_GATE, power_gate);
 527
 528                 REG_WAIT(DOMAIN4_PG_STATUS,
 529                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 530                                 1, 1000);
 531                 break;
 532         case 3: /* DCHUBP3 */
 533                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 534                                 DOMAIN6_POWER_GATE, power_gate);
 535
 536                 REG_WAIT(DOMAIN6_PG_STATUS,
 537                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 538                                 1, 1000);
 539                 break;
 540         case 4: /* DCHUBP4 */
 541                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 542                                 DOMAIN8_POWER_GATE, power_gate);
 543
 544                 REG_WAIT(DOMAIN8_PG_STATUS,
 545                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 546                                 1, 1000);
 547                 break;
 548         case 5: /* DCHUBP5 */
 549                 /*
 550                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 551                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 552                  * reset.
 553                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 554                  *              DOMAIN10_POWER_GATE, power_gate);
 555                  *
 556                  * REG_WAIT(DOMAIN10_PG_STATUS,
 557                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 558                  *              1, 1000);
 559                  */
 560                 break;
 561         default:
 562                 BREAK_TO_DEBUGGER();
 563                 break;
 564         }
 565 }
 566
 567
 568 /* disable HW used by plane.
 569  * note:  cannot disable until disconnect is complete
 570  */
 571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 572 {
 573         struct dce_hwseq *hws = dc->hwseq;
 574         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 575         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 576
 577         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 578
 579         /* In flip immediate with pipe splitting case GSL is used for
 580          * synchronization so we must disable it when the plane is disabled.
 581          */
 582         if (pipe_ctx->stream_res.gsl_group != 0)
 583                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 584
 585         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 586
 587         hubp->funcs->hubp_clk_cntl(hubp, false);
 588
 589         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 590
 591         hubp->power_gated = true;
 592
 593         hws->funcs.plane_atomic_power_down(dc,
 594                         pipe_ctx->plane_res.dpp,
 595                         pipe_ctx->plane_res.hubp);
 596
 597         pipe_ctx->stream = NULL;
 598         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 599         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 600         pipe_ctx->top_pipe = NULL;
 601         pipe_ctx->bottom_pipe = NULL;
 602         pipe_ctx->plane_state = NULL;
 603 }
 604
 605
 606 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 607 {
 608         DC_LOGGER_INIT(dc->ctx->logger);
 609
 610         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 611                 return;
 612
 613         dcn20_plane_atomic_disable(dc, pipe_ctx);
 614
 615         DC_LOG_DC("Power down front end %d\n",
 616                                         pipe_ctx->pipe_idx);
 617 }
 618
 619 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
 620 {
 621         dcn20_blank_pixel_data(dc, pipe_ctx, blank);
 622 }
 623
 624 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 625                 int opp_cnt)
 626 {
 627         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 628         int flow_ctrl_cnt;
 629
 630         if (opp_cnt >= 2)
 631                 hblank_halved = true;
 632
 633         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 634                         stream->timing.h_border_left -
 635                         stream->timing.h_border_right;
 636
 637         if (hblank_halved)
 638                 flow_ctrl_cnt /= 2;
 639
 640         /* ODM combine 4:1 case */
 641         if (opp_cnt == 4)
 642                 flow_ctrl_cnt /= 2;
 643
 644         return flow_ctrl_cnt;
 645 }
 646
 647 enum dc_status dcn20_enable_stream_timing(
 648                 struct pipe_ctx *pipe_ctx,
 649                 struct dc_state *context,
 650                 struct dc *dc)
 651 {
 652         struct dce_hwseq *hws = dc->hwseq;
 653         struct dc_stream_state *stream = pipe_ctx->stream;
 654         struct drr_params params = {0};
 655         unsigned int event_triggers = 0;
 656         struct pipe_ctx *odm_pipe;
 657         int opp_cnt = 1;
 658         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 659         bool interlace = stream->timing.flags.INTERLACE;
 660         int i;
 661         struct mpc_dwb_flow_control flow_control;
 662         struct mpc *mpc = dc->res_pool->mpc;
 663         bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
 664         unsigned int k1_div = PIXEL_RATE_DIV_NA;
 665         unsigned int k2_div = PIXEL_RATE_DIV_NA;
 666
 667         if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
 668                 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
 669
 670                 dc->res_pool->dccg->funcs->set_pixel_rate_div(
 671                         dc->res_pool->dccg,
 672                         pipe_ctx->stream_res.tg->inst,
 673                         k1_div, k2_div);
 674         }
 675         /* by upper caller loop, pipe0 is parent pipe and be called first.
 676          * back end is set up by for pipe0. Other children pipe share back end
 677          * with pipe 0. No program is needed.
 678          */
 679         if (pipe_ctx->top_pipe != NULL)
 680                 return DC_OK;
 681
 682         /* TODO check if timing_changed, disable stream if timing changed */
 683
 684         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 685                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 686                 opp_cnt++;
 687         }
 688
 689         if (opp_cnt > 1)
 690                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 691                                 pipe_ctx->stream_res.tg,
 692                                 opp_inst, opp_cnt,
 693                                 &pipe_ctx->stream->timing);
 694
 695         /* HW program guide assume display already disable
 696          * by unplug sequence. OTG assume stop.
 697          */
 698         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 699
 700         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 701                         pipe_ctx->clock_source,
 702                         &pipe_ctx->stream_res.pix_clk_params,
 703                         &pipe_ctx->pll_settings)) {
 704                 BREAK_TO_DEBUGGER();
 705                 return DC_ERROR_UNEXPECTED;
 706         }
 707
 708         if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
 709                 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
 710
 711         pipe_ctx->stream_res.tg->funcs->program_timing(
 712                         pipe_ctx->stream_res.tg,
 713                         &stream->timing,
 714                         pipe_ctx->pipe_dlg_param.vready_offset,
 715                         pipe_ctx->pipe_dlg_param.vstartup_start,
 716                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 717                         pipe_ctx->pipe_dlg_param.vupdate_width,
 718                         pipe_ctx->stream->signal,
 719                         true);
 720
 721         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
 722         flow_control.flow_ctrl_mode = 0;
 723         flow_control.flow_ctrl_cnt0 = 0x80;
 724         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
 725         if (mpc->funcs->set_out_rate_control) {
 726                 for (i = 0; i < opp_cnt; ++i) {
 727                         mpc->funcs->set_out_rate_control(
 728                                         mpc, opp_inst[i],
 729                                         true,
 730                                         rate_control_2x_pclk,
 731                                         &flow_control);
 732                 }
 733         }
 734
 735         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 736                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 737                                 odm_pipe->stream_res.opp,
 738                                 true);
 739
 740         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 741                         pipe_ctx->stream_res.opp,
 742                         true);
 743
 744         hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
 745
 746         /* VTG is  within DCHUB command block. DCFCLK is always on */
 747         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 748                 BREAK_TO_DEBUGGER();
 749                 return DC_ERROR_UNEXPECTED;
 750         }
 751
 752         hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 753
 754         params.vertical_total_min = stream->adjust.v_total_min;
 755         params.vertical_total_max = stream->adjust.v_total_max;
 756         params.vertical_total_mid = stream->adjust.v_total_mid;
 757         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 758         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 759                 pipe_ctx->stream_res.tg->funcs->set_drr(
 760                         pipe_ctx->stream_res.tg, &params);
 761
 762         // DRR should set trigger event to monitor surface update event
 763         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 764                 event_triggers = 0x80;
 765         /* Event triggers and num frames initialized for DRR, but can be
 766          * later updated for PSR use. Note DRR trigger events are generated
 767          * regardless of whether num frames met.
 768          */
 769         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 770                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 771                                 pipe_ctx->stream_res.tg, event_triggers, 2);
 772
 773         /* TODO program crtc source select for non-virtual signal*/
 774         /* TODO program FMT */
 775         /* TODO setup link_enc */
 776         /* TODO set stream attributes */
 777         /* TODO program audio */
 778         /* TODO enable stream if timing changed */
 779         /* TODO unblank stream if DP */
 780
 781         if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 782                 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
 783                         pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
 784         }
 785         return DC_OK;
 786 }
 787
 788 void dcn20_program_output_csc(struct dc *dc,
 789                 struct pipe_ctx *pipe_ctx,
 790                 enum dc_color_space colorspace,
 791                 uint16_t *matrix,
 792                 int opp_id)
 793 {
 794         struct mpc *mpc = dc->res_pool->mpc;
 795         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 796         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 797
 798         if (mpc->funcs->power_on_mpc_mem_pwr)
 799                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 800
 801         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 802                 if (mpc->funcs->set_output_csc != NULL)
 803                         mpc->funcs->set_output_csc(mpc,
 804                                         opp_id,
 805                                         matrix,
 806                                         ocsc_mode);
 807         } else {
 808                 if (mpc->funcs->set_ocsc_default != NULL)
 809                         mpc->funcs->set_ocsc_default(mpc,
 810                                         opp_id,
 811                                         colorspace,
 812                                         ocsc_mode);
 813         }
 814 }
 815
 816 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 817                                 const struct dc_stream_state *stream)
 818 {
 819         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 820         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 821         struct pwl_params *params = NULL;
 822         /*
 823          * program OGAM only for the top pipe
 824          * if there is a pipe split then fix diagnostic is required:
 825          * how to pass OGAM parameter for stream.
 826          * if programming for all pipes is required then remove condition
 827          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 828          */
 829         if (mpc->funcs->power_on_mpc_mem_pwr)
 830                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 831         if (pipe_ctx->top_pipe == NULL
 832                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 833                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 834                         params = &stream->out_transfer_func->pwl;
 835                 else if (pipe_ctx->stream->out_transfer_func->type ==
 836                         TF_TYPE_DISTRIBUTED_POINTS &&
 837                         cm_helper_translate_curve_to_hw_format(
 838                         stream->out_transfer_func,
 839                         &mpc->blender_params, false))
 840                         params = &mpc->blender_params;
 841                 /*
 842                  * there is no ROM
 843                  */
 844                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 845                         BREAK_TO_DEBUGGER();
 846         }
 847         /*
 848          * if above if is not executed then 'params' equal to 0 and set in bypass
 849          */
 850         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 851
 852         return true;
 853 }
 854
 855 bool dcn20_set_blend_lut(
 856         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 857 {
 858         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 859         bool result = true;
 860         struct pwl_params *blend_lut = NULL;
 861
 862         if (plane_state->blend_tf) {
 863                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 864                         blend_lut = &plane_state->blend_tf->pwl;
 865                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 866                         cm_helper_translate_curve_to_hw_format(
 867                                         plane_state->blend_tf,
 868                                         &dpp_base->regamma_params, false);
 869                         blend_lut = &dpp_base->regamma_params;
 870                 }
 871         }
 872         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 873
 874         return result;
 875 }
 876
 877 bool dcn20_set_shaper_3dlut(
 878         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 879 {
 880         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 881         bool result = true;
 882         struct pwl_params *shaper_lut = NULL;
 883
 884         if (plane_state->in_shaper_func) {
 885                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 886                         shaper_lut = &plane_state->in_shaper_func->pwl;
 887                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 888                         cm_helper_translate_curve_to_hw_format(
 889                                         plane_state->in_shaper_func,
 890                                         &dpp_base->shaper_params, true);
 891                         shaper_lut = &dpp_base->shaper_params;
 892                 }
 893         }
 894
 895         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 896         if (plane_state->lut3d_func &&
 897                 plane_state->lut3d_func->state.bits.initialized == 1)
 898                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 899                                                                 &plane_state->lut3d_func->lut_3d);
 900         else
 901                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 902
 903         return result;
 904 }
 905
 906 bool dcn20_set_input_transfer_func(struct dc *dc,
 907                                 struct pipe_ctx *pipe_ctx,
 908                                 const struct dc_plane_state *plane_state)
 909 {
 910         struct dce_hwseq *hws = dc->hwseq;
 911         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 912         const struct dc_transfer_func *tf = NULL;
 913         bool result = true;
 914         bool use_degamma_ram = false;
 915
 916         if (dpp_base == NULL || plane_state == NULL)
 917                 return false;
 918
 919         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 920         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 921
 922         if (plane_state->in_transfer_func)
 923                 tf = plane_state->in_transfer_func;
 924
 925
 926         if (tf == NULL) {
 927                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 928                                 IPP_DEGAMMA_MODE_BYPASS);
 929                 return true;
 930         }
 931
 932         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 933                 use_degamma_ram = true;
 934
 935         if (use_degamma_ram == true) {
 936                 if (tf->type == TF_TYPE_HWPWL)
 937                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 938                                         &tf->pwl);
 939                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 940                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 941                                         &dpp_base->degamma_params);
 942                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 943                                 &dpp_base->degamma_params);
 944                 }
 945                 return true;
 946         }
 947         /* handle here the optimized cases when de-gamma ROM could be used.
 948          *
 949          */
 950         if (tf->type == TF_TYPE_PREDEFINED) {
 951                 switch (tf->tf) {
 952                 case TRANSFER_FUNCTION_SRGB:
 953                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 954                                         IPP_DEGAMMA_MODE_HW_sRGB);
 955                         break;
 956                 case TRANSFER_FUNCTION_BT709:
 957                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 958                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 959                         break;
 960                 case TRANSFER_FUNCTION_LINEAR:
 961                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 962                                         IPP_DEGAMMA_MODE_BYPASS);
 963                         break;
 964                 case TRANSFER_FUNCTION_PQ:
 965                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
 966                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
 967                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
 968                         result = true;
 969                         break;
 970                 default:
 971                         result = false;
 972                         break;
 973                 }
 974         } else if (tf->type == TF_TYPE_BYPASS)
 975                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 976                                 IPP_DEGAMMA_MODE_BYPASS);
 977         else {
 978                 /*
 979                  * if we are here, we did not handle correctly.
 980                  * fix is required for this use case
 981                  */
 982                 BREAK_TO_DEBUGGER();
 983                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 984                                 IPP_DEGAMMA_MODE_BYPASS);
 985         }
 986
 987         return result;
 988 }
 989
 990 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 991 {
 992         struct pipe_ctx *odm_pipe;
 993         int opp_cnt = 1;
 994         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 995
 996         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 997                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 998                 opp_cnt++;
 999         }
1000
1001         if (opp_cnt > 1)
1002                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1003                                 pipe_ctx->stream_res.tg,
1004                                 opp_inst, opp_cnt,
1005                                 &pipe_ctx->stream->timing);
1006         else
1007                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1008                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1009 }
1010
1011 void dcn20_blank_pixel_data(
1012                 struct dc *dc,
1013                 struct pipe_ctx *pipe_ctx,
1014                 bool blank)
1015 {
1016         struct tg_color black_color = {0};
1017         struct stream_resource *stream_res = &pipe_ctx->stream_res;
1018         struct dc_stream_state *stream = pipe_ctx->stream;
1019         enum dc_color_space color_space = stream->output_color_space;
1020         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1021         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1022         struct pipe_ctx *odm_pipe;
1023         int odm_cnt = 1;
1024
1025         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1026         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1027
1028         if (stream->link->test_pattern_enabled)
1029                 return;
1030
1031         /* get opp dpg blank color */
1032         color_space_to_black_color(dc, color_space, &black_color);
1033
1034         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1035                 odm_cnt++;
1036
1037         width = width / odm_cnt;
1038
1039         if (blank) {
1040                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1041
1042                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1043                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1044                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1045                 }
1046         } else {
1047                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1048         }
1049
1050         dc->hwss.set_disp_pattern_generator(dc,
1051                         pipe_ctx,
1052                         test_pattern,
1053                         test_pattern_color_space,
1054                         stream->timing.display_color_depth,
1055                         &black_color,
1056                         width,
1057                         height,
1058                         0);
1059
1060         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1061                 dc->hwss.set_disp_pattern_generator(dc,
1062                                 odm_pipe,
1063                                 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
1064                                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
1065                                 test_pattern_color_space,
1066                                 stream->timing.display_color_depth,
1067                                 &black_color,
1068                                 width,
1069                                 height,
1070                                 0);
1071         }
1072
1073         if (!blank)
1074                 if (stream_res->abm) {
1075                         dc->hwss.set_pipe(pipe_ctx);
1076                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1077                 }
1078 }
1079
1080
1081 static void dcn20_power_on_plane(
1082         struct dce_hwseq *hws,
1083         struct pipe_ctx *pipe_ctx)
1084 {
1085         DC_LOGGER_INIT(hws->ctx->logger);
1086         if (REG(DC_IP_REQUEST_CNTL)) {
1087                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1088                                 IP_REQUEST_EN, 1);
1089
1090                 if (hws->funcs.dpp_pg_control)
1091                         hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1092
1093                 if (hws->funcs.hubp_pg_control)
1094                         hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1095
1096                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1097                                 IP_REQUEST_EN, 0);
1098                 DC_LOG_DEBUG(
1099                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1100         }
1101 }
1102
1103 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1104                                struct dc_state *context)
1105 {
1106         //if (dc->debug.sanity_checks) {
1107         //      dcn10_verify_allow_pstate_change_high(dc);
1108         //}
1109         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1110
1111         /* enable DCFCLK current DCHUB */
1112         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1113
1114         /* initialize HUBP on power up */
1115         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1116
1117         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1118         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1119                         pipe_ctx->stream_res.opp,
1120                         true);
1121
1122 /* TODO: enable/disable in dm as per update type.
1123         if (plane_state) {
1124                 DC_LOG_DC(dc->ctx->logger,
1125                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1126                                 "addr low:0x%x, "
1127                                 "src: %d, %d, %d,"
1128                                 " %d; dst: %d, %d, %d, %d;\n",
1129                                 pipe_ctx->pipe_idx,
1130                                 plane_state,
1131                                 plane_state->address.grph.addr.high_part,
1132                                 plane_state->address.grph.addr.low_part,
1133                                 plane_state->src_rect.x,
1134                                 plane_state->src_rect.y,
1135                                 plane_state->src_rect.width,
1136                                 plane_state->src_rect.height,
1137                                 plane_state->dst_rect.x,
1138                                 plane_state->dst_rect.y,
1139                                 plane_state->dst_rect.width,
1140                                 plane_state->dst_rect.height);
1141
1142                 DC_LOG_DC(dc->ctx->logger,
1143                                 "Pipe %d: width, height, x, y         format:%d\n"
1144                                 "viewport:%d, %d, %d, %d\n"
1145                                 "recout:  %d, %d, %d, %d\n",
1146                                 pipe_ctx->pipe_idx,
1147                                 plane_state->format,
1148                                 pipe_ctx->plane_res.scl_data.viewport.width,
1149                                 pipe_ctx->plane_res.scl_data.viewport.height,
1150                                 pipe_ctx->plane_res.scl_data.viewport.x,
1151                                 pipe_ctx->plane_res.scl_data.viewport.y,
1152                                 pipe_ctx->plane_res.scl_data.recout.width,
1153                                 pipe_ctx->plane_res.scl_data.recout.height,
1154                                 pipe_ctx->plane_res.scl_data.recout.x,
1155                                 pipe_ctx->plane_res.scl_data.recout.y);
1156                 print_rq_dlg_ttu(dc, pipe_ctx);
1157         }
1158 */
1159         if (dc->vm_pa_config.valid) {
1160                 struct vm_system_aperture_param apt;
1161
1162                 apt.sys_default.quad_part = 0;
1163
1164                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1165                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1166
1167                 // Program system aperture settings
1168                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1169         }
1170
1171         if (!pipe_ctx->top_pipe
1172                 && pipe_ctx->plane_state
1173                 && pipe_ctx->plane_state->flip_int_enabled
1174                 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1175                         pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1176
1177 //      if (dc->debug.sanity_checks) {
1178 //              dcn10_verify_allow_pstate_change_high(dc);
1179 //      }
1180 }
1181
1182 void dcn20_pipe_control_lock(
1183         struct dc *dc,
1184         struct pipe_ctx *pipe,
1185         bool lock)
1186 {
1187         struct pipe_ctx *temp_pipe;
1188         bool flip_immediate = false;
1189
1190         /* use TG master update lock to lock everything on the TG
1191          * therefore only top pipe need to lock
1192          */
1193         if (!pipe || pipe->top_pipe)
1194                 return;
1195
1196         if (pipe->plane_state != NULL)
1197                 flip_immediate = pipe->plane_state->flip_immediate;
1198
1199         if  (pipe->stream_res.gsl_group > 0) {
1200             temp_pipe = pipe->bottom_pipe;
1201             while (!flip_immediate && temp_pipe) {
1202                     if (temp_pipe->plane_state != NULL)
1203                             flip_immediate = temp_pipe->plane_state->flip_immediate;
1204                     temp_pipe = temp_pipe->bottom_pipe;
1205             }
1206         }
1207
1208         if (flip_immediate && lock) {
1209                 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1210                 int i;
1211
1212                 temp_pipe = pipe;
1213                 while (temp_pipe) {
1214                         if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1215                                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1216                                         if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1217                                                 break;
1218                                         udelay(1);
1219                                 }
1220
1221                                 /* no reason it should take this long for immediate flips */
1222                                 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
1223                         }
1224                         temp_pipe = temp_pipe->bottom_pipe;
1225                 }
1226         }
1227
1228         /* In flip immediate and pipe splitting case, we need to use GSL
1229          * for synchronization. Only do setup on locking and on flip type change.
1230          */
1231         if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
1232                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1233                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1234                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1235
1236         if (pipe->plane_state != NULL)
1237                 flip_immediate = pipe->plane_state->flip_immediate;
1238
1239         temp_pipe = pipe->bottom_pipe;
1240         while (flip_immediate && temp_pipe) {
1241             if (temp_pipe->plane_state != NULL)
1242                 flip_immediate = temp_pipe->plane_state->flip_immediate;
1243             temp_pipe = temp_pipe->bottom_pipe;
1244         }
1245
1246         if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1247                 !flip_immediate)
1248             dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1249
1250         if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1251                 union dmub_hw_lock_flags hw_locks = { 0 };
1252                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1253
1254                 hw_locks.bits.lock_pipe = 1;
1255                 inst_flags.otg_inst =  pipe->stream_res.tg->inst;
1256
1257                 if (pipe->plane_state != NULL)
1258                         hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1259
1260                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1261                                         lock,
1262                                         &hw_locks,
1263                                         &inst_flags);
1264         } else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
1265                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
1266                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
1267                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
1268                 hw_lock_cmd.bits.lock_pipe = 1;
1269                 hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst;
1270                 hw_lock_cmd.bits.lock = lock;
1271                 if (!lock)
1272                         hw_lock_cmd.bits.should_release = 1;
1273                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
1274         } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1275                 if (lock)
1276                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1277                 else
1278                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1279         } else {
1280                 if (lock)
1281                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1282                 else
1283                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1284         }
1285 }
1286
1287 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1288 {
1289         new_pipe->update_flags.raw = 0;
1290
1291         /* Exit on unchanged, unused pipe */
1292         if (!old_pipe->plane_state && !new_pipe->plane_state)
1293                 return;
1294         /* Detect pipe enable/disable */
1295         if (!old_pipe->plane_state && new_pipe->plane_state) {
1296                 new_pipe->update_flags.bits.enable = 1;
1297                 new_pipe->update_flags.bits.mpcc = 1;
1298                 new_pipe->update_flags.bits.dppclk = 1;
1299                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1300                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1301                 new_pipe->update_flags.bits.gamut_remap = 1;
1302                 new_pipe->update_flags.bits.scaler = 1;
1303                 new_pipe->update_flags.bits.viewport = 1;
1304                 new_pipe->update_flags.bits.det_size = 1;
1305                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1306                         new_pipe->update_flags.bits.odm = 1;
1307                         new_pipe->update_flags.bits.global_sync = 1;
1308                 }
1309                 return;
1310         }
1311
1312         /* For SubVP we need to unconditionally enable because any phantom pipes are
1313          * always removed then newly added for every full updates whenever SubVP is in use.
1314          * The remove-add sequence of the phantom pipe always results in the pipe
1315          * being blanked in enable_stream_timing (DPG).
1316          */
1317         if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1318                 new_pipe->update_flags.bits.enable = 1;
1319
1320         if (old_pipe->plane_state && !new_pipe->plane_state) {
1321                 new_pipe->update_flags.bits.disable = 1;
1322                 return;
1323         }
1324
1325         /* Detect plane change */
1326         if (old_pipe->plane_state != new_pipe->plane_state) {
1327                 new_pipe->update_flags.bits.plane_changed = true;
1328         }
1329
1330         /* Detect top pipe only changes */
1331         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1332                 /* Detect odm changes */
1333                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1334                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1335                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1336                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1337                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1338                         new_pipe->update_flags.bits.odm = 1;
1339
1340                 /* Detect global sync changes */
1341                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1342                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1343                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1344                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1345                         new_pipe->update_flags.bits.global_sync = 1;
1346         }
1347
1348         if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1349                 new_pipe->update_flags.bits.det_size = 1;
1350
1351         /*
1352          * Detect opp / tg change, only set on change, not on enable
1353          * Assume mpcc inst = pipe index, if not this code needs to be updated
1354          * since mpcc is what is affected by these. In fact all of our sequence
1355          * makes this assumption at the moment with how hubp reset is matched to
1356          * same index mpcc reset.
1357          */
1358         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1359                 new_pipe->update_flags.bits.opp_changed = 1;
1360         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1361                 new_pipe->update_flags.bits.tg_changed = 1;
1362
1363         /*
1364          * Detect mpcc blending changes, only dpp inst and opp matter here,
1365          * mpccs getting removed/inserted update connected ones during their own
1366          * programming
1367          */
1368         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1369                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1370                 new_pipe->update_flags.bits.mpcc = 1;
1371
1372         /* Detect dppclk change */
1373         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1374                 new_pipe->update_flags.bits.dppclk = 1;
1375
1376         /* Check for scl update */
1377         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1378                         new_pipe->update_flags.bits.scaler = 1;
1379         /* Check for vp update */
1380         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1381                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1382                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1383                 new_pipe->update_flags.bits.viewport = 1;
1384
1385         /* Detect dlg/ttu/rq updates */
1386         {
1387                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1388                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1389                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1390                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1391
1392                 /* Detect pipe interdependent updates */
1393                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1394                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1395                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1396                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1397                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1398                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1399                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1400                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1401                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1402                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1403                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1404                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1405                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1406                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1407                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1408                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1409                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1410                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1411                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1412                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1413                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1414                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1415                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1416                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1417                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1418                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1419                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1420                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1421                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1422                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1423                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1424                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1425                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1426                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1427                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1428                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1429                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1430                 }
1431                 /* Detect any other updates to ttu/rq/dlg */
1432                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1433                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1434                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1435                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1436         }
1437 }
1438
1439 static void dcn20_update_dchubp_dpp(
1440         struct dc *dc,
1441         struct pipe_ctx *pipe_ctx,
1442         struct dc_state *context)
1443 {
1444         struct dce_hwseq *hws = dc->hwseq;
1445         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1446         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1447         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1448         struct dccg *dccg = dc->res_pool->dccg;
1449         bool viewport_changed = false;
1450
1451         if (pipe_ctx->update_flags.bits.dppclk)
1452                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1453
1454         if (pipe_ctx->update_flags.bits.enable)
1455                 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
1456
1457         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1458          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1459          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1460          */
1461         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1462                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1463
1464                 hubp->funcs->hubp_setup(
1465                         hubp,
1466                         &pipe_ctx->dlg_regs,
1467                         &pipe_ctx->ttu_regs,
1468                         &pipe_ctx->rq_regs,
1469                         &pipe_ctx->pipe_dlg_param);
1470
1471                 if (hubp->funcs->set_unbounded_requesting)
1472                         hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
1473         }
1474         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1475                 hubp->funcs->hubp_setup_interdependent(
1476                         hubp,
1477                         &pipe_ctx->dlg_regs,
1478                         &pipe_ctx->ttu_regs);
1479
1480         if (pipe_ctx->update_flags.bits.enable ||
1481                         pipe_ctx->update_flags.bits.plane_changed ||
1482                         plane_state->update_flags.bits.bpp_change ||
1483                         plane_state->update_flags.bits.input_csc_change ||
1484                         plane_state->update_flags.bits.color_space_change ||
1485                         plane_state->update_flags.bits.coeff_reduction_change) {
1486                 struct dc_bias_and_scale bns_params = {0};
1487
1488                 // program the input csc
1489                 dpp->funcs->dpp_setup(dpp,
1490                                 plane_state->format,
1491                                 EXPANSION_MODE_ZERO,
1492                                 plane_state->input_csc_color_matrix,
1493                                 plane_state->color_space,
1494                                 NULL);
1495
1496                 if (dpp->funcs->dpp_program_bias_and_scale) {
1497                         //TODO :for CNVC set scale and bias registers if necessary
1498                         build_prescale_params(&bns_params, plane_state);
1499                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1500                 }
1501         }
1502
1503         if (pipe_ctx->update_flags.bits.mpcc
1504                         || pipe_ctx->update_flags.bits.plane_changed
1505                         || plane_state->update_flags.bits.global_alpha_change
1506                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1507                 // MPCC inst is equal to pipe index in practice
1508                 int mpcc_inst = hubp->inst;
1509                 int opp_inst;
1510                 int opp_count = dc->res_pool->pipe_count;
1511
1512                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1513                         if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1514                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1515                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1516                                 break;
1517                         }
1518                 }
1519                 hws->funcs.update_mpcc(dc, pipe_ctx);
1520         }
1521
1522         if (pipe_ctx->update_flags.bits.scaler ||
1523                         plane_state->update_flags.bits.scaling_change ||
1524                         plane_state->update_flags.bits.position_change ||
1525                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1526                         pipe_ctx->stream->update_flags.bits.scaling) {
1527                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1528                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
1529                 /* scaler configuration */
1530                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1531                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1532         }
1533
1534         if (pipe_ctx->update_flags.bits.viewport ||
1535                         (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1536                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1537                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1538
1539                 hubp->funcs->mem_program_viewport(
1540                         hubp,
1541                         &pipe_ctx->plane_res.scl_data.viewport,
1542                         &pipe_ctx->plane_res.scl_data.viewport_c);
1543                 viewport_changed = true;
1544         }
1545
1546         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1547         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1548                         pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1549                         pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1550                 dc->hwss.set_cursor_position(pipe_ctx);
1551                 dc->hwss.set_cursor_attribute(pipe_ctx);
1552
1553                 if (dc->hwss.set_cursor_sdr_white_level)
1554                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1555         }
1556
1557         /* Any updates are handled in dc interface, just need
1558          * to apply existing for plane enable / opp change */
1559         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1560                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1561                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1562                 /* dpp/cm gamut remap*/
1563                 dc->hwss.program_gamut_remap(pipe_ctx);
1564
1565                 /*call the dcn2 method which uses mpc csc*/
1566                 dc->hwss.program_output_csc(dc,
1567                                 pipe_ctx,
1568                                 pipe_ctx->stream->output_color_space,
1569                                 pipe_ctx->stream->csc_color_matrix.matrix,
1570                                 hubp->opp_id);
1571         }
1572
1573         if (pipe_ctx->update_flags.bits.enable ||
1574                         pipe_ctx->update_flags.bits.plane_changed ||
1575                         pipe_ctx->update_flags.bits.opp_changed ||
1576                         plane_state->update_flags.bits.pixel_format_change ||
1577                         plane_state->update_flags.bits.horizontal_mirror_change ||
1578                         plane_state->update_flags.bits.rotation_change ||
1579                         plane_state->update_flags.bits.swizzle_change ||
1580                         plane_state->update_flags.bits.dcc_change ||
1581                         plane_state->update_flags.bits.bpp_change ||
1582                         plane_state->update_flags.bits.scaling_change ||
1583                         plane_state->update_flags.bits.plane_size_change) {
1584                 struct plane_size size = plane_state->plane_size;
1585
1586                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1587                 hubp->funcs->hubp_program_surface_config(
1588                         hubp,
1589                         plane_state->format,
1590                         &plane_state->tiling_info,
1591                         &size,
1592                         plane_state->rotation,
1593                         &plane_state->dcc,
1594                         plane_state->horizontal_mirror,
1595                         0);
1596                 hubp->power_gated = false;
1597         }
1598
1599         if (pipe_ctx->update_flags.bits.enable ||
1600                 pipe_ctx->update_flags.bits.plane_changed ||
1601                 plane_state->update_flags.bits.addr_update)
1602                 hws->funcs.update_plane_addr(dc, pipe_ctx);
1603
1604         if (pipe_ctx->update_flags.bits.enable)
1605                 hubp->funcs->set_blank(hubp, false);
1606         /* If the stream paired with this plane is phantom, the plane is also phantom */
1607         if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
1608                         && hubp->funcs->phantom_hubp_post_enable)
1609                 hubp->funcs->phantom_hubp_post_enable(hubp);
1610 }
1611
1612
1613 static void dcn20_program_pipe(
1614                 struct dc *dc,
1615                 struct pipe_ctx *pipe_ctx,
1616                 struct dc_state *context)
1617 {
1618         struct dce_hwseq *hws = dc->hwseq;
1619         /* Only need to unblank on top pipe */
1620
1621         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1622                         && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1623                 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1624
1625         /* Only update TG on top pipe */
1626         if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1627                         && !pipe_ctx->prev_odm_pipe) {
1628                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1629                                 pipe_ctx->stream_res.tg,
1630                                 pipe_ctx->pipe_dlg_param.vready_offset,
1631                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1632                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1633                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1634
1635                 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1636                         pipe_ctx->stream_res.tg->funcs->wait_for_state(
1637                                 pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
1638                         pipe_ctx->stream_res.tg->funcs->wait_for_state(
1639                                 pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1640                 }
1641
1642                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1643                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1644
1645                 if (hws->funcs.setup_vupdate_interrupt)
1646                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1647         }
1648
1649         if (pipe_ctx->update_flags.bits.odm)
1650                 hws->funcs.update_odm(dc, context, pipe_ctx);
1651
1652         if (pipe_ctx->update_flags.bits.enable) {
1653                 dcn20_enable_plane(dc, pipe_ctx, context);
1654                 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1655                         dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1656         }
1657
1658         if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1659                 dc->res_pool->hubbub->funcs->program_det_size(
1660                         dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
1661
1662         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1663                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1664
1665         if (pipe_ctx->update_flags.bits.enable
1666                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1667                 hws->funcs.set_hdr_multiplier(pipe_ctx);
1668
1669         if (pipe_ctx->update_flags.bits.enable ||
1670                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1671                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1672                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1673
1674         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1675          * only do gamma programming for powering on, internal memcmp to avoid
1676          * updating on slave planes
1677          */
1678         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1679                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1680
1681         /* If the pipe has been enabled or has a different opp, we
1682          * should reprogram the fmt. This deals with cases where
1683          * interation between mpc and odm combine on different streams
1684          * causes a different pipe to be chosen to odm combine with.
1685          */
1686         if (pipe_ctx->update_flags.bits.enable
1687             || pipe_ctx->update_flags.bits.opp_changed) {
1688
1689                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1690                         pipe_ctx->stream_res.opp,
1691                         COLOR_SPACE_YCBCR601,
1692                         pipe_ctx->stream->timing.display_color_depth,
1693                         pipe_ctx->stream->signal);
1694
1695                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1696                         pipe_ctx->stream_res.opp,
1697                         &pipe_ctx->stream->bit_depth_params,
1698                         &pipe_ctx->stream->clamping);
1699         }
1700 }
1701
1702 void dcn20_program_front_end_for_ctx(
1703                 struct dc *dc,
1704                 struct dc_state *context)
1705 {
1706         int i;
1707         struct dce_hwseq *hws = dc->hwseq;
1708         DC_LOGGER_INIT(dc->ctx->logger);
1709
1710         /* Carry over GSL groups in case the context is changing. */
1711        for (i = 0; i < dc->res_pool->pipe_count; i++) {
1712                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1713                struct pipe_ctx *old_pipe_ctx =
1714                        &dc->current_state->res_ctx.pipe_ctx[i];
1715
1716                if (pipe_ctx->stream == old_pipe_ctx->stream)
1717                        pipe_ctx->stream_res.gsl_group =
1718                                old_pipe_ctx->stream_res.gsl_group;
1719        }
1720
1721         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1722                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1723                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1724
1725                         if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1726                                 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1727                                 /*turn off triple buffer for full update*/
1728                                 dc->hwss.program_triplebuffer(
1729                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1730                         }
1731                 }
1732         }
1733
1734         /* Set pipe update flags and lock pipes */
1735         for (i = 0; i < dc->res_pool->pipe_count; i++)
1736                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1737                                 &context->res_ctx.pipe_ctx[i]);
1738
1739         /* OTG blank before disabling all front ends */
1740         for (i = 0; i < dc->res_pool->pipe_count; i++)
1741                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1742                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1743                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1744                                 && context->res_ctx.pipe_ctx[i].stream)
1745                         hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1746
1747
1748         /* Disconnect mpcc */
1749         for (i = 0; i < dc->res_pool->pipe_count; i++)
1750                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1751                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1752                         struct hubbub *hubbub = dc->res_pool->hubbub;
1753
1754                         if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1755                                 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
1756                         hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1757                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1758                 }
1759
1760         /*
1761          * Program all updated pipes, order matters for mpcc setup. Start with
1762          * top pipe and program all pipes that follow in order
1763          */
1764         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1765                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1766
1767                 if (pipe->plane_state && !pipe->top_pipe) {
1768                         while (pipe) {
1769                                 if (hws->funcs.program_pipe)
1770                                         hws->funcs.program_pipe(dc, pipe, context);
1771                                 else
1772                                         dcn20_program_pipe(dc, pipe, context);
1773
1774                                 pipe = pipe->bottom_pipe;
1775                         }
1776                 }
1777                 /* Program secondary blending tree and writeback pipes */
1778                 pipe = &context->res_ctx.pipe_ctx[i];
1779                 if (!pipe->top_pipe && !pipe->prev_odm_pipe
1780                                 && pipe->stream && pipe->stream->num_wb_info > 0
1781                                 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1782                                         || pipe->stream->update_flags.raw)
1783                                 && hws->funcs.program_all_writeback_pipes_in_tree)
1784                         hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1785
1786                 /* Avoid underflow by check of pipe line read when adding 2nd plane. */
1787                 if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1788                         !pipe->top_pipe &&
1789                         pipe->stream &&
1790                         pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1791                         dc->current_state->stream_status[0].plane_count == 1 &&
1792                         context->stream_status[0].plane_count > 1) {
1793                         pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1794                 }
1795         }
1796         if (hws->funcs.program_mall_pipe_config)
1797                 hws->funcs.program_mall_pipe_config(dc, context);
1798 }
1799
1800 void dcn20_post_unlock_program_front_end(
1801                 struct dc *dc,
1802                 struct dc_state *context)
1803 {
1804         int i;
1805         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1806         struct dce_hwseq *hwseq = dc->hwseq;
1807
1808         DC_LOGGER_INIT(dc->ctx->logger);
1809
1810         for (i = 0; i < dc->res_pool->pipe_count; i++)
1811                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1812                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1813
1814         /*
1815          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1816          * part of the enable operation otherwise, DM may request an immediate flip which
1817          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1818          * is unsupported on DCN.
1819          */
1820         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1821                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1822                 // Don't check flip pending on phantom pipes
1823                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&
1824                                 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1825                         struct hubp *hubp = pipe->plane_res.hubp;
1826                         int j = 0;
1827
1828                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1829                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1830                                 mdelay(1);
1831                 }
1832         }
1833
1834         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1835                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1836                 struct pipe_ctx *mpcc_pipe;
1837
1838                 if (pipe->vtp_locked) {
1839                         dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp);
1840                         pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true);
1841                         pipe->vtp_locked = false;
1842
1843                         for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
1844                                 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
1845
1846                         for (i = 0; i < dc->res_pool->pipe_count; i++)
1847                                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1848                                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1849                 }
1850         }
1851         /* WA to apply WM setting*/
1852         if (hwseq->wa.DEGVIDCN21)
1853                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1854
1855
1856         /* WA for stutter underflow during MPO transitions when adding 2nd plane */
1857         if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1858
1859                 if (dc->current_state->stream_status[0].plane_count == 1 &&
1860                                 context->stream_status[0].plane_count > 1) {
1861
1862                         struct timing_generator *tg = dc->res_pool->timing_generators[0];
1863
1864                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1865
1866                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1867                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1868                 }
1869         }
1870 }
1871
1872 void dcn20_prepare_bandwidth(
1873                 struct dc *dc,
1874                 struct dc_state *context)
1875 {
1876         struct hubbub *hubbub = dc->res_pool->hubbub;
1877         unsigned int compbuf_size_kb = 0;
1878         unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;
1879         unsigned int i;
1880
1881         dc->clk_mgr->funcs->update_clocks(
1882                         dc->clk_mgr,
1883                         context,
1884                         false);
1885
1886         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1887                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1888
1889                 // At optimize don't restore the original watermark value
1890                 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
1891                         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
1892                         break;
1893                 }
1894         }
1895
1896         /* program dchubbub watermarks */
1897         dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
1898                                         &context->bw_ctx.bw.dcn.watermarks,
1899                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1900                                         false);
1901
1902         // Restore the real watermark so we can commit the value to DMCUB
1903         // DMCUB uses the "original" watermark value in SubVP MCLK switch
1904         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;
1905
1906         /* decrease compbuf size */
1907         if (hubbub->funcs->program_compbuf_size) {
1908                 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
1909                         compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
1910                 else
1911                         compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
1912
1913                 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
1914         }
1915 }
1916
1917 void dcn20_optimize_bandwidth(
1918                 struct dc *dc,
1919                 struct dc_state *context)
1920 {
1921         struct hubbub *hubbub = dc->res_pool->hubbub;
1922         int i;
1923
1924         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1925                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1926
1927                 // At optimize don't need  to restore the original watermark value
1928                 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
1929                         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
1930                         break;
1931                 }
1932         }
1933
1934         /* program dchubbub watermarks */
1935         hubbub->funcs->program_watermarks(hubbub,
1936                                         &context->bw_ctx.bw.dcn.watermarks,
1937                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1938                                         true);
1939
1940         if (dc->clk_mgr->dc_mode_softmax_enabled)
1941                 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1942                                 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1943                         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
1944
1945         dc->clk_mgr->funcs->update_clocks(
1946                         dc->clk_mgr,
1947                         context,
1948                         true);
1949         if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
1950                 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
1951                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1952
1953                         if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank
1954                                 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max
1955                                 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
1956                                         pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,
1957                                                 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start);
1958                 }
1959         }
1960         /* increase compbuf size */
1961         if (hubbub->funcs->program_compbuf_size)
1962                 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
1963 }
1964
1965 bool dcn20_update_bandwidth(
1966                 struct dc *dc,
1967                 struct dc_state *context)
1968 {
1969         int i;
1970         struct dce_hwseq *hws = dc->hwseq;
1971
1972         /* recalculate DML parameters */
1973         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1974                 return false;
1975
1976         /* apply updated bandwidth parameters */
1977         dc->hwss.prepare_bandwidth(dc, context);
1978
1979         /* update hubp configs for all pipes */
1980         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1981                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1982
1983                 if (pipe_ctx->plane_state == NULL)
1984                         continue;
1985
1986                 if (pipe_ctx->top_pipe == NULL) {
1987                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1988
1989                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1990                                         pipe_ctx->stream_res.tg,
1991                                         pipe_ctx->pipe_dlg_param.vready_offset,
1992                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1993                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1994                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1995
1996                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1997                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
1998
1999                         if (pipe_ctx->prev_odm_pipe == NULL)
2000                                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
2001
2002                         if (hws->funcs.setup_vupdate_interrupt)
2003                                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
2004                 }
2005
2006                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
2007                                 pipe_ctx->plane_res.hubp,
2008                                         &pipe_ctx->dlg_regs,
2009                                         &pipe_ctx->ttu_regs,
2010                                         &pipe_ctx->rq_regs,
2011                                         &pipe_ctx->pipe_dlg_param);
2012         }
2013
2014         return true;
2015 }
2016
2017 void dcn20_enable_writeback(
2018                 struct dc *dc,
2019                 struct dc_writeback_info *wb_info,
2020                 struct dc_state *context)
2021 {
2022         struct dwbc *dwb;
2023         struct mcif_wb *mcif_wb;
2024         struct timing_generator *optc;
2025
2026         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
2027         ASSERT(wb_info->wb_enabled);
2028         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
2029         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
2030
2031         /* set the OPTC source mux */
2032         optc = dc->res_pool->timing_generators[dwb->otg_inst];
2033         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
2034         /* set MCIF_WB buffer and arbitration configuration */
2035         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
2036         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
2037         /* Enable MCIF_WB */
2038         mcif_wb->funcs->enable_mcif(mcif_wb);
2039         /* Enable DWB */
2040         dwb->funcs->enable(dwb, &wb_info->dwb_params);
2041         /* TODO: add sequence to enable/disable warmup */
2042 }
2043
2044 void dcn20_disable_writeback(
2045                 struct dc *dc,
2046                 unsigned int dwb_pipe_inst)
2047 {
2048         struct dwbc *dwb;
2049         struct mcif_wb *mcif_wb;
2050
2051         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
2052         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
2053         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
2054
2055         dwb->funcs->disable(dwb);
2056         mcif_wb->funcs->disable_mcif(mcif_wb);
2057 }
2058
2059 bool dcn20_wait_for_blank_complete(
2060                 struct output_pixel_processor *opp)
2061 {
2062         int counter;
2063
2064         for (counter = 0; counter < 1000; counter++) {
2065                 if (opp->funcs->dpg_is_blanked(opp))
2066                         break;
2067
2068                 udelay(100);
2069         }
2070
2071         if (counter == 1000) {
2072                 dm_error("DC: failed to blank crtc!\n");
2073                 return false;
2074         }
2075
2076         return true;
2077 }
2078
2079 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
2080 {
2081         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2082
2083         if (!hubp)
2084                 return false;
2085         return hubp->funcs->dmdata_status_done(hubp);
2086 }
2087
2088 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2089 {
2090         struct dce_hwseq *hws = dc->hwseq;
2091
2092         if (pipe_ctx->stream_res.dsc) {
2093                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2094
2095                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
2096                 while (odm_pipe) {
2097                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
2098                         odm_pipe = odm_pipe->next_odm_pipe;
2099                 }
2100         }
2101 }
2102
2103 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2104 {
2105         struct dce_hwseq *hws = dc->hwseq;
2106
2107         if (pipe_ctx->stream_res.dsc) {
2108                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2109
2110                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
2111                 while (odm_pipe) {
2112                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
2113                         odm_pipe = odm_pipe->next_odm_pipe;
2114                 }
2115         }
2116 }
2117
2118 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2119 {
2120         struct dc_dmdata_attributes attr = { 0 };
2121         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2122
2123         attr.dmdata_mode = DMDATA_HW_MODE;
2124         attr.dmdata_size =
2125                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2126         attr.address.quad_part =
2127                         pipe_ctx->stream->dmdata_address.quad_part;
2128         attr.dmdata_dl_delta = 0;
2129         attr.dmdata_qos_mode = 0;
2130         attr.dmdata_qos_level = 0;
2131         attr.dmdata_repeat = 1; /* always repeat */
2132         attr.dmdata_updated = 1;
2133         attr.dmdata_sw_data = NULL;
2134
2135         hubp->funcs->dmdata_set_attributes(hubp, &attr);
2136 }
2137
2138 void dcn20_init_vm_ctx(
2139                 struct dce_hwseq *hws,
2140                 struct dc *dc,
2141                 struct dc_virtual_addr_space_config *va_config,
2142                 int vmid)
2143 {
2144         struct dcn_hubbub_virt_addr_config config;
2145
2146         if (vmid == 0) {
2147                 ASSERT(0); /* VMID cannot be 0 for vm context */
2148                 return;
2149         }
2150
2151         config.page_table_start_addr = va_config->page_table_start_addr;
2152         config.page_table_end_addr = va_config->page_table_end_addr;
2153         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2154         config.page_table_depth = va_config->page_table_depth;
2155         config.page_table_base_addr = va_config->page_table_base_addr;
2156
2157         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2158 }
2159
2160 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
2161 {
2162         struct dcn_hubbub_phys_addr_config config;
2163
2164         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2165         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2166         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2167         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2168         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2169         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2170         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2171         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2172         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
2173         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
2174
2175         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
2176 }
2177
2178 static bool patch_address_for_sbs_tb_stereo(
2179                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2180 {
2181         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2182         bool sec_split = pipe_ctx->top_pipe &&
2183                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2184         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2185                         (pipe_ctx->stream->timing.timing_3d_format ==
2186                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2187                         pipe_ctx->stream->timing.timing_3d_format ==
2188                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2189                 *addr = plane_state->address.grph_stereo.left_addr;
2190                 plane_state->address.grph_stereo.left_addr =
2191                                 plane_state->address.grph_stereo.right_addr;
2192                 return true;
2193         }
2194
2195         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2196                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2197                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2198                 plane_state->address.grph_stereo.right_addr =
2199                                 plane_state->address.grph_stereo.left_addr;
2200                 plane_state->address.grph_stereo.right_meta_addr =
2201                                 plane_state->address.grph_stereo.left_meta_addr;
2202         }
2203         return false;
2204 }
2205
2206 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2207 {
2208         bool addr_patched = false;
2209         PHYSICAL_ADDRESS_LOC addr;
2210         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2211
2212         if (plane_state == NULL)
2213                 return;
2214
2215         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2216
2217         // Call Helper to track VMID use
2218         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2219
2220         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2221                         pipe_ctx->plane_res.hubp,
2222                         &plane_state->address,
2223                         plane_state->flip_immediate);
2224
2225         plane_state->status.requested_address = plane_state->address;
2226
2227         if (plane_state->flip_immediate)
2228                 plane_state->status.current_address = plane_state->address;
2229
2230         if (addr_patched)
2231                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2232 }
2233
2234 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2235                 struct dc_link_settings *link_settings)
2236 {
2237         struct encoder_unblank_param params = {0};
2238         struct dc_stream_state *stream = pipe_ctx->stream;
2239         struct dc_link *link = stream->link;
2240         struct dce_hwseq *hws = link->dc->hwseq;
2241         struct pipe_ctx *odm_pipe;
2242
2243         params.opp_cnt = 1;
2244         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2245                 params.opp_cnt++;
2246         }
2247         /* only 3 items below are used by unblank */
2248         params.timing = pipe_ctx->stream->timing;
2249
2250         params.link_settings.link_rate = link_settings->link_rate;
2251
2252         if (is_dp_128b_132b_signal(pipe_ctx)) {
2253                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2254                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2255                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
2256                                 pipe_ctx->stream_res.tg->inst);
2257         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2258                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2259                         params.timing.pix_clk_100hz /= 2;
2260                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2261                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2262                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
2263         }
2264
2265         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2266                 hws->funcs.edp_backlight_control(link, true);
2267         }
2268 }
2269
2270 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2271 {
2272         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2273         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2274
2275         if (start_line < 0)
2276                 start_line = 0;
2277
2278         if (tg->funcs->setup_vertical_interrupt2)
2279                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2280 }
2281
2282 static void dcn20_reset_back_end_for_pipe(
2283                 struct dc *dc,
2284                 struct pipe_ctx *pipe_ctx,
2285                 struct dc_state *context)
2286 {
2287         int i;
2288         struct dc_link *link;
2289         DC_LOGGER_INIT(dc->ctx->logger);
2290         if (pipe_ctx->stream_res.stream_enc == NULL) {
2291                 pipe_ctx->stream = NULL;
2292                 return;
2293         }
2294
2295         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2296                 link = pipe_ctx->stream->link;
2297                 /* DPMS may already disable or */
2298                 /* dpms_off status is incorrect due to fastboot
2299                  * feature. When system resume from S4 with second
2300                  * screen only, the dpms_off would be true but
2301                  * VBIOS lit up eDP, so check link status too.
2302                  */
2303                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2304                         core_link_disable_stream(pipe_ctx);
2305                 else if (pipe_ctx->stream_res.audio)
2306                         dc->hwss.disable_audio_stream(pipe_ctx);
2307
2308                 /* free acquired resources */
2309                 if (pipe_ctx->stream_res.audio) {
2310                         /*disable az_endpoint*/
2311                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2312
2313                         /*free audio*/
2314                         if (dc->caps.dynamic_audio == true) {
2315                                 /*we have to dynamic arbitrate the audio endpoints*/
2316                                 /*we free the resource, need reset is_audio_acquired*/
2317                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2318                                                 pipe_ctx->stream_res.audio, false);
2319                                 pipe_ctx->stream_res.audio = NULL;
2320                         }
2321                 }
2322         }
2323         else if (pipe_ctx->stream_res.dsc) {
2324                 dp_set_dsc_enable(pipe_ctx, false);
2325         }
2326
2327         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2328          * back end share by all pipes and will be disable only when disable
2329          * parent pipe.
2330          */
2331         if (pipe_ctx->top_pipe == NULL) {
2332
2333                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2334
2335                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2336
2337                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2338                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2339                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2340                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2341
2342                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2343                         pipe_ctx->stream_res.tg->funcs->set_drr(
2344                                         pipe_ctx->stream_res.tg, NULL);
2345         }
2346
2347         for (i = 0; i < dc->res_pool->pipe_count; i++)
2348                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2349                         break;
2350
2351         if (i == dc->res_pool->pipe_count)
2352                 return;
2353
2354         pipe_ctx->stream = NULL;
2355         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2356                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2357 }
2358
2359 void dcn20_reset_hw_ctx_wrap(
2360                 struct dc *dc,
2361                 struct dc_state *context)
2362 {
2363         int i;
2364         struct dce_hwseq *hws = dc->hwseq;
2365
2366         /* Reset Back End*/
2367         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2368                 struct pipe_ctx *pipe_ctx_old =
2369                         &dc->current_state->res_ctx.pipe_ctx[i];
2370                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2371
2372                 if (!pipe_ctx_old->stream)
2373                         continue;
2374
2375                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2376                         continue;
2377
2378                 if (!pipe_ctx->stream ||
2379                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2380                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2381
2382                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2383                         if (hws->funcs.enable_stream_gating)
2384                                 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
2385                         if (old_clk)
2386                                 old_clk->funcs->cs_power_down(old_clk);
2387                 }
2388         }
2389 }
2390
2391 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
2392 {
2393         struct mpc *mpc = dc->res_pool->mpc;
2394
2395         // input to MPCC is always RGB, by default leave black_color at 0
2396         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
2397                 get_hdr_visual_confirm_color(pipe_ctx, color);
2398         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
2399                 get_surface_visual_confirm_color(pipe_ctx, color);
2400         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
2401                 get_mpctree_visual_confirm_color(pipe_ctx, color);
2402         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
2403                 get_surface_tile_visual_confirm_color(pipe_ctx, color);
2404
2405         if (mpc->funcs->set_bg_color)
2406                 mpc->funcs->set_bg_color(mpc, color, mpcc_id);
2407 }
2408
2409 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2410 {
2411         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2412         struct mpcc_blnd_cfg blnd_cfg = {0};
2413         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2414         int mpcc_id;
2415         struct mpcc *new_mpcc;
2416         struct mpc *mpc = dc->res_pool->mpc;
2417         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2418
2419         blnd_cfg.overlap_only = false;
2420         blnd_cfg.global_gain = 0xff;
2421
2422         if (per_pixel_alpha) {
2423                 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;
2424                 if (pipe_ctx->plane_state->global_alpha) {
2425                         blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2426                         blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2427                 } else {
2428                         blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2429                 }
2430         } else {
2431                 blnd_cfg.pre_multiplied_alpha = false;
2432                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2433         }
2434
2435         if (pipe_ctx->plane_state->global_alpha)
2436                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2437         else
2438                 blnd_cfg.global_alpha = 0xff;
2439
2440         blnd_cfg.background_color_bpc = 4;
2441         blnd_cfg.bottom_gain_mode = 0;
2442         blnd_cfg.top_gain = 0x1f000;
2443         blnd_cfg.bottom_inside_gain = 0x1f000;
2444         blnd_cfg.bottom_outside_gain = 0x1f000;
2445
2446         if (pipe_ctx->plane_state->format
2447                         == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2448                 blnd_cfg.pre_multiplied_alpha = false;
2449
2450         /*
2451          * TODO: remove hack
2452          * Note: currently there is a bug in init_hw such that
2453          * on resume from hibernate, BIOS sets up MPCC0, and
2454          * we do mpcc_remove but the mpcc cannot go to idle
2455          * after remove. This cause us to pick mpcc1 here,
2456          * which causes a pstate hang for yet unknown reason.
2457          */
2458         mpcc_id = hubp->inst;
2459
2460         /* If there is no full update, don't need to touch MPC tree*/
2461         if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2462                 !pipe_ctx->update_flags.bits.mpcc) {
2463                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2464                 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2465                 return;
2466         }
2467
2468         /* check if this MPCC is already being used */
2469         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2470         /* remove MPCC if being used */
2471         if (new_mpcc != NULL)
2472                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2473         else
2474                 if (dc->debug.sanity_checks)
2475                         mpc->funcs->assert_mpcc_idle_before_connect(
2476                                         dc->res_pool->mpc, mpcc_id);
2477
2478         /* Call MPC to insert new plane */
2479         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2480                         mpc_tree_params,
2481                         &blnd_cfg,
2482                         NULL,
2483                         NULL,
2484                         hubp->inst,
2485                         mpcc_id);
2486         dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2487
2488         ASSERT(new_mpcc != NULL);
2489         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2490         hubp->mpcc_id = mpcc_id;
2491 }
2492
2493 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2494 {
2495         enum dc_lane_count lane_count =
2496                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2497
2498         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2499         struct dc_link *link = pipe_ctx->stream->link;
2500
2501         uint32_t active_total_with_borders;
2502         uint32_t early_control = 0;
2503         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2504         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2505         struct dc *dc = pipe_ctx->stream->ctx->dc;
2506
2507         if (is_dp_128b_132b_signal(pipe_ctx)) {
2508                 if (dc->hwseq->funcs.setup_hpo_hw_control)
2509                         dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
2510         }
2511
2512         link_hwss->setup_stream_encoder(pipe_ctx);
2513
2514         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2515                 if (dc->hwss.program_dmdata_engine)
2516                         dc->hwss.program_dmdata_engine(pipe_ctx);
2517         }
2518
2519         dc->hwss.update_info_frame(pipe_ctx);
2520
2521         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2522                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2523
2524         /* enable early control to avoid corruption on DP monitor*/
2525         active_total_with_borders =
2526                         timing->h_addressable
2527                                 + timing->h_border_left
2528                                 + timing->h_border_right;
2529
2530         if (lane_count != 0)
2531                 early_control = active_total_with_borders % lane_count;
2532
2533         if (early_control == 0)
2534                 early_control = lane_count;
2535
2536         tg->funcs->set_early_control(tg, early_control);
2537
2538         if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
2539                 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
2540                         timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1);
2541
2542         /* enable audio only within mode set */
2543         if (pipe_ctx->stream_res.audio != NULL) {
2544                 if (is_dp_128b_132b_signal(pipe_ctx))
2545                         pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc);
2546                 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
2547                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2548         }
2549 }
2550
2551 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2552 {
2553         struct dc_stream_state    *stream     = pipe_ctx->stream;
2554         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2555         bool                       enable     = false;
2556         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2557         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2558                                                         ? dmdata_dp
2559                                                         : dmdata_hdmi;
2560
2561         /* if using dynamic meta, don't set up generic infopackets */
2562         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2563                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2564                 enable = true;
2565         }
2566
2567         if (!hubp)
2568                 return;
2569
2570         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2571                 return;
2572
2573         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2574                                                 hubp->inst, mode);
2575 }
2576
2577 void dcn20_fpga_init_hw(struct dc *dc)
2578 {
2579         int i, j;
2580         struct dce_hwseq *hws = dc->hwseq;
2581         struct resource_pool *res_pool = dc->res_pool;
2582         struct dc_state  *context = dc->current_state;
2583
2584         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2585                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2586
2587         // Initialize the dccg
2588         if (res_pool->dccg->funcs->dccg_init)
2589                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2590
2591         //Enable ability to power gate / don't force power on permanently
2592         hws->funcs.enable_power_gating_plane(hws, true);
2593
2594         // Specific to FPGA dccg and registers
2595         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2596         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2597
2598         hws->funcs.dccg_init(hws);
2599
2600         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2601         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2602         if (REG(REFCLK_CNTL))
2603                 REG_WRITE(REFCLK_CNTL, 0);
2604         //
2605
2606
2607         /* Blank pixel data with OPP DPG */
2608         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2609                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2610
2611                 if (tg->funcs->is_tg_enabled(tg))
2612                         dcn20_init_blank(dc, tg);
2613         }
2614
2615         for (i = 0; i < res_pool->timing_generator_count; i++) {
2616                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2617
2618                 if (tg->funcs->is_tg_enabled(tg))
2619                         tg->funcs->lock(tg);
2620         }
2621
2622         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2623                 struct dpp *dpp = res_pool->dpps[i];
2624
2625                 dpp->funcs->dpp_reset(dpp);
2626         }
2627
2628         /* Reset all MPCC muxes */
2629         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2630
2631         /* initialize OPP mpc_tree parameter */
2632         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2633                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2634                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2635                 for (j = 0; j < MAX_PIPES; j++)
2636                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2637         }
2638
2639         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2640                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2641                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2642                 struct hubp *hubp = dc->res_pool->hubps[i];
2643                 struct dpp *dpp = dc->res_pool->dpps[i];
2644
2645                 pipe_ctx->stream_res.tg = tg;
2646                 pipe_ctx->pipe_idx = i;
2647
2648                 pipe_ctx->plane_res.hubp = hubp;
2649                 pipe_ctx->plane_res.dpp = dpp;
2650                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2651                 hubp->mpcc_id = dpp->inst;
2652                 hubp->opp_id = OPP_ID_INVALID;
2653                 hubp->power_gated = false;
2654                 pipe_ctx->stream_res.opp = NULL;
2655
2656                 hubp->funcs->hubp_init(hubp);
2657
2658                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2659                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2660                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2661                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2662                 /*to do*/
2663                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2664         }
2665
2666         /* initialize DWB pointer to MCIF_WB */
2667         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2668                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2669
2670         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2671                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2672
2673                 if (tg->funcs->is_tg_enabled(tg))
2674                         tg->funcs->unlock(tg);
2675         }
2676
2677         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2678                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2679
2680                 dc->hwss.disable_plane(dc, pipe_ctx);
2681
2682                 pipe_ctx->stream_res.tg = NULL;
2683                 pipe_ctx->plane_res.hubp = NULL;
2684         }
2685
2686         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2687                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2688
2689                 tg->funcs->tg_init(tg);
2690         }
2691
2692         if (dc->res_pool->hubbub->funcs->init_crb)
2693                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
2694 }
2695 #ifndef TRIM_FSFT
2696 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2697                 struct dc_crtc_timing *timing,
2698                 unsigned int max_input_rate_in_khz)
2699 {
2700         unsigned int old_v_front_porch;
2701         unsigned int old_v_total;
2702         unsigned int max_input_rate_in_100hz;
2703         unsigned long long new_v_total;
2704
2705         max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2706         if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2707                 return false;
2708
2709         old_v_total = timing->v_total;
2710         old_v_front_porch = timing->v_front_porch;
2711
2712         timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2713         timing->pix_clk_100hz = max_input_rate_in_100hz;
2714
2715         new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2716
2717         timing->v_total = new_v_total;
2718         timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2719         return true;
2720 }
2721 #endif
2722
2723 void dcn20_set_disp_pattern_generator(const struct dc *dc,
2724                 struct pipe_ctx *pipe_ctx,
2725                 enum controller_dp_test_pattern test_pattern,
2726                 enum controller_dp_color_space color_space,
2727                 enum dc_color_depth color_depth,
2728                 const struct tg_color *solid_color,
2729                 int width, int height, int offset)
2730 {
2731         pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2732                         color_space, color_depth, solid_color, width, height, offset);
2733 }