drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dc_link_dp.h"
  50 #include "vm_helper.h"
  51 #include "dccg.h"
  52 #include "dc_dmub_srv.h"
  53 #include "dce/dmub_hw_lock_mgr.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61
  62 #undef FN
  63 #define FN(reg_name, field_name) \
  64         hws->shifts->field_name, hws->masks->field_name
  65
  66 static int find_free_gsl_group(const struct dc *dc)
  67 {
  68         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  69                 return 1;
  70         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  71                 return 2;
  72         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  73                 return 3;
  74
  75         return 0;
  76 }
  77
  78 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  79  * This is only used to lock pipes in pipe splitting case with immediate flip
  80  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  81  * so we get tearing with freesync since we cannot flip multiple pipes
  82  * atomically.
  83  * We use GSL for this:
  84  * - immediate flip: find first available GSL group if not already assigned
  85  *                   program gsl with that group, set current OTG as master
  86  *                   and always us 0x4 = AND of flip_ready from all pipes
  87  * - vsync flip: disable GSL if used
  88  *
  89  * Groups in stream_res are stored as +1 from HW registers, i.e.
  90  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  91  * Using a magic value like -1 would require tracking all inits/resets
  92  */
  93 static void dcn20_setup_gsl_group_as_lock(
  94                 const struct dc *dc,
  95                 struct pipe_ctx *pipe_ctx,
  96                 bool enable)
  97 {
  98         struct gsl_params gsl;
  99         int group_idx;
 100
 101         memset(&gsl, 0, sizeof(struct gsl_params));
 102
 103         if (enable) {
 104                 /* return if group already assigned since GSL was set up
 105                  * for vsync flip, we would unassign so it can't be "left over"
 106                  */
 107                 if (pipe_ctx->stream_res.gsl_group > 0)
 108                         return;
 109
 110                 group_idx = find_free_gsl_group(dc);
 111                 ASSERT(group_idx != 0);
 112                 pipe_ctx->stream_res.gsl_group = group_idx;
 113
 114                 /* set gsl group reg field and mark resource used */
 115                 switch (group_idx) {
 116                 case 1:
 117                         gsl.gsl0_en = 1;
 118                         dc->res_pool->gsl_groups.gsl_0 = 1;
 119                         break;
 120                 case 2:
 121                         gsl.gsl1_en = 1;
 122                         dc->res_pool->gsl_groups.gsl_1 = 1;
 123                         break;
 124                 case 3:
 125                         gsl.gsl2_en = 1;
 126                         dc->res_pool->gsl_groups.gsl_2 = 1;
 127                         break;
 128                 default:
 129                         BREAK_TO_DEBUGGER();
 130                         return; // invalid case
 131                 }
 132                 gsl.gsl_master_en = 1;
 133         } else {
 134                 group_idx = pipe_ctx->stream_res.gsl_group;
 135                 if (group_idx == 0)
 136                         return; // if not in use, just return
 137
 138                 pipe_ctx->stream_res.gsl_group = 0;
 139
 140                 /* unset gsl group reg field and mark resource free */
 141                 switch (group_idx) {
 142                 case 1:
 143                         gsl.gsl0_en = 0;
 144                         dc->res_pool->gsl_groups.gsl_0 = 0;
 145                         break;
 146                 case 2:
 147                         gsl.gsl1_en = 0;
 148                         dc->res_pool->gsl_groups.gsl_1 = 0;
 149                         break;
 150                 case 3:
 151                         gsl.gsl2_en = 0;
 152                         dc->res_pool->gsl_groups.gsl_2 = 0;
 153                         break;
 154                 default:
 155                         BREAK_TO_DEBUGGER();
 156                         return;
 157                 }
 158                 gsl.gsl_master_en = 0;
 159         }
 160
 161         /* at this point we want to program whether it's to enable or disable */
 162         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 163                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 164                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 165                         pipe_ctx->stream_res.tg,
 166                         &gsl);
 167
 168                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 169                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 170         } else
 171                 BREAK_TO_DEBUGGER();
 172 }
 173
 174 void dcn20_set_flip_control_gsl(
 175                 struct pipe_ctx *pipe_ctx,
 176                 bool flip_immediate)
 177 {
 178         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 179                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 180                                 pipe_ctx->plane_res.hubp, flip_immediate);
 181
 182 }
 183
 184 void dcn20_enable_power_gating_plane(
 185         struct dce_hwseq *hws,
 186         bool enable)
 187 {
 188         bool force_on = true; /* disable power gating */
 189
 190         if (enable)
 191                 force_on = false;
 192
 193         /* DCHUBP0/1/2/3/4/5 */
 194         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 195         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 196         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 197         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 198         if (REG(DOMAIN8_PG_CONFIG))
 199                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 200         if (REG(DOMAIN10_PG_CONFIG))
 201                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 202
 203         /* DPP0/1/2/3/4/5 */
 204         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 205         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 206         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 207         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 208         if (REG(DOMAIN9_PG_CONFIG))
 209                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 210         if (REG(DOMAIN11_PG_CONFIG))
 211                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 212
 213         /* DCS0/1/2/3/4/5 */
 214         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 215         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 216         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 217         if (REG(DOMAIN19_PG_CONFIG))
 218                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 219         if (REG(DOMAIN20_PG_CONFIG))
 220                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 221         if (REG(DOMAIN21_PG_CONFIG))
 222                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 223 }
 224
 225 void dcn20_dccg_init(struct dce_hwseq *hws)
 226 {
 227         /*
 228          * set MICROSECOND_TIME_BASE_DIV
 229          * 100Mhz refclk -> 0x120264
 230          * 27Mhz refclk -> 0x12021b
 231          * 48Mhz refclk -> 0x120230
 232          *
 233          */
 234         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 235
 236         /*
 237          * set MILLISECOND_TIME_BASE_DIV
 238          * 100Mhz refclk -> 0x1186a0
 239          * 27Mhz refclk -> 0x106978
 240          * 48Mhz refclk -> 0x10bb80
 241          *
 242          */
 243         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 244
 245         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 246         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
 247 }
 248
 249 void dcn20_disable_vga(
 250         struct dce_hwseq *hws)
 251 {
 252         REG_WRITE(D1VGA_CONTROL, 0);
 253         REG_WRITE(D2VGA_CONTROL, 0);
 254         REG_WRITE(D3VGA_CONTROL, 0);
 255         REG_WRITE(D4VGA_CONTROL, 0);
 256         REG_WRITE(D5VGA_CONTROL, 0);
 257         REG_WRITE(D6VGA_CONTROL, 0);
 258 }
 259
 260 void dcn20_program_triple_buffer(
 261         const struct dc *dc,
 262         struct pipe_ctx *pipe_ctx,
 263         bool enable_triple_buffer)
 264 {
 265         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 266                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 267                         pipe_ctx->plane_res.hubp,
 268                         enable_triple_buffer);
 269         }
 270 }
 271
 272 /* Blank pixel data during initialization */
 273 void dcn20_init_blank(
 274                 struct dc *dc,
 275                 struct timing_generator *tg)
 276 {
 277         struct dce_hwseq *hws = dc->hwseq;
 278         enum dc_color_space color_space;
 279         struct tg_color black_color = {0};
 280         struct output_pixel_processor *opp = NULL;
 281         struct output_pixel_processor *bottom_opp = NULL;
 282         uint32_t num_opps, opp_id_src0, opp_id_src1;
 283         uint32_t otg_active_width, otg_active_height;
 284
 285         /* program opp dpg blank color */
 286         color_space = COLOR_SPACE_SRGB;
 287         color_space_to_black_color(dc, color_space, &black_color);
 288
 289         /* get the OTG active size */
 290         tg->funcs->get_otg_active_size(tg,
 291                         &otg_active_width,
 292                         &otg_active_height);
 293
 294         /* get the OPTC source */
 295         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 296
 297         if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
 298                 ASSERT(false);
 299                 return;
 300         }
 301         opp = dc->res_pool->opps[opp_id_src0];
 302
 303         if (num_opps == 2) {
 304                 otg_active_width = otg_active_width / 2;
 305
 306                 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
 307                         ASSERT(false);
 308                         return;
 309                 }
 310                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 311         }
 312
 313         opp->funcs->opp_set_disp_pattern_generator(
 314                         opp,
 315                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 316                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 317                         COLOR_DEPTH_UNDEFINED,
 318                         &black_color,
 319                         otg_active_width,
 320                         otg_active_height,
 321                         0);
 322
 323         if (num_opps == 2) {
 324                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 325                                 bottom_opp,
 326                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 327                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 328                                 COLOR_DEPTH_UNDEFINED,
 329                                 &black_color,
 330                                 otg_active_width,
 331                                 otg_active_height,
 332                                 0);
 333         }
 334
 335         hws->funcs.wait_for_blank_complete(opp);
 336 }
 337
 338 void dcn20_dsc_pg_control(
 339                 struct dce_hwseq *hws,
 340                 unsigned int dsc_inst,
 341                 bool power_on)
 342 {
 343         uint32_t power_gate = power_on ? 0 : 1;
 344         uint32_t pwr_status = power_on ? 0 : 2;
 345         uint32_t org_ip_request_cntl = 0;
 346
 347         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 348                 return;
 349
 350         if (REG(DOMAIN16_PG_CONFIG) == 0)
 351                 return;
 352
 353         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 354         if (org_ip_request_cntl == 0)
 355                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 356
 357         switch (dsc_inst) {
 358         case 0: /* DSC0 */
 359                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 360                                 DOMAIN16_POWER_GATE, power_gate);
 361
 362                 REG_WAIT(DOMAIN16_PG_STATUS,
 363                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 364                                 1, 1000);
 365                 break;
 366         case 1: /* DSC1 */
 367                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 368                                 DOMAIN17_POWER_GATE, power_gate);
 369
 370                 REG_WAIT(DOMAIN17_PG_STATUS,
 371                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 372                                 1, 1000);
 373                 break;
 374         case 2: /* DSC2 */
 375                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 376                                 DOMAIN18_POWER_GATE, power_gate);
 377
 378                 REG_WAIT(DOMAIN18_PG_STATUS,
 379                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 380                                 1, 1000);
 381                 break;
 382         case 3: /* DSC3 */
 383                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 384                                 DOMAIN19_POWER_GATE, power_gate);
 385
 386                 REG_WAIT(DOMAIN19_PG_STATUS,
 387                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 388                                 1, 1000);
 389                 break;
 390         case 4: /* DSC4 */
 391                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 392                                 DOMAIN20_POWER_GATE, power_gate);
 393
 394                 REG_WAIT(DOMAIN20_PG_STATUS,
 395                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 396                                 1, 1000);
 397                 break;
 398         case 5: /* DSC5 */
 399                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 400                                 DOMAIN21_POWER_GATE, power_gate);
 401
 402                 REG_WAIT(DOMAIN21_PG_STATUS,
 403                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 404                                 1, 1000);
 405                 break;
 406         default:
 407                 BREAK_TO_DEBUGGER();
 408                 break;
 409         }
 410
 411         if (org_ip_request_cntl == 0)
 412                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 413 }
 414
 415 void dcn20_dpp_pg_control(
 416                 struct dce_hwseq *hws,
 417                 unsigned int dpp_inst,
 418                 bool power_on)
 419 {
 420         uint32_t power_gate = power_on ? 0 : 1;
 421         uint32_t pwr_status = power_on ? 0 : 2;
 422
 423         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 424                 return;
 425         if (REG(DOMAIN1_PG_CONFIG) == 0)
 426                 return;
 427
 428         switch (dpp_inst) {
 429         case 0: /* DPP0 */
 430                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 431                                 DOMAIN1_POWER_GATE, power_gate);
 432
 433                 REG_WAIT(DOMAIN1_PG_STATUS,
 434                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 435                                 1, 1000);
 436                 break;
 437         case 1: /* DPP1 */
 438                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 439                                 DOMAIN3_POWER_GATE, power_gate);
 440
 441                 REG_WAIT(DOMAIN3_PG_STATUS,
 442                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 443                                 1, 1000);
 444                 break;
 445         case 2: /* DPP2 */
 446                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 447                                 DOMAIN5_POWER_GATE, power_gate);
 448
 449                 REG_WAIT(DOMAIN5_PG_STATUS,
 450                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 451                                 1, 1000);
 452                 break;
 453         case 3: /* DPP3 */
 454                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 455                                 DOMAIN7_POWER_GATE, power_gate);
 456
 457                 REG_WAIT(DOMAIN7_PG_STATUS,
 458                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 459                                 1, 1000);
 460                 break;
 461         case 4: /* DPP4 */
 462                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 463                                 DOMAIN9_POWER_GATE, power_gate);
 464
 465                 REG_WAIT(DOMAIN9_PG_STATUS,
 466                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 467                                 1, 1000);
 468                 break;
 469         case 5: /* DPP5 */
 470                 /*
 471                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 472                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 473                  * reset.
 474                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 475                  *              DOMAIN11_POWER_GATE, power_gate);
 476                  *
 477                  * REG_WAIT(DOMAIN11_PG_STATUS,
 478                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 479                  *              1, 1000);
 480                  */
 481                 break;
 482         default:
 483                 BREAK_TO_DEBUGGER();
 484                 break;
 485         }
 486 }
 487
 488
 489 void dcn20_hubp_pg_control(
 490                 struct dce_hwseq *hws,
 491                 unsigned int hubp_inst,
 492                 bool power_on)
 493 {
 494         uint32_t power_gate = power_on ? 0 : 1;
 495         uint32_t pwr_status = power_on ? 0 : 2;
 496
 497         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 498                 return;
 499         if (REG(DOMAIN0_PG_CONFIG) == 0)
 500                 return;
 501
 502         switch (hubp_inst) {
 503         case 0: /* DCHUBP0 */
 504                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 505                                 DOMAIN0_POWER_GATE, power_gate);
 506
 507                 REG_WAIT(DOMAIN0_PG_STATUS,
 508                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 509                                 1, 1000);
 510                 break;
 511         case 1: /* DCHUBP1 */
 512                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 513                                 DOMAIN2_POWER_GATE, power_gate);
 514
 515                 REG_WAIT(DOMAIN2_PG_STATUS,
 516                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 517                                 1, 1000);
 518                 break;
 519         case 2: /* DCHUBP2 */
 520                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 521                                 DOMAIN4_POWER_GATE, power_gate);
 522
 523                 REG_WAIT(DOMAIN4_PG_STATUS,
 524                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 525                                 1, 1000);
 526                 break;
 527         case 3: /* DCHUBP3 */
 528                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 529                                 DOMAIN6_POWER_GATE, power_gate);
 530
 531                 REG_WAIT(DOMAIN6_PG_STATUS,
 532                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 533                                 1, 1000);
 534                 break;
 535         case 4: /* DCHUBP4 */
 536                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 537                                 DOMAIN8_POWER_GATE, power_gate);
 538
 539                 REG_WAIT(DOMAIN8_PG_STATUS,
 540                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 541                                 1, 1000);
 542                 break;
 543         case 5: /* DCHUBP5 */
 544                 /*
 545                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 546                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 547                  * reset.
 548                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 549                  *              DOMAIN10_POWER_GATE, power_gate);
 550                  *
 551                  * REG_WAIT(DOMAIN10_PG_STATUS,
 552                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 553                  *              1, 1000);
 554                  */
 555                 break;
 556         default:
 557                 BREAK_TO_DEBUGGER();
 558                 break;
 559         }
 560 }
 561
 562
 563 /* disable HW used by plane.
 564  * note:  cannot disable until disconnect is complete
 565  */
 566 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 567 {
 568         struct dce_hwseq *hws = dc->hwseq;
 569         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 570         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 571
 572         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 573
 574         /* In flip immediate with pipe splitting case GSL is used for
 575          * synchronization so we must disable it when the plane is disabled.
 576          */
 577         if (pipe_ctx->stream_res.gsl_group != 0)
 578                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 579
 580         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 581
 582         hubp->funcs->hubp_clk_cntl(hubp, false);
 583
 584         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 585
 586         hubp->power_gated = true;
 587
 588         hws->funcs.plane_atomic_power_down(dc,
 589                         pipe_ctx->plane_res.dpp,
 590                         pipe_ctx->plane_res.hubp);
 591
 592         pipe_ctx->stream = NULL;
 593         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 594         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 595         pipe_ctx->top_pipe = NULL;
 596         pipe_ctx->bottom_pipe = NULL;
 597         pipe_ctx->plane_state = NULL;
 598 }
 599
 600
 601 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 602 {
 603         DC_LOGGER_INIT(dc->ctx->logger);
 604
 605         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 606                 return;
 607
 608         dcn20_plane_atomic_disable(dc, pipe_ctx);
 609
 610         DC_LOG_DC("Power down front end %d\n",
 611                                         pipe_ctx->pipe_idx);
 612 }
 613
 614 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 615                 int opp_cnt)
 616 {
 617         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 618         int flow_ctrl_cnt;
 619
 620         if (opp_cnt >= 2)
 621                 hblank_halved = true;
 622
 623         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 624                         stream->timing.h_border_left -
 625                         stream->timing.h_border_right;
 626
 627         if (hblank_halved)
 628                 flow_ctrl_cnt /= 2;
 629
 630         /* ODM combine 4:1 case */
 631         if (opp_cnt == 4)
 632                 flow_ctrl_cnt /= 2;
 633
 634         return flow_ctrl_cnt;
 635 }
 636
 637 enum dc_status dcn20_enable_stream_timing(
 638                 struct pipe_ctx *pipe_ctx,
 639                 struct dc_state *context,
 640                 struct dc *dc)
 641 {
 642         struct dce_hwseq *hws = dc->hwseq;
 643         struct dc_stream_state *stream = pipe_ctx->stream;
 644         struct drr_params params = {0};
 645         unsigned int event_triggers = 0;
 646         struct pipe_ctx *odm_pipe;
 647         int opp_cnt = 1;
 648         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 649         bool interlace = stream->timing.flags.INTERLACE;
 650         int i;
 651         struct mpc_dwb_flow_control flow_control;
 652         struct mpc *mpc = dc->res_pool->mpc;
 653         bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
 654
 655         /* by upper caller loop, pipe0 is parent pipe and be called first.
 656          * back end is set up by for pipe0. Other children pipe share back end
 657          * with pipe 0. No program is needed.
 658          */
 659         if (pipe_ctx->top_pipe != NULL)
 660                 return DC_OK;
 661
 662         /* TODO check if timing_changed, disable stream if timing changed */
 663
 664         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 665                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 666                 opp_cnt++;
 667         }
 668
 669         if (opp_cnt > 1)
 670                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 671                                 pipe_ctx->stream_res.tg,
 672                                 opp_inst, opp_cnt,
 673                                 &pipe_ctx->stream->timing);
 674
 675         /* HW program guide assume display already disable
 676          * by unplug sequence. OTG assume stop.
 677          */
 678         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 679
 680         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 681                         pipe_ctx->clock_source,
 682                         &pipe_ctx->stream_res.pix_clk_params,
 683                         &pipe_ctx->pll_settings)) {
 684                 BREAK_TO_DEBUGGER();
 685                 return DC_ERROR_UNEXPECTED;
 686         }
 687
 688         if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
 689                 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
 690
 691         pipe_ctx->stream_res.tg->funcs->program_timing(
 692                         pipe_ctx->stream_res.tg,
 693                         &stream->timing,
 694                         pipe_ctx->pipe_dlg_param.vready_offset,
 695                         pipe_ctx->pipe_dlg_param.vstartup_start,
 696                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 697                         pipe_ctx->pipe_dlg_param.vupdate_width,
 698                         pipe_ctx->stream->signal,
 699                         true);
 700
 701         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
 702         flow_control.flow_ctrl_mode = 0;
 703         flow_control.flow_ctrl_cnt0 = 0x80;
 704         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
 705         if (mpc->funcs->set_out_rate_control) {
 706                 for (i = 0; i < opp_cnt; ++i) {
 707                         mpc->funcs->set_out_rate_control(
 708                                         mpc, opp_inst[i],
 709                                         true,
 710                                         rate_control_2x_pclk,
 711                                         &flow_control);
 712                 }
 713         }
 714
 715         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 716                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 717                                 odm_pipe->stream_res.opp,
 718                                 true);
 719
 720         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 721                         pipe_ctx->stream_res.opp,
 722                         true);
 723
 724         hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
 725
 726         /* VTG is  within DCHUB command block. DCFCLK is always on */
 727         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 728                 BREAK_TO_DEBUGGER();
 729                 return DC_ERROR_UNEXPECTED;
 730         }
 731
 732         hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 733
 734         params.vertical_total_min = stream->adjust.v_total_min;
 735         params.vertical_total_max = stream->adjust.v_total_max;
 736         params.vertical_total_mid = stream->adjust.v_total_mid;
 737         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 738         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 739                 pipe_ctx->stream_res.tg->funcs->set_drr(
 740                         pipe_ctx->stream_res.tg, &params);
 741
 742         // DRR should set trigger event to monitor surface update event
 743         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 744                 event_triggers = 0x80;
 745         /* Event triggers and num frames initialized for DRR, but can be
 746          * later updated for PSR use. Note DRR trigger events are generated
 747          * regardless of whether num frames met.
 748          */
 749         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 750                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 751                                 pipe_ctx->stream_res.tg, event_triggers, 2);
 752
 753         /* TODO program crtc source select for non-virtual signal*/
 754         /* TODO program FMT */
 755         /* TODO setup link_enc */
 756         /* TODO set stream attributes */
 757         /* TODO program audio */
 758         /* TODO enable stream if timing changed */
 759         /* TODO unblank stream if DP */
 760
 761         return DC_OK;
 762 }
 763
 764 void dcn20_program_output_csc(struct dc *dc,
 765                 struct pipe_ctx *pipe_ctx,
 766                 enum dc_color_space colorspace,
 767                 uint16_t *matrix,
 768                 int opp_id)
 769 {
 770         struct mpc *mpc = dc->res_pool->mpc;
 771         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 772         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 773
 774         if (mpc->funcs->power_on_mpc_mem_pwr)
 775                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 776
 777         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 778                 if (mpc->funcs->set_output_csc != NULL)
 779                         mpc->funcs->set_output_csc(mpc,
 780                                         opp_id,
 781                                         matrix,
 782                                         ocsc_mode);
 783         } else {
 784                 if (mpc->funcs->set_ocsc_default != NULL)
 785                         mpc->funcs->set_ocsc_default(mpc,
 786                                         opp_id,
 787                                         colorspace,
 788                                         ocsc_mode);
 789         }
 790 }
 791
 792 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 793                                 const struct dc_stream_state *stream)
 794 {
 795         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 796         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 797         struct pwl_params *params = NULL;
 798         /*
 799          * program OGAM only for the top pipe
 800          * if there is a pipe split then fix diagnostic is required:
 801          * how to pass OGAM parameter for stream.
 802          * if programming for all pipes is required then remove condition
 803          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 804          */
 805         if (mpc->funcs->power_on_mpc_mem_pwr)
 806                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 807         if (pipe_ctx->top_pipe == NULL
 808                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 809                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 810                         params = &stream->out_transfer_func->pwl;
 811                 else if (pipe_ctx->stream->out_transfer_func->type ==
 812                         TF_TYPE_DISTRIBUTED_POINTS &&
 813                         cm_helper_translate_curve_to_hw_format(
 814                         stream->out_transfer_func,
 815                         &mpc->blender_params, false))
 816                         params = &mpc->blender_params;
 817                 /*
 818                  * there is no ROM
 819                  */
 820                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 821                         BREAK_TO_DEBUGGER();
 822         }
 823         /*
 824          * if above if is not executed then 'params' equal to 0 and set in bypass
 825          */
 826         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 827
 828         return true;
 829 }
 830
 831 bool dcn20_set_blend_lut(
 832         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 833 {
 834         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 835         bool result = true;
 836         struct pwl_params *blend_lut = NULL;
 837
 838         if (plane_state->blend_tf) {
 839                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 840                         blend_lut = &plane_state->blend_tf->pwl;
 841                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 842                         cm_helper_translate_curve_to_hw_format(
 843                                         plane_state->blend_tf,
 844                                         &dpp_base->regamma_params, false);
 845                         blend_lut = &dpp_base->regamma_params;
 846                 }
 847         }
 848         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 849
 850         return result;
 851 }
 852
 853 bool dcn20_set_shaper_3dlut(
 854         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 855 {
 856         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 857         bool result = true;
 858         struct pwl_params *shaper_lut = NULL;
 859
 860         if (plane_state->in_shaper_func) {
 861                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 862                         shaper_lut = &plane_state->in_shaper_func->pwl;
 863                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 864                         cm_helper_translate_curve_to_hw_format(
 865                                         plane_state->in_shaper_func,
 866                                         &dpp_base->shaper_params, true);
 867                         shaper_lut = &dpp_base->shaper_params;
 868                 }
 869         }
 870
 871         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 872         if (plane_state->lut3d_func &&
 873                 plane_state->lut3d_func->state.bits.initialized == 1)
 874                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 875                                                                 &plane_state->lut3d_func->lut_3d);
 876         else
 877                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 878
 879         return result;
 880 }
 881
 882 bool dcn20_set_input_transfer_func(struct dc *dc,
 883                                 struct pipe_ctx *pipe_ctx,
 884                                 const struct dc_plane_state *plane_state)
 885 {
 886         struct dce_hwseq *hws = dc->hwseq;
 887         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 888         const struct dc_transfer_func *tf = NULL;
 889         bool result = true;
 890         bool use_degamma_ram = false;
 891
 892         if (dpp_base == NULL || plane_state == NULL)
 893                 return false;
 894
 895         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 896         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 897
 898         if (plane_state->in_transfer_func)
 899                 tf = plane_state->in_transfer_func;
 900
 901
 902         if (tf == NULL) {
 903                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 904                                 IPP_DEGAMMA_MODE_BYPASS);
 905                 return true;
 906         }
 907
 908         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 909                 use_degamma_ram = true;
 910
 911         if (use_degamma_ram == true) {
 912                 if (tf->type == TF_TYPE_HWPWL)
 913                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 914                                         &tf->pwl);
 915                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 916                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 917                                         &dpp_base->degamma_params);
 918                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 919                                 &dpp_base->degamma_params);
 920                 }
 921                 return true;
 922         }
 923         /* handle here the optimized cases when de-gamma ROM could be used.
 924          *
 925          */
 926         if (tf->type == TF_TYPE_PREDEFINED) {
 927                 switch (tf->tf) {
 928                 case TRANSFER_FUNCTION_SRGB:
 929                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 930                                         IPP_DEGAMMA_MODE_HW_sRGB);
 931                         break;
 932                 case TRANSFER_FUNCTION_BT709:
 933                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 934                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 935                         break;
 936                 case TRANSFER_FUNCTION_LINEAR:
 937                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 938                                         IPP_DEGAMMA_MODE_BYPASS);
 939                         break;
 940                 case TRANSFER_FUNCTION_PQ:
 941                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
 942                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
 943                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
 944                         result = true;
 945                         break;
 946                 default:
 947                         result = false;
 948                         break;
 949                 }
 950         } else if (tf->type == TF_TYPE_BYPASS)
 951                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 952                                 IPP_DEGAMMA_MODE_BYPASS);
 953         else {
 954                 /*
 955                  * if we are here, we did not handle correctly.
 956                  * fix is required for this use case
 957                  */
 958                 BREAK_TO_DEBUGGER();
 959                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 960                                 IPP_DEGAMMA_MODE_BYPASS);
 961         }
 962
 963         return result;
 964 }
 965
 966 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 967 {
 968         struct pipe_ctx *odm_pipe;
 969         int opp_cnt = 1;
 970         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 971
 972         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 973                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 974                 opp_cnt++;
 975         }
 976
 977         if (opp_cnt > 1)
 978                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 979                                 pipe_ctx->stream_res.tg,
 980                                 opp_inst, opp_cnt,
 981                                 &pipe_ctx->stream->timing);
 982         else
 983                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 984                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 985 }
 986
 987 void dcn20_blank_pixel_data(
 988                 struct dc *dc,
 989                 struct pipe_ctx *pipe_ctx,
 990                 bool blank)
 991 {
 992         struct tg_color black_color = {0};
 993         struct stream_resource *stream_res = &pipe_ctx->stream_res;
 994         struct dc_stream_state *stream = pipe_ctx->stream;
 995         enum dc_color_space color_space = stream->output_color_space;
 996         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
 997         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
 998         struct pipe_ctx *odm_pipe;
 999         int odm_cnt = 1;
1000
1001         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1002         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1003
1004         if (stream->link->test_pattern_enabled)
1005                 return;
1006
1007         /* get opp dpg blank color */
1008         color_space_to_black_color(dc, color_space, &black_color);
1009
1010         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1011                 odm_cnt++;
1012
1013         width = width / odm_cnt;
1014
1015         if (blank) {
1016                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1017
1018                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1019                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1020                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1021                 }
1022         } else {
1023                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1024         }
1025
1026         dc->hwss.set_disp_pattern_generator(dc,
1027                         pipe_ctx,
1028                         test_pattern,
1029                         test_pattern_color_space,
1030                         stream->timing.display_color_depth,
1031                         &black_color,
1032                         width,
1033                         height,
1034                         0);
1035
1036         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1037                 dc->hwss.set_disp_pattern_generator(dc,
1038                                 odm_pipe,
1039                                 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
1040                                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
1041                                 test_pattern_color_space,
1042                                 stream->timing.display_color_depth,
1043                                 &black_color,
1044                                 width,
1045                                 height,
1046                                 0);
1047         }
1048
1049         if (!blank)
1050                 if (stream_res->abm) {
1051                         dc->hwss.set_pipe(pipe_ctx);
1052                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1053                 }
1054 }
1055
1056
1057 static void dcn20_power_on_plane(
1058         struct dce_hwseq *hws,
1059         struct pipe_ctx *pipe_ctx)
1060 {
1061         DC_LOGGER_INIT(hws->ctx->logger);
1062         if (REG(DC_IP_REQUEST_CNTL)) {
1063                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1064                                 IP_REQUEST_EN, 1);
1065
1066                 if (hws->funcs.dpp_pg_control)
1067                         hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1068
1069                 if (hws->funcs.hubp_pg_control)
1070                         hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1071
1072                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1073                                 IP_REQUEST_EN, 0);
1074                 DC_LOG_DEBUG(
1075                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1076         }
1077 }
1078
1079 void dcn20_enable_plane(
1080         struct dc *dc,
1081         struct pipe_ctx *pipe_ctx,
1082         struct dc_state *context)
1083 {
1084         //if (dc->debug.sanity_checks) {
1085         //      dcn10_verify_allow_pstate_change_high(dc);
1086         //}
1087         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1088
1089         /* enable DCFCLK current DCHUB */
1090         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1091
1092         /* initialize HUBP on power up */
1093         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1094
1095         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1096         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1097                         pipe_ctx->stream_res.opp,
1098                         true);
1099
1100 /* TODO: enable/disable in dm as per update type.
1101         if (plane_state) {
1102                 DC_LOG_DC(dc->ctx->logger,
1103                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1104                                 "addr low:0x%x, "
1105                                 "src: %d, %d, %d,"
1106                                 " %d; dst: %d, %d, %d, %d;\n",
1107                                 pipe_ctx->pipe_idx,
1108                                 plane_state,
1109                                 plane_state->address.grph.addr.high_part,
1110                                 plane_state->address.grph.addr.low_part,
1111                                 plane_state->src_rect.x,
1112                                 plane_state->src_rect.y,
1113                                 plane_state->src_rect.width,
1114                                 plane_state->src_rect.height,
1115                                 plane_state->dst_rect.x,
1116                                 plane_state->dst_rect.y,
1117                                 plane_state->dst_rect.width,
1118                                 plane_state->dst_rect.height);
1119
1120                 DC_LOG_DC(dc->ctx->logger,
1121                                 "Pipe %d: width, height, x, y         format:%d\n"
1122                                 "viewport:%d, %d, %d, %d\n"
1123                                 "recout:  %d, %d, %d, %d\n",
1124                                 pipe_ctx->pipe_idx,
1125                                 plane_state->format,
1126                                 pipe_ctx->plane_res.scl_data.viewport.width,
1127                                 pipe_ctx->plane_res.scl_data.viewport.height,
1128                                 pipe_ctx->plane_res.scl_data.viewport.x,
1129                                 pipe_ctx->plane_res.scl_data.viewport.y,
1130                                 pipe_ctx->plane_res.scl_data.recout.width,
1131                                 pipe_ctx->plane_res.scl_data.recout.height,
1132                                 pipe_ctx->plane_res.scl_data.recout.x,
1133                                 pipe_ctx->plane_res.scl_data.recout.y);
1134                 print_rq_dlg_ttu(dc, pipe_ctx);
1135         }
1136 */
1137         if (dc->vm_pa_config.valid) {
1138                 struct vm_system_aperture_param apt;
1139
1140                 apt.sys_default.quad_part = 0;
1141
1142                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1143                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1144
1145                 // Program system aperture settings
1146                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1147         }
1148
1149         if (!pipe_ctx->top_pipe
1150                 && pipe_ctx->plane_state
1151                 && pipe_ctx->plane_state->flip_int_enabled
1152                 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1153                         pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1154
1155 //      if (dc->debug.sanity_checks) {
1156 //              dcn10_verify_allow_pstate_change_high(dc);
1157 //      }
1158 }
1159
1160 void dcn20_pipe_control_lock(
1161         struct dc *dc,
1162         struct pipe_ctx *pipe,
1163         bool lock)
1164 {
1165         struct pipe_ctx *temp_pipe;
1166         bool flip_immediate = false;
1167
1168         /* use TG master update lock to lock everything on the TG
1169          * therefore only top pipe need to lock
1170          */
1171         if (!pipe || pipe->top_pipe)
1172                 return;
1173
1174         if (pipe->plane_state != NULL)
1175                 flip_immediate = pipe->plane_state->flip_immediate;
1176
1177         if  (pipe->stream_res.gsl_group > 0) {
1178             temp_pipe = pipe->bottom_pipe;
1179             while (!flip_immediate && temp_pipe) {
1180                     if (temp_pipe->plane_state != NULL)
1181                             flip_immediate = temp_pipe->plane_state->flip_immediate;
1182                     temp_pipe = temp_pipe->bottom_pipe;
1183             }
1184         }
1185
1186         if (flip_immediate && lock) {
1187                 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1188                 int i;
1189
1190                 temp_pipe = pipe;
1191                 while (temp_pipe) {
1192                         if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1193                                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1194                                         if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1195                                                 break;
1196                                         udelay(1);
1197                                 }
1198
1199                                 /* no reason it should take this long for immediate flips */
1200                                 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
1201                         }
1202                         temp_pipe = temp_pipe->bottom_pipe;
1203                 }
1204         }
1205
1206         /* In flip immediate and pipe splitting case, we need to use GSL
1207          * for synchronization. Only do setup on locking and on flip type change.
1208          */
1209         if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
1210                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1211                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1212                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1213
1214         if (pipe->plane_state != NULL)
1215                 flip_immediate = pipe->plane_state->flip_immediate;
1216
1217         temp_pipe = pipe->bottom_pipe;
1218         while (flip_immediate && temp_pipe) {
1219             if (temp_pipe->plane_state != NULL)
1220                 flip_immediate = temp_pipe->plane_state->flip_immediate;
1221             temp_pipe = temp_pipe->bottom_pipe;
1222         }
1223
1224         if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1225                 !flip_immediate)
1226             dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1227
1228         if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1229                 union dmub_hw_lock_flags hw_locks = { 0 };
1230                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1231
1232                 hw_locks.bits.lock_pipe = 1;
1233                 inst_flags.otg_inst =  pipe->stream_res.tg->inst;
1234
1235                 if (pipe->plane_state != NULL)
1236                         hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1237
1238                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1239                                         lock,
1240                                         &hw_locks,
1241                                         &inst_flags);
1242         } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1243                 if (lock)
1244                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1245                 else
1246                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1247         } else {
1248                 if (lock)
1249                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1250                 else
1251                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1252         }
1253 }
1254
1255 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1256 {
1257         new_pipe->update_flags.raw = 0;
1258
1259         /* Exit on unchanged, unused pipe */
1260         if (!old_pipe->plane_state && !new_pipe->plane_state)
1261                 return;
1262         /* Detect pipe enable/disable */
1263         if (!old_pipe->plane_state && new_pipe->plane_state) {
1264                 new_pipe->update_flags.bits.enable = 1;
1265                 new_pipe->update_flags.bits.mpcc = 1;
1266                 new_pipe->update_flags.bits.dppclk = 1;
1267                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1268                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1269                 new_pipe->update_flags.bits.gamut_remap = 1;
1270                 new_pipe->update_flags.bits.scaler = 1;
1271                 new_pipe->update_flags.bits.viewport = 1;
1272                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1273                         new_pipe->update_flags.bits.odm = 1;
1274                         new_pipe->update_flags.bits.global_sync = 1;
1275                 }
1276                 return;
1277         }
1278         if (old_pipe->plane_state && !new_pipe->plane_state) {
1279                 new_pipe->update_flags.bits.disable = 1;
1280                 return;
1281         }
1282
1283         /* Detect plane change */
1284         if (old_pipe->plane_state != new_pipe->plane_state) {
1285                 new_pipe->update_flags.bits.plane_changed = true;
1286         }
1287
1288         /* Detect top pipe only changes */
1289         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1290                 /* Detect odm changes */
1291                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1292                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1293                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1294                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1295                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1296                         new_pipe->update_flags.bits.odm = 1;
1297
1298                 /* Detect global sync changes */
1299                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1300                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1301                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1302                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1303                         new_pipe->update_flags.bits.global_sync = 1;
1304         }
1305
1306         /*
1307          * Detect opp / tg change, only set on change, not on enable
1308          * Assume mpcc inst = pipe index, if not this code needs to be updated
1309          * since mpcc is what is affected by these. In fact all of our sequence
1310          * makes this assumption at the moment with how hubp reset is matched to
1311          * same index mpcc reset.
1312          */
1313         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1314                 new_pipe->update_flags.bits.opp_changed = 1;
1315         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1316                 new_pipe->update_flags.bits.tg_changed = 1;
1317
1318         /*
1319          * Detect mpcc blending changes, only dpp inst and opp matter here,
1320          * mpccs getting removed/inserted update connected ones during their own
1321          * programming
1322          */
1323         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1324                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1325                 new_pipe->update_flags.bits.mpcc = 1;
1326
1327         /* Detect dppclk change */
1328         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1329                 new_pipe->update_flags.bits.dppclk = 1;
1330
1331         /* Check for scl update */
1332         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1333                         new_pipe->update_flags.bits.scaler = 1;
1334         /* Check for vp update */
1335         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1336                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1337                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1338                 new_pipe->update_flags.bits.viewport = 1;
1339
1340         /* Detect dlg/ttu/rq updates */
1341         {
1342                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1343                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1344                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1345                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1346
1347                 /* Detect pipe interdependent updates */
1348                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1349                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1350                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1351                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1352                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1353                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1354                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1355                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1356                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1357                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1358                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1359                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1360                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1361                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1362                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1363                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1364                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1365                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1366                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1367                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1368                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1369                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1370                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1371                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1372                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1373                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1374                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1375                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1376                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1377                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1378                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1379                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1380                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1381                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1382                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1383                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1384                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1385                 }
1386                 /* Detect any other updates to ttu/rq/dlg */
1387                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1388                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1389                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1390                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1391         }
1392 }
1393
1394 static void dcn20_update_dchubp_dpp(
1395         struct dc *dc,
1396         struct pipe_ctx *pipe_ctx,
1397         struct dc_state *context)
1398 {
1399         struct dce_hwseq *hws = dc->hwseq;
1400         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1401         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1402         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1403         bool viewport_changed = false;
1404
1405         if (pipe_ctx->update_flags.bits.dppclk)
1406                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1407
1408         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1409          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1410          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1411          */
1412         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1413                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1414
1415                 hubp->funcs->hubp_setup(
1416                         hubp,
1417                         &pipe_ctx->dlg_regs,
1418                         &pipe_ctx->ttu_regs,
1419                         &pipe_ctx->rq_regs,
1420                         &pipe_ctx->pipe_dlg_param);
1421         }
1422         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1423                 hubp->funcs->hubp_setup_interdependent(
1424                         hubp,
1425                         &pipe_ctx->dlg_regs,
1426                         &pipe_ctx->ttu_regs);
1427
1428         if (pipe_ctx->update_flags.bits.enable ||
1429                         pipe_ctx->update_flags.bits.plane_changed ||
1430                         plane_state->update_flags.bits.bpp_change ||
1431                         plane_state->update_flags.bits.input_csc_change ||
1432                         plane_state->update_flags.bits.color_space_change ||
1433                         plane_state->update_flags.bits.coeff_reduction_change) {
1434                 struct dc_bias_and_scale bns_params = {0};
1435
1436                 // program the input csc
1437                 dpp->funcs->dpp_setup(dpp,
1438                                 plane_state->format,
1439                                 EXPANSION_MODE_ZERO,
1440                                 plane_state->input_csc_color_matrix,
1441                                 plane_state->color_space,
1442                                 NULL);
1443
1444                 if (dpp->funcs->dpp_program_bias_and_scale) {
1445                         //TODO :for CNVC set scale and bias registers if necessary
1446                         build_prescale_params(&bns_params, plane_state);
1447                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1448                 }
1449         }
1450
1451         if (pipe_ctx->update_flags.bits.mpcc
1452                         || pipe_ctx->update_flags.bits.plane_changed
1453                         || plane_state->update_flags.bits.global_alpha_change
1454                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1455                 // MPCC inst is equal to pipe index in practice
1456                 int mpcc_inst = hubp->inst;
1457                 int opp_inst;
1458                 int opp_count = dc->res_pool->pipe_count;
1459
1460                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1461                         if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1462                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1463                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1464                                 break;
1465                         }
1466                 }
1467                 hws->funcs.update_mpcc(dc, pipe_ctx);
1468         }
1469
1470         if (pipe_ctx->update_flags.bits.scaler ||
1471                         plane_state->update_flags.bits.scaling_change ||
1472                         plane_state->update_flags.bits.position_change ||
1473                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1474                         pipe_ctx->stream->update_flags.bits.scaling) {
1475                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1476                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1477                 /* scaler configuration */
1478                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1479                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1480         }
1481
1482         if (pipe_ctx->update_flags.bits.viewport ||
1483                         (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1484                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1485                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1486
1487                 hubp->funcs->mem_program_viewport(
1488                         hubp,
1489                         &pipe_ctx->plane_res.scl_data.viewport,
1490                         &pipe_ctx->plane_res.scl_data.viewport_c);
1491                 viewport_changed = true;
1492         }
1493
1494         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1495         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1496                         pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1497                         pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1498                 dc->hwss.set_cursor_position(pipe_ctx);
1499                 dc->hwss.set_cursor_attribute(pipe_ctx);
1500
1501                 if (dc->hwss.set_cursor_sdr_white_level)
1502                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1503         }
1504
1505         /* Any updates are handled in dc interface, just need
1506          * to apply existing for plane enable / opp change */
1507         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1508                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1509                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1510                 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
1511
1512                 if (mpc->funcs->set_gamut_remap) {
1513                         int i;
1514                         int mpcc_id = hubp->inst;
1515                         struct mpc_grph_gamut_adjustment adjust;
1516                         bool enable_remap_dpp = false;
1517
1518                         memset(&adjust, 0, sizeof(adjust));
1519                         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1520
1521                         /* save the enablement of gamut remap for dpp */
1522                         enable_remap_dpp = pipe_ctx->stream->gamut_remap_matrix.enable_remap;
1523
1524                         /* force bypass gamut remap for dpp/cm */
1525                         pipe_ctx->stream->gamut_remap_matrix.enable_remap = false;
1526                         dc->hwss.program_gamut_remap(pipe_ctx);
1527
1528                         /* restore gamut remap flag and use this remap into mpc */
1529                         pipe_ctx->stream->gamut_remap_matrix.enable_remap = enable_remap_dpp;
1530
1531                         /* build remap matrix for top plane if enabled */
1532                         if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) {
1533                                         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1534                                         for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1535                                                 adjust.temperature_matrix[i] =
1536                                                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1537                         }
1538                         mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust);
1539                 } else
1540                         /* dpp/cm gamut remap*/
1541                         dc->hwss.program_gamut_remap(pipe_ctx);
1542
1543                 /*call the dcn2 method which uses mpc csc*/
1544                 dc->hwss.program_output_csc(dc,
1545                                 pipe_ctx,
1546                                 pipe_ctx->stream->output_color_space,
1547                                 pipe_ctx->stream->csc_color_matrix.matrix,
1548                                 hubp->opp_id);
1549         }
1550
1551         if (pipe_ctx->update_flags.bits.enable ||
1552                         pipe_ctx->update_flags.bits.plane_changed ||
1553                         pipe_ctx->update_flags.bits.opp_changed ||
1554                         plane_state->update_flags.bits.pixel_format_change ||
1555                         plane_state->update_flags.bits.horizontal_mirror_change ||
1556                         plane_state->update_flags.bits.rotation_change ||
1557                         plane_state->update_flags.bits.swizzle_change ||
1558                         plane_state->update_flags.bits.dcc_change ||
1559                         plane_state->update_flags.bits.bpp_change ||
1560                         plane_state->update_flags.bits.scaling_change ||
1561                         plane_state->update_flags.bits.plane_size_change) {
1562                 struct plane_size size = plane_state->plane_size;
1563
1564                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1565                 hubp->funcs->hubp_program_surface_config(
1566                         hubp,
1567                         plane_state->format,
1568                         &plane_state->tiling_info,
1569                         &size,
1570                         plane_state->rotation,
1571                         &plane_state->dcc,
1572                         plane_state->horizontal_mirror,
1573                         0);
1574                 hubp->power_gated = false;
1575         }
1576
1577         if (pipe_ctx->update_flags.bits.enable ||
1578                 pipe_ctx->update_flags.bits.plane_changed ||
1579                 plane_state->update_flags.bits.addr_update)
1580                 hws->funcs.update_plane_addr(dc, pipe_ctx);
1581
1582
1583
1584         if (is_pipe_tree_visible(pipe_ctx))
1585                 dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
1586 }
1587
1588
1589 static void dcn20_program_pipe(
1590                 struct dc *dc,
1591                 struct pipe_ctx *pipe_ctx,
1592                 struct dc_state *context)
1593 {
1594         struct dce_hwseq *hws = dc->hwseq;
1595         /* Only need to unblank on top pipe */
1596         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1597                         && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1598                 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1599
1600         /* Only update TG on top pipe */
1601         if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1602                         && !pipe_ctx->prev_odm_pipe) {
1603
1604                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1605                                 pipe_ctx->stream_res.tg,
1606                                 pipe_ctx->pipe_dlg_param.vready_offset,
1607                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1608                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1609                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1610
1611                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
1612                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1613
1614                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1615                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1616
1617                 if (hws->funcs.setup_vupdate_interrupt)
1618                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1619         }
1620
1621         if (pipe_ctx->update_flags.bits.odm)
1622                 hws->funcs.update_odm(dc, context, pipe_ctx);
1623
1624         if (pipe_ctx->update_flags.bits.enable) {
1625                 dcn20_enable_plane(dc, pipe_ctx, context);
1626                 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1627                         dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1628         }
1629
1630         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1631                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1632
1633         if (pipe_ctx->update_flags.bits.enable
1634                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1635                 hws->funcs.set_hdr_multiplier(pipe_ctx);
1636
1637         if (pipe_ctx->update_flags.bits.enable ||
1638                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1639                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1640                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1641
1642         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1643          * only do gamma programming for powering on, internal memcmp to avoid
1644          * updating on slave planes
1645          */
1646         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1647                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1648
1649         /* If the pipe has been enabled or has a different opp, we
1650          * should reprogram the fmt. This deals with cases where
1651          * interation between mpc and odm combine on different streams
1652          * causes a different pipe to be chosen to odm combine with.
1653          */
1654         if (pipe_ctx->update_flags.bits.enable
1655             || pipe_ctx->update_flags.bits.opp_changed) {
1656
1657                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1658                         pipe_ctx->stream_res.opp,
1659                         COLOR_SPACE_YCBCR601,
1660                         pipe_ctx->stream->timing.display_color_depth,
1661                         pipe_ctx->stream->signal);
1662
1663                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1664                         pipe_ctx->stream_res.opp,
1665                         &pipe_ctx->stream->bit_depth_params,
1666                         &pipe_ctx->stream->clamping);
1667         }
1668 }
1669
1670 void dcn20_program_front_end_for_ctx(
1671                 struct dc *dc,
1672                 struct dc_state *context)
1673 {
1674         int i;
1675         struct dce_hwseq *hws = dc->hwseq;
1676         DC_LOGGER_INIT(dc->ctx->logger);
1677
1678         /* Carry over GSL groups in case the context is changing. */
1679        for (i = 0; i < dc->res_pool->pipe_count; i++) {
1680                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1681                struct pipe_ctx *old_pipe_ctx =
1682                        &dc->current_state->res_ctx.pipe_ctx[i];
1683
1684                if (pipe_ctx->stream == old_pipe_ctx->stream)
1685                        pipe_ctx->stream_res.gsl_group =
1686                                old_pipe_ctx->stream_res.gsl_group;
1687        }
1688
1689         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1690                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1691                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1692
1693                         if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1694                                 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1695                                 /*turn off triple buffer for full update*/
1696                                 dc->hwss.program_triplebuffer(
1697                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1698                         }
1699                 }
1700         }
1701
1702         /* Set pipe update flags and lock pipes */
1703         for (i = 0; i < dc->res_pool->pipe_count; i++)
1704                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1705                                 &context->res_ctx.pipe_ctx[i]);
1706
1707         /* OTG blank before disabling all front ends */
1708         for (i = 0; i < dc->res_pool->pipe_count; i++)
1709                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1710                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1711                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1712                                 && context->res_ctx.pipe_ctx[i].stream)
1713                         hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1714
1715
1716         /* Disconnect mpcc */
1717         for (i = 0; i < dc->res_pool->pipe_count; i++)
1718                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1719                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1720                         hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1721                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1722                 }
1723
1724         /*
1725          * Program all updated pipes, order matters for mpcc setup. Start with
1726          * top pipe and program all pipes that follow in order
1727          */
1728         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1729                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1730
1731                 if (pipe->plane_state && !pipe->top_pipe) {
1732                         while (pipe) {
1733                                 dcn20_program_pipe(dc, pipe, context);
1734                                 pipe = pipe->bottom_pipe;
1735                         }
1736                         /* Program secondary blending tree and writeback pipes */
1737                         pipe = &context->res_ctx.pipe_ctx[i];
1738                         if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1739                                         && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
1740                                         && hws->funcs.program_all_writeback_pipes_in_tree)
1741                                 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1742                 }
1743         }
1744 }
1745
1746 void dcn20_post_unlock_program_front_end(
1747                 struct dc *dc,
1748                 struct dc_state *context)
1749 {
1750         int i;
1751         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1752         struct dce_hwseq *hwseq = dc->hwseq;
1753
1754         DC_LOGGER_INIT(dc->ctx->logger);
1755
1756         for (i = 0; i < dc->res_pool->pipe_count; i++)
1757                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1758                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1759
1760         /*
1761          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1762          * part of the enable operation otherwise, DM may request an immediate flip which
1763          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1764          * is unsupported on DCN.
1765          */
1766         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1767                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1768
1769                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1770                         struct hubp *hubp = pipe->plane_res.hubp;
1771                         int j = 0;
1772
1773                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1774                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1775                                 mdelay(1);
1776                 }
1777         }
1778
1779         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1780                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1781
1782                 if (pipe->vtp_locked) {
1783                         dc->hwss.set_hubp_blank(dc, pipe, true);
1784                         pipe->vtp_locked = false;
1785                 }
1786         }
1787         /* WA to apply WM setting*/
1788         if (hwseq->wa.DEGVIDCN21)
1789                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1790
1791
1792         /* WA for stutter underflow during MPO transitions when adding 2nd plane */
1793         if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1794
1795                 if (dc->current_state->stream_status[0].plane_count == 1 &&
1796                                 context->stream_status[0].plane_count > 1) {
1797
1798                         struct timing_generator *tg = dc->res_pool->timing_generators[0];
1799
1800                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1801
1802                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1803                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1804                 }
1805         }
1806 }
1807
1808 void dcn20_prepare_bandwidth(
1809                 struct dc *dc,
1810                 struct dc_state *context)
1811 {
1812         struct hubbub *hubbub = dc->res_pool->hubbub;
1813
1814         dc->clk_mgr->funcs->update_clocks(
1815                         dc->clk_mgr,
1816                         context,
1817                         false);
1818
1819         /* program dchubbub watermarks */
1820         dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
1821                                         &context->bw_ctx.bw.dcn.watermarks,
1822                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1823                                         false);
1824 }
1825
1826 void dcn20_optimize_bandwidth(
1827                 struct dc *dc,
1828                 struct dc_state *context)
1829 {
1830         struct hubbub *hubbub = dc->res_pool->hubbub;
1831
1832         /* program dchubbub watermarks */
1833         hubbub->funcs->program_watermarks(hubbub,
1834                                         &context->bw_ctx.bw.dcn.watermarks,
1835                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1836                                         true);
1837
1838         dc->clk_mgr->funcs->update_clocks(
1839                         dc->clk_mgr,
1840                         context,
1841                         true);
1842 }
1843
1844 bool dcn20_update_bandwidth(
1845                 struct dc *dc,
1846                 struct dc_state *context)
1847 {
1848         int i;
1849         struct dce_hwseq *hws = dc->hwseq;
1850
1851         /* recalculate DML parameters */
1852         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1853                 return false;
1854
1855         /* apply updated bandwidth parameters */
1856         dc->hwss.prepare_bandwidth(dc, context);
1857
1858         /* update hubp configs for all pipes */
1859         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1860                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1861
1862                 if (pipe_ctx->plane_state == NULL)
1863                         continue;
1864
1865                 if (pipe_ctx->top_pipe == NULL) {
1866                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1867
1868                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1869                                         pipe_ctx->stream_res.tg,
1870                                         pipe_ctx->pipe_dlg_param.vready_offset,
1871                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1872                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1873                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1874
1875                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1876                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
1877
1878                         if (pipe_ctx->prev_odm_pipe == NULL)
1879                                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1880
1881                         if (hws->funcs.setup_vupdate_interrupt)
1882                                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1883                 }
1884
1885                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1886                                 pipe_ctx->plane_res.hubp,
1887                                         &pipe_ctx->dlg_regs,
1888                                         &pipe_ctx->ttu_regs,
1889                                         &pipe_ctx->rq_regs,
1890                                         &pipe_ctx->pipe_dlg_param);
1891         }
1892
1893         return true;
1894 }
1895
1896 void dcn20_enable_writeback(
1897                 struct dc *dc,
1898                 struct dc_writeback_info *wb_info,
1899                 struct dc_state *context)
1900 {
1901         struct dwbc *dwb;
1902         struct mcif_wb *mcif_wb;
1903         struct timing_generator *optc;
1904
1905         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1906         ASSERT(wb_info->wb_enabled);
1907         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1908         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1909
1910         /* set the OPTC source mux */
1911         optc = dc->res_pool->timing_generators[dwb->otg_inst];
1912         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1913         /* set MCIF_WB buffer and arbitration configuration */
1914         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1915         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1916         /* Enable MCIF_WB */
1917         mcif_wb->funcs->enable_mcif(mcif_wb);
1918         /* Enable DWB */
1919         dwb->funcs->enable(dwb, &wb_info->dwb_params);
1920         /* TODO: add sequence to enable/disable warmup */
1921 }
1922
1923 void dcn20_disable_writeback(
1924                 struct dc *dc,
1925                 unsigned int dwb_pipe_inst)
1926 {
1927         struct dwbc *dwb;
1928         struct mcif_wb *mcif_wb;
1929
1930         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1931         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1932         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1933
1934         dwb->funcs->disable(dwb);
1935         mcif_wb->funcs->disable_mcif(mcif_wb);
1936 }
1937
1938 bool dcn20_wait_for_blank_complete(
1939                 struct output_pixel_processor *opp)
1940 {
1941         int counter;
1942
1943         for (counter = 0; counter < 1000; counter++) {
1944                 if (opp->funcs->dpg_is_blanked(opp))
1945                         break;
1946
1947                 udelay(100);
1948         }
1949
1950         if (counter == 1000) {
1951                 dm_error("DC: failed to blank crtc!\n");
1952                 return false;
1953         }
1954
1955         return true;
1956 }
1957
1958 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1959 {
1960         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1961
1962         if (!hubp)
1963                 return false;
1964         return hubp->funcs->dmdata_status_done(hubp);
1965 }
1966
1967 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1968 {
1969         struct dce_hwseq *hws = dc->hwseq;
1970
1971         if (pipe_ctx->stream_res.dsc) {
1972                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1973
1974                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1975                 while (odm_pipe) {
1976                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1977                         odm_pipe = odm_pipe->next_odm_pipe;
1978                 }
1979         }
1980 }
1981
1982 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1983 {
1984         struct dce_hwseq *hws = dc->hwseq;
1985
1986         if (pipe_ctx->stream_res.dsc) {
1987                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1988
1989                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1990                 while (odm_pipe) {
1991                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1992                         odm_pipe = odm_pipe->next_odm_pipe;
1993                 }
1994         }
1995 }
1996
1997 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1998 {
1999         struct dc_dmdata_attributes attr = { 0 };
2000         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2001
2002         attr.dmdata_mode = DMDATA_HW_MODE;
2003         attr.dmdata_size =
2004                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2005         attr.address.quad_part =
2006                         pipe_ctx->stream->dmdata_address.quad_part;
2007         attr.dmdata_dl_delta = 0;
2008         attr.dmdata_qos_mode = 0;
2009         attr.dmdata_qos_level = 0;
2010         attr.dmdata_repeat = 1; /* always repeat */
2011         attr.dmdata_updated = 1;
2012         attr.dmdata_sw_data = NULL;
2013
2014         hubp->funcs->dmdata_set_attributes(hubp, &attr);
2015 }
2016
2017 void dcn20_init_vm_ctx(
2018                 struct dce_hwseq *hws,
2019                 struct dc *dc,
2020                 struct dc_virtual_addr_space_config *va_config,
2021                 int vmid)
2022 {
2023         struct dcn_hubbub_virt_addr_config config;
2024
2025         if (vmid == 0) {
2026                 ASSERT(0); /* VMID cannot be 0 for vm context */
2027                 return;
2028         }
2029
2030         config.page_table_start_addr = va_config->page_table_start_addr;
2031         config.page_table_end_addr = va_config->page_table_end_addr;
2032         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2033         config.page_table_depth = va_config->page_table_depth;
2034         config.page_table_base_addr = va_config->page_table_base_addr;
2035
2036         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2037 }
2038
2039 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
2040 {
2041         struct dcn_hubbub_phys_addr_config config;
2042
2043         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2044         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2045         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2046         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2047         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2048         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2049         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2050         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2051         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
2052         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
2053
2054         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
2055 }
2056
2057 static bool patch_address_for_sbs_tb_stereo(
2058                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2059 {
2060         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2061         bool sec_split = pipe_ctx->top_pipe &&
2062                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2063         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2064                         (pipe_ctx->stream->timing.timing_3d_format ==
2065                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2066                         pipe_ctx->stream->timing.timing_3d_format ==
2067                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2068                 *addr = plane_state->address.grph_stereo.left_addr;
2069                 plane_state->address.grph_stereo.left_addr =
2070                                 plane_state->address.grph_stereo.right_addr;
2071                 return true;
2072         }
2073
2074         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2075                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2076                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2077                 plane_state->address.grph_stereo.right_addr =
2078                                 plane_state->address.grph_stereo.left_addr;
2079                 plane_state->address.grph_stereo.right_meta_addr =
2080                                 plane_state->address.grph_stereo.left_meta_addr;
2081         }
2082         return false;
2083 }
2084
2085 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2086 {
2087         bool addr_patched = false;
2088         PHYSICAL_ADDRESS_LOC addr;
2089         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2090
2091         if (plane_state == NULL)
2092                 return;
2093
2094         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2095
2096         // Call Helper to track VMID use
2097         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2098
2099         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2100                         pipe_ctx->plane_res.hubp,
2101                         &plane_state->address,
2102                         plane_state->flip_immediate);
2103
2104         plane_state->status.requested_address = plane_state->address;
2105
2106         if (plane_state->flip_immediate)
2107                 plane_state->status.current_address = plane_state->address;
2108
2109         if (addr_patched)
2110                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2111 }
2112
2113 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2114                 struct dc_link_settings *link_settings)
2115 {
2116         struct encoder_unblank_param params = { { 0 } };
2117         struct dc_stream_state *stream = pipe_ctx->stream;
2118         struct dc_link *link = stream->link;
2119         struct dce_hwseq *hws = link->dc->hwseq;
2120         struct pipe_ctx *odm_pipe;
2121
2122         params.opp_cnt = 1;
2123         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2124                 params.opp_cnt++;
2125         }
2126         /* only 3 items below are used by unblank */
2127         params.timing = pipe_ctx->stream->timing;
2128
2129         params.link_settings.link_rate = link_settings->link_rate;
2130
2131         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2132                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2133                         params.timing.pix_clk_100hz /= 2;
2134                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2135                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2136                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
2137         }
2138
2139         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2140                 hws->funcs.edp_backlight_control(link, true);
2141         }
2142 }
2143
2144 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2145 {
2146         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2147         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2148
2149         if (start_line < 0)
2150                 start_line = 0;
2151
2152         if (tg->funcs->setup_vertical_interrupt2)
2153                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2154 }
2155
2156 static void dcn20_reset_back_end_for_pipe(
2157                 struct dc *dc,
2158                 struct pipe_ctx *pipe_ctx,
2159                 struct dc_state *context)
2160 {
2161         int i;
2162         struct dc_link *link;
2163         DC_LOGGER_INIT(dc->ctx->logger);
2164         if (pipe_ctx->stream_res.stream_enc == NULL) {
2165                 pipe_ctx->stream = NULL;
2166                 return;
2167         }
2168
2169         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2170                 link = pipe_ctx->stream->link;
2171                 /* DPMS may already disable or */
2172                 /* dpms_off status is incorrect due to fastboot
2173                  * feature. When system resume from S4 with second
2174                  * screen only, the dpms_off would be true but
2175                  * VBIOS lit up eDP, so check link status too.
2176                  */
2177                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2178                         core_link_disable_stream(pipe_ctx);
2179                 else if (pipe_ctx->stream_res.audio)
2180                         dc->hwss.disable_audio_stream(pipe_ctx);
2181
2182                 /* free acquired resources */
2183                 if (pipe_ctx->stream_res.audio) {
2184                         /*disable az_endpoint*/
2185                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2186
2187                         /*free audio*/
2188                         if (dc->caps.dynamic_audio == true) {
2189                                 /*we have to dynamic arbitrate the audio endpoints*/
2190                                 /*we free the resource, need reset is_audio_acquired*/
2191                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2192                                                 pipe_ctx->stream_res.audio, false);
2193                                 pipe_ctx->stream_res.audio = NULL;
2194                         }
2195                 }
2196         }
2197         else if (pipe_ctx->stream_res.dsc) {
2198                 dp_set_dsc_enable(pipe_ctx, false);
2199         }
2200
2201         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2202          * back end share by all pipes and will be disable only when disable
2203          * parent pipe.
2204          */
2205         if (pipe_ctx->top_pipe == NULL) {
2206
2207                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2208
2209                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2210
2211                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2212                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2213                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2214                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2215
2216                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2217                         pipe_ctx->stream_res.tg->funcs->set_drr(
2218                                         pipe_ctx->stream_res.tg, NULL);
2219         }
2220
2221         for (i = 0; i < dc->res_pool->pipe_count; i++)
2222                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2223                         break;
2224
2225         if (i == dc->res_pool->pipe_count)
2226                 return;
2227
2228         pipe_ctx->stream = NULL;
2229         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2230                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2231 }
2232
2233 void dcn20_reset_hw_ctx_wrap(
2234                 struct dc *dc,
2235                 struct dc_state *context)
2236 {
2237         int i;
2238         struct dce_hwseq *hws = dc->hwseq;
2239
2240         /* Reset Back End*/
2241         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2242                 struct pipe_ctx *pipe_ctx_old =
2243                         &dc->current_state->res_ctx.pipe_ctx[i];
2244                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2245
2246                 if (!pipe_ctx_old->stream)
2247                         continue;
2248
2249                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2250                         continue;
2251
2252                 if (!pipe_ctx->stream ||
2253                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2254                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2255
2256                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2257                         if (hws->funcs.enable_stream_gating)
2258                                 hws->funcs.enable_stream_gating(dc, pipe_ctx);
2259                         if (old_clk)
2260                                 old_clk->funcs->cs_power_down(old_clk);
2261                 }
2262         }
2263 }
2264
2265 void dcn20_get_mpctree_visual_confirm_color(
2266                 struct pipe_ctx *pipe_ctx,
2267                 struct tg_color *color)
2268 {
2269         const struct tg_color pipe_colors[6] = {
2270                         {MAX_TG_COLOR_VALUE, 0, 0}, // red
2271                         {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, // orange
2272                         {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, // yellow
2273                         {0, MAX_TG_COLOR_VALUE, 0}, // green
2274                         {0, 0, MAX_TG_COLOR_VALUE}, // blue
2275                         {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
2276         };
2277
2278         struct pipe_ctx *top_pipe = pipe_ctx;
2279
2280         while (top_pipe->top_pipe) {
2281                 top_pipe = top_pipe->top_pipe;
2282         }
2283
2284         *color = pipe_colors[top_pipe->pipe_idx];
2285 }
2286
2287 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2288 {
2289         struct dce_hwseq *hws = dc->hwseq;
2290         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2291         struct mpcc_blnd_cfg blnd_cfg = { {0} };
2292         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2293         int mpcc_id;
2294         struct mpcc *new_mpcc;
2295         struct mpc *mpc = dc->res_pool->mpc;
2296         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2297
2298         // input to MPCC is always RGB, by default leave black_color at 0
2299         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2300                 hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
2301         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2302                 hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
2303         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
2304                 dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
2305         }
2306
2307         if (per_pixel_alpha)
2308                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2309         else
2310                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2311
2312         blnd_cfg.overlap_only = false;
2313         blnd_cfg.global_gain = 0xff;
2314
2315         if (pipe_ctx->plane_state->global_alpha)
2316                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2317         else
2318                 blnd_cfg.global_alpha = 0xff;
2319
2320         blnd_cfg.background_color_bpc = 4;
2321         blnd_cfg.bottom_gain_mode = 0;
2322         blnd_cfg.top_gain = 0x1f000;
2323         blnd_cfg.bottom_inside_gain = 0x1f000;
2324         blnd_cfg.bottom_outside_gain = 0x1f000;
2325         blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2326         if (pipe_ctx->plane_state->format
2327                         == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2328                 blnd_cfg.pre_multiplied_alpha = false;
2329
2330         /*
2331          * TODO: remove hack
2332          * Note: currently there is a bug in init_hw such that
2333          * on resume from hibernate, BIOS sets up MPCC0, and
2334          * we do mpcc_remove but the mpcc cannot go to idle
2335          * after remove. This cause us to pick mpcc1 here,
2336          * which causes a pstate hang for yet unknown reason.
2337          */
2338         mpcc_id = hubp->inst;
2339
2340         /* If there is no full update, don't need to touch MPC tree*/
2341         if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2342                 !pipe_ctx->update_flags.bits.mpcc) {
2343                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2344                 return;
2345         }
2346
2347         /* check if this MPCC is already being used */
2348         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2349         /* remove MPCC if being used */
2350         if (new_mpcc != NULL)
2351                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2352         else
2353                 if (dc->debug.sanity_checks)
2354                         mpc->funcs->assert_mpcc_idle_before_connect(
2355                                         dc->res_pool->mpc, mpcc_id);
2356
2357         /* Call MPC to insert new plane */
2358         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2359                         mpc_tree_params,
2360                         &blnd_cfg,
2361                         NULL,
2362                         NULL,
2363                         hubp->inst,
2364                         mpcc_id);
2365
2366         ASSERT(new_mpcc != NULL);
2367         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2368         hubp->mpcc_id = mpcc_id;
2369 }
2370
2371 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2372 {
2373         enum dc_lane_count lane_count =
2374                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2375
2376         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2377         struct dc_link *link = pipe_ctx->stream->link;
2378
2379         uint32_t active_total_with_borders;
2380         uint32_t early_control = 0;
2381         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2382
2383         /* For MST, there are multiply stream go to only one link.
2384          * connect DIG back_end to front_end while enable_stream and
2385          * disconnect them during disable_stream
2386          * BY this, it is logic clean to separate stream and link
2387          */
2388         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2389                                                     pipe_ctx->stream_res.stream_enc->id, true);
2390
2391         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2392                 if (link->dc->hwss.program_dmdata_engine)
2393                         link->dc->hwss.program_dmdata_engine(pipe_ctx);
2394         }
2395
2396         link->dc->hwss.update_info_frame(pipe_ctx);
2397
2398         /* enable early control to avoid corruption on DP monitor*/
2399         active_total_with_borders =
2400                         timing->h_addressable
2401                                 + timing->h_border_left
2402                                 + timing->h_border_right;
2403
2404         if (lane_count != 0)
2405                 early_control = active_total_with_borders % lane_count;
2406
2407         if (early_control == 0)
2408                 early_control = lane_count;
2409
2410         tg->funcs->set_early_control(tg, early_control);
2411
2412         /* enable audio only within mode set */
2413         if (pipe_ctx->stream_res.audio != NULL) {
2414                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2415                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2416         }
2417 }
2418
2419 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2420 {
2421         struct dc_stream_state    *stream     = pipe_ctx->stream;
2422         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2423         bool                       enable     = false;
2424         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2425         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2426                                                         ? dmdata_dp
2427                                                         : dmdata_hdmi;
2428
2429         /* if using dynamic meta, don't set up generic infopackets */
2430         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2431                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2432                 enable = true;
2433         }
2434
2435         if (!hubp)
2436                 return;
2437
2438         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2439                 return;
2440
2441         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2442                                                 hubp->inst, mode);
2443 }
2444
2445 void dcn20_fpga_init_hw(struct dc *dc)
2446 {
2447         int i, j;
2448         struct dce_hwseq *hws = dc->hwseq;
2449         struct resource_pool *res_pool = dc->res_pool;
2450         struct dc_state  *context = dc->current_state;
2451
2452         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2453                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2454
2455         // Initialize the dccg
2456         if (res_pool->dccg->funcs->dccg_init)
2457                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2458
2459         //Enable ability to power gate / don't force power on permanently
2460         hws->funcs.enable_power_gating_plane(hws, true);
2461
2462         // Specific to FPGA dccg and registers
2463         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2464         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2465
2466         hws->funcs.dccg_init(hws);
2467
2468         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2469         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2470         if (REG(REFCLK_CNTL))
2471                 REG_WRITE(REFCLK_CNTL, 0);
2472         //
2473
2474
2475         /* Blank pixel data with OPP DPG */
2476         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2477                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2478
2479                 if (tg->funcs->is_tg_enabled(tg))
2480                         dcn20_init_blank(dc, tg);
2481         }
2482
2483         for (i = 0; i < res_pool->timing_generator_count; i++) {
2484                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2485
2486                 if (tg->funcs->is_tg_enabled(tg))
2487                         tg->funcs->lock(tg);
2488         }
2489
2490         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2491                 struct dpp *dpp = res_pool->dpps[i];
2492
2493                 dpp->funcs->dpp_reset(dpp);
2494         }
2495
2496         /* Reset all MPCC muxes */
2497         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2498
2499         /* initialize OPP mpc_tree parameter */
2500         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2501                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2502                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2503                 for (j = 0; j < MAX_PIPES; j++)
2504                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2505         }
2506
2507         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2508                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2509                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2510                 struct hubp *hubp = dc->res_pool->hubps[i];
2511                 struct dpp *dpp = dc->res_pool->dpps[i];
2512
2513                 pipe_ctx->stream_res.tg = tg;
2514                 pipe_ctx->pipe_idx = i;
2515
2516                 pipe_ctx->plane_res.hubp = hubp;
2517                 pipe_ctx->plane_res.dpp = dpp;
2518                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2519                 hubp->mpcc_id = dpp->inst;
2520                 hubp->opp_id = OPP_ID_INVALID;
2521                 hubp->power_gated = false;
2522                 pipe_ctx->stream_res.opp = NULL;
2523
2524                 hubp->funcs->hubp_init(hubp);
2525
2526                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2527                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2528                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2529                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2530                 /*to do*/
2531                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2532         }
2533
2534         /* initialize DWB pointer to MCIF_WB */
2535         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2536                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2537
2538         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2539                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2540
2541                 if (tg->funcs->is_tg_enabled(tg))
2542                         tg->funcs->unlock(tg);
2543         }
2544
2545         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2546                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2547
2548                 dc->hwss.disable_plane(dc, pipe_ctx);
2549
2550                 pipe_ctx->stream_res.tg = NULL;
2551                 pipe_ctx->plane_res.hubp = NULL;
2552         }
2553
2554         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2555                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2556
2557                 tg->funcs->tg_init(tg);
2558         }
2559 }
2560 #ifndef TRIM_FSFT
2561 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2562                 struct dc_crtc_timing *timing,
2563                 unsigned int max_input_rate_in_khz)
2564 {
2565         unsigned int old_v_front_porch;
2566         unsigned int old_v_total;
2567         unsigned int max_input_rate_in_100hz;
2568         unsigned long long new_v_total;
2569
2570         max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2571         if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2572                 return false;
2573
2574         old_v_total = timing->v_total;
2575         old_v_front_porch = timing->v_front_porch;
2576
2577         timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2578         timing->pix_clk_100hz = max_input_rate_in_100hz;
2579
2580         new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2581
2582         timing->v_total = new_v_total;
2583         timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2584         return true;
2585 }
2586 #endif
2587
2588 void dcn20_set_disp_pattern_generator(const struct dc *dc,
2589                 struct pipe_ctx *pipe_ctx,
2590                 enum controller_dp_test_pattern test_pattern,
2591                 enum controller_dp_color_space color_space,
2592                 enum dc_color_depth color_depth,
2593                 const struct tg_color *solid_color,
2594                 int width, int height, int offset)
2595 {
2596         pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2597                         color_space, color_depth, solid_color, width, height, offset);
2598 }