drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c

   1 /*
   2  * Copyright 2012-2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dcn20_hubp.h"
  27
  28 #include "dm_services.h"
  29 #include "dce_calcs.h"
  30 #include "reg_helper.h"
  31 #include "basics/conversion.h"
  32
  33 #define DC_LOGGER_INIT(logger)
  34
  35 #define REG(reg)\
  36         hubp2->hubp_regs->reg
  37
  38 #define CTX \
  39         hubp2->base.ctx
  40
  41 #undef FN
  42 #define FN(reg_name, field_name) \
  43         hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
  44
  45 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
  46                 struct vm_system_aperture_param *apt)
  47 {
  48         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
  49
  50         PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
  51         PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
  52         PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
  53
  54         // The format of default addr is 48:12 of the 48 bit addr
  55         mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
  56
  57         // The format of high/low are 48:18 of the 48 bit addr
  58         mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
  59         mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
  60
  61         REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
  62                 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
  63                 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
  64
  65         REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
  66                         DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
  67
  68         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
  69                         MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
  70
  71         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
  72                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
  73
  74         REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
  75                         ENABLE_L1_TLB, 1,
  76                         SYSTEM_ACCESS_MODE, 0x3);
  77 }
  78
  79 void hubp2_program_deadline(
  80                 struct hubp *hubp,
  81                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
  82                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
  83 {
  84         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
  85
  86         /* DLG - Per hubp */
  87         REG_SET_2(BLANK_OFFSET_0, 0,
  88                 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
  89                 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
  90
  91         REG_SET(BLANK_OFFSET_1, 0,
  92                 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
  93
  94         REG_SET(DST_DIMENSIONS, 0,
  95                 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
  96
  97         REG_SET_2(DST_AFTER_SCALER, 0,
  98                 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
  99                 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
 100
 101         REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
 102                 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
 103
 104         /* DLG - Per luma/chroma */
 105         REG_SET(VBLANK_PARAMETERS_1, 0,
 106                 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
 107
 108         if (REG(NOM_PARAMETERS_0))
 109                 REG_SET(NOM_PARAMETERS_0, 0,
 110                         DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
 111
 112         if (REG(NOM_PARAMETERS_1))
 113                 REG_SET(NOM_PARAMETERS_1, 0,
 114                         REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
 115
 116         REG_SET(NOM_PARAMETERS_4, 0,
 117                 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
 118
 119         REG_SET(NOM_PARAMETERS_5, 0,
 120                 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
 121
 122         REG_SET_2(PER_LINE_DELIVERY, 0,
 123                 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
 124                 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
 125
 126         REG_SET(VBLANK_PARAMETERS_2, 0,
 127                 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
 128
 129         if (REG(NOM_PARAMETERS_2))
 130                 REG_SET(NOM_PARAMETERS_2, 0,
 131                         DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
 132
 133         if (REG(NOM_PARAMETERS_3))
 134                 REG_SET(NOM_PARAMETERS_3, 0,
 135                         REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
 136
 137         REG_SET(NOM_PARAMETERS_6, 0,
 138                 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
 139
 140         REG_SET(NOM_PARAMETERS_7, 0,
 141                 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
 142
 143         /* TTU - per hubp */
 144         REG_SET_2(DCN_TTU_QOS_WM, 0,
 145                 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
 146                 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
 147
 148         /* TTU - per luma/chroma */
 149         /* Assumed surf0 is luma and 1 is chroma */
 150
 151         REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
 152                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
 153                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
 154                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
 155
 156         REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
 157                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
 158                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
 159                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
 160
 161         REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
 162                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
 163                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
 164                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
 165
 166         REG_SET(FLIP_PARAMETERS_1, 0,
 167                 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
 168 }
 169
 170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
 171                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 172 {
 173         uint32_t value = 0;
 174         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 175         /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */
 176         REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
 177         /*
 178         if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
 179         <= OTG_V_BLANK_END
 180                 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1
 181         else
 182                 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0
 183         */
 184         if (pipe_dest->htotal != 0) {
 185                 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
 186                         + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
 187                         value = 1;
 188                 } else
 189                         value = 0;
 190         }
 191
 192         REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
 193 }
 194
 195 static void hubp2_program_requestor(struct hubp *hubp,
 196                                     struct _vcs_dpi_display_rq_regs_st *rq_regs)
 197 {
 198         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 199
 200         REG_UPDATE(HUBPRET_CONTROL,
 201                         DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
 202         REG_SET_4(DCN_EXPANSION_MODE, 0,
 203                         DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
 204                         PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
 205                         MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
 206                         CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
 207         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
 208                 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
 209                 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
 210                 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
 211                 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
 212                 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
 213                 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
 214                 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
 215                 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
 216         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
 217                 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
 218                 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
 219                 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
 220                 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
 221                 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
 222                 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
 223                 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
 224                 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
 225 }
 226
 227 static void hubp2_setup(
 228                 struct hubp *hubp,
 229                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 230                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
 231                 struct _vcs_dpi_display_rq_regs_st *rq_regs,
 232                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 233 {
 234         /* otg is locked when this func is called. Register are double buffered.
 235          * disable the requestors is not needed
 236          */
 237
 238         hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
 239         hubp2_program_requestor(hubp, rq_regs);
 240         hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
 241
 242 }
 243
 244 void hubp2_setup_interdependent(
 245                 struct hubp *hubp,
 246                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 247                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
 248 {
 249         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 250
 251         REG_SET_2(PREFETCH_SETTINGS, 0,
 252                         DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
 253                         VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
 254
 255         REG_SET(PREFETCH_SETTINGS_C, 0,
 256                         VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
 257
 258         REG_SET_2(VBLANK_PARAMETERS_0, 0,
 259                 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
 260                 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
 261
 262         REG_SET_2(FLIP_PARAMETERS_0, 0,
 263                 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,
 264                 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
 265
 266         REG_SET(VBLANK_PARAMETERS_3, 0,
 267                 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
 268
 269         REG_SET(VBLANK_PARAMETERS_4, 0,
 270                 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
 271
 272         REG_SET(FLIP_PARAMETERS_2, 0,
 273                 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);
 274
 275         REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
 276                 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
 277                 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
 278
 279         REG_SET(DCN_SURF0_TTU_CNTL1, 0,
 280                 REFCYC_PER_REQ_DELIVERY_PRE,
 281                 ttu_attr->refcyc_per_req_delivery_pre_l);
 282         REG_SET(DCN_SURF1_TTU_CNTL1, 0,
 283                 REFCYC_PER_REQ_DELIVERY_PRE,
 284                 ttu_attr->refcyc_per_req_delivery_pre_c);
 285         REG_SET(DCN_CUR0_TTU_CNTL1, 0,
 286                 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
 287         REG_SET(DCN_CUR1_TTU_CNTL1, 0,
 288                 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);
 289
 290         REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
 291                 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
 292                 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
 293 }
 294
 295 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used:
 296  *      NUM_BANKS
 297  *      NUM_SE
 298  *      NUM_RB_PER_SE
 299  *      RB_ALIGNED
 300  * Other things can be defaulted, since they never change:
 301  *      PIPE_ALIGNED = 0
 302  *      META_LINEAR = 0
 303  * In GFX10, only these apply:
 304  *      PIPE_INTERLEAVE
 305  *      NUM_PIPES
 306  *      MAX_COMPRESSED_FRAGS
 307  *      SW_MODE
 308  */
 309 static void hubp2_program_tiling(
 310         struct dcn20_hubp *hubp2,
 311         const union dc_tiling_info *info,
 312         const enum surface_pixel_format pixel_format)
 313 {
 314         REG_UPDATE_3(DCSURF_ADDR_CONFIG,
 315                         NUM_PIPES, log_2(info->gfx9.num_pipes),
 316                         PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
 317                         MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
 318
 319         REG_UPDATE_4(DCSURF_TILING_CONFIG,
 320                         SW_MODE, info->gfx9.swizzle,
 321                         META_LINEAR, 0,
 322                         RB_ALIGNED, 0,
 323                         PIPE_ALIGNED, 0);
 324 }
 325
 326 void hubp2_program_size(
 327         struct hubp *hubp,
 328         enum surface_pixel_format format,
 329         const struct plane_size *plane_size,
 330         struct dc_plane_dcc_param *dcc)
 331 {
 332         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 333         uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
 334         bool use_pitch_c = false;
 335
 336         /* Program data and meta surface pitch (calculation from addrlib)
 337          * 444 or 420 luma
 338          */
 339         use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
 340                 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
 341         use_pitch_c = use_pitch_c
 342                 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
 343         if (use_pitch_c) {
 344                 ASSERT(plane_size->chroma_pitch != 0);
 345                 /* Chroma pitch zero can cause system hang! */
 346
 347                 pitch = plane_size->surface_pitch - 1;
 348                 meta_pitch = dcc->meta_pitch - 1;
 349                 pitch_c = plane_size->chroma_pitch - 1;
 350                 meta_pitch_c = dcc->meta_pitch_c - 1;
 351         } else {
 352                 pitch = plane_size->surface_pitch - 1;
 353                 meta_pitch = dcc->meta_pitch - 1;
 354                 pitch_c = 0;
 355                 meta_pitch_c = 0;
 356         }
 357
 358         if (!dcc->enable) {
 359                 meta_pitch = 0;
 360                 meta_pitch_c = 0;
 361         }
 362
 363         REG_UPDATE_2(DCSURF_SURFACE_PITCH,
 364                         PITCH, pitch, META_PITCH, meta_pitch);
 365
 366         use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
 367         use_pitch_c = use_pitch_c
 368                 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
 369         if (use_pitch_c)
 370                 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
 371                         PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
 372 }
 373
 374 void hubp2_program_rotation(
 375         struct hubp *hubp,
 376         enum dc_rotation_angle rotation,
 377         bool horizontal_mirror)
 378 {
 379         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 380         uint32_t mirror;
 381
 382
 383         if (horizontal_mirror)
 384                 mirror = 1;
 385         else
 386                 mirror = 0;
 387
 388         /* Program rotation angle and horz mirror - no mirror */
 389         if (rotation == ROTATION_ANGLE_0)
 390                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 391                                 ROTATION_ANGLE, 0,
 392                                 H_MIRROR_EN, mirror);
 393         else if (rotation == ROTATION_ANGLE_90)
 394                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 395                                 ROTATION_ANGLE, 1,
 396                                 H_MIRROR_EN, mirror);
 397         else if (rotation == ROTATION_ANGLE_180)
 398                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 399                                 ROTATION_ANGLE, 2,
 400                                 H_MIRROR_EN, mirror);
 401         else if (rotation == ROTATION_ANGLE_270)
 402                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 403                                 ROTATION_ANGLE, 3,
 404                                 H_MIRROR_EN, mirror);
 405 }
 406
 407 void hubp2_dcc_control(struct hubp *hubp, bool enable,
 408                 enum hubp_ind_block_size independent_64b_blks)
 409 {
 410         uint32_t dcc_en = enable ? 1 : 0;
 411         uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
 412         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 413
 414         REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 415                         PRIMARY_SURFACE_DCC_EN, dcc_en,
 416                         PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
 417                         SECONDARY_SURFACE_DCC_EN, dcc_en,
 418                         SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 419 }
 420
 421 void hubp2_program_pixel_format(
 422         struct hubp *hubp,
 423         enum surface_pixel_format format)
 424 {
 425         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 426         uint32_t red_bar = 3;
 427         uint32_t blue_bar = 2;
 428
 429         /* swap for ABGR format */
 430         if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
 431                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
 432                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
 433                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
 434                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 435                 red_bar = 2;
 436                 blue_bar = 3;
 437         }
 438
 439         REG_UPDATE_2(HUBPRET_CONTROL,
 440                         CROSSBAR_SRC_CB_B, blue_bar,
 441                         CROSSBAR_SRC_CR_R, red_bar);
 442
 443         /* Mapping is same as ipp programming (cnvc) */
 444
 445         switch (format) {
 446         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 447                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 448                                 SURFACE_PIXEL_FORMAT, 1);
 449                 break;
 450         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 451                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 452                                 SURFACE_PIXEL_FORMAT, 3);
 453                 break;
 454         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 455         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 456                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 457                                 SURFACE_PIXEL_FORMAT, 8);
 458                 break;
 459         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 460         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 461         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 462                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 463                                 SURFACE_PIXEL_FORMAT, 10);
 464                 break;
 465         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 466                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 467                                 SURFACE_PIXEL_FORMAT, 22);
 468                 break;
 469         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
 470                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 471                                 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
 472                 break;
 473         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 474         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
 475                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 476                                 SURFACE_PIXEL_FORMAT, 24);
 477                 break;
 478
 479         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 480                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 481                                 SURFACE_PIXEL_FORMAT, 65);
 482                 break;
 483         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 484                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 485                                 SURFACE_PIXEL_FORMAT, 64);
 486                 break;
 487         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 488                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 489                                 SURFACE_PIXEL_FORMAT, 67);
 490                 break;
 491         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 492                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 493                                 SURFACE_PIXEL_FORMAT, 66);
 494                 break;
 495         case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
 496                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 497                                 SURFACE_PIXEL_FORMAT, 12);
 498                 break;
 499         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
 500                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 501                                 SURFACE_PIXEL_FORMAT, 112);
 502                 break;
 503         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 504                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 505                                 SURFACE_PIXEL_FORMAT, 113);
 506                 break;
 507         case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
 508                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 509                                 SURFACE_PIXEL_FORMAT, 114);
 510                 break;
 511         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 512                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 513                                 SURFACE_PIXEL_FORMAT, 118);
 514                 break;
 515         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
 516                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 517                                 SURFACE_PIXEL_FORMAT, 119);
 518                 break;
 519         case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 520                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 521                                 SURFACE_PIXEL_FORMAT, 116,
 522                                 ALPHA_PLANE_EN, 0);
 523                 break;
 524         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 525                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 526                                 SURFACE_PIXEL_FORMAT, 116,
 527                                 ALPHA_PLANE_EN, 1);
 528                 break;
 529         default:
 530                 BREAK_TO_DEBUGGER();
 531                 break;
 532         }
 533
 534         /* don't see the need of program the xbar in DCN 1.0 */
 535 }
 536
 537 void hubp2_program_surface_config(
 538         struct hubp *hubp,
 539         enum surface_pixel_format format,
 540         union dc_tiling_info *tiling_info,
 541         struct plane_size *plane_size,
 542         enum dc_rotation_angle rotation,
 543         struct dc_plane_dcc_param *dcc,
 544         bool horizontal_mirror,
 545         unsigned int compat_level)
 546 {
 547         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 548
 549         hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
 550         hubp2_program_tiling(hubp2, tiling_info, format);
 551         hubp2_program_size(hubp, format, plane_size, dcc);
 552         hubp2_program_rotation(hubp, rotation, horizontal_mirror);
 553         hubp2_program_pixel_format(hubp, format);
 554 }
 555
 556 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
 557         unsigned int cursor_width,
 558         enum dc_cursor_color_format cursor_mode)
 559 {
 560         enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 561
 562         if (cursor_mode == CURSOR_MODE_MONO)
 563                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 564         else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND ||
 565                  cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
 566                  cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
 567                 if (cursor_width >= 1   && cursor_width <= 32)
 568                         line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 569                 else if (cursor_width >= 33  && cursor_width <= 64)
 570                         line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
 571                 else if (cursor_width >= 65  && cursor_width <= 128)
 572                         line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
 573                 else if (cursor_width >= 129 && cursor_width <= 256)
 574                         line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
 575         } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED ||
 576                    cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) {
 577                 if (cursor_width >= 1   && cursor_width <= 16)
 578                         line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 579                 else if (cursor_width >= 17  && cursor_width <= 32)
 580                         line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
 581                 else if (cursor_width >= 33  && cursor_width <= 64)
 582                         line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
 583                 else if (cursor_width >= 65 && cursor_width <= 128)
 584                         line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
 585                 else if (cursor_width >= 129 && cursor_width <= 256)
 586                         line_per_chunk = CURSOR_LINE_PER_CHUNK_1;
 587         }
 588
 589         return line_per_chunk;
 590 }
 591
 592 void hubp2_cursor_set_attributes(
 593                 struct hubp *hubp,
 594                 const struct dc_cursor_attributes *attr)
 595 {
 596         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 597         enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
 598         enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
 599                         attr->width, attr->color_format);
 600
 601         hubp->curs_attr = *attr;
 602
 603         REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
 604                         CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
 605         REG_UPDATE(CURSOR_SURFACE_ADDRESS,
 606                         CURSOR_SURFACE_ADDRESS, attr->address.low_part);
 607
 608         REG_UPDATE_2(CURSOR_SIZE,
 609                         CURSOR_WIDTH, attr->width,
 610                         CURSOR_HEIGHT, attr->height);
 611
 612         REG_UPDATE_4(CURSOR_CONTROL,
 613                         CURSOR_MODE, attr->color_format,
 614                         CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
 615                         CURSOR_PITCH, hw_pitch,
 616                         CURSOR_LINES_PER_CHUNK, lpc);
 617
 618         REG_SET_2(CURSOR_SETTINGS, 0,
 619                         /* no shift of the cursor HDL schedule */
 620                         CURSOR0_DST_Y_OFFSET, 0,
 621                          /* used to shift the cursor chunk request deadline */
 622                         CURSOR0_CHUNK_HDL_ADJUST, 3);
 623 }
 624
 625 void hubp2_dmdata_set_attributes(
 626                 struct hubp *hubp,
 627                 const struct dc_dmdata_attributes *attr)
 628 {
 629         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 630
 631         if (attr->dmdata_mode == DMDATA_HW_MODE) {
 632                 /* set to HW mode */
 633                 REG_UPDATE(DMDATA_CNTL,
 634                                 DMDATA_MODE, 1);
 635
 636                 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
 637                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
 638
 639                 /* toggle DMDATA_UPDATED and set repeat and size */
 640                 REG_UPDATE(DMDATA_CNTL,
 641                                 DMDATA_UPDATED, 0);
 642                 REG_UPDATE_3(DMDATA_CNTL,
 643                                 DMDATA_UPDATED, 1,
 644                                 DMDATA_REPEAT, attr->dmdata_repeat,
 645                                 DMDATA_SIZE, attr->dmdata_size);
 646
 647                 /* set DMDATA address */
 648                 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
 649                 REG_UPDATE(DMDATA_ADDRESS_HIGH,
 650                                 DMDATA_ADDRESS_HIGH, attr->address.high_part);
 651
 652                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
 653
 654         } else {
 655                 /* set to SW mode before loading data */
 656                 REG_SET(DMDATA_CNTL, 0,
 657                                 DMDATA_MODE, 0);
 658                 /* toggle DMDATA_SW_UPDATED to start loading sequence */
 659                 REG_UPDATE(DMDATA_SW_CNTL,
 660                                 DMDATA_SW_UPDATED, 0);
 661                 REG_UPDATE_3(DMDATA_SW_CNTL,
 662                                 DMDATA_SW_UPDATED, 1,
 663                                 DMDATA_SW_REPEAT, attr->dmdata_repeat,
 664                                 DMDATA_SW_SIZE, attr->dmdata_size);
 665                 /* load data into hubp dmdata buffer */
 666                 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);
 667         }
 668
 669         /* Note that DL_DELTA must be programmed if we want to use TTU mode */
 670         REG_SET_3(DMDATA_QOS_CNTL, 0,
 671                         DMDATA_QOS_MODE, attr->dmdata_qos_mode,
 672                         DMDATA_QOS_LEVEL, attr->dmdata_qos_level,
 673                         DMDATA_DL_DELTA, attr->dmdata_dl_delta);
 674 }
 675
 676 void hubp2_dmdata_load(
 677                 struct hubp *hubp,
 678                 uint32_t dmdata_sw_size,
 679                 const uint32_t *dmdata_sw_data)
 680 {
 681         int i;
 682         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 683
 684         /* load dmdata into HUBP buffer in SW mode */
 685         for (i = 0; i < dmdata_sw_size / 4; i++)
 686                 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
 687 }
 688
 689 bool hubp2_dmdata_status_done(struct hubp *hubp)
 690 {
 691         uint32_t status;
 692         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 693
 694         REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
 695         return (status == 1);
 696 }
 697
 698 bool hubp2_program_surface_flip_and_addr(
 699         struct hubp *hubp,
 700         const struct dc_plane_address *address,
 701         bool flip_immediate)
 702 {
 703         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 704
 705         //program flip type
 706         REG_UPDATE(DCSURF_FLIP_CONTROL,
 707                         SURFACE_FLIP_TYPE, flip_immediate);
 708
 709         // Program VMID reg
 710         REG_UPDATE(VMID_SETTINGS_0,
 711                         VMID, address->vmid);
 712
 713
 714         /* HW automatically latch rest of address register on write to
 715          * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
 716          *
 717          * program high first and then the low addr, order matters!
 718          */
 719         switch (address->type) {
 720         case PLN_ADDR_TYPE_GRAPHICS:
 721                 /* DCN1.0 does not support const color
 722                  * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
 723                  * base on address->grph.dcc_const_color
 724                  * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
 725                  * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
 726                  */
 727
 728                 if (address->grph.addr.quad_part == 0)
 729                         break;
 730
 731                 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
 732                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 733                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
 734
 735                 if (address->grph.meta_addr.quad_part != 0) {
 736                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 737                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 738                                         address->grph.meta_addr.high_part);
 739
 740                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 741                                         PRIMARY_META_SURFACE_ADDRESS,
 742                                         address->grph.meta_addr.low_part);
 743                 }
 744
 745                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 746                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 747                                 address->grph.addr.high_part);
 748
 749                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 750                                 PRIMARY_SURFACE_ADDRESS,
 751                                 address->grph.addr.low_part);
 752                 break;
 753         case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
 754                 if (address->video_progressive.luma_addr.quad_part == 0
 755                                 || address->video_progressive.chroma_addr.quad_part == 0)
 756                         break;
 757
 758                 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 759                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 760                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 761                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 762                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 763
 764                 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
 765                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
 766                                         PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
 767                                         address->video_progressive.chroma_meta_addr.high_part);
 768
 769                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
 770                                         PRIMARY_META_SURFACE_ADDRESS_C,
 771                                         address->video_progressive.chroma_meta_addr.low_part);
 772
 773                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 774                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 775                                         address->video_progressive.luma_meta_addr.high_part);
 776
 777                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 778                                         PRIMARY_META_SURFACE_ADDRESS,
 779                                         address->video_progressive.luma_meta_addr.low_part);
 780                 }
 781
 782                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
 783                                 PRIMARY_SURFACE_ADDRESS_HIGH_C,
 784                                 address->video_progressive.chroma_addr.high_part);
 785
 786                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
 787                                 PRIMARY_SURFACE_ADDRESS_C,
 788                                 address->video_progressive.chroma_addr.low_part);
 789
 790                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 791                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 792                                 address->video_progressive.luma_addr.high_part);
 793
 794                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 795                                 PRIMARY_SURFACE_ADDRESS,
 796                                 address->video_progressive.luma_addr.low_part);
 797                 break;
 798         case PLN_ADDR_TYPE_GRPH_STEREO:
 799                 if (address->grph_stereo.left_addr.quad_part == 0)
 800                         break;
 801                 if (address->grph_stereo.right_addr.quad_part == 0)
 802                         break;
 803
 804                 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
 805                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 806                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 807                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 808                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
 809                                 SECONDARY_SURFACE_TMZ, address->tmz_surface,
 810                                 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
 811                                 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
 812                                 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
 813
 814                 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 815
 816                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
 817                                         SECONDARY_META_SURFACE_ADDRESS_HIGH,
 818                                         address->grph_stereo.right_meta_addr.high_part);
 819
 820                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
 821                                         SECONDARY_META_SURFACE_ADDRESS,
 822                                         address->grph_stereo.right_meta_addr.low_part);
 823                 }
 824                 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
 825
 826                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 827                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 828                                         address->grph_stereo.left_meta_addr.high_part);
 829
 830                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 831                                         PRIMARY_META_SURFACE_ADDRESS,
 832                                         address->grph_stereo.left_meta_addr.low_part);
 833                 }
 834
 835                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
 836                                 SECONDARY_SURFACE_ADDRESS_HIGH,
 837                                 address->grph_stereo.right_addr.high_part);
 838
 839                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
 840                                 SECONDARY_SURFACE_ADDRESS,
 841                                 address->grph_stereo.right_addr.low_part);
 842
 843                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 844                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 845                                 address->grph_stereo.left_addr.high_part);
 846
 847                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 848                                 PRIMARY_SURFACE_ADDRESS,
 849                                 address->grph_stereo.left_addr.low_part);
 850                 break;
 851         default:
 852                 BREAK_TO_DEBUGGER();
 853                 break;
 854         }
 855
 856         hubp->request_address = *address;
 857
 858         return true;
 859 }
 860
 861 void hubp2_enable_triplebuffer(
 862         struct hubp *hubp,
 863         bool enable)
 864 {
 865         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 866         uint32_t triple_buffer_en = 0;
 867         bool tri_buffer_en;
 868
 869         REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
 870         tri_buffer_en = (triple_buffer_en == 1);
 871         if (tri_buffer_en != enable) {
 872                 REG_UPDATE(DCSURF_FLIP_CONTROL2,
 873                         SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);
 874         }
 875 }
 876
 877 bool hubp2_is_triplebuffer_enabled(
 878         struct hubp *hubp)
 879 {
 880         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 881         uint32_t triple_buffer_en = 0;
 882
 883         REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
 884
 885         return (bool)triple_buffer_en;
 886 }
 887
 888 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
 889 {
 890         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 891
 892         REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
 893 }
 894
 895 bool hubp2_is_flip_pending(struct hubp *hubp)
 896 {
 897         uint32_t flip_pending = 0;
 898         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 899         struct dc_plane_address earliest_inuse_address;
 900
 901         if (hubp && hubp->power_gated)
 902                 return false;
 903
 904         REG_GET(DCSURF_FLIP_CONTROL,
 905                         SURFACE_FLIP_PENDING, &flip_pending);
 906
 907         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
 908                         SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
 909
 910         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
 911                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
 912
 913         if (flip_pending)
 914                 return true;
 915
 916         if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
 917                 return true;
 918
 919         return false;
 920 }
 921
 922 void hubp2_set_blank(struct hubp *hubp, bool blank)
 923 {
 924         hubp2_set_blank_regs(hubp, blank);
 925
 926         if (blank) {
 927                 hubp->mpcc_id = 0xf;
 928                 hubp->opp_id = OPP_ID_INVALID;
 929         }
 930 }
 931
 932 void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
 933 {
 934         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 935         uint32_t blank_en = blank ? 1 : 0;
 936
 937         if (blank) {
 938                 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
 939
 940                 if (reg_val) {
 941                         /* init sequence workaround: in case HUBP is
 942                          * power gated, this wait would timeout.
 943                          *
 944                          * we just wrote reg_val to non-0, if it stay 0
 945                          * it means HUBP is gated
 946                          */
 947                         REG_WAIT(DCHUBP_CNTL,
 948                                         HUBP_NO_OUTSTANDING_REQ, 1,
 949                                         1, 100000);
 950                 }
 951         }
 952
 953         REG_UPDATE_2(DCHUBP_CNTL,
 954                         HUBP_BLANK_EN, blank_en,
 955                         HUBP_TTU_DISABLE, 0);
 956 }
 957
 958 void hubp2_cursor_set_position(
 959                 struct hubp *hubp,
 960                 const struct dc_cursor_position *pos,
 961                 const struct dc_cursor_mi_param *param)
 962 {
 963         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 964         int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
 965         int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
 966         int x_hotspot = pos->x_hotspot;
 967         int y_hotspot = pos->y_hotspot;
 968         int cursor_height = (int)hubp->curs_attr.height;
 969         int cursor_width = (int)hubp->curs_attr.width;
 970         uint32_t dst_x_offset;
 971         uint32_t cur_en = pos->enable ? 1 : 0;
 972
 973         hubp->curs_pos = *pos;
 974
 975         /*
 976          * Guard aganst cursor_set_position() from being called with invalid
 977          * attributes
 978          *
 979          * TODO: Look at combining cursor_set_position() and
 980          * cursor_set_attributes() into cursor_update()
 981          */
 982         if (hubp->curs_attr.address.quad_part == 0)
 983                 return;
 984
 985         // Rotated cursor width/height and hotspots tweaks for offset calculation
 986         if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
 987                 swap(cursor_height, cursor_width);
 988                 if (param->rotation == ROTATION_ANGLE_90) {
 989                         src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
 990                         src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
 991                 }
 992         } else if (param->rotation == ROTATION_ANGLE_180) {
 993                 src_x_offset = pos->x - param->viewport.x;
 994                 src_y_offset = pos->y - param->viewport.y;
 995         }
 996
 997         if (param->mirror) {
 998                 x_hotspot = param->viewport.width - x_hotspot;
 999                 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
1000         }
1001
1002         dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1003         dst_x_offset *= param->ref_clk_khz;
1004         dst_x_offset /= param->pixel_clk_khz;
1005
1006         ASSERT(param->h_scale_ratio.value);
1007
1008         if (param->h_scale_ratio.value)
1009                 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1010                                 dc_fixpt_from_int(dst_x_offset),
1011                                 param->h_scale_ratio));
1012
1013         if (src_x_offset >= (int)param->viewport.width)
1014                 cur_en = 0;  /* not visible beyond right edge*/
1015
1016         if (src_x_offset + cursor_width <= 0)
1017                 cur_en = 0;  /* not visible beyond left edge*/
1018
1019         if (src_y_offset >= (int)param->viewport.height)
1020                 cur_en = 0;  /* not visible beyond bottom edge*/
1021
1022         if (src_y_offset + cursor_height <= 0)
1023                 cur_en = 0;  /* not visible beyond top edge*/
1024
1025         if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1026                 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1027
1028         REG_UPDATE(CURSOR_CONTROL,
1029                         CURSOR_ENABLE, cur_en);
1030
1031         REG_SET_2(CURSOR_POSITION, 0,
1032                         CURSOR_X_POSITION, pos->x,
1033                         CURSOR_Y_POSITION, pos->y);
1034
1035         REG_SET_2(CURSOR_HOT_SPOT, 0,
1036                         CURSOR_HOT_SPOT_X, x_hotspot,
1037                         CURSOR_HOT_SPOT_Y, y_hotspot);
1038
1039         REG_SET(CURSOR_DST_OFFSET, 0,
1040                         CURSOR_DST_X_OFFSET, dst_x_offset);
1041         /* TODO Handle surface pixel formats other than 4:4:4 */
1042 }
1043
1044 void hubp2_clk_cntl(struct hubp *hubp, bool enable)
1045 {
1046         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1047         uint32_t clk_enable = enable ? 1 : 0;
1048
1049         REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1050 }
1051
1052 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1053 {
1054         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1055
1056         REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1057 }
1058
1059 void hubp2_clear_underflow(struct hubp *hubp)
1060 {
1061         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1062
1063         REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
1064 }
1065
1066 void hubp2_read_state_common(struct hubp *hubp)
1067 {
1068         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1069         struct dcn_hubp_state *s = &hubp2->state;
1070         struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
1071         struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
1072         struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1073
1074         /* Requester */
1075         REG_GET(HUBPRET_CONTROL,
1076                         DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
1077         REG_GET_4(DCN_EXPANSION_MODE,
1078                         DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
1079                         PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
1080                         MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
1081                         CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
1082
1083         REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
1084                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);
1085
1086         REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
1087                         MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);
1088
1089         /* DLG - Per hubp */
1090         REG_GET_2(BLANK_OFFSET_0,
1091                 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
1092                 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
1093
1094         REG_GET(BLANK_OFFSET_1,
1095                 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1096
1097         REG_GET(DST_DIMENSIONS,
1098                 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
1099
1100         REG_GET_2(DST_AFTER_SCALER,
1101                 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
1102                 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
1103
1104         if (REG(PREFETCH_SETTINS))
1105                 REG_GET_2(PREFETCH_SETTINS,
1106                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1107                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1108         else
1109                 REG_GET_2(PREFETCH_SETTINGS,
1110                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1111                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1112
1113         REG_GET_2(VBLANK_PARAMETERS_0,
1114                 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
1115                 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
1116
1117         REG_GET(REF_FREQ_TO_PIX_FREQ,
1118                 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
1119
1120         /* DLG - Per luma/chroma */
1121         REG_GET(VBLANK_PARAMETERS_1,
1122                 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
1123
1124         REG_GET(VBLANK_PARAMETERS_3,
1125                 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
1126
1127         if (REG(NOM_PARAMETERS_0))
1128                 REG_GET(NOM_PARAMETERS_0,
1129                         DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
1130
1131         if (REG(NOM_PARAMETERS_1))
1132                 REG_GET(NOM_PARAMETERS_1,
1133                         REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
1134
1135         REG_GET(NOM_PARAMETERS_4,
1136                 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
1137
1138         REG_GET(NOM_PARAMETERS_5,
1139                 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
1140
1141         REG_GET_2(PER_LINE_DELIVERY_PRE,
1142                 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
1143                 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
1144
1145         REG_GET_2(PER_LINE_DELIVERY,
1146                 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
1147                 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
1148
1149         if (REG(PREFETCH_SETTINS_C))
1150                 REG_GET(PREFETCH_SETTINS_C,
1151                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1152         else
1153                 REG_GET(PREFETCH_SETTINGS_C,
1154                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1155
1156         REG_GET(VBLANK_PARAMETERS_2,
1157                 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
1158
1159         REG_GET(VBLANK_PARAMETERS_4,
1160                 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
1161
1162         if (REG(NOM_PARAMETERS_2))
1163                 REG_GET(NOM_PARAMETERS_2,
1164                         DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
1165
1166         if (REG(NOM_PARAMETERS_3))
1167                 REG_GET(NOM_PARAMETERS_3,
1168                         REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
1169
1170         REG_GET(NOM_PARAMETERS_6,
1171                 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
1172
1173         REG_GET(NOM_PARAMETERS_7,
1174                 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
1175
1176         /* TTU - per hubp */
1177         REG_GET_2(DCN_TTU_QOS_WM,
1178                 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
1179                 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1180
1181         REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1182                 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1183                 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1184
1185         /* TTU - per luma/chroma */
1186         /* Assumed surf0 is luma and 1 is chroma */
1187
1188         REG_GET_3(DCN_SURF0_TTU_CNTL0,
1189                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1190                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1191                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1192
1193         REG_GET(DCN_SURF0_TTU_CNTL1,
1194                 REFCYC_PER_REQ_DELIVERY_PRE,
1195                 &ttu_attr->refcyc_per_req_delivery_pre_l);
1196
1197         REG_GET_3(DCN_SURF1_TTU_CNTL0,
1198                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1199                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1200                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1201
1202         REG_GET(DCN_SURF1_TTU_CNTL1,
1203                 REFCYC_PER_REQ_DELIVERY_PRE,
1204                 &ttu_attr->refcyc_per_req_delivery_pre_c);
1205
1206         /* Rest of hubp */
1207         REG_GET(DCSURF_SURFACE_CONFIG,
1208                         SURFACE_PIXEL_FORMAT, &s->pixel_format);
1209
1210         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1211                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1212
1213         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1214                         SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1215
1216         REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1217                         PRI_VIEWPORT_WIDTH, &s->viewport_width,
1218                         PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1219
1220         REG_GET_2(DCSURF_SURFACE_CONFIG,
1221                         ROTATION_ANGLE, &s->rotation_angle,
1222                         H_MIRROR_EN, &s->h_mirror_en);
1223
1224         REG_GET(DCSURF_TILING_CONFIG,
1225                         SW_MODE, &s->sw_mode);
1226
1227         REG_GET(DCSURF_SURFACE_CONTROL,
1228                         PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1229
1230         REG_GET_3(DCHUBP_CNTL,
1231                         HUBP_BLANK_EN, &s->blank_en,
1232                         HUBP_TTU_DISABLE, &s->ttu_disable,
1233                         HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1234
1235         REG_GET(HUBP_CLK_CNTL,
1236                         HUBP_CLOCK_ENABLE, &s->clock_en);
1237
1238         REG_GET(DCN_GLOBAL_TTU_CNTL,
1239                         MIN_TTU_VBLANK, &s->min_ttu_vblank);
1240
1241         REG_GET_2(DCN_TTU_QOS_WM,
1242                         QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1243                         QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1244
1245         REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1246                         PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1247
1248         REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1249                         PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1250
1251         REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1252                         PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1253
1254         REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1255                         PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1256 }
1257
1258 void hubp2_read_state(struct hubp *hubp)
1259 {
1260         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1261         struct dcn_hubp_state *s = &hubp2->state;
1262         struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1263
1264         hubp2_read_state_common(hubp);
1265
1266         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1267                 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1268                 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1269                 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1270                 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1271                 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1272                 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1273                 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1274                 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1275
1276         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1277                 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1278                 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1279                 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1280                 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1281                 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1282                 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1283                 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1284                 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1285
1286 }
1287
1288 static void hubp2_validate_dml_output(struct hubp *hubp,
1289                 struct dc_context *ctx,
1290                 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
1291                 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
1292                 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
1293 {
1294         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1295         struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
1296         struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
1297         struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
1298         DC_LOGGER_INIT(ctx->logger);
1299         DC_LOG_DEBUG("DML Validation | Running Validation");
1300
1301         /* Requestor Regs */
1302         REG_GET(HUBPRET_CONTROL,
1303                 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
1304         REG_GET_4(DCN_EXPANSION_MODE,
1305                 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
1306                 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
1307                 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
1308                 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
1309         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1310                 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
1311                 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
1312                 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
1313                 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
1314                 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
1315                 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
1316                 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
1317                 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
1318         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1319                 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
1320                 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
1321                 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
1322                 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
1323                 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
1324                 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
1325                 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
1326                 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
1327
1328         if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
1329                 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1330                                 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
1331         if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
1332                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1333                                 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
1334         if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
1335                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1336                                 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
1337         if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
1338                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1339                                 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
1340         if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
1341                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1342                                 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
1343
1344         if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
1345                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
1346                                 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
1347         if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
1348                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1349                                 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
1350         if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
1351                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1352                                 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
1353         if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
1354                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1355                                 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
1356         if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
1357                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1358                                 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
1359         if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
1360                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1361                                 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
1362         if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
1363                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
1364                                 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
1365         if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
1366                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
1367                                 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
1368
1369         if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
1370                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1371                                 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
1372         if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
1373                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1374                                 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
1375         if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
1376                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1377                                 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
1378         if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
1379                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1380                                 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
1381         if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
1382                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1383                                 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
1384         if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
1385                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1386                                 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
1387         if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
1388                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
1389                                 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
1390         if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
1391                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
1392                                 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
1393
1394         /* DLG - Per hubp */
1395         REG_GET_2(BLANK_OFFSET_0,
1396                 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
1397                 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
1398         REG_GET(BLANK_OFFSET_1,
1399                 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1400         REG_GET(DST_DIMENSIONS,
1401                 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
1402         REG_GET_2(DST_AFTER_SCALER,
1403                 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
1404                 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
1405         REG_GET(REF_FREQ_TO_PIX_FREQ,
1406                 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
1407
1408         if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
1409                 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
1410                                 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
1411         if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
1412                 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
1413                                 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
1414         if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1415                 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
1416                                 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
1417         if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
1418                 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
1419                                 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
1420         if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
1421                 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
1422                                 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
1423         if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
1424                 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
1425                                 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
1426         if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
1427                 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
1428                                 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
1429
1430         /* DLG - Per luma/chroma */
1431         REG_GET(VBLANK_PARAMETERS_1,
1432                 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
1433         if (REG(NOM_PARAMETERS_0))
1434                 REG_GET(NOM_PARAMETERS_0,
1435                         DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
1436         if (REG(NOM_PARAMETERS_1))
1437                 REG_GET(NOM_PARAMETERS_1,
1438                         REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
1439         REG_GET(NOM_PARAMETERS_4,
1440                 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
1441         REG_GET(NOM_PARAMETERS_5,
1442                 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
1443         REG_GET_2(PER_LINE_DELIVERY,
1444                 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
1445                 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
1446         REG_GET_2(PER_LINE_DELIVERY_PRE,
1447                 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
1448                 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
1449         REG_GET(VBLANK_PARAMETERS_2,
1450                 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
1451         if (REG(NOM_PARAMETERS_2))
1452                 REG_GET(NOM_PARAMETERS_2,
1453                         DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
1454         if (REG(NOM_PARAMETERS_3))
1455                 REG_GET(NOM_PARAMETERS_3,
1456                         REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
1457         REG_GET(NOM_PARAMETERS_6,
1458                 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
1459         REG_GET(NOM_PARAMETERS_7,
1460                 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
1461         REG_GET(VBLANK_PARAMETERS_3,
1462                         REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
1463         REG_GET(VBLANK_PARAMETERS_4,
1464                         REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
1465
1466         if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
1467                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
1468                                 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
1469         if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
1470                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
1471                                 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
1472         if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
1473                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
1474                                 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
1475         if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
1476                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
1477                                 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
1478         if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
1479                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
1480                                 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
1481         if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
1482                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
1483                                 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
1484         if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
1485                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
1486                                 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
1487         if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
1488                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
1489                                 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
1490         if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
1491                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
1492                                 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
1493         if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
1494                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
1495                                 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
1496         if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
1497                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
1498                                 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
1499         if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
1500                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
1501                                 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
1502         if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
1503                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
1504                                 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
1505         if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
1506                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
1507                                 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
1508         if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
1509                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
1510                                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
1511         if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
1512                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
1513                                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
1514
1515         /* TTU - per hubp */
1516         REG_GET_2(DCN_TTU_QOS_WM,
1517                 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
1518                 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1519
1520         if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
1521                 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
1522                                 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
1523         if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
1524                 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
1525                                 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
1526
1527         /* TTU - per luma/chroma */
1528         /* Assumed surf0 is luma and 1 is chroma */
1529         REG_GET_3(DCN_SURF0_TTU_CNTL0,
1530                 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
1531                 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
1532                 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
1533         REG_GET_3(DCN_SURF1_TTU_CNTL0,
1534                 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
1535                 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
1536                 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
1537         REG_GET_3(DCN_CUR0_TTU_CNTL0,
1538                 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
1539                 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
1540                 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
1541         REG_GET(FLIP_PARAMETERS_1,
1542                 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
1543         REG_GET(DCN_CUR0_TTU_CNTL1,
1544                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
1545         REG_GET(DCN_CUR1_TTU_CNTL1,
1546                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
1547         REG_GET(DCN_SURF0_TTU_CNTL1,
1548                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
1549         REG_GET(DCN_SURF1_TTU_CNTL1,
1550                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
1551
1552         if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
1553                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1554                                 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
1555         if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
1556                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1557                                 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
1558         if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
1559                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1560                                 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
1561         if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
1562                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1563                                 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
1564         if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
1565                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1566                                 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
1567         if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
1568                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1569                                 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
1570         if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
1571                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1572                                 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
1573         if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
1574                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1575                                 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
1576         if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
1577                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1578                                 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
1579         if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
1580                 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
1581                                 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
1582         if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
1583                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1584                                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
1585         if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
1586                 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1587                                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
1588         if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
1589                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1590                                 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
1591         if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
1592                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1593                                 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
1594 }
1595
1596 static struct hubp_funcs dcn20_hubp_funcs = {
1597         .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
1598         .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
1599         .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
1600         .hubp_program_surface_config = hubp2_program_surface_config,
1601         .hubp_is_flip_pending = hubp2_is_flip_pending,
1602         .hubp_setup = hubp2_setup,
1603         .hubp_setup_interdependent = hubp2_setup_interdependent,
1604         .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
1605         .set_blank = hubp2_set_blank,
1606         .set_blank_regs = hubp2_set_blank_regs,
1607         .dcc_control = hubp2_dcc_control,
1608         .mem_program_viewport = min_set_viewport,
1609         .set_cursor_attributes  = hubp2_cursor_set_attributes,
1610         .set_cursor_position    = hubp2_cursor_set_position,
1611         .hubp_clk_cntl = hubp2_clk_cntl,
1612         .hubp_vtg_sel = hubp2_vtg_sel,
1613         .dmdata_set_attributes = hubp2_dmdata_set_attributes,
1614         .dmdata_load = hubp2_dmdata_load,
1615         .dmdata_status_done = hubp2_dmdata_status_done,
1616         .hubp_read_state = hubp2_read_state,
1617         .hubp_clear_underflow = hubp2_clear_underflow,
1618         .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
1619         .hubp_init = hubp1_init,
1620         .validate_dml_output = hubp2_validate_dml_output,
1621         .hubp_in_blank = hubp1_in_blank,
1622         .hubp_soft_reset = hubp1_soft_reset,
1623         .hubp_set_flip_int = hubp1_set_flip_int,
1624 };
1625
1626
1627 bool hubp2_construct(
1628         struct dcn20_hubp *hubp2,
1629         struct dc_context *ctx,
1630         uint32_t inst,
1631         const struct dcn_hubp2_registers *hubp_regs,
1632         const struct dcn_hubp2_shift *hubp_shift,
1633         const struct dcn_hubp2_mask *hubp_mask)
1634 {
1635         hubp2->base.funcs = &dcn20_hubp_funcs;
1636         hubp2->base.ctx = ctx;
1637         hubp2->hubp_regs = hubp_regs;
1638         hubp2->hubp_shift = hubp_shift;
1639         hubp2->hubp_mask = hubp_mask;
1640         hubp2->base.inst = inst;
1641         hubp2->base.opp_id = OPP_ID_INVALID;
1642         hubp2->base.mpcc_id = 0xf;
1643
1644         return true;
1645 }