2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "reg_helper.h"
28 #include "dcn10_optc.h"
38 #define FN(reg_name, field_name) \
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
44 * apply_front_porch_workaround TODO FPGA still need?
46 * This is a workaround for a bug that has existed since R5xx and has not been
47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
49 static void optc1_apply_front_porch_workaround(
50 struct timing_generator *optc,
51 struct dc_crtc_timing *timing)
53 if (timing->flags.INTERLACE == 1) {
54 if (timing->v_front_porch < 2)
55 timing->v_front_porch = 2;
57 if (timing->v_front_porch < 1)
58 timing->v_front_porch = 1;
62 void optc1_program_global_sync(
63 struct timing_generator *optc)
65 struct optc *optc1 = DCN10TG_FROM_TG(optc);
67 if (optc->dlg_otg_param.vstartup_start == 0) {
72 REG_SET(OTG_VSTARTUP_PARAM, 0,
73 VSTARTUP_START, optc->dlg_otg_param.vstartup_start);
75 REG_SET_2(OTG_VUPDATE_PARAM, 0,
76 VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset,
77 VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width);
79 REG_SET(OTG_VREADY_PARAM, 0,
80 VREADY_OFFSET, optc->dlg_otg_param.vready_offset);
83 static void optc1_disable_stereo(struct timing_generator *optc)
85 struct optc *optc1 = DCN10TG_FROM_TG(optc);
87 REG_SET(OTG_STEREO_CONTROL, 0,
90 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
91 OTG_3D_STRUCTURE_EN, 0,
92 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
95 void optc1_setup_vertical_interrupt0(
96 struct timing_generator *optc,
100 struct optc *optc1 = DCN10TG_FROM_TG(optc);
102 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
103 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
104 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
107 void optc1_setup_vertical_interrupt1(
108 struct timing_generator *optc,
111 struct optc *optc1 = DCN10TG_FROM_TG(optc);
113 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
114 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
117 void optc1_setup_vertical_interrupt2(
118 struct timing_generator *optc,
121 struct optc *optc1 = DCN10TG_FROM_TG(optc);
123 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
124 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
128 * program_timing_generator used by mode timing set
129 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
130 * Including SYNC. Call BIOS command table to program Timings.
132 void optc1_program_timing(
133 struct timing_generator *optc,
134 const struct dc_crtc_timing *dc_crtc_timing,
137 struct dc_crtc_timing patched_crtc_timing;
138 uint32_t vesa_sync_start;
139 uint32_t asic_blank_end;
140 uint32_t asic_blank_start;
143 uint32_t v_init, v_fp2;
144 uint32_t h_sync_polarity, v_sync_polarity;
145 uint32_t start_point = 0;
146 uint32_t field_num = 0;
148 int32_t vertical_line_start;
150 struct optc *optc1 = DCN10TG_FROM_TG(optc);
152 patched_crtc_timing = *dc_crtc_timing;
153 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
155 /* Load horizontal timing */
157 /* CRTC_H_TOTAL = vesa.h_total - 1 */
158 REG_SET(OTG_H_TOTAL, 0,
159 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
161 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
162 REG_UPDATE_2(OTG_H_SYNC_A,
163 OTG_H_SYNC_A_START, 0,
164 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
166 /* asic_h_blank_end = HsyncWidth + HbackPorch =
167 * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart -
170 vesa_sync_start = patched_crtc_timing.h_addressable +
171 patched_crtc_timing.h_border_right +
172 patched_crtc_timing.h_front_porch;
174 asic_blank_end = patched_crtc_timing.h_total -
176 patched_crtc_timing.h_border_left;
178 /* h_blank_start = v_blank_end + v_active */
179 asic_blank_start = asic_blank_end +
180 patched_crtc_timing.h_border_left +
181 patched_crtc_timing.h_addressable +
182 patched_crtc_timing.h_border_right;
184 REG_UPDATE_2(OTG_H_BLANK_START_END,
185 OTG_H_BLANK_START, asic_blank_start,
186 OTG_H_BLANK_END, asic_blank_end);
188 /* h_sync polarity */
189 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
192 REG_UPDATE(OTG_H_SYNC_A_CNTL,
193 OTG_H_SYNC_A_POL, h_sync_polarity);
195 v_total = patched_crtc_timing.v_total - 1;
197 REG_SET(OTG_V_TOTAL, 0,
198 OTG_V_TOTAL, v_total);
200 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
201 * OTG_V_TOTAL_MIN are equal to V_TOTAL.
203 REG_SET(OTG_V_TOTAL_MAX, 0,
204 OTG_V_TOTAL_MAX, v_total);
205 REG_SET(OTG_V_TOTAL_MIN, 0,
206 OTG_V_TOTAL_MIN, v_total);
208 /* v_sync_start = 0, v_sync_end = v_sync_width */
209 v_sync_end = patched_crtc_timing.v_sync_width;
211 REG_UPDATE_2(OTG_V_SYNC_A,
212 OTG_V_SYNC_A_START, 0,
213 OTG_V_SYNC_A_END, v_sync_end);
215 vesa_sync_start = patched_crtc_timing.v_addressable +
216 patched_crtc_timing.v_border_bottom +
217 patched_crtc_timing.v_front_porch;
219 asic_blank_end = (patched_crtc_timing.v_total -
221 patched_crtc_timing.v_border_top);
223 /* v_blank_start = v_blank_end + v_active */
224 asic_blank_start = asic_blank_end +
225 (patched_crtc_timing.v_border_top +
226 patched_crtc_timing.v_addressable +
227 patched_crtc_timing.v_border_bottom);
229 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
231 if (vertical_line_start < 0)
232 v_fp2 = -vertical_line_start;
234 REG_UPDATE_2(OTG_V_BLANK_START_END,
235 OTG_V_BLANK_START, asic_blank_start,
236 OTG_V_BLANK_END, asic_blank_end);
238 /* v_sync polarity */
239 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
242 REG_UPDATE(OTG_V_SYNC_A_CNTL,
243 OTG_V_SYNC_A_POL, v_sync_polarity);
245 v_init = asic_blank_start;
246 if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
247 optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
248 optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {
250 if (patched_crtc_timing.flags.INTERLACE == 1)
255 if (REG(OTG_INTERLACE_CONTROL)) {
256 if (patched_crtc_timing.flags.INTERLACE == 1) {
257 REG_UPDATE(OTG_INTERLACE_CONTROL,
258 OTG_INTERLACE_ENABLE, 1);
260 if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
263 REG_UPDATE(OTG_INTERLACE_CONTROL,
264 OTG_INTERLACE_ENABLE, 0);
267 /* VTG enable set to 0 first VInit */
271 REG_UPDATE_2(CONTROL,
273 VTG0_VCOUNT_INIT, v_init);
275 /* original code is using VTG offset to address OTG reg, seems wrong */
276 REG_UPDATE_2(OTG_CONTROL,
277 OTG_START_POINT_CNTL, start_point,
278 OTG_FIELD_NUMBER_CNTL, field_num);
280 optc1_program_global_sync(optc);
283 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
284 * program_horz_count_by_2
285 * for DVI 30bpp mode, 0 otherwise
286 * program_horz_count_by_2(optc, &patched_crtc_timing);
289 /* Enable stereo - only when we need to pack 3D frame. Other types
290 * of stereo handled in explicit call
293 h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
294 REG_UPDATE(OTG_H_TIMING_CNTL,
295 OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf);
299 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
301 struct optc *optc1 = DCN10TG_FROM_TG(optc);
303 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
305 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
306 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
311 * Call ASIC Control Object to UnBlank CRTC.
313 static void optc1_unblank_crtc(struct timing_generator *optc)
315 struct optc *optc1 = DCN10TG_FROM_TG(optc);
317 REG_UPDATE_2(OTG_BLANK_CONTROL,
318 OTG_BLANK_DATA_EN, 0,
319 OTG_BLANK_DE_MODE, 0);
321 /* W/A for automated testing
322 * Automated testing will fail underflow test as there
323 * sporadic underflows which occur during the optc blank
324 * sequence. As a w/a, clear underflow on unblank.
325 * This prevents the failure, but will not mask actual
326 * underflow that affect real use cases.
328 optc1_clear_optc_underflow(optc);
333 * Call ASIC Control Object to Blank CRTC.
336 static void optc1_blank_crtc(struct timing_generator *optc)
338 struct optc *optc1 = DCN10TG_FROM_TG(optc);
340 REG_UPDATE_2(OTG_BLANK_CONTROL,
341 OTG_BLANK_DATA_EN, 1,
342 OTG_BLANK_DE_MODE, 0);
344 optc1_set_blank_data_double_buffer(optc, false);
347 void optc1_set_blank(struct timing_generator *optc,
348 bool enable_blanking)
351 optc1_blank_crtc(optc);
353 optc1_unblank_crtc(optc);
356 bool optc1_is_blanked(struct timing_generator *optc)
358 struct optc *optc1 = DCN10TG_FROM_TG(optc);
360 uint32_t blank_state;
362 REG_GET_2(OTG_BLANK_CONTROL,
363 OTG_BLANK_DATA_EN, &blank_en,
364 OTG_CURRENT_BLANK_STATE, &blank_state);
366 return blank_en && blank_state;
369 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
371 struct optc *optc1 = DCN10TG_FROM_TG(optc);
374 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
375 OPTC_INPUT_CLK_EN, 1,
376 OPTC_INPUT_CLK_GATE_DIS, 1);
378 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
379 OPTC_INPUT_CLK_ON, 1,
383 REG_UPDATE_2(OTG_CLOCK_CONTROL,
385 OTG_CLOCK_GATE_DIS, 1);
386 REG_WAIT(OTG_CLOCK_CONTROL,
390 REG_UPDATE_2(OTG_CLOCK_CONTROL,
391 OTG_CLOCK_GATE_DIS, 0,
394 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
395 OPTC_INPUT_CLK_GATE_DIS, 0,
396 OPTC_INPUT_CLK_EN, 0);
402 * Enable CRTC - call ASIC Control Object to enable Timing generator.
404 static bool optc1_enable_crtc(struct timing_generator *optc)
406 /* TODO FPGA wait for answer
407 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
408 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
410 struct optc *optc1 = DCN10TG_FROM_TG(optc);
412 /* opp instance for OTG. For DCN1.0, ODM is remoed.
413 * OPP and OPTC should 1:1 mapping
415 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
416 OPTC_SRC_SEL, optc->inst);
418 /* VTG enable first is for HW workaround */
423 REG_UPDATE_2(OTG_CONTROL,
424 OTG_DISABLE_POINT_CNTL, 3,
430 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
431 bool optc1_disable_crtc(struct timing_generator *optc)
433 struct optc *optc1 = DCN10TG_FROM_TG(optc);
435 /* disable otg request until end of the first line
436 * in the vertical blank region
438 REG_UPDATE_2(OTG_CONTROL,
439 OTG_DISABLE_POINT_CNTL, 3,
445 /* CRTC disabled, so disable clock. */
446 REG_WAIT(OTG_CLOCK_CONTROL,
454 void optc1_program_blank_color(
455 struct timing_generator *optc,
456 const struct tg_color *black_color)
458 struct optc *optc1 = DCN10TG_FROM_TG(optc);
460 REG_SET_3(OTG_BLACK_COLOR, 0,
461 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
462 OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
463 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
466 bool optc1_validate_timing(
467 struct timing_generator *optc,
468 const struct dc_crtc_timing *timing)
472 uint32_t min_v_blank;
473 struct optc *optc1 = DCN10TG_FROM_TG(optc);
475 ASSERT(timing != NULL);
477 v_blank = (timing->v_total - timing->v_addressable -
478 timing->v_border_top - timing->v_border_bottom);
480 h_blank = (timing->h_total - timing->h_addressable -
481 timing->h_border_right -
482 timing->h_border_left);
484 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
485 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
486 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
487 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
488 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
489 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
492 /* Temporarily blocking interlacing mode until it's supported */
493 if (timing->flags.INTERLACE == 1)
496 /* Check maximum number of pixels supported by Timing Generator
497 * (Currently will never fail, in order to fail needs display which
498 * needs more than 8192 horizontal and
499 * more than 8192 vertical total pixels)
501 if (timing->h_total > optc1->max_h_total ||
502 timing->v_total > optc1->max_v_total)
506 if (h_blank < optc1->min_h_blank)
509 if (timing->h_sync_width < optc1->min_h_sync_width ||
510 timing->v_sync_width < optc1->min_v_sync_width)
513 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
515 if (v_blank < min_v_blank)
526 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
527 * holds the counter of frames.
530 * struct timing_generator *optc - [in] timing generator which controls the
534 * Counter of frames, which should equal to number of vblanks.
536 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
538 struct optc *optc1 = DCN10TG_FROM_TG(optc);
539 uint32_t frame_count;
541 REG_GET(OTG_STATUS_FRAME_COUNT,
542 OTG_FRAME_COUNT, &frame_count);
547 void optc1_lock(struct timing_generator *optc)
549 struct optc *optc1 = DCN10TG_FROM_TG(optc);
551 REG_SET(OTG_GLOBAL_CONTROL0, 0,
552 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
553 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
554 OTG_MASTER_UPDATE_LOCK, 1);
556 /* Should be fast, status does not update on maximus */
557 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
558 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
559 UPDATE_LOCK_STATUS, 1,
563 void optc1_unlock(struct timing_generator *optc)
565 struct optc *optc1 = DCN10TG_FROM_TG(optc);
567 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
568 OTG_MASTER_UPDATE_LOCK, 0);
571 void optc1_get_position(struct timing_generator *optc,
572 struct crtc_position *position)
574 struct optc *optc1 = DCN10TG_FROM_TG(optc);
576 REG_GET_2(OTG_STATUS_POSITION,
577 OTG_HORZ_COUNT, &position->horizontal_count,
578 OTG_VERT_COUNT, &position->vertical_count);
580 REG_GET(OTG_NOM_VERT_POSITION,
581 OTG_VERT_COUNT_NOM, &position->nominal_vcount);
584 bool optc1_is_counter_moving(struct timing_generator *optc)
586 struct crtc_position position1, position2;
588 optc->funcs->get_position(optc, &position1);
589 optc->funcs->get_position(optc, &position2);
591 if (position1.horizontal_count == position2.horizontal_count &&
592 position1.vertical_count == position2.vertical_count)
598 bool optc1_did_triggered_reset_occur(
599 struct timing_generator *optc)
601 struct optc *optc1 = DCN10TG_FROM_TG(optc);
602 uint32_t occurred_force, occurred_vsync;
604 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
605 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
607 REG_GET(OTG_VERT_SYNC_CONTROL,
608 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
610 return occurred_vsync != 0 || occurred_force != 0;
613 void optc1_disable_reset_trigger(struct timing_generator *optc)
615 struct optc *optc1 = DCN10TG_FROM_TG(optc);
617 REG_WRITE(OTG_TRIGA_CNTL, 0);
619 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
620 OTG_FORCE_COUNT_NOW_CLEAR, 1);
622 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
623 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
626 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
628 struct optc *optc1 = DCN10TG_FROM_TG(optc);
629 uint32_t falling_edge;
631 REG_GET(OTG_V_SYNC_A_CNTL,
632 OTG_V_SYNC_A_POL, &falling_edge);
635 REG_SET_3(OTG_TRIGA_CNTL, 0,
636 /* vsync signal from selected OTG pipe based
637 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
639 OTG_TRIGA_SOURCE_SELECT, 20,
640 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
641 /* always detect falling edge */
642 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
644 REG_SET_3(OTG_TRIGA_CNTL, 0,
645 /* vsync signal from selected OTG pipe based
646 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
648 OTG_TRIGA_SOURCE_SELECT, 20,
649 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
650 /* always detect rising edge */
651 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
653 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
654 /* force H count to H_TOTAL and V count to V_TOTAL in
655 * progressive mode and V_TOTAL-1 in interlaced mode
657 OTG_FORCE_COUNT_NOW_MODE, 2);
660 void optc1_enable_crtc_reset(
661 struct timing_generator *optc,
663 struct crtc_trigger_info *crtc_tp)
665 struct optc *optc1 = DCN10TG_FROM_TG(optc);
666 uint32_t falling_edge = 0;
667 uint32_t rising_edge = 0;
669 switch (crtc_tp->event) {
671 case CRTC_EVENT_VSYNC_RISING:
675 case CRTC_EVENT_VSYNC_FALLING:
680 REG_SET_4(OTG_TRIGA_CNTL, 0,
681 /* vsync signal from selected OTG pipe based
682 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
684 OTG_TRIGA_SOURCE_SELECT, 20,
685 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
686 /* always detect falling edge */
687 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
688 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
690 switch (crtc_tp->delay) {
691 case TRIGGER_DELAY_NEXT_LINE:
692 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
693 OTG_AUTO_FORCE_VSYNC_MODE, 1);
695 case TRIGGER_DELAY_NEXT_PIXEL:
696 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
697 /* force H count to H_TOTAL and V count to V_TOTAL in
698 * progressive mode and V_TOTAL-1 in interlaced mode
700 OTG_FORCE_COUNT_NOW_MODE, 2);
705 void optc1_wait_for_state(struct timing_generator *optc,
706 enum crtc_state state)
708 struct optc *optc1 = DCN10TG_FROM_TG(optc);
711 case CRTC_STATE_VBLANK:
714 1, 100000); /* 1 vupdate at 10hz */
717 case CRTC_STATE_VACTIVE:
719 OTG_V_ACTIVE_DISP, 1,
720 1, 100000); /* 1 vupdate at 10hz */
728 void optc1_set_early_control(
729 struct timing_generator *optc,
732 /* asic design change, do not need this control
733 * empty for share caller logic
738 void optc1_set_static_screen_control(
739 struct timing_generator *optc,
742 struct optc *optc1 = DCN10TG_FROM_TG(optc);
744 /* Bit 8 is no longer applicable in RV for PSR case,
745 * set bit 8 to 0 if given
747 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
750 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
752 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
753 OTG_STATIC_SCREEN_EVENT_MASK, value,
754 OTG_STATIC_SCREEN_FRAME_COUNT, 2);
759 *****************************************************************************
763 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
765 *****************************************************************************
768 struct timing_generator *optc,
769 const struct drr_params *params)
771 struct optc *optc1 = DCN10TG_FROM_TG(optc);
773 if (params != NULL &&
774 params->vertical_total_max > 0 &&
775 params->vertical_total_min > 0) {
777 REG_SET(OTG_V_TOTAL_MAX, 0,
778 OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
780 REG_SET(OTG_V_TOTAL_MIN, 0,
781 OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
783 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
784 OTG_V_TOTAL_MIN_SEL, 1,
785 OTG_V_TOTAL_MAX_SEL, 1,
786 OTG_FORCE_LOCK_ON_EVENT, 0,
787 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
788 OTG_SET_V_TOTAL_MIN_MASK, 0);
790 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
791 OTG_SET_V_TOTAL_MIN_MASK, 0,
792 OTG_V_TOTAL_MIN_SEL, 0,
793 OTG_V_TOTAL_MAX_SEL, 0,
794 OTG_FORCE_LOCK_ON_EVENT, 0);
796 REG_SET(OTG_V_TOTAL_MIN, 0,
799 REG_SET(OTG_V_TOTAL_MAX, 0,
804 static void optc1_set_test_pattern(
805 struct timing_generator *optc,
806 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
807 * because this is not DP-specific (which is probably somewhere in DP
809 enum controller_dp_test_pattern test_pattern,
810 enum dc_color_depth color_depth)
812 struct optc *optc1 = DCN10TG_FROM_TG(optc);
813 enum test_pattern_color_format bit_depth;
814 enum test_pattern_dyn_range dyn_range;
815 enum test_pattern_mode mode;
816 uint32_t pattern_mask;
817 uint32_t pattern_data;
818 /* color ramp generator mixes 16-bits color */
819 uint32_t src_bpc = 16;
823 /* RGB values of the color bars.
824 * Produce two RGB colors: RGB0 - white (all Fs)
825 * and RGB1 - black (all 0s)
826 * (three RGB components for two colors)
828 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
830 /* dest color (converted to the specified color format) */
831 uint16_t dst_color[6];
834 /* translate to bit depth */
835 switch (color_depth) {
836 case COLOR_DEPTH_666:
837 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
839 case COLOR_DEPTH_888:
840 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
842 case COLOR_DEPTH_101010:
843 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
845 case COLOR_DEPTH_121212:
846 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
849 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
853 switch (test_pattern) {
854 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
855 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
857 dyn_range = (test_pattern ==
858 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
859 TEST_PATTERN_DYN_RANGE_CEA :
860 TEST_PATTERN_DYN_RANGE_VESA);
861 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
863 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
864 OTG_TEST_PATTERN_VRES, 6,
865 OTG_TEST_PATTERN_HRES, 6);
867 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
868 OTG_TEST_PATTERN_EN, 1,
869 OTG_TEST_PATTERN_MODE, mode,
870 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
871 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
875 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
876 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
878 mode = (test_pattern ==
879 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
880 TEST_PATTERN_MODE_VERTICALBARS :
881 TEST_PATTERN_MODE_HORIZONTALBARS);
884 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
887 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
890 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
898 /* adjust color to the required colorFormat */
899 for (index = 0; index < 6; index++) {
900 /* dst = 2^dstBpc * src / 2^srcBpc = src >>
904 src_color[index] >> (src_bpc - dst_bpc);
905 /* CRTC_TEST_PATTERN_DATA has 16 bits,
906 * lowest 6 are hardwired to ZERO
907 * color bits should be left aligned aligned to MSB
908 * XXXXXXXXXX000000 for 10 bit,
909 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
911 dst_color[index] <<= (16 - dst_bpc);
914 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
916 /* We have to write the mask before data, similar to pipeline.
917 * For example, for 8 bpc, if we want RGB0 to be magenta,
918 * and RGB1 to be cyan,
919 * we need to make 7 writes:
921 * 000001 00000000 00000000 set mask to R0
922 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0
923 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0
924 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1
925 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1
926 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1
927 * 100000 11111111 00000000 B1 255, 0xFF00
929 * we will make a loop of 6 in which we prepare the mask,
930 * then write, then prepare the color for next write.
931 * first iteration will write mask only,
932 * but each next iteration color prepared in
933 * previous iteration will be written within new mask,
934 * the last component will written separately,
935 * mask is not changing between 6th and 7th write
936 * and color will be prepared by last iteration
939 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
940 * is B1, G1, R1, B0, G0, R0
943 for (index = 0; index < 6; index++) {
944 /* prepare color mask, first write PATTERN_DATA
945 * will have all zeros
947 pattern_mask = (1 << index);
949 /* write color component */
950 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
951 OTG_TEST_PATTERN_MASK, pattern_mask,
952 OTG_TEST_PATTERN_DATA, pattern_data);
954 /* prepare next color component,
955 * will be written in the next iteration
957 pattern_data = dst_color[index];
959 /* write last color component,
960 * it's been already prepared in the loop
962 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
963 OTG_TEST_PATTERN_MASK, pattern_mask,
964 OTG_TEST_PATTERN_DATA, pattern_data);
966 /* enable test pattern */
967 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
968 OTG_TEST_PATTERN_EN, 1,
969 OTG_TEST_PATTERN_MODE, mode,
970 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
971 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
975 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
978 TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
979 TEST_PATTERN_MODE_DUALRAMP_RGB :
980 TEST_PATTERN_MODE_SINGLERAMP_RGB);
983 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
986 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
989 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
997 /* increment for the first ramp for one color gradation
998 * 1 gradation for 6-bit color is 2^10
999 * gradations in 16-bit color
1001 inc_base = (src_bpc - dst_bpc);
1003 switch (bit_depth) {
1004 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1006 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1007 OTG_TEST_PATTERN_INC0, inc_base,
1008 OTG_TEST_PATTERN_INC1, 0,
1009 OTG_TEST_PATTERN_HRES, 6,
1010 OTG_TEST_PATTERN_VRES, 6,
1011 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1014 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1016 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1017 OTG_TEST_PATTERN_INC0, inc_base,
1018 OTG_TEST_PATTERN_INC1, 0,
1019 OTG_TEST_PATTERN_HRES, 8,
1020 OTG_TEST_PATTERN_VRES, 6,
1021 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1024 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1026 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1027 OTG_TEST_PATTERN_INC0, inc_base,
1028 OTG_TEST_PATTERN_INC1, inc_base + 2,
1029 OTG_TEST_PATTERN_HRES, 8,
1030 OTG_TEST_PATTERN_VRES, 5,
1031 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1038 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1040 /* enable test pattern */
1041 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1043 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1044 OTG_TEST_PATTERN_EN, 1,
1045 OTG_TEST_PATTERN_MODE, mode,
1046 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1047 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1050 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1052 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1053 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1054 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1063 void optc1_get_crtc_scanoutpos(
1064 struct timing_generator *optc,
1065 uint32_t *v_blank_start,
1066 uint32_t *v_blank_end,
1067 uint32_t *h_position,
1068 uint32_t *v_position)
1070 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1071 struct crtc_position position;
1073 REG_GET_2(OTG_V_BLANK_START_END,
1074 OTG_V_BLANK_START, v_blank_start,
1075 OTG_V_BLANK_END, v_blank_end);
1077 optc1_get_position(optc, &position);
1079 *h_position = position.horizontal_count;
1080 *v_position = position.vertical_count;
1083 static void optc1_enable_stereo(struct timing_generator *optc,
1084 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1086 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1090 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1092 if (flags->PROGRAM_STEREO)
1093 REG_UPDATE_3(OTG_STEREO_CONTROL,
1094 OTG_STEREO_EN, stereo_en,
1095 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1096 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
1098 if (flags->PROGRAM_POLARITY)
1099 REG_UPDATE(OTG_STEREO_CONTROL,
1100 OTG_STEREO_EYE_FLAG_POLARITY,
1101 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1103 if (flags->DISABLE_STEREO_DP_SYNC)
1104 REG_UPDATE(OTG_STEREO_CONTROL,
1105 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1107 if (flags->PROGRAM_STEREO)
1108 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1109 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1110 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1115 void optc1_program_stereo(struct timing_generator *optc,
1116 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1118 if (flags->PROGRAM_STEREO)
1119 optc1_enable_stereo(optc, timing, flags);
1121 optc1_disable_stereo(optc);
1125 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1128 uint32_t left_eye = 0;
1129 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1131 REG_GET(OTG_STEREO_STATUS,
1132 OTG_STEREO_CURRENT_EYE, &left_eye);
1141 bool optc1_is_matching_timing(struct timing_generator *tg,
1142 const struct dc_crtc_timing *otg_timing)
1144 struct dc_crtc_timing hw_crtc_timing = {0};
1145 struct dcn_otg_state s = {0};
1147 if (tg == NULL || otg_timing == NULL)
1150 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1152 hw_crtc_timing.h_total = s.h_total + 1;
1153 hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1154 hw_crtc_timing.h_front_porch = s.h_total + 1 - s.h_blank_start;
1155 hw_crtc_timing.h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1157 hw_crtc_timing.v_total = s.v_total + 1;
1158 hw_crtc_timing.v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1159 hw_crtc_timing.v_front_porch = s.v_total + 1 - s.v_blank_start;
1160 hw_crtc_timing.v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1162 if (otg_timing->h_total != hw_crtc_timing.h_total)
1165 if (otg_timing->h_border_left != hw_crtc_timing.h_border_left)
1168 if (otg_timing->h_addressable != hw_crtc_timing.h_addressable)
1171 if (otg_timing->h_border_right != hw_crtc_timing.h_border_right)
1174 if (otg_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1177 if (otg_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1180 if (otg_timing->v_total != hw_crtc_timing.v_total)
1183 if (otg_timing->v_border_top != hw_crtc_timing.v_border_top)
1186 if (otg_timing->v_addressable != hw_crtc_timing.v_addressable)
1189 if (otg_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1192 if (otg_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1199 void optc1_read_otg_state(struct optc *optc1,
1200 struct dcn_otg_state *s)
1202 REG_GET(OTG_CONTROL,
1203 OTG_MASTER_EN, &s->otg_enabled);
1205 REG_GET_2(OTG_V_BLANK_START_END,
1206 OTG_V_BLANK_START, &s->v_blank_start,
1207 OTG_V_BLANK_END, &s->v_blank_end);
1209 REG_GET(OTG_V_SYNC_A_CNTL,
1210 OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1212 REG_GET(OTG_V_TOTAL,
1213 OTG_V_TOTAL, &s->v_total);
1215 REG_GET(OTG_V_TOTAL_MAX,
1216 OTG_V_TOTAL_MAX, &s->v_total_max);
1218 REG_GET(OTG_V_TOTAL_MIN,
1219 OTG_V_TOTAL_MIN, &s->v_total_min);
1221 REG_GET(OTG_V_TOTAL_CONTROL,
1222 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1224 REG_GET(OTG_V_TOTAL_CONTROL,
1225 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1227 REG_GET_2(OTG_V_SYNC_A,
1228 OTG_V_SYNC_A_START, &s->v_sync_a_start,
1229 OTG_V_SYNC_A_END, &s->v_sync_a_end);
1231 REG_GET_2(OTG_H_BLANK_START_END,
1232 OTG_H_BLANK_START, &s->h_blank_start,
1233 OTG_H_BLANK_END, &s->h_blank_end);
1235 REG_GET_2(OTG_H_SYNC_A,
1236 OTG_H_SYNC_A_START, &s->h_sync_a_start,
1237 OTG_H_SYNC_A_END, &s->h_sync_a_end);
1239 REG_GET(OTG_H_SYNC_A_CNTL,
1240 OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1242 REG_GET(OTG_H_TOTAL,
1243 OTG_H_TOTAL, &s->h_total);
1245 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1246 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1249 bool optc1_get_otg_active_size(struct timing_generator *optc,
1250 uint32_t *otg_active_width,
1251 uint32_t *otg_active_height)
1253 uint32_t otg_enabled;
1254 uint32_t v_blank_start;
1255 uint32_t v_blank_end;
1256 uint32_t h_blank_start;
1257 uint32_t h_blank_end;
1258 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1261 REG_GET(OTG_CONTROL,
1262 OTG_MASTER_EN, &otg_enabled);
1264 if (otg_enabled == 0)
1267 REG_GET_2(OTG_V_BLANK_START_END,
1268 OTG_V_BLANK_START, &v_blank_start,
1269 OTG_V_BLANK_END, &v_blank_end);
1271 REG_GET_2(OTG_H_BLANK_START_END,
1272 OTG_H_BLANK_START, &h_blank_start,
1273 OTG_H_BLANK_END, &h_blank_end);
1275 *otg_active_width = v_blank_start - v_blank_end;
1276 *otg_active_height = h_blank_start - h_blank_end;
1280 void optc1_clear_optc_underflow(struct timing_generator *optc)
1282 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1284 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1287 void optc1_tg_init(struct timing_generator *optc)
1289 optc1_set_blank_data_double_buffer(optc, true);
1290 optc1_clear_optc_underflow(optc);
1293 bool optc1_is_tg_enabled(struct timing_generator *optc)
1295 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1296 uint32_t otg_enabled = 0;
1298 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1300 return (otg_enabled != 0);
1304 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1306 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1307 uint32_t underflow_occurred = 0;
1309 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1310 OPTC_UNDERFLOW_OCCURRED_STATUS,
1311 &underflow_occurred);
1313 return (underflow_occurred == 1);
1316 bool optc1_configure_crc(struct timing_generator *optc,
1317 const struct crc_params *params)
1319 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1321 /* Cannot configure crc on a CRTC that is disabled */
1322 if (!optc1_is_tg_enabled(optc))
1325 REG_WRITE(OTG_CRC_CNTL, 0);
1327 if (!params->enable)
1330 /* Program frame boundaries */
1331 /* Window A x axis start and end. */
1332 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1333 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1334 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1336 /* Window A y axis start and end. */
1337 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1338 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1339 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1341 /* Window B x axis start and end. */
1342 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1343 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1344 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1346 /* Window B y axis start and end. */
1347 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1348 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1349 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1351 /* Set crc mode and selection, and enable. Only using CRC0*/
1352 REG_UPDATE_3(OTG_CRC_CNTL,
1353 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1354 OTG_CRC0_SELECT, params->selection,
1360 bool optc1_get_crc(struct timing_generator *optc,
1361 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1364 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1366 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1368 /* Early return if CRC is not enabled for this CRTC */
1372 REG_GET_2(OTG_CRC0_DATA_RG,
1376 REG_GET(OTG_CRC0_DATA_B,
1382 static const struct timing_generator_funcs dcn10_tg_funcs = {
1383 .validate_timing = optc1_validate_timing,
1384 .program_timing = optc1_program_timing,
1385 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1386 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1387 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1388 .program_global_sync = optc1_program_global_sync,
1389 .enable_crtc = optc1_enable_crtc,
1390 .disable_crtc = optc1_disable_crtc,
1391 /* used by enable_timing_synchronization. Not need for FPGA */
1392 .is_counter_moving = optc1_is_counter_moving,
1393 .get_position = optc1_get_position,
1394 .get_frame_count = optc1_get_vblank_counter,
1395 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1396 .get_otg_active_size = optc1_get_otg_active_size,
1397 .is_matching_timing = optc1_is_matching_timing,
1398 .set_early_control = optc1_set_early_control,
1399 /* used by enable_timing_synchronization. Not need for FPGA */
1400 .wait_for_state = optc1_wait_for_state,
1401 .set_blank = optc1_set_blank,
1402 .is_blanked = optc1_is_blanked,
1403 .set_blank_color = optc1_program_blank_color,
1404 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1405 .enable_reset_trigger = optc1_enable_reset_trigger,
1406 .enable_crtc_reset = optc1_enable_crtc_reset,
1407 .disable_reset_trigger = optc1_disable_reset_trigger,
1409 .unlock = optc1_unlock,
1410 .enable_optc_clock = optc1_enable_optc_clock,
1411 .set_drr = optc1_set_drr,
1412 .set_static_screen_control = optc1_set_static_screen_control,
1413 .set_test_pattern = optc1_set_test_pattern,
1414 .program_stereo = optc1_program_stereo,
1415 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1416 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1417 .tg_init = optc1_tg_init,
1418 .is_tg_enabled = optc1_is_tg_enabled,
1419 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1420 .clear_optc_underflow = optc1_clear_optc_underflow,
1421 .get_crc = optc1_get_crc,
1422 .configure_crc = optc1_configure_crc,
1425 void dcn10_timing_generator_init(struct optc *optc1)
1427 optc1->base.funcs = &dcn10_tg_funcs;
1429 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1430 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1432 optc1->min_h_blank = 32;
1433 optc1->min_v_blank = 3;
1434 optc1->min_v_blank_interlace = 5;
1435 optc1->min_h_sync_width = 8;
1436 optc1->min_v_sync_width = 1;
1437 optc1->comb_opp_id = 0xf;
1440 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1442 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;