drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10_optc.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "custom_float.h"
  44 #include "dcn10_hubp.h"
  45 #include "dcn10_hubbub.h"
  46 #include "dcn10_cm_common.h"
  47
  48 #define CTX \
  49         hws->ctx
  50 #define REG(reg)\
  51         hws->regs->reg
  52
  53 #undef FN
  54 #define FN(reg_name, field_name) \
  55         hws->shifts->field_name, hws->masks->field_name
  56
  57 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  58         print_microsec(dc_ctx, ref_cycle)
  59
  60 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
  61 {
  62         static const uint32_t ref_clk_mhz = 48;
  63         static const unsigned int frac = 10;
  64         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  65
  66         DTN_INFO("%d.%d \t ",
  67                         us_x10 / frac,
  68                         us_x10 % frac);
  69 }
  70
  71
  72 static void log_mpc_crc(struct dc *dc)
  73 {
  74         struct dc_context *dc_ctx = dc->ctx;
  75         struct dce_hwseq *hws = dc->hwseq;
  76
  77         if (REG(MPC_CRC_RESULT_GB))
  78                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  79                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  80         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  81                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  82                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  83 }
  84
  85 void dcn10_log_hubbub_state(struct dc *dc)
  86 {
  87         struct dc_context *dc_ctx = dc->ctx;
  88         struct dcn_hubbub_wm wm;
  89         int i;
  90
  91         hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
  92
  93         DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
  94                         "sr_enter \t sr_exit \t dram_clk_change \n");
  95
  96         for (i = 0; i < 4; i++) {
  97                 struct dcn_hubbub_wm_set *s;
  98
  99                 s = &wm.sets[i];
 100                 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
 101                 DTN_INFO_MICRO_SEC(s->data_urgent);
 102                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 103                 DTN_INFO_MICRO_SEC(s->sr_enter);
 104                 DTN_INFO_MICRO_SEC(s->sr_exit);
 105                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 106                 DTN_INFO("\n");
 107         }
 108
 109         DTN_INFO("\n");
 110 }
 111
 112 void dcn10_log_hw_state(struct dc *dc)
 113 {
 114         struct dc_context *dc_ctx = dc->ctx;
 115         struct resource_pool *pool = dc->res_pool;
 116         int i;
 117
 118         DTN_INFO_BEGIN();
 119
 120         dcn10_log_hubbub_state(dc);
 121
 122         DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
 123                         "rotation \t mirror \t  sw_mode \t "
 124                         "dcc_en \t blank_en \t ttu_dis \t underflow \t "
 125                         "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
 126
 127         for (i = 0; i < pool->pipe_count; i++) {
 128                 struct hubp *hubp = pool->hubps[i];
 129                 struct dcn_hubp_state s;
 130
 131                 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 132
 133                 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
 134                                 "%xh \t %xh \t %xh \t "
 135                                 "%d \t %d \t %d \t %xh \t",
 136                                 i,
 137                                 s.pixel_format,
 138                                 s.inuse_addr_hi,
 139                                 s.viewport_width,
 140                                 s.viewport_height,
 141                                 s.rotation_angle,
 142                                 s.h_mirror_en,
 143                                 s.sw_mode,
 144                                 s.dcc_en,
 145                                 s.blank_en,
 146                                 s.ttu_disable,
 147                                 s.underflow_status);
 148                 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
 149                 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
 150                 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
 151                 DTN_INFO("\n");
 152         }
 153         DTN_INFO("\n");
 154
 155         DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
 156                         "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 157
 158         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
 159                 struct timing_generator *tg = pool->timing_generators[i];
 160                 struct dcn_otg_state s = {0};
 161
 162                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 163
 164                 //only print if OTG master is enabled
 165                 if ((s.otg_enabled & 1) == 0)
 166                         continue;
 167
 168                 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 169                                 "%d \t %d \t %d \t %d \t %d \t %d \t "
 170                                 "%d \t %d \t %d \t %d \t %d \t ",
 171                                 i,
 172                                 s.v_blank_start,
 173                                 s.v_blank_end,
 174                                 s.v_sync_a_start,
 175                                 s.v_sync_a_end,
 176                                 s.v_sync_a_pol,
 177                                 s.v_total_max,
 178                                 s.v_total_min,
 179                                 s.h_blank_start,
 180                                 s.h_blank_end,
 181                                 s.h_sync_a_start,
 182                                 s.h_sync_a_end,
 183                                 s.h_sync_a_pol,
 184                                 s.h_total,
 185                                 s.v_total,
 186                                 s.underflow_occurred_status);
 187                 DTN_INFO("\n");
 188         }
 189         DTN_INFO("\n");
 190
 191         log_mpc_crc(dc);
 192
 193         DTN_INFO_END();
 194 }
 195
 196 static void enable_dppclk(
 197         struct dce_hwseq *hws,
 198         uint8_t plane_id,
 199         uint32_t requested_pix_clk,
 200         bool dppclk_div)
 201 {
 202         dm_logger_write(hws->ctx->logger, LOG_SURFACE,
 203                         "dppclk_rate_control for pipe %d programed to %d\n",
 204                         plane_id,
 205                         dppclk_div);
 206
 207         if (hws->shifts->DPPCLK_RATE_CONTROL)
 208                 REG_UPDATE_2(DPP_CONTROL[plane_id],
 209                         DPPCLK_RATE_CONTROL, dppclk_div,
 210                         DPP_CLOCK_ENABLE, 1);
 211         else
 212                 REG_UPDATE(DPP_CONTROL[plane_id],
 213                         DPP_CLOCK_ENABLE, 1);
 214 }
 215
 216 static void enable_power_gating_plane(
 217         struct dce_hwseq *hws,
 218         bool enable)
 219 {
 220         bool force_on = 1; /* disable power gating */
 221
 222         if (enable)
 223                 force_on = 0;
 224
 225         /* DCHUBP0/1/2/3 */
 226         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 227         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 228         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 229         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 230
 231         /* DPP0/1/2/3 */
 232         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 233         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 234         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 235         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 236 }
 237
 238 static void disable_vga(
 239         struct dce_hwseq *hws)
 240 {
 241         unsigned int in_vga1_mode = 0;
 242         unsigned int in_vga2_mode = 0;
 243         unsigned int in_vga3_mode = 0;
 244         unsigned int in_vga4_mode = 0;
 245
 246         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 247         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 248         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 249         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 250
 251         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 252                         in_vga3_mode == 0 && in_vga4_mode == 0)
 253                 return;
 254
 255         REG_WRITE(D1VGA_CONTROL, 0);
 256         REG_WRITE(D2VGA_CONTROL, 0);
 257         REG_WRITE(D3VGA_CONTROL, 0);
 258         REG_WRITE(D4VGA_CONTROL, 0);
 259
 260         /* HW Engineer's Notes:
 261          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 262          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 263          *
 264          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 265          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 266          */
 267         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 268         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 269 }
 270
 271 static void dpp_pg_control(
 272                 struct dce_hwseq *hws,
 273                 unsigned int dpp_inst,
 274                 bool power_on)
 275 {
 276         uint32_t power_gate = power_on ? 0 : 1;
 277         uint32_t pwr_status = power_on ? 0 : 2;
 278
 279         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 280                 return;
 281
 282         switch (dpp_inst) {
 283         case 0: /* DPP0 */
 284                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 285                                 DOMAIN1_POWER_GATE, power_gate);
 286
 287                 REG_WAIT(DOMAIN1_PG_STATUS,
 288                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 289                                 1, 1000);
 290                 break;
 291         case 1: /* DPP1 */
 292                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 293                                 DOMAIN3_POWER_GATE, power_gate);
 294
 295                 REG_WAIT(DOMAIN3_PG_STATUS,
 296                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 297                                 1, 1000);
 298                 break;
 299         case 2: /* DPP2 */
 300                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 301                                 DOMAIN5_POWER_GATE, power_gate);
 302
 303                 REG_WAIT(DOMAIN5_PG_STATUS,
 304                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 305                                 1, 1000);
 306                 break;
 307         case 3: /* DPP3 */
 308                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 309                                 DOMAIN7_POWER_GATE, power_gate);
 310
 311                 REG_WAIT(DOMAIN7_PG_STATUS,
 312                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 313                                 1, 1000);
 314                 break;
 315         default:
 316                 BREAK_TO_DEBUGGER();
 317                 break;
 318         }
 319 }
 320
 321 static void hubp_pg_control(
 322                 struct dce_hwseq *hws,
 323                 unsigned int hubp_inst,
 324                 bool power_on)
 325 {
 326         uint32_t power_gate = power_on ? 0 : 1;
 327         uint32_t pwr_status = power_on ? 0 : 2;
 328
 329         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 330                 return;
 331
 332         switch (hubp_inst) {
 333         case 0: /* DCHUBP0 */
 334                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 335                                 DOMAIN0_POWER_GATE, power_gate);
 336
 337                 REG_WAIT(DOMAIN0_PG_STATUS,
 338                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 339                                 1, 1000);
 340                 break;
 341         case 1: /* DCHUBP1 */
 342                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 343                                 DOMAIN2_POWER_GATE, power_gate);
 344
 345                 REG_WAIT(DOMAIN2_PG_STATUS,
 346                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 347                                 1, 1000);
 348                 break;
 349         case 2: /* DCHUBP2 */
 350                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 351                                 DOMAIN4_POWER_GATE, power_gate);
 352
 353                 REG_WAIT(DOMAIN4_PG_STATUS,
 354                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 355                                 1, 1000);
 356                 break;
 357         case 3: /* DCHUBP3 */
 358                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 359                                 DOMAIN6_POWER_GATE, power_gate);
 360
 361                 REG_WAIT(DOMAIN6_PG_STATUS,
 362                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 363                                 1, 1000);
 364                 break;
 365         default:
 366                 BREAK_TO_DEBUGGER();
 367                 break;
 368         }
 369 }
 370
 371 static void power_on_plane(
 372         struct dce_hwseq *hws,
 373         int plane_id)
 374 {
 375         if (REG(DC_IP_REQUEST_CNTL)) {
 376                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 377                                 IP_REQUEST_EN, 1);
 378                 dpp_pg_control(hws, plane_id, true);
 379                 hubp_pg_control(hws, plane_id, true);
 380                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 381                                 IP_REQUEST_EN, 0);
 382                 dm_logger_write(hws->ctx->logger, LOG_DEBUG,
 383                                 "Un-gated front end for pipe %d\n", plane_id);
 384         }
 385 }
 386
 387 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 388 {
 389         struct dce_hwseq *hws = dc->hwseq;
 390         struct hubp *hubp = dc->res_pool->hubps[0];
 391
 392         if (!hws->wa_state.DEGVIDCN10_253_applied)
 393                 return;
 394
 395         hubp->funcs->set_blank(hubp, true);
 396
 397         REG_SET(DC_IP_REQUEST_CNTL, 0,
 398                         IP_REQUEST_EN, 1);
 399
 400         hubp_pg_control(hws, 0, false);
 401         REG_SET(DC_IP_REQUEST_CNTL, 0,
 402                         IP_REQUEST_EN, 0);
 403
 404         hws->wa_state.DEGVIDCN10_253_applied = false;
 405 }
 406
 407 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 408 {
 409         struct dce_hwseq *hws = dc->hwseq;
 410         struct hubp *hubp = dc->res_pool->hubps[0];
 411         int i;
 412
 413         if (dc->debug.disable_stutter)
 414                 return;
 415
 416         if (!hws->wa.DEGVIDCN10_253)
 417                 return;
 418
 419         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 420                 if (!dc->res_pool->hubps[i]->power_gated)
 421                         return;
 422         }
 423
 424         /* all pipe power gated, apply work around to enable stutter. */
 425
 426         REG_SET(DC_IP_REQUEST_CNTL, 0,
 427                         IP_REQUEST_EN, 1);
 428
 429         hubp_pg_control(hws, 0, true);
 430         REG_SET(DC_IP_REQUEST_CNTL, 0,
 431                         IP_REQUEST_EN, 0);
 432
 433         hubp->funcs->set_hubp_blank_en(hubp, false);
 434         hws->wa_state.DEGVIDCN10_253_applied = true;
 435 }
 436
 437 static void bios_golden_init(struct dc *dc)
 438 {
 439         struct dc_bios *bp = dc->ctx->dc_bios;
 440         int i;
 441
 442         /* initialize dcn global */
 443         bp->funcs->enable_disp_power_gating(bp,
 444                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 445
 446         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 447                 /* initialize dcn per pipe */
 448                 bp->funcs->enable_disp_power_gating(bp,
 449                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 450         }
 451 }
 452
 453 static void false_optc_underflow_wa(
 454                 struct dc *dc,
 455                 const struct dc_stream_state *stream,
 456                 struct timing_generator *tg)
 457 {
 458         int i;
 459         bool underflow;
 460
 461         if (!dc->hwseq->wa.false_optc_underflow)
 462                 return;
 463
 464         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 465
 466         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 467                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 468
 469                 if (old_pipe_ctx->stream != stream)
 470                         continue;
 471
 472                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 473         }
 474
 475         tg->funcs->set_blank_data_double_buffer(tg, true);
 476
 477         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 478                 tg->funcs->clear_optc_underflow(tg);
 479 }
 480
 481 static enum dc_status dcn10_prog_pixclk_crtc_otg(
 482                 struct pipe_ctx *pipe_ctx,
 483                 struct dc_state *context,
 484                 struct dc *dc)
 485 {
 486         struct dc_stream_state *stream = pipe_ctx->stream;
 487         enum dc_color_space color_space;
 488         struct tg_color black_color = {0};
 489
 490         /* by upper caller loop, pipe0 is parent pipe and be called first.
 491          * back end is set up by for pipe0. Other children pipe share back end
 492          * with pipe 0. No program is needed.
 493          */
 494         if (pipe_ctx->top_pipe != NULL)
 495                 return DC_OK;
 496
 497         /* TODO check if timing_changed, disable stream if timing changed */
 498
 499         /* HW program guide assume display already disable
 500          * by unplug sequence. OTG assume stop.
 501          */
 502         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 503
 504         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 505                         pipe_ctx->clock_source,
 506                         &pipe_ctx->stream_res.pix_clk_params,
 507                         &pipe_ctx->pll_settings)) {
 508                 BREAK_TO_DEBUGGER();
 509                 return DC_ERROR_UNEXPECTED;
 510         }
 511         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 512         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 513         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 514         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 515
 516         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 517
 518         pipe_ctx->stream_res.tg->funcs->program_timing(
 519                         pipe_ctx->stream_res.tg,
 520                         &stream->timing,
 521                         true);
 522
 523 #if 0 /* move to after enable_crtc */
 524         /* TODO: OPP FMT, ABM. etc. should be done here. */
 525         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 526
 527         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 528
 529         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 530                                 pipe_ctx->stream_res.opp,
 531                                 &stream->bit_depth_params,
 532                                 &stream->clamping);
 533 #endif
 534         /* program otg blank color */
 535         color_space = stream->output_color_space;
 536         color_space_to_black_color(dc, color_space, &black_color);
 537
 538         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 539                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 540                                 pipe_ctx->stream_res.tg,
 541                                 &black_color);
 542
 543         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 544                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 545                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 546                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 547                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 548         }
 549
 550         /* VTG is  within DCHUB command block. DCFCLK is always on */
 551         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 552                 BREAK_TO_DEBUGGER();
 553                 return DC_ERROR_UNEXPECTED;
 554         }
 555
 556         /* TODO program crtc source select for non-virtual signal*/
 557         /* TODO program FMT */
 558         /* TODO setup link_enc */
 559         /* TODO set stream attributes */
 560         /* TODO program audio */
 561         /* TODO enable stream if timing changed */
 562         /* TODO unblank stream if DP */
 563
 564         return DC_OK;
 565 }
 566
 567 static void reset_back_end_for_pipe(
 568                 struct dc *dc,
 569                 struct pipe_ctx *pipe_ctx,
 570                 struct dc_state *context)
 571 {
 572         int i;
 573
 574         if (pipe_ctx->stream_res.stream_enc == NULL) {
 575                 pipe_ctx->stream = NULL;
 576                 return;
 577         }
 578
 579         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 580                 /* DPMS may already disable */
 581                 if (!pipe_ctx->stream->dpms_off)
 582                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 583         }
 584
 585         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 586          * back end share by all pipes and will be disable only when disable
 587          * parent pipe.
 588          */
 589         if (pipe_ctx->top_pipe == NULL) {
 590                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 591
 592                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 593         }
 594
 595         for (i = 0; i < dc->res_pool->pipe_count; i++)
 596                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 597                         break;
 598
 599         if (i == dc->res_pool->pipe_count)
 600                 return;
 601
 602         pipe_ctx->stream = NULL;
 603         dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 604                                         "Reset back end for pipe %d, tg:%d\n",
 605                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 606 }
 607
 608 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 609 {
 610         static bool should_log_hw_state; /* prevent hw state log by default */
 611
 612         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 613                 if (should_log_hw_state) {
 614                         dcn10_log_hw_state(dc);
 615                 }
 616
 617                 BREAK_TO_DEBUGGER();
 618         }
 619 }
 620
 621 /* trigger HW to start disconnect plane from stream on the next vsync */
 622 static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 623 {
 624         int fe_idx = pipe_ctx->pipe_idx;
 625         struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 626         struct mpc *mpc = dc->res_pool->mpc;
 627         int opp_id;
 628         struct mpc_tree *mpc_tree_params;
 629         struct mpcc *mpcc_to_remove = NULL;
 630
 631         /* look at tree rather than mi here to know if we already reset */
 632         for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
 633                 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
 634
 635                 mpc_tree_params = &(opp->mpc_tree_params);
 636                 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, fe_idx);
 637                 if (mpcc_to_remove != NULL)
 638                         break;
 639         }
 640
 641         /*Already reset*/
 642         if (opp_id == dc->res_pool->pipe_count)
 643                 return;
 644
 645         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 646         dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[fe_idx] = true;
 647
 648         dc->optimized_required = true;
 649
 650         if (hubp->funcs->hubp_disconnect)
 651                 hubp->funcs->hubp_disconnect(hubp);
 652
 653         if (dc->debug.sanity_checks)
 654                 dcn10_verify_allow_pstate_change_high(dc);
 655 }
 656
 657 static void plane_atomic_power_down(struct dc *dc, int fe_idx)
 658 {
 659         struct dce_hwseq *hws = dc->hwseq;
 660         struct dpp *dpp = dc->res_pool->dpps[fe_idx];
 661
 662         if (REG(DC_IP_REQUEST_CNTL)) {
 663                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 664                                 IP_REQUEST_EN, 1);
 665                 dpp_pg_control(hws, fe_idx, false);
 666                 hubp_pg_control(hws, fe_idx, false);
 667                 dpp->funcs->dpp_reset(dpp);
 668                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 669                                 IP_REQUEST_EN, 0);
 670                 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 671                                 "Power gated front end %d\n", fe_idx);
 672         }
 673 }
 674
 675 /* disable HW used by plane.
 676  * note:  cannot disable until disconnect is complete
 677  */
 678 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 679 {
 680         int fe_idx = pipe_ctx->pipe_idx;
 681         struct dce_hwseq *hws = dc->hwseq;
 682         struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 683         int opp_id = hubp->opp_id;
 684
 685         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 686
 687         REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
 688                         HUBP_CLOCK_ENABLE, 0);
 689         REG_UPDATE(DPP_CONTROL[fe_idx],
 690                         DPP_CLOCK_ENABLE, 0);
 691
 692         if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree_params.opp_list == NULL)
 693                 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
 694                                 OPP_PIPE_CLOCK_EN, 0);
 695
 696         hubp->power_gated = true;
 697         dc->optimized_required = false; /* We're powering off, no need to optimize */
 698
 699         plane_atomic_power_down(dc, fe_idx);
 700
 701         pipe_ctx->stream = NULL;
 702         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 703         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 704         pipe_ctx->top_pipe = NULL;
 705         pipe_ctx->bottom_pipe = NULL;
 706         pipe_ctx->plane_state = NULL;
 707 }
 708
 709 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 710 {
 711         if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
 712                 return;
 713
 714         plane_atomic_disable(dc, pipe_ctx);
 715
 716         apply_DEGVIDCN10_253_wa(dc);
 717
 718         dm_logger_write(dc->ctx->logger, LOG_DC,
 719                                         "Power down front end %d\n",
 720                                         pipe_ctx->pipe_idx);
 721 }
 722
 723 static void dcn10_init_hw(struct dc *dc)
 724 {
 725         int i;
 726         struct abm *abm = dc->res_pool->abm;
 727         struct dmcu *dmcu = dc->res_pool->dmcu;
 728         struct dce_hwseq *hws = dc->hwseq;
 729         struct dc_bios *dcb = dc->ctx->dc_bios;
 730         struct dc_state  *context = dc->current_state;
 731
 732         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 733                 REG_WRITE(REFCLK_CNTL, 0);
 734                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 735                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 736
 737                 if (!dc->debug.disable_clock_gate) {
 738                         /* enable all DCN clock gating */
 739                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 740
 741                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 742
 743                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 744                 }
 745
 746                 enable_power_gating_plane(dc->hwseq, true);
 747                 return;
 748         }
 749         /* end of FPGA. Below if real ASIC */
 750
 751         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 752                 bios_golden_init(dc);
 753                 disable_vga(dc->hwseq);
 754         }
 755
 756         for (i = 0; i < dc->link_count; i++) {
 757                 /* Power up AND update implementation according to the
 758                  * required signal (which may be different from the
 759                  * default signal on connector).
 760                  */
 761                 struct dc_link *link = dc->links[i];
 762
 763                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
 764                         dc->hwss.edp_power_control(link, true);
 765
 766                 link->link_enc->funcs->hw_init(link->link_enc);
 767         }
 768
 769         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 770                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 771
 772                 if (tg->funcs->is_tg_enabled(tg))
 773                         tg->funcs->lock(tg);
 774         }
 775
 776         /* Blank controller using driver code instead of
 777          * command table.
 778          */
 779         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 780                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 781
 782                 if (tg->funcs->is_tg_enabled(tg)) {
 783                         tg->funcs->set_blank(tg, true);
 784                         hwss_wait_for_blank_complete(tg);
 785                 }
 786         }
 787
 788         /* Reset all MPCC muxes */
 789         dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
 790
 791         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 792                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 793                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 794                 struct hubp *hubp = dc->res_pool->hubps[i];
 795
 796                 pipe_ctx->stream_res.tg = tg;
 797                 pipe_ctx->pipe_idx = i;
 798
 799                 pipe_ctx->plane_res.hubp = hubp;
 800                 hubp->mpcc_id = i;
 801                 hubp->opp_id = 0xf;
 802                 hubp->power_gated = false;
 803
 804                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 805                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 806                 dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true;
 807                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 808
 809                 plane_atomic_disconnect(dc, pipe_ctx);
 810         }
 811
 812         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 813                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 814
 815                 if (tg->funcs->is_tg_enabled(tg))
 816                         tg->funcs->unlock(tg);
 817         }
 818
 819         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 820                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 821                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 822
 823                 dcn10_disable_plane(dc, pipe_ctx);
 824
 825                 pipe_ctx->stream_res.tg = NULL;
 826                 pipe_ctx->plane_res.hubp = NULL;
 827
 828                 tg->funcs->tg_init(tg);
 829         }
 830
 831         for (i = 0; i < dc->res_pool->audio_count; i++) {
 832                 struct audio *audio = dc->res_pool->audios[i];
 833
 834                 audio->funcs->hw_init(audio);
 835         }
 836
 837         if (abm != NULL) {
 838                 abm->funcs->init_backlight(abm);
 839                 abm->funcs->abm_init(abm);
 840         }
 841
 842         if (dmcu != NULL)
 843                 dmcu->funcs->dmcu_init(dmcu);
 844
 845         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 846         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 847
 848         if (!dc->debug.disable_clock_gate) {
 849                 /* enable all DCN clock gating */
 850                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 851
 852                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 853
 854                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 855         }
 856
 857         enable_power_gating_plane(dc->hwseq, true);
 858 }
 859
 860 static void reset_hw_ctx_wrap(
 861                 struct dc *dc,
 862                 struct dc_state *context)
 863 {
 864         int i;
 865
 866         /* Reset Back End*/
 867         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 868                 struct pipe_ctx *pipe_ctx_old =
 869                         &dc->current_state->res_ctx.pipe_ctx[i];
 870                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 871
 872                 if (!pipe_ctx_old->stream)
 873                         continue;
 874
 875                 if (pipe_ctx_old->top_pipe)
 876                         continue;
 877
 878                 if (!pipe_ctx->stream ||
 879                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
 880                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 881
 882                         reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
 883                         if (old_clk)
 884                                 old_clk->funcs->cs_power_down(old_clk);
 885                 }
 886         }
 887
 888 }
 889
 890 static bool patch_address_for_sbs_tb_stereo(
 891                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 892 {
 893         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 894         bool sec_split = pipe_ctx->top_pipe &&
 895                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 896         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
 897                 (pipe_ctx->stream->timing.timing_3d_format ==
 898                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
 899                  pipe_ctx->stream->timing.timing_3d_format ==
 900                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
 901                 *addr = plane_state->address.grph_stereo.left_addr;
 902                 plane_state->address.grph_stereo.left_addr =
 903                 plane_state->address.grph_stereo.right_addr;
 904                 return true;
 905         } else {
 906                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
 907                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
 908                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 909                         plane_state->address.grph_stereo.right_addr =
 910                         plane_state->address.grph_stereo.left_addr;
 911                 }
 912         }
 913         return false;
 914 }
 915
 916
 917
 918 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 919 {
 920         bool addr_patched = false;
 921         PHYSICAL_ADDRESS_LOC addr;
 922         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 923
 924         if (plane_state == NULL)
 925                 return;
 926         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 927         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 928                         pipe_ctx->plane_res.hubp,
 929                         &plane_state->address,
 930                         plane_state->flip_immediate);
 931         plane_state->status.requested_address = plane_state->address;
 932         if (addr_patched)
 933                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 934 }
 935
 936 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 937                                           const struct dc_plane_state *plane_state)
 938 {
 939         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 940         const struct dc_transfer_func *tf = NULL;
 941         bool result = true;
 942
 943         if (dpp_base == NULL)
 944                 return false;
 945
 946         if (plane_state->in_transfer_func)
 947                 tf = plane_state->in_transfer_func;
 948
 949         if (plane_state->gamma_correction && dce_use_lut(plane_state))
 950                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 951
 952         if (tf == NULL)
 953                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 954         else if (tf->type == TF_TYPE_PREDEFINED) {
 955                 switch (tf->tf) {
 956                 case TRANSFER_FUNCTION_SRGB:
 957                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
 958                         break;
 959                 case TRANSFER_FUNCTION_BT709:
 960                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
 961                         break;
 962                 case TRANSFER_FUNCTION_LINEAR:
 963                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 964                         break;
 965                 case TRANSFER_FUNCTION_PQ:
 966                 default:
 967                         result = false;
 968                         break;
 969                 }
 970         } else if (tf->type == TF_TYPE_BYPASS) {
 971                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 972         } else {
 973                 /*TF_TYPE_DISTRIBUTED_POINTS*/
 974                 result = false;
 975         }
 976
 977         return result;
 978 }
 979
 980
 981
 982
 983
 984 static bool
 985 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 986                                const struct dc_stream_state *stream)
 987 {
 988         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 989
 990         if (dpp == NULL)
 991                 return false;
 992
 993         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 994
 995         if (stream->out_transfer_func &&
 996             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 997             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
 998                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
 999
1000         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1001          * update.
1002          */
1003         else if (cm_helper_translate_curve_to_hw_format(
1004                         stream->out_transfer_func,
1005                         &dpp->regamma_params, false)) {
1006                 dpp->funcs->dpp_program_regamma_pwl(
1007                                 dpp,
1008                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1009         } else
1010                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1011
1012         return true;
1013 }
1014
1015 static void dcn10_pipe_control_lock(
1016         struct dc *dc,
1017         struct pipe_ctx *pipe,
1018         bool lock)
1019 {
1020         struct hubp *hubp = NULL;
1021         hubp = dc->res_pool->hubps[pipe->pipe_idx];
1022         /* use TG master update lock to lock everything on the TG
1023          * therefore only top pipe need to lock
1024          */
1025         if (pipe->top_pipe)
1026                 return;
1027
1028         if (dc->debug.sanity_checks)
1029                 dcn10_verify_allow_pstate_change_high(dc);
1030
1031         if (lock)
1032                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1033         else
1034                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1035
1036         if (dc->debug.sanity_checks)
1037                 dcn10_verify_allow_pstate_change_high(dc);
1038 }
1039
1040 static bool wait_for_reset_trigger_to_occur(
1041         struct dc_context *dc_ctx,
1042         struct timing_generator *tg)
1043 {
1044         bool rc = false;
1045
1046         /* To avoid endless loop we wait at most
1047          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1048         const uint32_t frames_to_wait_on_triggered_reset = 10;
1049         int i;
1050
1051         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1052
1053                 if (!tg->funcs->is_counter_moving(tg)) {
1054                         DC_ERROR("TG counter is not moving!\n");
1055                         break;
1056                 }
1057
1058                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1059                         rc = true;
1060                         /* usually occurs at i=1 */
1061                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1062                                         i);
1063                         break;
1064                 }
1065
1066                 /* Wait for one frame. */
1067                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1068                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1069         }
1070
1071         if (false == rc)
1072                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1073
1074         return rc;
1075 }
1076
1077 static void dcn10_enable_timing_synchronization(
1078         struct dc *dc,
1079         int group_index,
1080         int group_size,
1081         struct pipe_ctx *grouped_pipes[])
1082 {
1083         struct dc_context *dc_ctx = dc->ctx;
1084         int i;
1085
1086         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1087
1088         for (i = 1; i < group_size; i++)
1089                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1090                                 grouped_pipes[i]->stream_res.tg,
1091                                 grouped_pipes[0]->stream_res.tg->inst);
1092
1093         DC_SYNC_INFO("Waiting for trigger\n");
1094
1095         /* Need to get only check 1 pipe for having reset as all the others are
1096          * synchronized. Look at last pipe programmed to reset.
1097          */
1098
1099         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1100         for (i = 1; i < group_size; i++)
1101                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1102                                 grouped_pipes[i]->stream_res.tg);
1103
1104         DC_SYNC_INFO("Sync complete\n");
1105 }
1106
1107 static void dcn10_enable_per_frame_crtc_position_reset(
1108         struct dc *dc,
1109         int group_size,
1110         struct pipe_ctx *grouped_pipes[])
1111 {
1112         struct dc_context *dc_ctx = dc->ctx;
1113         int i;
1114
1115         DC_SYNC_INFO("Setting up\n");
1116         for (i = 0; i < group_size; i++)
1117                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1118                                 grouped_pipes[i]->stream_res.tg,
1119                                 grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1120                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
1121
1122         DC_SYNC_INFO("Waiting for trigger\n");
1123
1124         for (i = 1; i < group_size; i++)
1125                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1126
1127         DC_SYNC_INFO("Multi-display sync is complete\n");
1128 }
1129
1130 /*static void print_rq_dlg_ttu(
1131                 struct dc *core_dc,
1132                 struct pipe_ctx *pipe_ctx)
1133 {
1134         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1135                         "\n============== DML TTU Output parameters [%d] ==============\n"
1136                         "qos_level_low_wm: %d, \n"
1137                         "qos_level_high_wm: %d, \n"
1138                         "min_ttu_vblank: %d, \n"
1139                         "qos_level_flip: %d, \n"
1140                         "refcyc_per_req_delivery_l: %d, \n"
1141                         "qos_level_fixed_l: %d, \n"
1142                         "qos_ramp_disable_l: %d, \n"
1143                         "refcyc_per_req_delivery_pre_l: %d, \n"
1144                         "refcyc_per_req_delivery_c: %d, \n"
1145                         "qos_level_fixed_c: %d, \n"
1146                         "qos_ramp_disable_c: %d, \n"
1147                         "refcyc_per_req_delivery_pre_c: %d\n"
1148                         "=============================================================\n",
1149                         pipe_ctx->pipe_idx,
1150                         pipe_ctx->ttu_regs.qos_level_low_wm,
1151                         pipe_ctx->ttu_regs.qos_level_high_wm,
1152                         pipe_ctx->ttu_regs.min_ttu_vblank,
1153                         pipe_ctx->ttu_regs.qos_level_flip,
1154                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1155                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1156                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1157                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1158                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1159                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1160                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1161                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1162                         );
1163
1164         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1165                         "\n============== DML DLG Output parameters [%d] ==============\n"
1166                         "refcyc_h_blank_end: %d, \n"
1167                         "dlg_vblank_end: %d, \n"
1168                         "min_dst_y_next_start: %d, \n"
1169                         "refcyc_per_htotal: %d, \n"
1170                         "refcyc_x_after_scaler: %d, \n"
1171                         "dst_y_after_scaler: %d, \n"
1172                         "dst_y_prefetch: %d, \n"
1173                         "dst_y_per_vm_vblank: %d, \n"
1174                         "dst_y_per_row_vblank: %d, \n"
1175                         "ref_freq_to_pix_freq: %d, \n"
1176                         "vratio_prefetch: %d, \n"
1177                         "refcyc_per_pte_group_vblank_l: %d, \n"
1178                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1179                         "dst_y_per_pte_row_nom_l: %d, \n"
1180                         "refcyc_per_pte_group_nom_l: %d, \n",
1181                         pipe_ctx->pipe_idx,
1182                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1183                         pipe_ctx->dlg_regs.dlg_vblank_end,
1184                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1185                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1186                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1187                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1188                         pipe_ctx->dlg_regs.dst_y_prefetch,
1189                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1190                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1191                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1192                         pipe_ctx->dlg_regs.vratio_prefetch,
1193                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1194                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1195                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1196                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1197                         );
1198
1199         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1200                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1201                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1202                         "refcyc_per_line_delivery_pre_l: %d, \n"
1203                         "refcyc_per_line_delivery_l: %d, \n"
1204                         "vratio_prefetch_c: %d, \n"
1205                         "refcyc_per_pte_group_vblank_c: %d, \n"
1206                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1207                         "dst_y_per_pte_row_nom_c: %d, \n"
1208                         "refcyc_per_pte_group_nom_c: %d, \n"
1209                         "dst_y_per_meta_row_nom_c: %d, \n"
1210                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1211                         "refcyc_per_line_delivery_pre_c: %d, \n"
1212                         "refcyc_per_line_delivery_c: %d \n"
1213                         "========================================================\n",
1214                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1215                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1216                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1217                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1218                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1219                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1220                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1221                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1222                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1223                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1224                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1225                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1226                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1227                         );
1228
1229         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1230                         "\n============== DML RQ Output parameters [%d] ==============\n"
1231                         "chunk_size: %d \n"
1232                         "min_chunk_size: %d \n"
1233                         "meta_chunk_size: %d \n"
1234                         "min_meta_chunk_size: %d \n"
1235                         "dpte_group_size: %d \n"
1236                         "mpte_group_size: %d \n"
1237                         "swath_height: %d \n"
1238                         "pte_row_height_linear: %d \n"
1239                         "========================================================\n",
1240                         pipe_ctx->pipe_idx,
1241                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1242                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1243                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1244                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1245                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1246                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1247                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1248                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1249                         );
1250 }
1251 */
1252
1253 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1254                 struct vm_system_aperture_param *apt,
1255                 struct dce_hwseq *hws)
1256 {
1257         PHYSICAL_ADDRESS_LOC physical_page_number;
1258         uint32_t logical_addr_low;
1259         uint32_t logical_addr_high;
1260
1261         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1262                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1263         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1264                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1265
1266         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1267                         LOGICAL_ADDR, &logical_addr_low);
1268
1269         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1270                         LOGICAL_ADDR, &logical_addr_high);
1271
1272         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1273         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1274         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1275 }
1276
1277 /* Temporary read settings, future will get values from kmd directly */
1278 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1279                 struct vm_context0_param *vm0,
1280                 struct dce_hwseq *hws)
1281 {
1282         PHYSICAL_ADDRESS_LOC fb_base;
1283         PHYSICAL_ADDRESS_LOC fb_offset;
1284         uint32_t fb_base_value;
1285         uint32_t fb_offset_value;
1286
1287         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1288         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1289
1290         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1291                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1292         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1293                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1294
1295         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1296                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1297         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1298                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1299
1300         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1301                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1302         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1303                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1304
1305         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1306                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1307         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1308                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1309
1310         /*
1311          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1312          * Therefore we need to do
1313          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1314          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1315          */
1316         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1317         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1318         vm0->pte_base.quad_part += fb_base.quad_part;
1319         vm0->pte_base.quad_part -= fb_offset.quad_part;
1320 }
1321
1322
1323 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1324 {
1325         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1326         struct vm_system_aperture_param apt = { {{ 0 } } };
1327         struct vm_context0_param vm0 = { { { 0 } } };
1328
1329         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1330         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1331
1332         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1333         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1334 }
1335
1336 static void dcn10_enable_plane(
1337         struct dc *dc,
1338         struct pipe_ctx *pipe_ctx,
1339         struct dc_state *context)
1340 {
1341         struct dce_hwseq *hws = dc->hwseq;
1342
1343         if (dc->debug.sanity_checks) {
1344                 dcn10_verify_allow_pstate_change_high(dc);
1345         }
1346
1347         undo_DEGVIDCN10_253_wa(dc);
1348
1349         power_on_plane(dc->hwseq,
1350                 pipe_ctx->pipe_idx);
1351
1352         /* enable DCFCLK current DCHUB */
1353         REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1354                         HUBP_CLOCK_ENABLE, 1);
1355
1356         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1357         REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
1358                         OPP_PIPE_CLOCK_EN, 1);
1359
1360 /* TODO: enable/disable in dm as per update type.
1361         if (plane_state) {
1362                 dm_logger_write(dc->ctx->logger, LOG_DC,
1363                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1364                                 "addr low:0x%x, "
1365                                 "src: %d, %d, %d,"
1366                                 " %d; dst: %d, %d, %d, %d;\n",
1367                                 pipe_ctx->pipe_idx,
1368                                 plane_state,
1369                                 plane_state->address.grph.addr.high_part,
1370                                 plane_state->address.grph.addr.low_part,
1371                                 plane_state->src_rect.x,
1372                                 plane_state->src_rect.y,
1373                                 plane_state->src_rect.width,
1374                                 plane_state->src_rect.height,
1375                                 plane_state->dst_rect.x,
1376                                 plane_state->dst_rect.y,
1377                                 plane_state->dst_rect.width,
1378                                 plane_state->dst_rect.height);
1379
1380                 dm_logger_write(dc->ctx->logger, LOG_DC,
1381                                 "Pipe %d: width, height, x, y         format:%d\n"
1382                                 "viewport:%d, %d, %d, %d\n"
1383                                 "recout:  %d, %d, %d, %d\n",
1384                                 pipe_ctx->pipe_idx,
1385                                 plane_state->format,
1386                                 pipe_ctx->plane_res.scl_data.viewport.width,
1387                                 pipe_ctx->plane_res.scl_data.viewport.height,
1388                                 pipe_ctx->plane_res.scl_data.viewport.x,
1389                                 pipe_ctx->plane_res.scl_data.viewport.y,
1390                                 pipe_ctx->plane_res.scl_data.recout.width,
1391                                 pipe_ctx->plane_res.scl_data.recout.height,
1392                                 pipe_ctx->plane_res.scl_data.recout.x,
1393                                 pipe_ctx->plane_res.scl_data.recout.y);
1394                 print_rq_dlg_ttu(dc, pipe_ctx);
1395         }
1396 */
1397         if (dc->config.gpu_vm_support)
1398                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1399
1400         if (dc->debug.sanity_checks) {
1401                 dcn10_verify_allow_pstate_change_high(dc);
1402         }
1403 }
1404
1405 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1406 {
1407         struct dpp_grph_csc_adjustment adjust;
1408         memset(&adjust, 0, sizeof(adjust));
1409         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1410
1411
1412         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1413                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1414                 adjust.temperature_matrix[0] =
1415                                 pipe_ctx->stream->
1416                                 gamut_remap_matrix.matrix[0];
1417                 adjust.temperature_matrix[1] =
1418                                 pipe_ctx->stream->
1419                                 gamut_remap_matrix.matrix[1];
1420                 adjust.temperature_matrix[2] =
1421                                 pipe_ctx->stream->
1422                                 gamut_remap_matrix.matrix[2];
1423                 adjust.temperature_matrix[3] =
1424                                 pipe_ctx->stream->
1425                                 gamut_remap_matrix.matrix[4];
1426                 adjust.temperature_matrix[4] =
1427                                 pipe_ctx->stream->
1428                                 gamut_remap_matrix.matrix[5];
1429                 adjust.temperature_matrix[5] =
1430                                 pipe_ctx->stream->
1431                                 gamut_remap_matrix.matrix[6];
1432                 adjust.temperature_matrix[6] =
1433                                 pipe_ctx->stream->
1434                                 gamut_remap_matrix.matrix[8];
1435                 adjust.temperature_matrix[7] =
1436                                 pipe_ctx->stream->
1437                                 gamut_remap_matrix.matrix[9];
1438                 adjust.temperature_matrix[8] =
1439                                 pipe_ctx->stream->
1440                                 gamut_remap_matrix.matrix[10];
1441         }
1442
1443         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1444 }
1445
1446
1447 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1448                 enum dc_color_space colorspace,
1449                 uint16_t *matrix)
1450 {
1451         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1452                         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1453                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1454         } else {
1455                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1456                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1457         }
1458 }
1459
1460 static void program_output_csc(struct dc *dc,
1461                 struct pipe_ctx *pipe_ctx,
1462                 enum dc_color_space colorspace,
1463                 uint16_t *matrix,
1464                 int opp_id)
1465 {
1466         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1467                 program_csc_matrix(pipe_ctx,
1468                                 colorspace,
1469                                 matrix);
1470 }
1471
1472 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1473 {
1474         if (pipe_ctx->plane_state->visible)
1475                 return true;
1476         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1477                 return true;
1478         return false;
1479 }
1480
1481 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1482 {
1483         if (pipe_ctx->plane_state->visible)
1484                 return true;
1485         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1486                 return true;
1487         return false;
1488 }
1489
1490 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1491 {
1492         if (pipe_ctx->plane_state->visible)
1493                 return true;
1494         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1495                 return true;
1496         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1497                 return true;
1498         return false;
1499 }
1500
1501 static bool is_rgb_cspace(enum dc_color_space output_color_space)
1502 {
1503         switch (output_color_space) {
1504         case COLOR_SPACE_SRGB:
1505         case COLOR_SPACE_SRGB_LIMITED:
1506         case COLOR_SPACE_2020_RGB_FULLRANGE:
1507         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1508         case COLOR_SPACE_ADOBERGB:
1509                 return true;
1510         case COLOR_SPACE_YCBCR601:
1511         case COLOR_SPACE_YCBCR709:
1512         case COLOR_SPACE_YCBCR601_LIMITED:
1513         case COLOR_SPACE_YCBCR709_LIMITED:
1514         case COLOR_SPACE_2020_YCBCR:
1515                 return false;
1516         default:
1517                 /* Add a case to switch */
1518                 BREAK_TO_DEBUGGER();
1519                 return false;
1520         }
1521 }
1522
1523 static void dcn10_get_surface_visual_confirm_color(
1524                 const struct pipe_ctx *pipe_ctx,
1525                 struct tg_color *color)
1526 {
1527         uint32_t color_value = MAX_TG_COLOR_VALUE;
1528
1529         switch (pipe_ctx->plane_res.scl_data.format) {
1530         case PIXEL_FORMAT_ARGB8888:
1531                 /* set boarder color to red */
1532                 color->color_r_cr = color_value;
1533                 break;
1534
1535         case PIXEL_FORMAT_ARGB2101010:
1536                 /* set boarder color to blue */
1537                 color->color_b_cb = color_value;
1538                 break;
1539         case PIXEL_FORMAT_420BPP8:
1540                 /* set boarder color to green */
1541                 color->color_g_y = color_value;
1542                 break;
1543         case PIXEL_FORMAT_420BPP10:
1544                 /* set boarder color to yellow */
1545                 color->color_g_y = color_value;
1546                 color->color_r_cr = color_value;
1547                 break;
1548         case PIXEL_FORMAT_FP16:
1549                 /* set boarder color to white */
1550                 color->color_r_cr = color_value;
1551                 color->color_b_cb = color_value;
1552                 color->color_g_y = color_value;
1553                 break;
1554         default:
1555                 break;
1556         }
1557 }
1558
1559 static uint16_t fixed_point_to_int_frac(
1560         struct fixed31_32 arg,
1561         uint8_t integer_bits,
1562         uint8_t fractional_bits)
1563 {
1564         int32_t numerator;
1565         int32_t divisor = 1 << fractional_bits;
1566
1567         uint16_t result;
1568
1569         uint16_t d = (uint16_t)dal_fixed31_32_floor(
1570                 dal_fixed31_32_abs(
1571                         arg));
1572
1573         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1574                 numerator = (uint16_t)dal_fixed31_32_floor(
1575                         dal_fixed31_32_mul_int(
1576                                 arg,
1577                                 divisor));
1578         else {
1579                 numerator = dal_fixed31_32_floor(
1580                         dal_fixed31_32_sub(
1581                                 dal_fixed31_32_from_int(
1582                                         1LL << integer_bits),
1583                                 dal_fixed31_32_recip(
1584                                         dal_fixed31_32_from_int(
1585                                                 divisor))));
1586         }
1587
1588         if (numerator >= 0)
1589                 result = (uint16_t)numerator;
1590         else
1591                 result = (uint16_t)(
1592                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1593
1594         if ((result != 0) && dal_fixed31_32_lt(
1595                 arg, dal_fixed31_32_zero))
1596                 result |= 1 << (integer_bits + fractional_bits);
1597
1598         return result;
1599 }
1600
1601 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1602                 const struct dc_plane_state *plane_state)
1603 {
1604         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1605                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1606                         && plane_state->input_csc_color_matrix.enable_adjustment
1607                         && plane_state->coeff_reduction_factor.value != 0) {
1608                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1609                         dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
1610                                         dal_fixed31_32_from_fraction(256, 255)),
1611                                 2,
1612                                 13);
1613                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1614                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1615         } else {
1616                 bias_and_scale->scale_blue = 0x2000;
1617                 bias_and_scale->scale_red = 0x2000;
1618                 bias_and_scale->scale_green = 0x2000;
1619         }
1620 }
1621
1622 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1623 {
1624         struct dc_bias_and_scale bns_params = {0};
1625
1626         // program the input csc
1627         dpp->funcs->dpp_setup(dpp,
1628                         plane_state->format,
1629                         EXPANSION_MODE_ZERO,
1630                         plane_state->input_csc_color_matrix,
1631                         COLOR_SPACE_YCBCR601_LIMITED);
1632
1633         //set scale and bias registers
1634         build_prescale_params(&bns_params, plane_state);
1635         if (dpp->funcs->dpp_program_bias_and_scale)
1636                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1637 }
1638
1639 static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1640 {
1641         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1642         struct mpcc_blnd_cfg blnd_cfg;
1643         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1644         int mpcc_id;
1645         struct mpcc *new_mpcc;
1646         struct mpc *mpc = dc->res_pool->mpc;
1647         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1648
1649         /* TODO: proper fix once fpga works */
1650
1651         if (dc->debug.surface_visual_confirm)
1652                 dcn10_get_surface_visual_confirm_color(
1653                                 pipe_ctx, &blnd_cfg.black_color);
1654         else
1655                 color_space_to_black_color(
1656                         dc, pipe_ctx->stream->output_color_space,
1657                         &blnd_cfg.black_color);
1658
1659         if (per_pixel_alpha)
1660                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1661         else
1662                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1663
1664         blnd_cfg.overlap_only = false;
1665         blnd_cfg.global_alpha = 0xff;
1666         blnd_cfg.global_gain = 0xff;
1667
1668         /* DCN1.0 has output CM before MPC which seems to screw with
1669          * pre-multiplied alpha.
1670          */
1671         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1672                         pipe_ctx->stream->output_color_space)
1673                                         && per_pixel_alpha;
1674
1675         /*
1676          * TODO: remove hack
1677          * Note: currently there is a bug in init_hw such that
1678          * on resume from hibernate, BIOS sets up MPCC0, and
1679          * we do mpcc_remove but the mpcc cannot go to idle
1680          * after remove. This cause us to pick mpcc1 here,
1681          * which causes a pstate hang for yet unknown reason.
1682          */
1683         mpcc_id = hubp->inst;
1684
1685         /* check if this MPCC is already being used */
1686         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1687         /* remove MPCC if being used */
1688         if (new_mpcc != NULL)
1689                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1690         else
1691                 if (dc->debug.sanity_checks)
1692                         mpc->funcs->assert_mpcc_idle_before_connect(
1693                                         dc->res_pool->mpc, mpcc_id);
1694
1695         /* Call MPC to insert new plane */
1696         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1697                         mpc_tree_params,
1698                         &blnd_cfg,
1699                         NULL,
1700                         NULL,
1701                         hubp->inst,
1702                         mpcc_id);
1703
1704         ASSERT(new_mpcc != NULL);
1705
1706         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1707         hubp->mpcc_id = mpcc_id;
1708 }
1709
1710 static void update_scaler(struct pipe_ctx *pipe_ctx)
1711 {
1712         bool per_pixel_alpha =
1713                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1714
1715         /* TODO: proper fix once fpga works */
1716
1717         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1718         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1719         /* scaler configuration */
1720         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1721                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1722 }
1723
1724 static void update_dchubp_dpp(
1725         struct dc *dc,
1726         struct pipe_ctx *pipe_ctx,
1727         struct dc_state *context)
1728 {
1729         struct dce_hwseq *hws = dc->hwseq;
1730         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1731         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1732         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1733         union plane_size size = plane_state->plane_size;
1734
1735         /* depends on DML calculation, DPP clock value may change dynamically */
1736         if (plane_state->update_flags.bits.full_update) {
1737                 enable_dppclk(
1738                         dc->hwseq,
1739                         pipe_ctx->pipe_idx,
1740                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
1741                         context->bw.dcn.calc_clk.dppclk_div);
1742                 dc->current_state->bw.dcn.cur_clk.dppclk_div =
1743                                 context->bw.dcn.calc_clk.dppclk_div;
1744                 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
1745         }
1746
1747         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1748          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1749          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1750          */
1751         if (plane_state->update_flags.bits.full_update) {
1752                 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
1753
1754                 hubp->funcs->hubp_setup(
1755                         hubp,
1756                         &pipe_ctx->dlg_regs,
1757                         &pipe_ctx->ttu_regs,
1758                         &pipe_ctx->rq_regs,
1759                         &pipe_ctx->pipe_dlg_param);
1760         }
1761
1762         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1763
1764         if (plane_state->update_flags.bits.full_update ||
1765                 plane_state->update_flags.bits.bpp_change)
1766                 update_dpp(dpp, plane_state);
1767
1768         if (plane_state->update_flags.bits.full_update ||
1769                 plane_state->update_flags.bits.per_pixel_alpha_change)
1770                 update_mpcc(dc, pipe_ctx);
1771
1772         if (plane_state->update_flags.bits.full_update ||
1773                 plane_state->update_flags.bits.per_pixel_alpha_change ||
1774                 plane_state->update_flags.bits.scaling_change ||
1775                 plane_state->update_flags.bits.position_change) {
1776                 update_scaler(pipe_ctx);
1777         }
1778
1779         if (plane_state->update_flags.bits.full_update ||
1780                 plane_state->update_flags.bits.scaling_change ||
1781                 plane_state->update_flags.bits.position_change) {
1782                 hubp->funcs->mem_program_viewport(
1783                         hubp,
1784                         &pipe_ctx->plane_res.scl_data.viewport,
1785                         &pipe_ctx->plane_res.scl_data.viewport_c);
1786         }
1787
1788         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1789                 dc->hwss.set_cursor_position(pipe_ctx);
1790                 dc->hwss.set_cursor_attribute(pipe_ctx);
1791         }
1792
1793         if (plane_state->update_flags.bits.full_update) {
1794                 /*gamut remap*/
1795                 program_gamut_remap(pipe_ctx);
1796
1797                 program_output_csc(dc,
1798                                 pipe_ctx,
1799                                 pipe_ctx->stream->output_color_space,
1800                                 pipe_ctx->stream->csc_color_matrix.matrix,
1801                                 hubp->opp_id);
1802         }
1803
1804         if (plane_state->update_flags.bits.full_update ||
1805                 plane_state->update_flags.bits.horizontal_mirror_change ||
1806                 plane_state->update_flags.bits.rotation_change ||
1807                 plane_state->update_flags.bits.swizzle_change ||
1808                 plane_state->update_flags.bits.dcc_change ||
1809                 plane_state->update_flags.bits.bpp_change ||
1810                 plane_state->update_flags.bits.scaling_change) {
1811                 hubp->funcs->hubp_program_surface_config(
1812                         hubp,
1813                         plane_state->format,
1814                         &plane_state->tiling_info,
1815                         &size,
1816                         plane_state->rotation,
1817                         &plane_state->dcc,
1818                         plane_state->horizontal_mirror);
1819         }
1820
1821         hubp->power_gated = false;
1822
1823         dc->hwss.update_plane_addr(dc, pipe_ctx);
1824
1825         if (is_pipe_tree_visible(pipe_ctx))
1826                 hubp->funcs->set_blank(hubp, false);
1827 }
1828
1829
1830 static void program_all_pipe_in_tree(
1831                 struct dc *dc,
1832                 struct pipe_ctx *pipe_ctx,
1833                 struct dc_state *context)
1834 {
1835
1836         if (pipe_ctx->top_pipe == NULL) {
1837
1838                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1839                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1840                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1841                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1842                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
1843
1844                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1845                                 pipe_ctx->stream_res.tg);
1846
1847                 if (pipe_ctx->stream_res.tg->funcs->set_blank)
1848                         pipe_ctx->stream_res.tg->funcs->set_blank(
1849                                         pipe_ctx->stream_res.tg,
1850                                         !is_pipe_tree_visible(pipe_ctx));
1851         }
1852
1853         if (pipe_ctx->plane_state != NULL) {
1854                 struct pipe_ctx *cur_pipe_ctx =
1855                                 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1856
1857                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1858                         dcn10_enable_plane(dc, pipe_ctx, context);
1859
1860                 update_dchubp_dpp(dc, pipe_ctx, context);
1861
1862                 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state)
1863                         dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1864
1865                 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1866                  * only do gamma programming for full update.
1867                  * TODO: This can be further optimized/cleaned up
1868                  * Always call this for now since it does memcmp inside before
1869                  * doing heavy calculation and programming
1870                  */
1871                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1872                         dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1873         }
1874
1875         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
1876                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1877 }
1878
1879 static void dcn10_pplib_apply_display_requirements(
1880         struct dc *dc,
1881         struct dc_state *context)
1882 {
1883         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1884
1885         pp_display_cfg->all_displays_in_sync = false;/*todo*/
1886         pp_display_cfg->nb_pstate_switch_disable = false;
1887         pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1888         pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
1889         pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1890         pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1891         pp_display_cfg->avail_mclk_switch_time_us =
1892                         context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
1893         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
1894                         context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
1895         pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1896         pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
1897         dce110_fill_display_configs(context, pp_display_cfg);
1898
1899         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
1900                         struct dm_pp_display_configuration)) !=  0)
1901                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
1902
1903         dc->prev_display_config = *pp_display_cfg;
1904 }
1905
1906 static void optimize_shared_resources(struct dc *dc)
1907 {
1908         if (dc->current_state->stream_count == 0) {
1909                 /* S0i2 message */
1910                 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
1911         }
1912
1913         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
1914                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1915 }
1916
1917 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
1918 {
1919         /* S0i2 message */
1920         if (dc->current_state->stream_count == 0 &&
1921                         context->stream_count != 0)
1922                 dcn10_pplib_apply_display_requirements(dc, context);
1923 }
1924
1925 static struct pipe_ctx *find_top_pipe_for_stream(
1926                 struct dc *dc,
1927                 struct dc_state *context,
1928                 const struct dc_stream_state *stream)
1929 {
1930         int i;
1931
1932         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1933                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1934                 struct pipe_ctx *old_pipe_ctx =
1935                                 &dc->current_state->res_ctx.pipe_ctx[i];
1936
1937                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
1938                         continue;
1939
1940                 if (pipe_ctx->stream != stream)
1941                         continue;
1942
1943                 if (!pipe_ctx->top_pipe)
1944                         return pipe_ctx;
1945         }
1946         return NULL;
1947 }
1948
1949 static void dcn10_apply_ctx_for_surface(
1950                 struct dc *dc,
1951                 const struct dc_stream_state *stream,
1952                 int num_planes,
1953                 struct dc_state *context)
1954 {
1955         int i;
1956         struct timing_generator *tg;
1957         struct output_pixel_processor *opp;
1958         bool removed_pipe[4] = { false };
1959         unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1960         bool program_water_mark = false;
1961
1962         struct pipe_ctx *top_pipe_to_program =
1963                         find_top_pipe_for_stream(dc, context, stream);
1964
1965         if (!top_pipe_to_program)
1966                 return;
1967
1968         opp = top_pipe_to_program->stream_res.opp;
1969
1970         tg = top_pipe_to_program->stream_res.tg;
1971
1972         tg->funcs->lock(tg);
1973
1974         if (num_planes == 0) {
1975
1976                 /* OTG blank before remove all front end */
1977                 if (tg->funcs->set_blank)
1978                         tg->funcs->set_blank(tg, true);
1979         }
1980
1981         /* Disconnect unused mpcc */
1982         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1983                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1984                 struct pipe_ctx *old_pipe_ctx =
1985                                 &dc->current_state->res_ctx.pipe_ctx[i];
1986                 /*
1987                  * Powergate reused pipes that are not powergated
1988                  * fairly hacky right now, using opp_id as indicator
1989                  * TODO: After move dc_post to dc_update, this will
1990                  * be removed.
1991                  */
1992                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1993                         if (old_pipe_ctx->stream_res.tg == tg &&
1994                                 old_pipe_ctx->plane_res.hubp &&
1995                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
1996                                 dcn10_disable_plane(dc, pipe_ctx);
1997                                 /*
1998                                  * power down fe will unlock when calling reset, need
1999                                  * to lock it back here. Messy, need rework.
2000                                  */
2001                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
2002                         }
2003                 }
2004
2005                 if (!pipe_ctx->plane_state &&
2006                         old_pipe_ctx->plane_state &&
2007                         old_pipe_ctx->stream_res.tg == tg) {
2008
2009                         plane_atomic_disconnect(dc, old_pipe_ctx);
2010                         removed_pipe[i] = true;
2011
2012                         dm_logger_write(dc->ctx->logger, LOG_DC,
2013                                         "Reset mpcc for pipe %d\n",
2014                                         old_pipe_ctx->pipe_idx);
2015                 }
2016         }
2017
2018         if (num_planes > 0)
2019                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2020
2021         tg->funcs->unlock(tg);
2022
2023         if (num_planes == 0)
2024                 false_optc_underflow_wa(dc, stream, tg);
2025
2026         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2027                 struct pipe_ctx *old_pipe_ctx =
2028                                 &dc->current_state->res_ctx.pipe_ctx[i];
2029                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2030
2031                 if (pipe_ctx->stream == stream &&
2032                                 pipe_ctx->plane_state &&
2033                         pipe_ctx->plane_state->update_flags.bits.full_update)
2034                         program_water_mark = true;
2035
2036                 if (removed_pipe[i])
2037                         dcn10_disable_plane(dc, old_pipe_ctx);
2038         }
2039
2040         if (program_water_mark) {
2041                 if (dc->debug.sanity_checks) {
2042                         /* pstate stuck check after watermark update */
2043                         dcn10_verify_allow_pstate_change_high(dc);
2044                 }
2045
2046                 /* watermark is for all pipes */
2047                 hubbub1_program_watermarks(dc->res_pool->hubbub,
2048                                 &context->bw.dcn.watermarks, ref_clk_mhz);
2049
2050                 if (dc->debug.sanity_checks) {
2051                         /* pstate stuck check after watermark update */
2052                         dcn10_verify_allow_pstate_change_high(dc);
2053                 }
2054         }
2055 /*      dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2056                         "\n============== Watermark parameters ==============\n"
2057                         "a.urgent_ns: %d \n"
2058                         "a.cstate_enter_plus_exit: %d \n"
2059                         "a.cstate_exit: %d \n"
2060                         "a.pstate_change: %d \n"
2061                         "a.pte_meta_urgent: %d \n"
2062                         "b.urgent_ns: %d \n"
2063                         "b.cstate_enter_plus_exit: %d \n"
2064                         "b.cstate_exit: %d \n"
2065                         "b.pstate_change: %d \n"
2066                         "b.pte_meta_urgent: %d \n",
2067                         context->bw.dcn.watermarks.a.urgent_ns,
2068                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2069                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2070                         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2071                         context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2072                         context->bw.dcn.watermarks.b.urgent_ns,
2073                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2074                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2075                         context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2076                         context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2077                         );
2078         dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2079                         "\nc.urgent_ns: %d \n"
2080                         "c.cstate_enter_plus_exit: %d \n"
2081                         "c.cstate_exit: %d \n"
2082                         "c.pstate_change: %d \n"
2083                         "c.pte_meta_urgent: %d \n"
2084                         "d.urgent_ns: %d \n"
2085                         "d.cstate_enter_plus_exit: %d \n"
2086                         "d.cstate_exit: %d \n"
2087                         "d.pstate_change: %d \n"
2088                         "d.pte_meta_urgent: %d \n"
2089                         "========================================================\n",
2090                         context->bw.dcn.watermarks.c.urgent_ns,
2091                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2092                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2093                         context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2094                         context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2095                         context->bw.dcn.watermarks.d.urgent_ns,
2096                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2097                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2098                         context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2099                         context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2100                         );
2101 */
2102 }
2103
2104 static void dcn10_set_bandwidth(
2105                 struct dc *dc,
2106                 struct dc_state *context,
2107                 bool decrease_allowed)
2108 {
2109         struct pp_smu_display_requirement_rv *smu_req_cur =
2110                         &dc->res_pool->pp_smu_req;
2111         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2112         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
2113
2114         if (dc->debug.sanity_checks) {
2115                 dcn10_verify_allow_pstate_change_high(dc);
2116         }
2117
2118         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2119                 return;
2120
2121         if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2122                         > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2123                 dc->res_pool->display_clock->funcs->set_clock(
2124                                 dc->res_pool->display_clock,
2125                                 context->bw.dcn.calc_clk.dispclk_khz);
2126                 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
2127                                 context->bw.dcn.calc_clk.dispclk_khz;
2128         }
2129         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2130                         > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2131                 smu_req.hard_min_dcefclk_khz =
2132                                 context->bw.dcn.calc_clk.dcfclk_khz;
2133         }
2134         if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2135                         > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2136                 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
2137         }
2138         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2139                         > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2140                 dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
2141                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2142                 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2143                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2144         }
2145
2146         smu_req.display_count = context->stream_count;
2147
2148         if (pp_smu->set_display_requirement)
2149                 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2150
2151         *smu_req_cur = smu_req;
2152
2153         /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2154         if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2155                         < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2156                 dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
2157                                 context->bw.dcn.calc_clk.dram_ccm_us;
2158                 context->bw.dcn.cur_clk.dram_ccm_us =
2159                                 context->bw.dcn.calc_clk.dram_ccm_us;
2160         }
2161         if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2162                         < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2163                 dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
2164                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2165                 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2166                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2167         }
2168         dcn10_pplib_apply_display_requirements(dc, context);
2169
2170         if (dc->debug.sanity_checks) {
2171                 dcn10_verify_allow_pstate_change_high(dc);
2172         }
2173
2174         /* need to fix this function.  not doing the right thing here */
2175 }
2176
2177 static void set_drr(struct pipe_ctx **pipe_ctx,
2178                 int num_pipes, int vmin, int vmax)
2179 {
2180         int i = 0;
2181         struct drr_params params = {0};
2182
2183         params.vertical_total_max = vmax;
2184         params.vertical_total_min = vmin;
2185
2186         /* TODO: If multiple pipes are to be supported, you need
2187          * some GSL stuff
2188          */
2189         for (i = 0; i < num_pipes; i++) {
2190                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
2191         }
2192 }
2193
2194 static void get_position(struct pipe_ctx **pipe_ctx,
2195                 int num_pipes,
2196                 struct crtc_position *position)
2197 {
2198         int i = 0;
2199
2200         /* TODO: handle pipes > 1
2201          */
2202         for (i = 0; i < num_pipes; i++)
2203                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2204 }
2205
2206 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2207                 int num_pipes, const struct dc_static_screen_events *events)
2208 {
2209         unsigned int i;
2210         unsigned int value = 0;
2211
2212         if (events->surface_update)
2213                 value |= 0x80;
2214         if (events->cursor_update)
2215                 value |= 0x2;
2216
2217         for (i = 0; i < num_pipes; i++)
2218                 pipe_ctx[i]->stream_res.tg->funcs->
2219                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2220 }
2221
2222 static void set_plane_config(
2223         const struct dc *dc,
2224         struct pipe_ctx *pipe_ctx,
2225         struct resource_context *res_ctx)
2226 {
2227         /* TODO */
2228         program_gamut_remap(pipe_ctx);
2229 }
2230
2231 static void dcn10_config_stereo_parameters(
2232                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2233 {
2234         enum view_3d_format view_format = stream->view_format;
2235         enum dc_timing_3d_format timing_3d_format =\
2236                         stream->timing.timing_3d_format;
2237         bool non_stereo_timing = false;
2238
2239         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2240                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2241                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2242                 non_stereo_timing = true;
2243
2244         if (non_stereo_timing == false &&
2245                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2246
2247                 flags->PROGRAM_STEREO         = 1;
2248                 flags->PROGRAM_POLARITY       = 1;
2249                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2250                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2251                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2252                         enum display_dongle_type dongle = \
2253                                         stream->sink->link->ddc->dongle_type;
2254                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2255                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2256                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2257                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2258                 }
2259                 flags->RIGHT_EYE_POLARITY =\
2260                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2261                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2262                         flags->FRAME_PACKED = 1;
2263         }
2264
2265         return;
2266 }
2267
2268 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2269 {
2270         struct crtc_stereo_flags flags = { 0 };
2271         struct dc_stream_state *stream = pipe_ctx->stream;
2272
2273         dcn10_config_stereo_parameters(stream, &flags);
2274
2275         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2276                 pipe_ctx->stream_res.opp,
2277                 flags.PROGRAM_STEREO == 1 ? true:false,
2278                 &stream->timing);
2279
2280         pipe_ctx->stream_res.tg->funcs->program_stereo(
2281                 pipe_ctx->stream_res.tg,
2282                 &stream->timing,
2283                 &flags);
2284
2285         return;
2286 }
2287
2288 static void dcn10_wait_for_mpcc_disconnect(
2289                 struct dc *dc,
2290                 struct resource_pool *res_pool,
2291                 struct pipe_ctx *pipe_ctx)
2292 {
2293         int i;
2294
2295         if (dc->debug.sanity_checks) {
2296                 dcn10_verify_allow_pstate_change_high(dc);
2297         }
2298
2299         if (!pipe_ctx->stream_res.opp)
2300                 return;
2301
2302         for (i = 0; i < MAX_PIPES; i++) {
2303                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
2304                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
2305                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
2306                         res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
2307                         /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2308                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2309                                         i);*/
2310                 }
2311         }
2312
2313         if (dc->debug.sanity_checks) {
2314                 dcn10_verify_allow_pstate_change_high(dc);
2315         }
2316
2317 }
2318
2319 static bool dcn10_dummy_display_power_gating(
2320         struct dc *dc,
2321         uint8_t controller_id,
2322         struct dc_bios *dcb,
2323         enum pipe_gating_control power_gating)
2324 {
2325         return true;
2326 }
2327
2328 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2329 {
2330         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2331         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2332
2333         if (plane_state == NULL)
2334                 return;
2335
2336         plane_state->status.is_flip_pending =
2337                         pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2338                                         pipe_ctx->plane_res.hubp);
2339
2340         plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2341         if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2342                         tg->funcs->is_stereo_left_eye) {
2343                 plane_state->status.is_right_eye =
2344                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2345         }
2346 }
2347
2348 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2349 {
2350         if (hws->ctx->dc->res_pool->hubbub != NULL)
2351                 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2352 }
2353
2354 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2355 {
2356         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2357         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2358         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2359         struct dc_cursor_mi_param param = {
2360                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2361                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2362                 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2363                 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2364                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2365         };
2366
2367         if (pipe_ctx->plane_state->address.type
2368                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2369                 pos_cpy.enable = false;
2370
2371         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2372                 pos_cpy.enable = false;
2373
2374         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2375         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
2376 }
2377
2378 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2379 {
2380         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2381
2382         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2383                         pipe_ctx->plane_res.hubp, attributes);
2384         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2385                 pipe_ctx->plane_res.dpp, attributes->color_format);
2386 }
2387
2388 static const struct hw_sequencer_funcs dcn10_funcs = {
2389         .program_gamut_remap = program_gamut_remap,
2390         .program_csc_matrix = program_csc_matrix,
2391         .init_hw = dcn10_init_hw,
2392         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2393         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2394         .set_plane_config = set_plane_config,
2395         .update_plane_addr = dcn10_update_plane_addr,
2396         .update_dchub = dcn10_update_dchub,
2397         .update_pending_status = dcn10_update_pending_status,
2398         .set_input_transfer_func = dcn10_set_input_transfer_func,
2399         .set_output_transfer_func = dcn10_set_output_transfer_func,
2400         .power_down = dce110_power_down,
2401         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2402         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2403         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2404         .update_info_frame = dce110_update_info_frame,
2405         .enable_stream = dce110_enable_stream,
2406         .disable_stream = dce110_disable_stream,
2407         .unblank_stream = dce110_unblank_stream,
2408         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2409         .disable_plane = dcn10_disable_plane,
2410         .pipe_control_lock = dcn10_pipe_control_lock,
2411         .set_bandwidth = dcn10_set_bandwidth,
2412         .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2413         .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2414         .set_drr = set_drr,
2415         .get_position = get_position,
2416         .set_static_screen_control = set_static_screen_control,
2417         .setup_stereo = dcn10_setup_stereo,
2418         .set_avmute = dce110_set_avmute,
2419         .log_hw_state = dcn10_log_hw_state,
2420         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2421         .ready_shared_resources = ready_shared_resources,
2422         .optimize_shared_resources = optimize_shared_resources,
2423         .pplib_apply_display_requirements =
2424                         dcn10_pplib_apply_display_requirements,
2425         .edp_backlight_control = hwss_edp_backlight_control,
2426         .edp_power_control = hwss_edp_power_control,
2427         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2428         .set_cursor_position = dcn10_set_cursor_position,
2429         .set_cursor_attribute = dcn10_set_cursor_attribute
2430 };
2431
2432
2433 void dcn10_hw_sequencer_construct(struct dc *dc)
2434 {
2435         dc->hwss = dcn10_funcs;
2436 }
2437