drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce/dce_8_0_d.h"
  27 #include "dce/dce_8_0_sh_mask.h"
  28
  29 #include "dm_services.h"
  30
  31 #include "link_encoder.h"
  32 #include "stream_encoder.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "irq/dce80/irq_service_dce80.h"
  37 #include "dce110/dce110_timing_generator.h"
  38 #include "dce110/dce110_resource.h"
  39 #include "dce80/dce80_timing_generator.h"
  40 #include "dce/dce_mem_input.h"
  41 #include "dce/dce_link_encoder.h"
  42 #include "dce/dce_stream_encoder.h"
  43 #include "dce/dce_mem_input.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_transform.h"
  46 #include "dce/dce_opp.h"
  47 #include "dce/dce_clocks.h"
  48 #include "dce/dce_clock_source.h"
  49 #include "dce/dce_audio.h"
  50 #include "dce/dce_hwseq.h"
  51 #include "dce80/dce80_hw_sequencer.h"
  52 #include "dce100/dce100_resource.h"
  53
  54 #include "reg_helper.h"
  55
  56 /* TODO remove this include */
  57
  58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  59 #include "gmc/gmc_7_1_d.h"
  60 #include "gmc/gmc_7_1_sh_mask.h"
  61 #endif
  62
  63 #ifndef mmDP_DPHY_INTERNAL_CTRL
  64 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
  65 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
  66 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
  67 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
  68 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
  69 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
  70 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
  71 #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
  72 #endif
  73
  74
  75 #ifndef mmBIOS_SCRATCH_2
  76         #define mmBIOS_SCRATCH_2 0x05CB
  77         #define mmBIOS_SCRATCH_6 0x05CF
  78 #endif
  79
  80 #ifndef mmDP_DPHY_FAST_TRAINING
  81         #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
  82         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
  83         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
  84         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
  85         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
  86         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
  87         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
  88         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
  89 #endif
  90
  91
  92 #ifndef mmHPD_DC_HPD_CONTROL
  93         #define mmHPD_DC_HPD_CONTROL                            0x189A
  94         #define mmHPD0_DC_HPD_CONTROL                           0x189A
  95         #define mmHPD1_DC_HPD_CONTROL                           0x18A2
  96         #define mmHPD2_DC_HPD_CONTROL                           0x18AA
  97         #define mmHPD3_DC_HPD_CONTROL                           0x18B2
  98         #define mmHPD4_DC_HPD_CONTROL                           0x18BA
  99         #define mmHPD5_DC_HPD_CONTROL                           0x18C2
 100 #endif
 101
 102 #define DCE11_DIG_FE_CNTL 0x4a00
 103 #define DCE11_DIG_BE_CNTL 0x4a47
 104 #define DCE11_DP_SEC 0x4ac3
 105
 106 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
 107                 {
 108                         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 109                         .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
 110                         .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
 111                                         - mmDPG_WATERMARK_MASK_CONTROL),
 112                 },
 113                 {
 114                         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 115                         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 116                         .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
 117                                         - mmDPG_WATERMARK_MASK_CONTROL),
 118                 },
 119                 {
 120                         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 121                         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 122                         .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
 123                                         - mmDPG_WATERMARK_MASK_CONTROL),
 124                 },
 125                 {
 126                         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 127                         .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 128                         .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
 129                                         - mmDPG_WATERMARK_MASK_CONTROL),
 130                 },
 131                 {
 132                         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 133                         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 134                         .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
 135                                         - mmDPG_WATERMARK_MASK_CONTROL),
 136                 },
 137                 {
 138                         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 139                         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 140                         .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
 141                                         - mmDPG_WATERMARK_MASK_CONTROL),
 142                 }
 143 };
 144
 145 /* set register offset */
 146 #define SR(reg_name)\
 147         .reg_name = mm ## reg_name
 148
 149 /* set register offset with instance */
 150 #define SRI(reg_name, block, id)\
 151         .reg_name = mm ## block ## id ## _ ## reg_name
 152
 153
 154 static const struct dce_disp_clk_registers disp_clk_regs = {
 155                 CLK_COMMON_REG_LIST_DCE_BASE()
 156 };
 157
 158 static const struct dce_disp_clk_shift disp_clk_shift = {
 159                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 160 };
 161
 162 static const struct dce_disp_clk_mask disp_clk_mask = {
 163                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 164 };
 165
 166 #define ipp_regs(id)\
 167 [id] = {\
 168                 IPP_COMMON_REG_LIST_DCE_BASE(id)\
 169 }
 170
 171 static const struct dce_ipp_registers ipp_regs[] = {
 172                 ipp_regs(0),
 173                 ipp_regs(1),
 174                 ipp_regs(2),
 175                 ipp_regs(3),
 176                 ipp_regs(4),
 177                 ipp_regs(5)
 178 };
 179
 180 static const struct dce_ipp_shift ipp_shift = {
 181                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 182 };
 183
 184 static const struct dce_ipp_mask ipp_mask = {
 185                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 186 };
 187
 188 #define transform_regs(id)\
 189 [id] = {\
 190                 XFM_COMMON_REG_LIST_DCE_BASE(id)\
 191 }
 192
 193 static const struct dce_transform_registers xfm_regs[] = {
 194                 transform_regs(0),
 195                 transform_regs(1),
 196                 transform_regs(2),
 197                 transform_regs(3),
 198                 transform_regs(4),
 199                 transform_regs(5)
 200 };
 201
 202 static const struct dce_transform_shift xfm_shift = {
 203                 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 204 };
 205
 206 static const struct dce_transform_mask xfm_mask = {
 207                 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 208 };
 209
 210 #define aux_regs(id)\
 211 [id] = {\
 212         AUX_REG_LIST(id)\
 213 }
 214
 215 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 216         aux_regs(0),
 217         aux_regs(1),
 218         aux_regs(2),
 219         aux_regs(3),
 220         aux_regs(4),
 221         aux_regs(5)
 222 };
 223
 224 #define hpd_regs(id)\
 225 [id] = {\
 226         HPD_REG_LIST(id)\
 227 }
 228
 229 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 230                 hpd_regs(0),
 231                 hpd_regs(1),
 232                 hpd_regs(2),
 233                 hpd_regs(3),
 234                 hpd_regs(4),
 235                 hpd_regs(5)
 236 };
 237
 238 #define link_regs(id)\
 239 [id] = {\
 240         LE_DCE80_REG_LIST(id)\
 241 }
 242
 243 static const struct dce110_link_enc_registers link_enc_regs[] = {
 244         link_regs(0),
 245         link_regs(1),
 246         link_regs(2),
 247         link_regs(3),
 248         link_regs(4),
 249         link_regs(5),
 250         link_regs(6),
 251 };
 252
 253 #define stream_enc_regs(id)\
 254 [id] = {\
 255         SE_COMMON_REG_LIST_DCE_BASE(id),\
 256         .AFMT_CNTL = 0,\
 257 }
 258
 259 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 260         stream_enc_regs(0),
 261         stream_enc_regs(1),
 262         stream_enc_regs(2),
 263         stream_enc_regs(3),
 264         stream_enc_regs(4),
 265         stream_enc_regs(5)
 266 };
 267
 268 static const struct dce_stream_encoder_shift se_shift = {
 269                 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
 270 };
 271
 272 static const struct dce_stream_encoder_mask se_mask = {
 273                 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
 274 };
 275
 276 #define opp_regs(id)\
 277 [id] = {\
 278         OPP_DCE_80_REG_LIST(id),\
 279 }
 280
 281 static const struct dce_opp_registers opp_regs[] = {
 282         opp_regs(0),
 283         opp_regs(1),
 284         opp_regs(2),
 285         opp_regs(3),
 286         opp_regs(4),
 287         opp_regs(5)
 288 };
 289
 290 static const struct dce_opp_shift opp_shift = {
 291         OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
 292 };
 293
 294 static const struct dce_opp_mask opp_mask = {
 295         OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
 296 };
 297
 298 #define audio_regs(id)\
 299 [id] = {\
 300         AUD_COMMON_REG_LIST(id)\
 301 }
 302
 303 static const struct dce_audio_registers audio_regs[] = {
 304         audio_regs(0),
 305         audio_regs(1),
 306         audio_regs(2),
 307         audio_regs(3),
 308         audio_regs(4),
 309         audio_regs(5),
 310         audio_regs(6),
 311 };
 312
 313 static const struct dce_audio_shift audio_shift = {
 314                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 315 };
 316
 317 static const struct dce_aduio_mask audio_mask = {
 318                 AUD_COMMON_MASK_SH_LIST(_MASK)
 319 };
 320
 321 #define clk_src_regs(id)\
 322 [id] = {\
 323         CS_COMMON_REG_LIST_DCE_80(id),\
 324 }
 325
 326
 327 static const struct dce110_clk_src_regs clk_src_regs[] = {
 328         clk_src_regs(0),
 329         clk_src_regs(1),
 330         clk_src_regs(2)
 331 };
 332
 333 static const struct dce110_clk_src_shift cs_shift = {
 334                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 335 };
 336
 337 static const struct dce110_clk_src_mask cs_mask = {
 338                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 339 };
 340
 341 static const struct bios_registers bios_regs = {
 342         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 343 };
 344
 345 static const struct resource_caps res_cap = {
 346                 .num_timing_generator = 6,
 347                 .num_audio = 6,
 348                 .num_stream_encoder = 6,
 349                 .num_pll = 3,
 350 };
 351
 352 #define CTX  ctx
 353 #define REG(reg) mm ## reg
 354
 355 #ifndef mmCC_DC_HDMI_STRAPS
 356 #define mmCC_DC_HDMI_STRAPS 0x1918
 357 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 358 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 359 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 360 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 361 #endif
 362
 363 static void read_dce_straps(
 364         struct dc_context *ctx,
 365         struct resource_straps *straps)
 366 {
 367         REG_GET_2(CC_DC_HDMI_STRAPS,
 368                         HDMI_DISABLE, &straps->hdmi_disable,
 369                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 370
 371         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 372 }
 373
 374 static struct audio *create_audio(
 375                 struct dc_context *ctx, unsigned int inst)
 376 {
 377         return dce_audio_create(ctx, inst,
 378                         &audio_regs[inst], &audio_shift, &audio_mask);
 379 }
 380
 381 static struct timing_generator *dce80_timing_generator_create(
 382                 struct dc_context *ctx,
 383                 uint32_t instance,
 384                 const struct dce110_timing_generator_offsets *offsets)
 385 {
 386         struct dce110_timing_generator *tg110 =
 387                 dm_alloc(sizeof(struct dce110_timing_generator));
 388
 389         if (!tg110)
 390                 return NULL;
 391
 392         if (dce80_timing_generator_construct(tg110, ctx, instance, offsets))
 393                 return &tg110->base;
 394
 395         BREAK_TO_DEBUGGER();
 396         dm_free(tg110);
 397         return NULL;
 398 }
 399
 400 static struct output_pixel_processor *dce80_opp_create(
 401         struct dc_context *ctx,
 402         uint32_t inst)
 403 {
 404         struct dce110_opp *opp =
 405                 dm_alloc(sizeof(struct dce110_opp));
 406
 407         if (!opp)
 408                 return NULL;
 409
 410         if (dce110_opp_construct(opp,
 411                         ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
 412                 return &opp->base;
 413
 414         BREAK_TO_DEBUGGER();
 415         dm_free(opp);
 416         return NULL;
 417 }
 418
 419 static struct stream_encoder *dce80_stream_encoder_create(
 420         enum engine_id eng_id,
 421         struct dc_context *ctx)
 422 {
 423         struct dce110_stream_encoder *enc110 =
 424                 dm_alloc(sizeof(struct dce110_stream_encoder));
 425
 426         if (!enc110)
 427                 return NULL;
 428
 429         if (dce110_stream_encoder_construct(
 430                         enc110, ctx, ctx->dc_bios, eng_id,
 431                         &stream_enc_regs[eng_id], &se_shift, &se_mask))
 432                 return &enc110->base;
 433
 434         BREAK_TO_DEBUGGER();
 435         dm_free(enc110);
 436         return NULL;
 437 }
 438
 439 #define SRII(reg_name, block, id)\
 440         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 441
 442 static const struct dce_hwseq_registers hwseq_reg = {
 443                 HWSEQ_DCE8_REG_LIST()
 444 };
 445
 446 static const struct dce_hwseq_shift hwseq_shift = {
 447                 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
 448 };
 449
 450 static const struct dce_hwseq_mask hwseq_mask = {
 451                 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
 452 };
 453
 454 static struct dce_hwseq *dce80_hwseq_create(
 455         struct dc_context *ctx)
 456 {
 457         struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
 458
 459         if (hws) {
 460                 hws->ctx = ctx;
 461                 hws->regs = &hwseq_reg;
 462                 hws->shifts = &hwseq_shift;
 463                 hws->masks = &hwseq_mask;
 464         }
 465         return hws;
 466 }
 467
 468 static const struct resource_create_funcs res_create_funcs = {
 469         .read_dce_straps = read_dce_straps,
 470         .create_audio = create_audio,
 471         .create_stream_encoder = dce80_stream_encoder_create,
 472         .create_hwseq = dce80_hwseq_create,
 473 };
 474
 475 #define mi_inst_regs(id) { \
 476         MI_DCE8_REG_LIST(id), \
 477         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 478 }
 479 static const struct dce_mem_input_registers mi_regs[] = {
 480                 mi_inst_regs(0),
 481                 mi_inst_regs(1),
 482                 mi_inst_regs(2),
 483                 mi_inst_regs(3),
 484                 mi_inst_regs(4),
 485                 mi_inst_regs(5),
 486 };
 487
 488 static const struct dce_mem_input_shift mi_shifts = {
 489                 MI_DCE8_MASK_SH_LIST(__SHIFT),
 490                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 491 };
 492
 493 static const struct dce_mem_input_mask mi_masks = {
 494                 MI_DCE8_MASK_SH_LIST(_MASK),
 495                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 496 };
 497
 498 static struct mem_input *dce80_mem_input_create(
 499         struct dc_context *ctx,
 500         uint32_t inst)
 501 {
 502         struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
 503
 504         if (!dce_mi) {
 505                 BREAK_TO_DEBUGGER();
 506                 return NULL;
 507         }
 508
 509         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 510         dce_mi->wa.single_head_rdreq_dmif_limit = 2;
 511         return &dce_mi->base;
 512 }
 513
 514 static void dce80_transform_destroy(struct transform **xfm)
 515 {
 516         dm_free(TO_DCE_TRANSFORM(*xfm));
 517         *xfm = NULL;
 518 }
 519
 520 static struct transform *dce80_transform_create(
 521         struct dc_context *ctx,
 522         uint32_t inst)
 523 {
 524         struct dce_transform *transform =
 525                 dm_alloc(sizeof(struct dce_transform));
 526
 527         if (!transform)
 528                 return NULL;
 529
 530         if (dce_transform_construct(transform, ctx, inst,
 531                         &xfm_regs[inst], &xfm_shift, &xfm_mask)) {
 532                 transform->prescaler_on = false;
 533                 return &transform->base;
 534         }
 535
 536         BREAK_TO_DEBUGGER();
 537         dm_free(transform);
 538         return NULL;
 539 }
 540
 541 static const struct encoder_feature_support link_enc_feature = {
 542                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 543                 .max_hdmi_pixel_clock = 297000,
 544                 .flags.bits.IS_HBR2_CAPABLE = true,
 545                 .flags.bits.IS_TPS3_CAPABLE = true,
 546                 .flags.bits.IS_YCBCR_CAPABLE = true
 547 };
 548
 549 struct link_encoder *dce80_link_encoder_create(
 550         const struct encoder_init_data *enc_init_data)
 551 {
 552         struct dce110_link_encoder *enc110 =
 553                 dm_alloc(sizeof(struct dce110_link_encoder));
 554
 555         if (!enc110)
 556                 return NULL;
 557
 558         if (dce110_link_encoder_construct(
 559                         enc110,
 560                         enc_init_data,
 561                         &link_enc_feature,
 562                         &link_enc_regs[enc_init_data->transmitter],
 563                         &link_enc_aux_regs[enc_init_data->channel - 1],
 564                         &link_enc_hpd_regs[enc_init_data->hpd_source])) {
 565
 566                 return &enc110->base;
 567         }
 568
 569         BREAK_TO_DEBUGGER();
 570         dm_free(enc110);
 571         return NULL;
 572 }
 573
 574 struct clock_source *dce80_clock_source_create(
 575         struct dc_context *ctx,
 576         struct dc_bios *bios,
 577         enum clock_source_id id,
 578         const struct dce110_clk_src_regs *regs,
 579         bool dp_clk_src)
 580 {
 581         struct dce110_clk_src *clk_src =
 582                 dm_alloc(sizeof(struct dce110_clk_src));
 583
 584         if (!clk_src)
 585                 return NULL;
 586
 587         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 588                         regs, &cs_shift, &cs_mask)) {
 589                 clk_src->base.dp_clk_src = dp_clk_src;
 590                 return &clk_src->base;
 591         }
 592
 593         BREAK_TO_DEBUGGER();
 594         return NULL;
 595 }
 596
 597 void dce80_clock_source_destroy(struct clock_source **clk_src)
 598 {
 599         dm_free(TO_DCE110_CLK_SRC(*clk_src));
 600         *clk_src = NULL;
 601 }
 602
 603 static struct input_pixel_processor *dce80_ipp_create(
 604         struct dc_context *ctx, uint32_t inst)
 605 {
 606         struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));
 607
 608         if (!ipp) {
 609                 BREAK_TO_DEBUGGER();
 610                 return NULL;
 611         }
 612
 613         dce_ipp_construct(ipp, ctx, inst,
 614                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 615         return &ipp->base;
 616 }
 617
 618 static void destruct(struct dce110_resource_pool *pool)
 619 {
 620         unsigned int i;
 621
 622         for (i = 0; i < pool->base.pipe_count; i++) {
 623                 if (pool->base.opps[i] != NULL)
 624                         dce110_opp_destroy(&pool->base.opps[i]);
 625
 626                 if (pool->base.transforms[i] != NULL)
 627                         dce80_transform_destroy(&pool->base.transforms[i]);
 628
 629                 if (pool->base.ipps[i] != NULL)
 630                         dce_ipp_destroy(&pool->base.ipps[i]);
 631
 632                 if (pool->base.mis[i] != NULL) {
 633                         dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 634                         pool->base.mis[i] = NULL;
 635                 }
 636
 637                 if (pool->base.timing_generators[i] != NULL)    {
 638                         dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 639                         pool->base.timing_generators[i] = NULL;
 640                 }
 641         }
 642
 643         for (i = 0; i < pool->base.stream_enc_count; i++) {
 644                 if (pool->base.stream_enc[i] != NULL)
 645                         dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 646         }
 647
 648         for (i = 0; i < pool->base.clk_src_count; i++) {
 649                 if (pool->base.clock_sources[i] != NULL) {
 650                         dce80_clock_source_destroy(&pool->base.clock_sources[i]);
 651                 }
 652         }
 653
 654         if (pool->base.dp_clock_source != NULL)
 655                 dce80_clock_source_destroy(&pool->base.dp_clock_source);
 656
 657         for (i = 0; i < pool->base.audio_count; i++)    {
 658                 if (pool->base.audios[i] != NULL) {
 659                         dce_aud_destroy(&pool->base.audios[i]);
 660                 }
 661         }
 662
 663         if (pool->base.display_clock != NULL)
 664                 dce_disp_clk_destroy(&pool->base.display_clock);
 665
 666         if (pool->base.irqs != NULL) {
 667                 dal_irq_service_destroy(&pool->base.irqs);
 668         }
 669 }
 670
 671 static enum dc_status build_mapped_resource(
 672                 const struct core_dc *dc,
 673                 struct validate_context *context,
 674                 struct validate_context *old_context)
 675 {
 676         enum dc_status status = DC_OK;
 677         uint8_t i, j;
 678
 679         for (i = 0; i < context->stream_count; i++) {
 680                 struct dc_stream_state *stream = context->streams[i];
 681
 682                 if (old_context && resource_is_stream_unchanged(old_context, stream))
 683                         continue;
 684
 685                 for (j = 0; j < MAX_PIPES; j++) {
 686                         struct pipe_ctx *pipe_ctx =
 687                                 &context->res_ctx.pipe_ctx[j];
 688
 689                         if (context->res_ctx.pipe_ctx[j].stream != stream)
 690                                 continue;
 691
 692                         status = dce110_resource_build_pipe_hw_param(pipe_ctx);
 693
 694                         if (status != DC_OK)
 695                                 return status;
 696
 697                         resource_build_info_frame(pipe_ctx);
 698
 699                         /* do not need to validate non root pipes */
 700                         break;
 701                 }
 702         }
 703
 704         return DC_OK;
 705 }
 706
 707 bool dce80_validate_bandwidth(
 708         const struct core_dc *dc,
 709         struct validate_context *context)
 710 {
 711         /* TODO implement when needed but for now hardcode max value*/
 712         context->bw.dce.dispclk_khz = 681000;
 713         context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
 714
 715         return true;
 716 }
 717
 718 static bool dce80_validate_surface_sets(
 719                 const struct dc_validation_set set[],
 720                 int set_count)
 721 {
 722         int i;
 723
 724         for (i = 0; i < set_count; i++) {
 725                 if (set[i].surface_count == 0)
 726                         continue;
 727
 728                 if (set[i].surface_count > 1)
 729                         return false;
 730
 731                 if (set[i].surfaces[0]->format
 732                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 733                         return false;
 734         }
 735
 736         return true;
 737 }
 738
 739 enum dc_status dce80_validate_with_context(
 740                 const struct core_dc *dc,
 741                 const struct dc_validation_set set[],
 742                 int set_count,
 743                 struct validate_context *context,
 744                 struct validate_context *old_context)
 745 {
 746         struct dc_context *dc_ctx = dc->ctx;
 747         enum dc_status result = DC_ERROR_UNEXPECTED;
 748         int i;
 749
 750         if (!dce80_validate_surface_sets(set, set_count))
 751                 return DC_FAIL_SURFACE_VALIDATE;
 752
 753         for (i = 0; i < set_count; i++) {
 754                 context->streams[i] = set[i].stream;
 755                 dc_stream_retain(context->streams[i]);
 756                 context->stream_count++;
 757         }
 758
 759         result = resource_map_pool_resources(dc, context, old_context);
 760
 761         if (result == DC_OK)
 762                 result = resource_map_clock_resources(dc, context, old_context);
 763
 764         if (!resource_validate_attach_surfaces(set, set_count,
 765                         old_context, context, dc->res_pool)) {
 766                 DC_ERROR("Failed to attach surface to stream!\n");
 767                 return DC_FAIL_ATTACH_SURFACES;
 768         }
 769
 770         if (result == DC_OK)
 771                 result = build_mapped_resource(dc, context, old_context);
 772
 773         if (result == DC_OK)
 774                 result = resource_build_scaling_params_for_context(dc, context);
 775
 776         if (result == DC_OK)
 777                 result = dce80_validate_bandwidth(dc, context);
 778
 779         return result;
 780 }
 781
 782 enum dc_status dce80_validate_guaranteed(
 783                 const struct core_dc *dc,
 784                 struct dc_stream_state *dc_stream,
 785                 struct validate_context *context)
 786 {
 787         enum dc_status result = DC_ERROR_UNEXPECTED;
 788
 789         context->streams[0] = dc_stream;
 790         dc_stream_retain(context->streams[0]);
 791         context->stream_count++;
 792
 793         result = resource_map_pool_resources(dc, context, NULL);
 794
 795         if (result == DC_OK)
 796                 result = resource_map_clock_resources(dc, context, NULL);
 797
 798         if (result == DC_OK)
 799                 result = build_mapped_resource(dc, context, NULL);
 800
 801         if (result == DC_OK) {
 802                 validate_guaranteed_copy_streams(
 803                                 context, dc->public.caps.max_streams);
 804                 result = resource_build_scaling_params_for_context(dc, context);
 805         }
 806
 807         if (result == DC_OK)
 808                 result = dce80_validate_bandwidth(dc, context);
 809
 810         return result;
 811 }
 812
 813 static void dce80_destroy_resource_pool(struct resource_pool **pool)
 814 {
 815         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 816
 817         destruct(dce110_pool);
 818         dm_free(dce110_pool);
 819         *pool = NULL;
 820 }
 821
 822 static const struct resource_funcs dce80_res_pool_funcs = {
 823         .destroy = dce80_destroy_resource_pool,
 824         .link_enc_create = dce80_link_encoder_create,
 825         .validate_with_context = dce80_validate_with_context,
 826         .validate_guaranteed = dce80_validate_guaranteed,
 827         .validate_bandwidth = dce80_validate_bandwidth,
 828         .validate_plane = dce100_validate_plane
 829 };
 830
 831 static bool construct(
 832         uint8_t num_virtual_links,
 833         struct core_dc *dc,
 834         struct dce110_resource_pool *pool)
 835 {
 836         unsigned int i;
 837         struct dc_context *ctx = dc->ctx;
 838         struct dc_firmware_info info;
 839         struct dc_bios *bp;
 840         struct dm_pp_static_clock_info static_clk_info = {0};
 841
 842         ctx->dc_bios->regs = &bios_regs;
 843
 844         pool->base.res_cap = &res_cap;
 845         pool->base.funcs = &dce80_res_pool_funcs;
 846
 847
 848         /*************************************************
 849          *  Resource + asic cap harcoding                *
 850          *************************************************/
 851         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 852         pool->base.pipe_count = res_cap.num_timing_generator;
 853         dc->public.caps.max_downscale_ratio = 200;
 854         dc->public.caps.i2c_speed_in_khz = 40;
 855         dc->public.caps.max_cursor_size = 128;
 856
 857         /*************************************************
 858          *  Create resources                             *
 859          *************************************************/
 860
 861         bp = ctx->dc_bios;
 862
 863         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
 864                 info.external_clock_source_frequency_for_dp != 0) {
 865                 pool->base.dp_clock_source =
 866                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 867
 868                 pool->base.clock_sources[0] =
 869                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 870                 pool->base.clock_sources[1] =
 871                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 872                 pool->base.clock_sources[2] =
 873                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 874                 pool->base.clk_src_count = 3;
 875
 876         } else {
 877                 pool->base.dp_clock_source =
 878                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 879
 880                 pool->base.clock_sources[0] =
 881                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 882                 pool->base.clock_sources[1] =
 883                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 884                 pool->base.clk_src_count = 2;
 885         }
 886
 887         if (pool->base.dp_clock_source == NULL) {
 888                 dm_error("DC: failed to create dp clock source!\n");
 889                 BREAK_TO_DEBUGGER();
 890                 goto res_create_fail;
 891         }
 892
 893         for (i = 0; i < pool->base.clk_src_count; i++) {
 894                 if (pool->base.clock_sources[i] == NULL) {
 895                         dm_error("DC: failed to create clock sources!\n");
 896                         BREAK_TO_DEBUGGER();
 897                         goto res_create_fail;
 898                 }
 899         }
 900
 901         pool->base.display_clock = dce_disp_clk_create(ctx,
 902                         &disp_clk_regs,
 903                         &disp_clk_shift,
 904                         &disp_clk_mask);
 905         if (pool->base.display_clock == NULL) {
 906                 dm_error("DC: failed to create display clock!\n");
 907                 BREAK_TO_DEBUGGER();
 908                 goto res_create_fail;
 909         }
 910
 911
 912         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
 913                 pool->base.display_clock->max_clks_state =
 914                                         static_clk_info.max_clocks_state;
 915
 916         {
 917                 struct irq_service_init_data init_data;
 918                 init_data.ctx = dc->ctx;
 919                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
 920                 if (!pool->base.irqs)
 921                         goto res_create_fail;
 922         }
 923
 924         for (i = 0; i < pool->base.pipe_count; i++) {
 925                 pool->base.timing_generators[i] = dce80_timing_generator_create(
 926                                 ctx, i, &dce80_tg_offsets[i]);
 927                 if (pool->base.timing_generators[i] == NULL) {
 928                         BREAK_TO_DEBUGGER();
 929                         dm_error("DC: failed to create tg!\n");
 930                         goto res_create_fail;
 931                 }
 932
 933                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
 934                 if (pool->base.mis[i] == NULL) {
 935                         BREAK_TO_DEBUGGER();
 936                         dm_error("DC: failed to create memory input!\n");
 937                         goto res_create_fail;
 938                 }
 939
 940                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
 941                 if (pool->base.ipps[i] == NULL) {
 942                         BREAK_TO_DEBUGGER();
 943                         dm_error("DC: failed to create input pixel processor!\n");
 944                         goto res_create_fail;
 945                 }
 946
 947                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
 948                 if (pool->base.transforms[i] == NULL) {
 949                         BREAK_TO_DEBUGGER();
 950                         dm_error("DC: failed to create transform!\n");
 951                         goto res_create_fail;
 952                 }
 953
 954                 pool->base.opps[i] = dce80_opp_create(ctx, i);
 955                 if (pool->base.opps[i] == NULL) {
 956                         BREAK_TO_DEBUGGER();
 957                         dm_error("DC: failed to create output pixel processor!\n");
 958                         goto res_create_fail;
 959                 }
 960         }
 961
 962         dc->public.caps.max_surfaces =  pool->base.pipe_count;
 963
 964         if (!resource_construct(num_virtual_links, dc, &pool->base,
 965                         &res_create_funcs))
 966                 goto res_create_fail;
 967
 968         /* Create hardware sequencer */
 969         if (!dce80_hw_sequencer_construct(dc))
 970                 goto res_create_fail;
 971
 972         return true;
 973
 974 res_create_fail:
 975         destruct(pool);
 976         return false;
 977 }
 978
 979 struct resource_pool *dce80_create_resource_pool(
 980         uint8_t num_virtual_links,
 981         struct core_dc *dc)
 982 {
 983         struct dce110_resource_pool *pool =
 984                 dm_alloc(sizeof(struct dce110_resource_pool));
 985
 986         if (!pool)
 987                 return NULL;
 988
 989         if (construct(num_virtual_links, dc, pool))
 990                 return &pool->base;
 991
 992         BREAK_TO_DEBUGGER();
 993         return NULL;
 994 }
 995