2 * Copyright 2015 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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26 #include "dm_services.h"
28 #include "core_types.h"
29 #include "dce120_hw_sequencer.h"
30 #include "dce/dce_hwseq.h"
32 #include "dce110/dce110_hw_sequencer.h"
34 #include "dce/dce_12_0_offset.h"
35 #include "dce/dce_12_0_sh_mask.h"
36 #include "soc15_hw_ip.h"
37 #include "vega10_ip_offset.h"
38 #include "reg_helper.h"
46 #define FN(reg_name, field_name) \
47 hws->shifts->field_name, hws->masks->field_name
49 struct dce120_hw_seq_reg_offsets {
53 static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
55 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
58 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
61 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
64 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
67 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
70 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
74 #define HW_REG_CRTC(reg, id)\
75 (reg + reg_offsets[id].crtc)
77 #define CNTL_ID(controller_id)\
79 /*******************************************************************************
81 ******************************************************************************/
83 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
87 uint32_t chunk_int = 0;
88 uint32_t chunk_mul = 0;
90 addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
91 (mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);
93 value = dm_read_reg(ctx, addr);
96 value, 0, DCP, controller_id,
100 set_reg_field_value_soc15(
101 value, 1, DCP, controller_id,
103 DVMM_PTE_BUFFER_MODE0);
105 set_reg_field_value_soc15(
106 value, 1, DCP, controller_id,
108 DVMM_PTE_BUFFER_MODE1);
110 dm_write_reg(ctx, addr, value);*/
112 addr = mmDVMM_PTE_REQ;
113 value = dm_read_reg(ctx, addr);
115 chunk_int = get_reg_field_value(
118 HFLIP_PTEREQ_PER_CHUNK_INT);
120 chunk_mul = get_reg_field_value(
123 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
125 if (chunk_int != 0x4 || chunk_mul != 0x4) {
131 MAX_PTEREQ_TO_ISSUE);
137 HFLIP_PTEREQ_PER_CHUNK_INT);
143 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
145 dm_write_reg(ctx, addr, value);
150 static bool dce120_enable_display_power_gating(
152 uint8_t controller_id,
154 enum pipe_gating_control power_gating)
156 /* disable for bringup */
158 enum bp_result bp_result = BP_RESULT_OK;
159 enum bp_pipe_control_action cntl;
160 struct dc_context *ctx = dc->ctx;
162 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
165 if (power_gating == PIPE_GATING_CONTROL_INIT)
166 cntl = ASIC_PIPE_INIT;
167 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
168 cntl = ASIC_PIPE_ENABLE;
170 cntl = ASIC_PIPE_DISABLE;
172 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
174 bp_result = dcb->funcs->enable_disp_power_gating(
175 dcb, controller_id + 1, cntl);
177 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
178 * by default when command table is called
181 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),
185 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
186 dce120_init_pte(ctx, controller_id);
188 if (bp_result == BP_RESULT_OK)
196 static void dce120_update_dchub(
197 struct dce_hwseq *hws,
198 struct dchub_init_data *dh_data)
200 /* TODO: port code from dal2 */
201 switch (dh_data->fb_mode) {
202 case FRAME_BUFFER_MODE_ZFB_ONLY:
203 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
204 REG_UPDATE_2(DCHUB_FB_LOCATION,
208 REG_UPDATE(DCHUB_AGP_BASE,
209 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
211 REG_UPDATE(DCHUB_AGP_BOT,
212 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
214 REG_UPDATE(DCHUB_AGP_TOP,
215 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
217 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
218 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
219 REG_UPDATE(DCHUB_AGP_BASE,
220 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
222 REG_UPDATE(DCHUB_AGP_BOT,
223 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
225 REG_UPDATE(DCHUB_AGP_TOP,
226 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
228 case FRAME_BUFFER_MODE_LOCAL_ONLY:
229 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
230 REG_UPDATE(DCHUB_AGP_BASE,
233 REG_UPDATE(DCHUB_AGP_BOT,
236 REG_UPDATE(DCHUB_AGP_TOP,
243 dh_data->dchub_initialzied = true;
244 dh_data->dchub_info_valid = false;
247 static void dce120_set_bandwidth(
249 struct dc_state *context,
250 bool decrease_allowed)
252 if (context->stream_count <= 0)
255 dce110_set_bandwidth(dc, context, decrease_allowed);
258 void dce120_hw_sequencer_construct(struct dc *dc)
260 /* All registers used by dce11.2 match those in dce11 in offset and
263 dce110_hw_sequencer_construct(dc);
264 dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
265 dc->hwss.update_dchub = dce120_update_dchub;
266 dc->hwss.set_bandwidth = dce120_set_bandwidth;