drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30 #include "dc_bios_types.h"
  31 #include "core_types.h"
  32 #include "core_status.h"
  33 #include "resource.h"
  34 #include "dm_helpers.h"
  35 #include "dce110_timing_generator.h"
  36 #include "dce/dce_hwseq.h"
  37 #include "gpio_service_interface.h"
  38
  39 #include "dce110_compressor.h"
  40
  41 #include "bios/bios_parser_helper.h"
  42 #include "timing_generator.h"
  43 #include "mem_input.h"
  44 #include "opp.h"
  45 #include "ipp.h"
  46 #include "transform.h"
  47 #include "stream_encoder.h"
  48 #include "link_encoder.h"
  49 #include "link_enc_cfg.h"
  50 #include "link_hwss.h"
  51 #include "dc_link_dp.h"
  52 #if defined(CONFIG_DRM_AMD_DC_DCN)
  53 #include "dccg.h"
  54 #endif
  55 #include "clock_source.h"
  56 #include "clk_mgr.h"
  57 #include "abm.h"
  58 #include "audio.h"
  59 #include "reg_helper.h"
  60 #include "panel_cntl.h"
  61 #include "inc/link_dpcd.h"
  62 #include "dpcd_defs.h"
  63 /* include DCE11 register header files */
  64 #include "dce/dce_11_0_d.h"
  65 #include "dce/dce_11_0_sh_mask.h"
  66 #include "custom_float.h"
  67
  68 #include "atomfirmware.h"
  69
  70 #include "dcn10/dcn10_hw_sequencer.h"
  71
  72 #define GAMMA_HW_POINTS_NUM 256
  73
  74 /*
  75  * All values are in milliseconds;
  76  * For eDP, after power-up/power/down,
  77  * 300/500 msec max. delay from LCDVCC to black video generation
  78  */
  79 #define PANEL_POWER_UP_TIMEOUT 300
  80 #define PANEL_POWER_DOWN_TIMEOUT 500
  81 #define HPD_CHECK_INTERVAL 10
  82 #define OLED_POST_T7_DELAY 100
  83 #define OLED_PRE_T11_DELAY 150
  84
  85 #define CTX \
  86         hws->ctx
  87
  88 #define DC_LOGGER_INIT()
  89
  90 #define REG(reg)\
  91         hws->regs->reg
  92
  93 #undef FN
  94 #define FN(reg_name, field_name) \
  95         hws->shifts->field_name, hws->masks->field_name
  96
  97 struct dce110_hw_seq_reg_offsets {
  98         uint32_t crtc;
  99 };
 100
 101 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
 102 {
 103         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 104 },
 105 {
 106         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 107 },
 108 {
 109         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 110 },
 111 {
 112         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 113 }
 114 };
 115
 116 #define HW_REG_BLND(reg, id)\
 117         (reg + reg_offsets[id].blnd)
 118
 119 #define HW_REG_CRTC(reg, id)\
 120         (reg + reg_offsets[id].crtc)
 121
 122 #define MAX_WATERMARK 0xFFFF
 123 #define SAFE_NBP_MARK 0x7FFF
 124
 125 /*******************************************************************************
 126  * Private definitions
 127  ******************************************************************************/
 128 /***************************PIPE_CONTROL***********************************/
 129 static void dce110_init_pte(struct dc_context *ctx)
 130 {
 131         uint32_t addr;
 132         uint32_t value = 0;
 133         uint32_t chunk_int = 0;
 134         uint32_t chunk_mul = 0;
 135
 136         addr = mmUNP_DVMM_PTE_CONTROL;
 137         value = dm_read_reg(ctx, addr);
 138
 139         set_reg_field_value(
 140                 value,
 141                 0,
 142                 DVMM_PTE_CONTROL,
 143                 DVMM_USE_SINGLE_PTE);
 144
 145         set_reg_field_value(
 146                 value,
 147                 1,
 148                 DVMM_PTE_CONTROL,
 149                 DVMM_PTE_BUFFER_MODE0);
 150
 151         set_reg_field_value(
 152                 value,
 153                 1,
 154                 DVMM_PTE_CONTROL,
 155                 DVMM_PTE_BUFFER_MODE1);
 156
 157         dm_write_reg(ctx, addr, value);
 158
 159         addr = mmDVMM_PTE_REQ;
 160         value = dm_read_reg(ctx, addr);
 161
 162         chunk_int = get_reg_field_value(
 163                 value,
 164                 DVMM_PTE_REQ,
 165                 HFLIP_PTEREQ_PER_CHUNK_INT);
 166
 167         chunk_mul = get_reg_field_value(
 168                 value,
 169                 DVMM_PTE_REQ,
 170                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 171
 172         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 173
 174                 set_reg_field_value(
 175                         value,
 176                         255,
 177                         DVMM_PTE_REQ,
 178                         MAX_PTEREQ_TO_ISSUE);
 179
 180                 set_reg_field_value(
 181                         value,
 182                         4,
 183                         DVMM_PTE_REQ,
 184                         HFLIP_PTEREQ_PER_CHUNK_INT);
 185
 186                 set_reg_field_value(
 187                         value,
 188                         4,
 189                         DVMM_PTE_REQ,
 190                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 191
 192                 dm_write_reg(ctx, addr, value);
 193         }
 194 }
 195 /**************************************************************************/
 196
 197 static void enable_display_pipe_clock_gating(
 198         struct dc_context *ctx,
 199         bool clock_gating)
 200 {
 201         /*TODO*/
 202 }
 203
 204 static bool dce110_enable_display_power_gating(
 205         struct dc *dc,
 206         uint8_t controller_id,
 207         struct dc_bios *dcb,
 208         enum pipe_gating_control power_gating)
 209 {
 210         enum bp_result bp_result = BP_RESULT_OK;
 211         enum bp_pipe_control_action cntl;
 212         struct dc_context *ctx = dc->ctx;
 213         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 214
 215         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 216                 return true;
 217
 218         if (power_gating == PIPE_GATING_CONTROL_INIT)
 219                 cntl = ASIC_PIPE_INIT;
 220         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 221                 cntl = ASIC_PIPE_ENABLE;
 222         else
 223                 cntl = ASIC_PIPE_DISABLE;
 224
 225         if (controller_id == underlay_idx)
 226                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 227
 228         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 229
 230                 bp_result = dcb->funcs->enable_disp_power_gating(
 231                                                 dcb, controller_id + 1, cntl);
 232
 233                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 234                  * by default when command table is called
 235                  *
 236                  * Bios parser accepts controller_id = 6 as indicative of
 237                  * underlay pipe in dce110. But we do not support more
 238                  * than 3.
 239                  */
 240                 if (controller_id < CONTROLLER_ID_MAX - 1)
 241                         dm_write_reg(ctx,
 242                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 243                                 0);
 244         }
 245
 246         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 247                 dce110_init_pte(ctx);
 248
 249         if (bp_result == BP_RESULT_OK)
 250                 return true;
 251         else
 252                 return false;
 253 }
 254
 255 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 256                 const struct dc_plane_state *plane_state)
 257 {
 258         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 259
 260         switch (plane_state->format) {
 261         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 262                 prescale_params->scale = 0x2082;
 263                 break;
 264         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 265         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 266                 prescale_params->scale = 0x2020;
 267                 break;
 268         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 269         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 270                 prescale_params->scale = 0x2008;
 271                 break;
 272         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 273         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 274         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 275                 prescale_params->scale = 0x2000;
 276                 break;
 277         default:
 278                 ASSERT(false);
 279                 break;
 280         }
 281 }
 282
 283 static bool
 284 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 285                                const struct dc_plane_state *plane_state)
 286 {
 287         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 288         const struct dc_transfer_func *tf = NULL;
 289         struct ipp_prescale_params prescale_params = { 0 };
 290         bool result = true;
 291
 292         if (ipp == NULL)
 293                 return false;
 294
 295         if (plane_state->in_transfer_func)
 296                 tf = plane_state->in_transfer_func;
 297
 298         build_prescale_params(&prescale_params, plane_state);
 299         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 300
 301         if (plane_state->gamma_correction &&
 302                         !plane_state->gamma_correction->is_identity &&
 303                         dce_use_lut(plane_state->format))
 304                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 305
 306         if (tf == NULL) {
 307                 /* Default case if no input transfer function specified */
 308                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 309         } else if (tf->type == TF_TYPE_PREDEFINED) {
 310                 switch (tf->tf) {
 311                 case TRANSFER_FUNCTION_SRGB:
 312                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 313                         break;
 314                 case TRANSFER_FUNCTION_BT709:
 315                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 316                         break;
 317                 case TRANSFER_FUNCTION_LINEAR:
 318                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 319                         break;
 320                 case TRANSFER_FUNCTION_PQ:
 321                 default:
 322                         result = false;
 323                         break;
 324                 }
 325         } else if (tf->type == TF_TYPE_BYPASS) {
 326                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 327         } else {
 328                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 329                 result = false;
 330         }
 331
 332         return result;
 333 }
 334
 335 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 336                                     struct curve_points *arr_points,
 337                                     uint32_t hw_points_num)
 338 {
 339         struct custom_float_format fmt;
 340
 341         struct pwl_result_data *rgb = rgb_resulted;
 342
 343         uint32_t i = 0;
 344
 345         fmt.exponenta_bits = 6;
 346         fmt.mantissa_bits = 12;
 347         fmt.sign = true;
 348
 349         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 350                                             &arr_points[0].custom_float_x)) {
 351                 BREAK_TO_DEBUGGER();
 352                 return false;
 353         }
 354
 355         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 356                                             &arr_points[0].custom_float_offset)) {
 357                 BREAK_TO_DEBUGGER();
 358                 return false;
 359         }
 360
 361         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 362                                             &arr_points[0].custom_float_slope)) {
 363                 BREAK_TO_DEBUGGER();
 364                 return false;
 365         }
 366
 367         fmt.mantissa_bits = 10;
 368         fmt.sign = false;
 369
 370         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 371                                             &arr_points[1].custom_float_x)) {
 372                 BREAK_TO_DEBUGGER();
 373                 return false;
 374         }
 375
 376         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 377                                             &arr_points[1].custom_float_y)) {
 378                 BREAK_TO_DEBUGGER();
 379                 return false;
 380         }
 381
 382         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 383                                             &arr_points[1].custom_float_slope)) {
 384                 BREAK_TO_DEBUGGER();
 385                 return false;
 386         }
 387
 388         fmt.mantissa_bits = 12;
 389         fmt.sign = true;
 390
 391         while (i != hw_points_num) {
 392                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 393                                                     &rgb->red_reg)) {
 394                         BREAK_TO_DEBUGGER();
 395                         return false;
 396                 }
 397
 398                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 399                                                     &rgb->green_reg)) {
 400                         BREAK_TO_DEBUGGER();
 401                         return false;
 402                 }
 403
 404                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 405                                                     &rgb->blue_reg)) {
 406                         BREAK_TO_DEBUGGER();
 407                         return false;
 408                 }
 409
 410                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 411                                                     &rgb->delta_red_reg)) {
 412                         BREAK_TO_DEBUGGER();
 413                         return false;
 414                 }
 415
 416                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 417                                                     &rgb->delta_green_reg)) {
 418                         BREAK_TO_DEBUGGER();
 419                         return false;
 420                 }
 421
 422                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 423                                                     &rgb->delta_blue_reg)) {
 424                         BREAK_TO_DEBUGGER();
 425                         return false;
 426                 }
 427
 428                 ++rgb;
 429                 ++i;
 430         }
 431
 432         return true;
 433 }
 434
 435 #define MAX_LOW_POINT      25
 436 #define NUMBER_REGIONS     16
 437 #define NUMBER_SW_SEGMENTS 16
 438
 439 static bool
 440 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 441                                       struct pwl_params *regamma_params)
 442 {
 443         struct curve_points *arr_points;
 444         struct pwl_result_data *rgb_resulted;
 445         struct pwl_result_data *rgb;
 446         struct pwl_result_data *rgb_plus_1;
 447         struct fixed31_32 y_r;
 448         struct fixed31_32 y_g;
 449         struct fixed31_32 y_b;
 450         struct fixed31_32 y1_min;
 451         struct fixed31_32 y3_max;
 452
 453         int32_t region_start, region_end;
 454         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 455
 456         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 457                 return false;
 458
 459         arr_points = regamma_params->arr_points;
 460         rgb_resulted = regamma_params->rgb_resulted;
 461         hw_points = 0;
 462
 463         memset(regamma_params, 0, sizeof(struct pwl_params));
 464
 465         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 466                 /* 16 segments
 467                  * segments are from 2^-11 to 2^5
 468                  */
 469                 region_start = -11;
 470                 region_end = region_start + NUMBER_REGIONS;
 471
 472                 for (i = 0; i < NUMBER_REGIONS; i++)
 473                         seg_distr[i] = 4;
 474
 475         } else {
 476                 /* 10 segments
 477                  * segment is from 2^-10 to 2^1
 478                  * We include an extra segment for range [2^0, 2^1). This is to
 479                  * ensure that colors with normalized values of 1 don't miss the
 480                  * LUT.
 481                  */
 482                 region_start = -10;
 483                 region_end = 1;
 484
 485                 seg_distr[0] = 4;
 486                 seg_distr[1] = 4;
 487                 seg_distr[2] = 4;
 488                 seg_distr[3] = 4;
 489                 seg_distr[4] = 4;
 490                 seg_distr[5] = 4;
 491                 seg_distr[6] = 4;
 492                 seg_distr[7] = 4;
 493                 seg_distr[8] = 4;
 494                 seg_distr[9] = 4;
 495                 seg_distr[10] = 0;
 496                 seg_distr[11] = -1;
 497                 seg_distr[12] = -1;
 498                 seg_distr[13] = -1;
 499                 seg_distr[14] = -1;
 500                 seg_distr[15] = -1;
 501         }
 502
 503         for (k = 0; k < 16; k++) {
 504                 if (seg_distr[k] != -1)
 505                         hw_points += (1 << seg_distr[k]);
 506         }
 507
 508         j = 0;
 509         for (k = 0; k < (region_end - region_start); k++) {
 510                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 511                 start_index = (region_start + k + MAX_LOW_POINT) *
 512                                 NUMBER_SW_SEGMENTS;
 513                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 514                                 i += increment) {
 515                         if (j == hw_points - 1)
 516                                 break;
 517                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 518                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 519                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 520                         j++;
 521                 }
 522         }
 523
 524         /* last point */
 525         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 526         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 527         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 528         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 529
 530         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 531                                              dc_fixpt_from_int(region_start));
 532         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 533                                              dc_fixpt_from_int(region_end));
 534
 535         y_r = rgb_resulted[0].red;
 536         y_g = rgb_resulted[0].green;
 537         y_b = rgb_resulted[0].blue;
 538
 539         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 540
 541         arr_points[0].y = y1_min;
 542         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 543                                                  arr_points[0].x);
 544
 545         y_r = rgb_resulted[hw_points - 1].red;
 546         y_g = rgb_resulted[hw_points - 1].green;
 547         y_b = rgb_resulted[hw_points - 1].blue;
 548
 549         /* see comment above, m_arrPoints[1].y should be the Y value for the
 550          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 551          */
 552         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 553
 554         arr_points[1].y = y3_max;
 555
 556         arr_points[1].slope = dc_fixpt_zero;
 557
 558         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 559                 /* for PQ, we want to have a straight line from last HW X point,
 560                  * and the slope to be such that we hit 1.0 at 10000 nits.
 561                  */
 562                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 563
 564                 arr_points[1].slope = dc_fixpt_div(
 565                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 566                                 dc_fixpt_sub(end_value, arr_points[1].x));
 567         }
 568
 569         regamma_params->hw_points_num = hw_points;
 570
 571         k = 0;
 572         for (i = 1; i < 16; i++) {
 573                 if (seg_distr[k] != -1) {
 574                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 575                         regamma_params->arr_curve_points[i].offset =
 576                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 577                 }
 578                 k++;
 579         }
 580
 581         if (seg_distr[k] != -1)
 582                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 583
 584         rgb = rgb_resulted;
 585         rgb_plus_1 = rgb_resulted + 1;
 586
 587         i = 1;
 588
 589         while (i != hw_points + 1) {
 590                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 591                         rgb_plus_1->red = rgb->red;
 592                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 593                         rgb_plus_1->green = rgb->green;
 594                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 595                         rgb_plus_1->blue = rgb->blue;
 596
 597                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 598                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 599                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 600
 601                 ++rgb_plus_1;
 602                 ++rgb;
 603                 ++i;
 604         }
 605
 606         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 607
 608         return true;
 609 }
 610
 611 static bool
 612 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 613                                 const struct dc_stream_state *stream)
 614 {
 615         struct transform *xfm = pipe_ctx->plane_res.xfm;
 616
 617         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 618         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 619
 620         if (stream->out_transfer_func &&
 621             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 622             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 623                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 624         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 625                                                          &xfm->regamma_params)) {
 626                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 627                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 628         } else {
 629                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 630         }
 631
 632         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 633
 634         return true;
 635 }
 636
 637 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 638 {
 639         bool is_hdmi_tmds;
 640         bool is_dp;
 641
 642         ASSERT(pipe_ctx->stream);
 643
 644         if (pipe_ctx->stream_res.stream_enc == NULL)
 645                 return;  /* this is not root pipe */
 646
 647         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 648         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 649
 650         if (!is_hdmi_tmds && !is_dp)
 651                 return;
 652
 653         if (is_hdmi_tmds)
 654                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 655                         pipe_ctx->stream_res.stream_enc,
 656                         &pipe_ctx->stream_res.encoder_info_frame);
 657         else
 658                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 659                         pipe_ctx->stream_res.stream_enc,
 660                         &pipe_ctx->stream_res.encoder_info_frame);
 661 }
 662
 663 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 664 {
 665         enum dc_lane_count lane_count =
 666                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 667         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 668         struct dc_link *link = pipe_ctx->stream->link;
 669         const struct dc *dc = link->dc;
 670
 671         uint32_t active_total_with_borders;
 672         uint32_t early_control = 0;
 673         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 674
 675         /* For MST, there are multiply stream go to only one link.
 676          * connect DIG back_end to front_end while enable_stream and
 677          * disconnect them during disable_stream
 678          * BY this, it is logic clean to separate stream and link */
 679         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 680                                                     pipe_ctx->stream_res.stream_enc->id, true);
 681
 682         dc->hwss.update_info_frame(pipe_ctx);
 683
 684         /* enable early control to avoid corruption on DP monitor*/
 685         active_total_with_borders =
 686                         timing->h_addressable
 687                                 + timing->h_border_left
 688                                 + timing->h_border_right;
 689
 690         if (lane_count != 0)
 691                 early_control = active_total_with_borders % lane_count;
 692
 693         if (early_control == 0)
 694                 early_control = lane_count;
 695
 696         tg->funcs->set_early_control(tg, early_control);
 697
 698         /* enable audio only within mode set */
 699         if (pipe_ctx->stream_res.audio != NULL) {
 700                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 701                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 702         }
 703
 704
 705
 706
 707 }
 708
 709 static enum bp_result link_transmitter_control(
 710                 struct dc_bios *bios,
 711         struct bp_transmitter_control *cntl)
 712 {
 713         enum bp_result result;
 714
 715         result = bios->funcs->transmitter_control(bios, cntl);
 716
 717         return result;
 718 }
 719
 720 /*
 721  * @brief
 722  * eDP only.
 723  */
 724 void dce110_edp_wait_for_hpd_ready(
 725                 struct dc_link *link,
 726                 bool power_up)
 727 {
 728         struct dc_context *ctx = link->ctx;
 729         struct graphics_object_id connector = link->link_enc->connector;
 730         struct gpio *hpd;
 731         struct dc_sink *sink = link->local_sink;
 732         bool edp_hpd_high = false;
 733         uint32_t time_elapsed = 0;
 734         uint32_t timeout = power_up ?
 735                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 736
 737         if (dal_graphics_object_id_get_connector_id(connector)
 738                         != CONNECTOR_ID_EDP) {
 739                 BREAK_TO_DEBUGGER();
 740                 return;
 741         }
 742
 743         if (!power_up)
 744                 /*
 745                  * From KV, we will not HPD low after turning off VCC -
 746                  * instead, we will check the SW timer in power_up().
 747                  */
 748                 return;
 749
 750         /*
 751          * When we power on/off the eDP panel,
 752          * we need to wait until SENSE bit is high/low.
 753          */
 754
 755         /* obtain HPD */
 756         /* TODO what to do with this? */
 757         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 758
 759         if (!hpd) {
 760                 BREAK_TO_DEBUGGER();
 761                 return;
 762         }
 763
 764         if (sink != NULL) {
 765                 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) {
 766                         int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 767
 768                         msleep(extra_t3_in_ms);
 769                 }
 770         }
 771
 772         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 773
 774         /* wait until timeout or panel detected */
 775
 776         do {
 777                 uint32_t detected = 0;
 778
 779                 dal_gpio_get_value(hpd, &detected);
 780
 781                 if (!(detected ^ power_up)) {
 782                         edp_hpd_high = true;
 783                         break;
 784                 }
 785
 786                 msleep(HPD_CHECK_INTERVAL);
 787
 788                 time_elapsed += HPD_CHECK_INTERVAL;
 789         } while (time_elapsed < timeout);
 790
 791         dal_gpio_close(hpd);
 792
 793         dal_gpio_destroy_irq(&hpd);
 794
 795         if (false == edp_hpd_high) {
 796                 DC_LOG_ERROR(
 797                                 "%s: wait timed out!\n", __func__);
 798         }
 799 }
 800
 801 void dce110_edp_power_control(
 802                 struct dc_link *link,
 803                 bool power_up)
 804 {
 805         struct dc_context *ctx = link->ctx;
 806         struct bp_transmitter_control cntl = { 0 };
 807         enum bp_result bp_result;
 808         uint8_t panel_instance;
 809
 810
 811         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 812                         != CONNECTOR_ID_EDP) {
 813                 BREAK_TO_DEBUGGER();
 814                 return;
 815         }
 816
 817         if (!link->panel_cntl)
 818                 return;
 819         if (power_up !=
 820                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 821
 822                 unsigned long long current_ts = dm_get_timestamp(ctx);
 823                 unsigned long long time_since_edp_poweroff_ms =
 824                                 div64_u64(dm_get_elapse_time_in_ns(
 825                                                 ctx,
 826                                                 current_ts,
 827                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 828                 unsigned long long time_since_edp_poweron_ms =
 829                                 div64_u64(dm_get_elapse_time_in_ns(
 830                                                 ctx,
 831                                                 current_ts,
 832                                                 link->link_trace.time_stamp.edp_poweron), 1000000);
 833                 DC_LOG_HW_RESUME_S3(
 834                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 835                                 __func__,
 836                                 power_up,
 837                                 current_ts,
 838                                 link->link_trace.time_stamp.edp_poweroff,
 839                                 link->link_trace.time_stamp.edp_poweron,
 840                                 time_since_edp_poweroff_ms,
 841                                 time_since_edp_poweron_ms);
 842
 843                 /* Send VBIOS command to prompt eDP panel power */
 844                 if (power_up) {
 845                         /* edp requires a min of 500ms from LCDVDD off to on */
 846                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 847
 848                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 849                         if (link->local_sink != NULL)
 850                                 remaining_min_edp_poweroff_time_ms +=
 851                                         link->local_sink->edid_caps.panel_patch.extra_t12_ms;
 852
 853                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 854                         if (link->link_trace.time_stamp.edp_poweroff != 0) {
 855                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 856                                         remaining_min_edp_poweroff_time_ms =
 857                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 858                                 else
 859                                         remaining_min_edp_poweroff_time_ms = 0;
 860                         }
 861
 862                         if (remaining_min_edp_poweroff_time_ms) {
 863                                 DC_LOG_HW_RESUME_S3(
 864                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 865                                                 __func__, remaining_min_edp_poweroff_time_ms);
 866                                 msleep(remaining_min_edp_poweroff_time_ms);
 867                                 DC_LOG_HW_RESUME_S3(
 868                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 869                                                 __func__, remaining_min_edp_poweroff_time_ms);
 870                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 871                                                 __func__, remaining_min_edp_poweroff_time_ms);
 872                         } else {
 873                                 DC_LOG_HW_RESUME_S3(
 874                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 875                                                 __func__, remaining_min_edp_poweroff_time_ms);
 876                         }
 877                 }
 878
 879                 DC_LOG_HW_RESUME_S3(
 880                                 "%s: BEGIN: Panel Power action: %s\n",
 881                                 __func__, (power_up ? "On":"Off"));
 882
 883                 cntl.action = power_up ?
 884                         TRANSMITTER_CONTROL_POWER_ON :
 885                         TRANSMITTER_CONTROL_POWER_OFF;
 886                 cntl.transmitter = link->link_enc->transmitter;
 887                 cntl.connector_obj_id = link->link_enc->connector;
 888                 cntl.coherent = false;
 889                 cntl.lanes_number = LANE_COUNT_FOUR;
 890                 cntl.hpd_sel = link->link_enc->hpd_source;
 891                 panel_instance = link->panel_cntl->inst;
 892
 893                 if (ctx->dc->ctx->dmub_srv &&
 894                                 ctx->dc->debug.dmub_command_table) {
 895                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
 896                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 897                                                 LVTMA_CONTROL_POWER_ON,
 898                                                 panel_instance);
 899                         else
 900                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 901                                                 LVTMA_CONTROL_POWER_OFF,
 902                                                 panel_instance);
 903                 }
 904
 905                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 906
 907                 DC_LOG_HW_RESUME_S3(
 908                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 909                                 __func__, (power_up ? "On":"Off"),
 910                                 bp_result);
 911
 912                 if (!power_up)
 913                         /*save driver power off time stamp*/
 914                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 915                 else
 916                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 917
 918                 DC_LOG_HW_RESUME_S3(
 919                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 920                                 __func__,
 921                                 link->link_trace.time_stamp.edp_poweroff,
 922                                 link->link_trace.time_stamp.edp_poweron);
 923
 924                 if (bp_result != BP_RESULT_OK)
 925                         DC_LOG_ERROR(
 926                                         "%s: Panel Power bp_result: %d\n",
 927                                         __func__, bp_result);
 928         } else {
 929                 DC_LOG_HW_RESUME_S3(
 930                                 "%s: Skipping Panel Power action: %s\n",
 931                                 __func__, (power_up ? "On":"Off"));
 932         }
 933 }
 934
 935 void dce110_edp_wait_for_T12(
 936                 struct dc_link *link)
 937 {
 938         struct dc_context *ctx = link->ctx;
 939
 940         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 941                         != CONNECTOR_ID_EDP) {
 942                 BREAK_TO_DEBUGGER();
 943                 return;
 944         }
 945
 946         if (!link->panel_cntl)
 947                 return;
 948
 949         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 950                         link->link_trace.time_stamp.edp_poweroff != 0) {
 951                 unsigned int t12_duration = 500; // Default T12 as per spec
 952                 unsigned long long current_ts = dm_get_timestamp(ctx);
 953                 unsigned long long time_since_edp_poweroff_ms =
 954                                 div64_u64(dm_get_elapse_time_in_ns(
 955                                                 ctx,
 956                                                 current_ts,
 957                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 958
 959                 t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
 960
 961                 if (time_since_edp_poweroff_ms < t12_duration)
 962                         msleep(t12_duration - time_since_edp_poweroff_ms);
 963         }
 964 }
 965
 966 /*todo: cloned in stream enc, fix*/
 967 /*
 968  * @brief
 969  * eDP only. Control the backlight of the eDP panel
 970  */
 971 void dce110_edp_backlight_control(
 972                 struct dc_link *link,
 973                 bool enable)
 974 {
 975         struct dc_context *ctx = link->ctx;
 976         struct bp_transmitter_control cntl = { 0 };
 977         uint8_t panel_instance;
 978
 979         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 980                 != CONNECTOR_ID_EDP) {
 981                 BREAK_TO_DEBUGGER();
 982                 return;
 983         }
 984
 985         if (link->panel_cntl) {
 986                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 987
 988                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 989                         DC_LOG_HW_RESUME_S3(
 990                                 "%s: panel already powered up/off. Do nothing.\n",
 991                                 __func__);
 992                         return;
 993                 }
 994         }
 995
 996         /* Send VBIOS command to control eDP panel backlight */
 997
 998         DC_LOG_HW_RESUME_S3(
 999                         "%s: backlight action: %s\n",
1000                         __func__, (enable ? "On":"Off"));
1001
1002         cntl.action = enable ?
1003                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
1004                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
1005
1006         /*cntl.engine_id = ctx->engine;*/
1007         cntl.transmitter = link->link_enc->transmitter;
1008         cntl.connector_obj_id = link->link_enc->connector;
1009         /*todo: unhardcode*/
1010         cntl.lanes_number = LANE_COUNT_FOUR;
1011         cntl.hpd_sel = link->link_enc->hpd_source;
1012         cntl.signal = SIGNAL_TYPE_EDP;
1013
1014         /* For eDP, the following delays might need to be considered
1015          * after link training completed:
1016          * idle period - min. accounts for required BS-Idle pattern,
1017          * max. allows for source frame synchronization);
1018          * 50 msec max. delay from valid video data from source
1019          * to video on dislpay or backlight enable.
1020          *
1021          * Disable the delay for now.
1022          * Enable it in the future if necessary.
1023          */
1024         /* dc_service_sleep_in_milliseconds(50); */
1025                 /*edp 1.2*/
1026         panel_instance = link->panel_cntl->inst;
1027
1028         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1029                 if (!link->dc->config.edp_no_power_sequencing)
1030                 /*
1031                  * Sometimes, DP receiver chip power-controlled externally by an
1032                  * Embedded Controller could be treated and used as eDP,
1033                  * if it drives mobile display. In this case,
1034                  * we shouldn't be doing power-sequencing, hence we can skip
1035                  * waiting for T7-ready.
1036                  */
1037                         edp_receiver_ready_T7(link);
1038                 else
1039                         DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1040         }
1041
1042         if (ctx->dc->ctx->dmub_srv &&
1043                         ctx->dc->debug.dmub_command_table) {
1044                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1045                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1046                                         LVTMA_CONTROL_LCD_BLON,
1047                                         panel_instance);
1048                 else
1049                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1050                                         LVTMA_CONTROL_LCD_BLOFF,
1051                                         panel_instance);
1052         }
1053
1054         link_transmitter_control(ctx->dc_bios, &cntl);
1055
1056         if (enable && link->dpcd_sink_ext_caps.bits.oled)
1057                 msleep(OLED_POST_T7_DELAY);
1058
1059         if (link->dpcd_sink_ext_caps.bits.oled ||
1060                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1061                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1062                 dc_link_backlight_enable_aux(link, enable);
1063
1064         /*edp 1.2*/
1065         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1066                 if (!link->dc->config.edp_no_power_sequencing)
1067                 /*
1068                  * Sometimes, DP receiver chip power-controlled externally by an
1069                  * Embedded Controller could be treated and used as eDP,
1070                  * if it drives mobile display. In this case,
1071                  * we shouldn't be doing power-sequencing, hence we can skip
1072                  * waiting for T9-ready.
1073                  */
1074                         edp_add_delay_for_T9(link);
1075                 else
1076                         DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1077         }
1078
1079         if (!enable && link->dpcd_sink_ext_caps.bits.oled)
1080                 msleep(OLED_PRE_T11_DELAY);
1081 }
1082
1083 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1084 {
1085         /* notify audio driver for audio modes of monitor */
1086         struct dc *dc;
1087         struct clk_mgr *clk_mgr;
1088         unsigned int i, num_audio = 1;
1089
1090         if (!pipe_ctx->stream)
1091                 return;
1092
1093         dc = pipe_ctx->stream->ctx->dc;
1094         clk_mgr = dc->clk_mgr;
1095
1096         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1097                 return;
1098
1099         if (pipe_ctx->stream_res.audio) {
1100                 for (i = 0; i < MAX_PIPES; i++) {
1101                         /*current_state not updated yet*/
1102                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1103                                 num_audio++;
1104                 }
1105
1106                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1107
1108                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1109                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1110                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1111                 /* un-mute audio */
1112                 /* TODO: audio should be per stream rather than per link */
1113 #if defined(CONFIG_DRM_AMD_DC_DCN)
1114                 if (is_dp_128b_132b_signal(pipe_ctx))
1115                         pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
1116                                         pipe_ctx->stream_res.hpo_dp_stream_enc, false);
1117                 else
1118                         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1119                                         pipe_ctx->stream_res.stream_enc, false);
1120 #else
1121                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1122                                 pipe_ctx->stream_res.stream_enc, false);
1123 #endif
1124                 if (pipe_ctx->stream_res.audio)
1125                         pipe_ctx->stream_res.audio->enabled = true;
1126         }
1127
1128         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1129                 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM);
1130 }
1131
1132 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1133 {
1134         struct dc *dc;
1135         struct clk_mgr *clk_mgr;
1136
1137         if (!pipe_ctx || !pipe_ctx->stream)
1138                 return;
1139
1140         dc = pipe_ctx->stream->ctx->dc;
1141         clk_mgr = dc->clk_mgr;
1142
1143         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1144                 return;
1145
1146 #if defined(CONFIG_DRM_AMD_DC_DCN)
1147         if (is_dp_128b_132b_signal(pipe_ctx))
1148                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
1149                                 pipe_ctx->stream_res.hpo_dp_stream_enc, true);
1150         else
1151                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1152                                 pipe_ctx->stream_res.stream_enc, true);
1153 #else
1154         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1155                         pipe_ctx->stream_res.stream_enc, true);
1156 #endif
1157         if (pipe_ctx->stream_res.audio) {
1158                 pipe_ctx->stream_res.audio->enabled = false;
1159
1160                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1161 #if defined(CONFIG_DRM_AMD_DC_DCN)
1162                         if (is_dp_128b_132b_signal(pipe_ctx))
1163                                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(
1164                                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1165                         else
1166                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1167                                                 pipe_ctx->stream_res.stream_enc);
1168 #else
1169                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1170                                         pipe_ctx->stream_res.stream_enc);
1171 #endif
1172                 else
1173                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1174                                         pipe_ctx->stream_res.stream_enc);
1175
1176                 if (clk_mgr->funcs->enable_pme_wa)
1177                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1178                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1179
1180                 /* TODO: notify audio driver for if audio modes list changed
1181                  * add audio mode list change flag */
1182                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1183                  * stream->stream_engine_id);
1184                  */
1185         }
1186
1187         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1188                 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM);
1189 }
1190
1191 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1192 {
1193         struct dc_stream_state *stream = pipe_ctx->stream;
1194         struct dc_link *link = stream->link;
1195         struct dc *dc = pipe_ctx->stream->ctx->dc;
1196         struct link_encoder *link_enc = NULL;
1197
1198         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1199                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1200                         pipe_ctx->stream_res.stream_enc);
1201                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1202                         pipe_ctx->stream_res.stream_enc);
1203         }
1204
1205 #if defined(CONFIG_DRM_AMD_DC_DCN)
1206         if (is_dp_128b_132b_signal(pipe_ctx)) {
1207                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1208                                         pipe_ctx->stream_res.hpo_dp_stream_enc);
1209         } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1210 #else
1211         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1212 #endif
1213                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1214                         pipe_ctx->stream_res.stream_enc);
1215
1216         dc->hwss.disable_audio_stream(pipe_ctx);
1217
1218         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
1219         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
1220                 link_enc = link->link_enc;
1221         else if (dc->res_pool->funcs->link_encs_assign)
1222                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
1223         ASSERT(link_enc);
1224
1225 #if defined(CONFIG_DRM_AMD_DC_DCN)
1226         if (is_dp_128b_132b_signal(pipe_ctx)) {
1227                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable(
1228                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1229                 setup_dp_hpo_stream(pipe_ctx, false);
1230         /* TODO - DP2.0 HW: unmap stream from link encoder here */
1231         } else {
1232                 if (link_enc)
1233                         link_enc->funcs->connect_dig_be_to_fe(
1234                                 link_enc,
1235                                 pipe_ctx->stream_res.stream_enc->id,
1236                                 false);
1237         }
1238 #else
1239         if (link_enc)
1240                 link_enc->funcs->connect_dig_be_to_fe(
1241                         link->link_enc,
1242                         pipe_ctx->stream_res.stream_enc->id,
1243                         false);
1244 #endif
1245         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1246                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
1247
1248 #if defined(CONFIG_DRM_AMD_DC_DCN)
1249         if (dc->hwseq->funcs.setup_hpo_hw_control && is_dp_128b_132b_signal(pipe_ctx))
1250                 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, false);
1251 #endif
1252
1253 }
1254
1255 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1256                 struct dc_link_settings *link_settings)
1257 {
1258         struct encoder_unblank_param params = { { 0 } };
1259         struct dc_stream_state *stream = pipe_ctx->stream;
1260         struct dc_link *link = stream->link;
1261         struct dce_hwseq *hws = link->dc->hwseq;
1262
1263         /* only 3 items below are used by unblank */
1264         params.timing = pipe_ctx->stream->timing;
1265         params.link_settings.link_rate = link_settings->link_rate;
1266
1267         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1268                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1269
1270         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1271                 hws->funcs.edp_backlight_control(link, true);
1272         }
1273 }
1274
1275 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1276 {
1277         struct dc_stream_state *stream = pipe_ctx->stream;
1278         struct dc_link *link = stream->link;
1279         struct dce_hwseq *hws = link->dc->hwseq;
1280
1281         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1282                 hws->funcs.edp_backlight_control(link, false);
1283                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1284         }
1285
1286 #if defined(CONFIG_DRM_AMD_DC_DCN)
1287         if (is_dp_128b_132b_signal(pipe_ctx)) {
1288                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1289                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1290                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1291         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1292 #else
1293         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1294 #endif
1295                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1296
1297                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1298                         /*
1299                          * After output is idle pattern some sinks need time to recognize the stream
1300                          * has changed or they enter protection state and hang.
1301                          */
1302                         msleep(60);
1303                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
1304                         edp_receiver_ready_T9(link);
1305         }
1306
1307 }
1308
1309
1310 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1311 {
1312         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1313                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1314 }
1315
1316 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1317 {
1318         switch (crtc_id) {
1319         case CONTROLLER_ID_D0:
1320                 return DTO_SOURCE_ID0;
1321         case CONTROLLER_ID_D1:
1322                 return DTO_SOURCE_ID1;
1323         case CONTROLLER_ID_D2:
1324                 return DTO_SOURCE_ID2;
1325         case CONTROLLER_ID_D3:
1326                 return DTO_SOURCE_ID3;
1327         case CONTROLLER_ID_D4:
1328                 return DTO_SOURCE_ID4;
1329         case CONTROLLER_ID_D5:
1330                 return DTO_SOURCE_ID5;
1331         default:
1332                 return DTO_SOURCE_UNKNOWN;
1333         }
1334 }
1335
1336 static void build_audio_output(
1337         struct dc_state *state,
1338         const struct pipe_ctx *pipe_ctx,
1339         struct audio_output *audio_output)
1340 {
1341         const struct dc_stream_state *stream = pipe_ctx->stream;
1342         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1343
1344         audio_output->signal = pipe_ctx->stream->signal;
1345
1346         /* audio_crtc_info  */
1347
1348         audio_output->crtc_info.h_total =
1349                 stream->timing.h_total;
1350
1351         /*
1352          * Audio packets are sent during actual CRTC blank physical signal, we
1353          * need to specify actual active signal portion
1354          */
1355         audio_output->crtc_info.h_active =
1356                         stream->timing.h_addressable
1357                         + stream->timing.h_border_left
1358                         + stream->timing.h_border_right;
1359
1360         audio_output->crtc_info.v_active =
1361                         stream->timing.v_addressable
1362                         + stream->timing.v_border_top
1363                         + stream->timing.v_border_bottom;
1364
1365         audio_output->crtc_info.pixel_repetition = 1;
1366
1367         audio_output->crtc_info.interlaced =
1368                         stream->timing.flags.INTERLACE;
1369
1370         audio_output->crtc_info.refresh_rate =
1371                 (stream->timing.pix_clk_100hz*100)/
1372                 (stream->timing.h_total*stream->timing.v_total);
1373
1374         audio_output->crtc_info.color_depth =
1375                 stream->timing.display_color_depth;
1376
1377         audio_output->crtc_info.requested_pixel_clock_100Hz =
1378                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1379
1380         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1381                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1382
1383 /*for HDMI, audio ACR is with deep color ratio factor*/
1384         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1385                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1386                                 (stream->timing.pix_clk_100hz)) {
1387                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1388                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1389                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1390                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1391                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1392
1393                 }
1394         }
1395
1396         if (state->clk_mgr &&
1397                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1398                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1399                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1400                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1401                                                 state->clk_mgr);
1402         }
1403
1404         audio_output->pll_info.feed_back_divider =
1405                         pipe_ctx->pll_settings.feedback_divider;
1406
1407         audio_output->pll_info.dto_source =
1408                 translate_to_dto_source(
1409                         pipe_ctx->stream_res.tg->inst + 1);
1410
1411         /* TODO hard code to enable for now. Need get from stream */
1412         audio_output->pll_info.ss_enabled = true;
1413
1414         audio_output->pll_info.ss_percentage =
1415                         pipe_ctx->pll_settings.ss_percentage;
1416 }
1417
1418 static void program_scaler(const struct dc *dc,
1419                 const struct pipe_ctx *pipe_ctx)
1420 {
1421         struct tg_color color = {0};
1422
1423 #if defined(CONFIG_DRM_AMD_DC_DCN)
1424         /* TOFPGA */
1425         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1426                 return;
1427 #endif
1428
1429         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1430                 get_surface_visual_confirm_color(pipe_ctx, &color);
1431         else
1432                 color_space_to_black_color(dc,
1433                                 pipe_ctx->stream->output_color_space,
1434                                 &color);
1435
1436         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1437                 pipe_ctx->plane_res.xfm,
1438                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1439                 &pipe_ctx->stream->bit_depth_params);
1440
1441         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1442                 /*
1443                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1444                  * alternate between Cb and Cr, so both channels need the pixel
1445                  * value for Y
1446                  */
1447                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1448                         color.color_r_cr = color.color_g_y;
1449
1450                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1451                                 pipe_ctx->stream_res.tg,
1452                                 &color);
1453         }
1454
1455         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1456                 &pipe_ctx->plane_res.scl_data);
1457 }
1458
1459 static enum dc_status dce110_enable_stream_timing(
1460                 struct pipe_ctx *pipe_ctx,
1461                 struct dc_state *context,
1462                 struct dc *dc)
1463 {
1464         struct dc_stream_state *stream = pipe_ctx->stream;
1465         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1466                         pipe_ctx[pipe_ctx->pipe_idx];
1467         struct tg_color black_color = {0};
1468
1469         if (!pipe_ctx_old->stream) {
1470
1471                 /* program blank color */
1472                 color_space_to_black_color(dc,
1473                                 stream->output_color_space, &black_color);
1474                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1475                                 pipe_ctx->stream_res.tg,
1476                                 &black_color);
1477
1478                 /*
1479                  * Must blank CRTC after disabling power gating and before any
1480                  * programming, otherwise CRTC will be hung in bad state
1481                  */
1482                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1483
1484                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1485                                 pipe_ctx->clock_source,
1486                                 &pipe_ctx->stream_res.pix_clk_params,
1487                                 &pipe_ctx->pll_settings)) {
1488                         BREAK_TO_DEBUGGER();
1489                         return DC_ERROR_UNEXPECTED;
1490                 }
1491
1492                 pipe_ctx->stream_res.tg->funcs->program_timing(
1493                                 pipe_ctx->stream_res.tg,
1494                                 &stream->timing,
1495                                 0,
1496                                 0,
1497                                 0,
1498                                 0,
1499                                 pipe_ctx->stream->signal,
1500                                 true);
1501         }
1502
1503         if (!pipe_ctx_old->stream) {
1504                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1505                                 pipe_ctx->stream_res.tg)) {
1506                         BREAK_TO_DEBUGGER();
1507                         return DC_ERROR_UNEXPECTED;
1508                 }
1509         }
1510
1511         return DC_OK;
1512 }
1513
1514 static enum dc_status apply_single_controller_ctx_to_hw(
1515                 struct pipe_ctx *pipe_ctx,
1516                 struct dc_state *context,
1517                 struct dc *dc)
1518 {
1519         struct dc_stream_state *stream = pipe_ctx->stream;
1520         struct dc_link *link = stream->link;
1521         struct drr_params params = {0};
1522         unsigned int event_triggers = 0;
1523         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1524         struct dce_hwseq *hws = dc->hwseq;
1525
1526         if (hws->funcs.disable_stream_gating) {
1527                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1528         }
1529
1530         if (pipe_ctx->stream_res.audio != NULL) {
1531                 struct audio_output audio_output;
1532
1533                 build_audio_output(context, pipe_ctx, &audio_output);
1534
1535                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1536 #if defined(CONFIG_DRM_AMD_DC_DCN)
1537                         if (is_dp_128b_132b_signal(pipe_ctx))
1538                                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(
1539                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1540                                                 pipe_ctx->stream_res.audio->inst,
1541                                                 &pipe_ctx->stream->audio_info);
1542                         else
1543                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1544                                                 pipe_ctx->stream_res.stream_enc,
1545                                                 pipe_ctx->stream_res.audio->inst,
1546                                                 &pipe_ctx->stream->audio_info);
1547 #else
1548                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1549                                         pipe_ctx->stream_res.stream_enc,
1550                                         pipe_ctx->stream_res.audio->inst,
1551                                         &pipe_ctx->stream->audio_info);
1552 #endif
1553                 else
1554                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1555                                         pipe_ctx->stream_res.stream_enc,
1556                                         pipe_ctx->stream_res.audio->inst,
1557                                         &pipe_ctx->stream->audio_info,
1558                                         &audio_output.crtc_info);
1559
1560                 pipe_ctx->stream_res.audio->funcs->az_configure(
1561                                 pipe_ctx->stream_res.audio,
1562                                 pipe_ctx->stream->signal,
1563                                 &audio_output.crtc_info,
1564                                 &pipe_ctx->stream->audio_info);
1565         }
1566
1567         /* make sure no pipes syncd to the pipe being enabled */
1568         if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1569                 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1570
1571 #if defined(CONFIG_DRM_AMD_DC_DCN)
1572         /* DCN3.1 FPGA Workaround
1573          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1574          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1575          * function core_link_enable_stream
1576          */
1577         if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)))
1578 #endif
1579                 /*  */
1580                 /* Do not touch stream timing on seamless boot optimization. */
1581                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1582                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1583
1584         if (hws->funcs.setup_vupdate_interrupt)
1585                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1586
1587         params.vertical_total_min = stream->adjust.v_total_min;
1588         params.vertical_total_max = stream->adjust.v_total_max;
1589         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1590                 pipe_ctx->stream_res.tg->funcs->set_drr(
1591                         pipe_ctx->stream_res.tg, &params);
1592
1593         // DRR should set trigger event to monitor surface update event
1594         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1595                 event_triggers = 0x80;
1596         /* Event triggers and num frames initialized for DRR, but can be
1597          * later updated for PSR use. Note DRR trigger events are generated
1598          * regardless of whether num frames met.
1599          */
1600         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1601                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1602                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1603
1604         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1605                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1606                         pipe_ctx->stream_res.stream_enc,
1607                         pipe_ctx->stream_res.tg->inst);
1608
1609         if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1610                 pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
1611                 pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
1612                         pipe_ctx->stream_res.stream_enc);
1613
1614         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1615                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1616
1617         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1618                         pipe_ctx->stream_res.opp,
1619                         COLOR_SPACE_YCBCR601,
1620                         stream->timing.display_color_depth,
1621                         stream->signal);
1622
1623         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1624                 pipe_ctx->stream_res.opp,
1625                 &stream->bit_depth_params,
1626                 &stream->clamping);
1627         while (odm_pipe) {
1628                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1629                                 odm_pipe->stream_res.opp,
1630                                 COLOR_SPACE_YCBCR601,
1631                                 stream->timing.display_color_depth,
1632                                 stream->signal);
1633
1634                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1635                                 odm_pipe->stream_res.opp,
1636                                 &stream->bit_depth_params,
1637                                 &stream->clamping);
1638                 odm_pipe = odm_pipe->next_odm_pipe;
1639         }
1640
1641         if (!stream->dpms_off)
1642                 core_link_enable_stream(context, pipe_ctx);
1643
1644 #if defined(CONFIG_DRM_AMD_DC_DCN)
1645         /* DCN3.1 FPGA Workaround
1646          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1647          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1648          * function core_link_enable_stream
1649          */
1650         if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) {
1651                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1652                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1653         }
1654 #endif
1655
1656         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1657
1658         pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1659
1660         return DC_OK;
1661 }
1662
1663 /******************************************************************************/
1664
1665 static void power_down_encoders(struct dc *dc)
1666 {
1667         int i;
1668
1669         for (i = 0; i < dc->link_count; i++) {
1670                 enum signal_type signal = dc->links[i]->connector_signal;
1671
1672                 dc_link_blank_dp_stream(dc->links[i], false);
1673
1674                 if (signal != SIGNAL_TYPE_EDP)
1675                         signal = SIGNAL_TYPE_NONE;
1676
1677                 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1678                         dc->links[i]->link_enc->funcs->disable_output(
1679                                         dc->links[i]->link_enc, signal);
1680
1681                 dc->links[i]->link_status.link_active = false;
1682                 memset(&dc->links[i]->cur_link_settings, 0,
1683                                 sizeof(dc->links[i]->cur_link_settings));
1684         }
1685 }
1686
1687 static void power_down_controllers(struct dc *dc)
1688 {
1689         int i;
1690
1691         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1692                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1693                                 dc->res_pool->timing_generators[i]);
1694         }
1695 }
1696
1697 static void power_down_clock_sources(struct dc *dc)
1698 {
1699         int i;
1700
1701         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1702                 dc->res_pool->dp_clock_source) == false)
1703                 dm_error("Failed to power down pll! (dp clk src)\n");
1704
1705         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1706                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1707                                 dc->res_pool->clock_sources[i]) == false)
1708                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1709         }
1710 }
1711
1712 static void power_down_all_hw_blocks(struct dc *dc)
1713 {
1714         power_down_encoders(dc);
1715
1716         power_down_controllers(dc);
1717
1718         power_down_clock_sources(dc);
1719
1720         if (dc->fbc_compressor)
1721                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1722 }
1723
1724 static void disable_vga_and_power_gate_all_controllers(
1725                 struct dc *dc)
1726 {
1727         int i;
1728         struct timing_generator *tg;
1729         struct dc_context *ctx = dc->ctx;
1730
1731         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1732                 tg = dc->res_pool->timing_generators[i];
1733
1734                 if (tg->funcs->disable_vga)
1735                         tg->funcs->disable_vga(tg);
1736         }
1737         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1738                 /* Enable CLOCK gating for each pipe BEFORE controller
1739                  * powergating. */
1740                 enable_display_pipe_clock_gating(ctx,
1741                                 true);
1742
1743                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1744                 dc->hwss.disable_plane(dc,
1745                         &dc->current_state->res_ctx.pipe_ctx[i]);
1746         }
1747 }
1748
1749
1750 static void get_edp_streams(struct dc_state *context,
1751                 struct dc_stream_state **edp_streams,
1752                 int *edp_stream_num)
1753 {
1754         int i;
1755
1756         *edp_stream_num = 0;
1757         for (i = 0; i < context->stream_count; i++) {
1758                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1759                         edp_streams[*edp_stream_num] = context->streams[i];
1760                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1761                                 return;
1762                 }
1763         }
1764 }
1765
1766 static void get_edp_links_with_sink(
1767                 struct dc *dc,
1768                 struct dc_link **edp_links_with_sink,
1769                 int *edp_with_sink_num)
1770 {
1771         int i;
1772
1773         /* check if there is an eDP panel not in use */
1774         *edp_with_sink_num = 0;
1775         for (i = 0; i < dc->link_count; i++) {
1776                 if (dc->links[i]->local_sink &&
1777                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1778                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1779                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1780                                 return;
1781                 }
1782         }
1783 }
1784
1785 /*
1786  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1787  *  1. Power down all DC HW blocks
1788  *  2. Disable VGA engine on all controllers
1789  *  3. Enable power gating for controller
1790  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1791  */
1792 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1793 {
1794         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1795         struct dc_link *edp_links[MAX_NUM_EDP];
1796         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1797         struct dc_link *edp_link_with_sink = NULL;
1798         struct dc_link *edp_link = NULL;
1799         struct dc_stream_state *edp_stream = NULL;
1800         struct dce_hwseq *hws = dc->hwseq;
1801         int edp_with_sink_num;
1802         int edp_num;
1803         int edp_stream_num;
1804         int i;
1805         bool can_apply_edp_fast_boot = false;
1806         bool can_apply_seamless_boot = false;
1807         bool keep_edp_vdd_on = false;
1808         DC_LOGGER_INIT();
1809
1810
1811         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1812         get_edp_links(dc, edp_links, &edp_num);
1813
1814         if (hws->funcs.init_pipes)
1815                 hws->funcs.init_pipes(dc, context);
1816
1817         get_edp_streams(context, edp_streams, &edp_stream_num);
1818
1819         // Check fastboot support, disable on DCE8 because of blank screens
1820         if (edp_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1821                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1822                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1823                 for (i = 0; i < edp_num; i++) {
1824                         edp_link = edp_links[i];
1825                         // enable fastboot if backend is enabled on eDP
1826                         if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
1827                                 /* Set optimization flag on eDP stream*/
1828                                 if (edp_stream_num && edp_link->link_status.link_active) {
1829                                         edp_stream = edp_streams[0];
1830                                         can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing);
1831                                         edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1832                                         if (can_apply_edp_fast_boot)
1833                                                 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1834
1835                                         break;
1836                                 }
1837                         }
1838                 }
1839                 // We are trying to enable eDP, don't power down VDD
1840                 if (edp_stream_num && can_apply_edp_fast_boot)
1841                         keep_edp_vdd_on = true;
1842         }
1843
1844         // Check seamless boot support
1845         for (i = 0; i < context->stream_count; i++) {
1846                 if (context->streams[i]->apply_seamless_boot_optimization) {
1847                         can_apply_seamless_boot = true;
1848                         break;
1849                 }
1850         }
1851
1852         /* eDP should not have stream in resume from S4 and so even with VBios post
1853          * it should get turned off
1854          */
1855         if (edp_with_sink_num)
1856                 edp_link_with_sink = edp_links_with_sink[0];
1857
1858         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1859                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1860                         /*turn off backlight before DP_blank and encoder powered down*/
1861                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1862                 }
1863                 /*resume from S3, no vbios posting, no need to power down again*/
1864                 power_down_all_hw_blocks(dc);
1865                 disable_vga_and_power_gate_all_controllers(dc);
1866                 if (edp_link_with_sink && !keep_edp_vdd_on)
1867                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1868         }
1869         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1870 }
1871
1872 static uint32_t compute_pstate_blackout_duration(
1873         struct bw_fixed blackout_duration,
1874         const struct dc_stream_state *stream)
1875 {
1876         uint32_t total_dest_line_time_ns;
1877         uint32_t pstate_blackout_duration_ns;
1878
1879         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1880
1881         total_dest_line_time_ns = 1000000UL *
1882                 (stream->timing.h_total * 10) /
1883                 stream->timing.pix_clk_100hz +
1884                 pstate_blackout_duration_ns;
1885
1886         return total_dest_line_time_ns;
1887 }
1888
1889 static void dce110_set_displaymarks(
1890         const struct dc *dc,
1891         struct dc_state *context)
1892 {
1893         uint8_t i, num_pipes;
1894         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1895
1896         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1897                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1898                 uint32_t total_dest_line_time_ns;
1899
1900                 if (pipe_ctx->stream == NULL)
1901                         continue;
1902
1903                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1904                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1905                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1906                         pipe_ctx->plane_res.mi,
1907                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1908                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1909                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1910                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1911                         total_dest_line_time_ns);
1912                 if (i == underlay_idx) {
1913                         num_pipes++;
1914                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1915                                 pipe_ctx->plane_res.mi,
1916                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1917                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1918                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1919                                 total_dest_line_time_ns);
1920                 }
1921                 num_pipes++;
1922         }
1923 }
1924
1925 void dce110_set_safe_displaymarks(
1926                 struct resource_context *res_ctx,
1927                 const struct resource_pool *pool)
1928 {
1929         int i;
1930         int underlay_idx = pool->underlay_pipe_index;
1931         struct dce_watermarks max_marks = {
1932                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1933         struct dce_watermarks nbp_marks = {
1934                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1935         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1936
1937         for (i = 0; i < MAX_PIPES; i++) {
1938                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1939                         continue;
1940
1941                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1942                                 res_ctx->pipe_ctx[i].plane_res.mi,
1943                                 nbp_marks,
1944                                 max_marks,
1945                                 min_marks,
1946                                 max_marks,
1947                                 MAX_WATERMARK);
1948
1949                 if (i == underlay_idx)
1950                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1951                                 res_ctx->pipe_ctx[i].plane_res.mi,
1952                                 nbp_marks,
1953                                 max_marks,
1954                                 max_marks,
1955                                 MAX_WATERMARK);
1956
1957         }
1958 }
1959
1960 /*******************************************************************************
1961  * Public functions
1962  ******************************************************************************/
1963
1964 static void set_drr(struct pipe_ctx **pipe_ctx,
1965                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1966 {
1967         int i = 0;
1968         struct drr_params params = {0};
1969         // DRR should set trigger event to monitor surface update event
1970         unsigned int event_triggers = 0x80;
1971         // Note DRR trigger events are generated regardless of whether num frames met.
1972         unsigned int num_frames = 2;
1973
1974         params.vertical_total_max = adjust.v_total_max;
1975         params.vertical_total_min = adjust.v_total_min;
1976
1977         /* TODO: If multiple pipes are to be supported, you need
1978          * some GSL stuff. Static screen triggers may be programmed differently
1979          * as well.
1980          */
1981         for (i = 0; i < num_pipes; i++) {
1982                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1983                         pipe_ctx[i]->stream_res.tg, &params);
1984
1985                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1986                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1987                                         pipe_ctx[i]->stream_res.tg,
1988                                         event_triggers, num_frames);
1989         }
1990 }
1991
1992 static void get_position(struct pipe_ctx **pipe_ctx,
1993                 int num_pipes,
1994                 struct crtc_position *position)
1995 {
1996         int i = 0;
1997
1998         /* TODO: handle pipes > 1
1999          */
2000         for (i = 0; i < num_pipes; i++)
2001                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2002 }
2003
2004 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2005                 int num_pipes, const struct dc_static_screen_params *params)
2006 {
2007         unsigned int i;
2008         unsigned int triggers = 0;
2009
2010         if (params->triggers.overlay_update)
2011                 triggers |= 0x100;
2012         if (params->triggers.surface_update)
2013                 triggers |= 0x80;
2014         if (params->triggers.cursor_update)
2015                 triggers |= 0x2;
2016         if (params->triggers.force_trigger)
2017                 triggers |= 0x1;
2018
2019         if (num_pipes) {
2020                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
2021
2022                 if (dc->fbc_compressor)
2023                         triggers |= 0x84;
2024         }
2025
2026         for (i = 0; i < num_pipes; i++)
2027                 pipe_ctx[i]->stream_res.tg->funcs->
2028                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
2029                                         triggers, params->num_frames);
2030 }
2031
2032 /*
2033  *  Check if FBC can be enabled
2034  */
2035 static bool should_enable_fbc(struct dc *dc,
2036                 struct dc_state *context,
2037                 uint32_t *pipe_idx)
2038 {
2039         uint32_t i;
2040         struct pipe_ctx *pipe_ctx = NULL;
2041         struct resource_context *res_ctx = &context->res_ctx;
2042         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2043
2044
2045         ASSERT(dc->fbc_compressor);
2046
2047         /* FBC memory should be allocated */
2048         if (!dc->ctx->fbc_gpu_addr)
2049                 return false;
2050
2051         /* Only supports single display */
2052         if (context->stream_count != 1)
2053                 return false;
2054
2055         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2056                 if (res_ctx->pipe_ctx[i].stream) {
2057
2058                         pipe_ctx = &res_ctx->pipe_ctx[i];
2059
2060                         if (!pipe_ctx)
2061                                 continue;
2062
2063                         /* fbc not applicable on underlay pipe */
2064                         if (pipe_ctx->pipe_idx != underlay_idx) {
2065                                 *pipe_idx = i;
2066                                 break;
2067                         }
2068                 }
2069         }
2070
2071         if (i == dc->res_pool->pipe_count)
2072                 return false;
2073
2074         if (!pipe_ctx->stream->link)
2075                 return false;
2076
2077         /* Only supports eDP */
2078         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2079                 return false;
2080
2081         /* PSR should not be enabled */
2082         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2083                 return false;
2084
2085         /* Nothing to compress */
2086         if (!pipe_ctx->plane_state)
2087                 return false;
2088
2089         /* Only for non-linear tiling */
2090         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2091                 return false;
2092
2093         return true;
2094 }
2095
2096 /*
2097  *  Enable FBC
2098  */
2099 static void enable_fbc(
2100                 struct dc *dc,
2101                 struct dc_state *context)
2102 {
2103         uint32_t pipe_idx = 0;
2104
2105         if (should_enable_fbc(dc, context, &pipe_idx)) {
2106                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2107                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2108                 struct compressor *compr = dc->fbc_compressor;
2109                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2110
2111                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2112                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2113                 params.inst = pipe_ctx->stream_res.tg->inst;
2114                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2115
2116                 compr->funcs->surface_address_and_pitch(compr, &params);
2117                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2118
2119                 compr->funcs->enable_fbc(compr, &params);
2120         }
2121 }
2122
2123 static void dce110_reset_hw_ctx_wrap(
2124                 struct dc *dc,
2125                 struct dc_state *context)
2126 {
2127         int i;
2128
2129         /* Reset old context */
2130         /* look up the targets that have been removed since last commit */
2131         for (i = 0; i < MAX_PIPES; i++) {
2132                 struct pipe_ctx *pipe_ctx_old =
2133                         &dc->current_state->res_ctx.pipe_ctx[i];
2134                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2135
2136                 /* Note: We need to disable output if clock sources change,
2137                  * since bios does optimization and doesn't apply if changing
2138                  * PHY when not already disabled.
2139                  */
2140
2141                 /* Skip underlay pipe since it will be handled in commit surface*/
2142                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2143                         continue;
2144
2145                 if (!pipe_ctx->stream ||
2146                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2147                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2148
2149                         /* Disable if new stream is null. O/w, if stream is
2150                          * disabled already, no need to disable again.
2151                          */
2152                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2153                                 core_link_disable_stream(pipe_ctx_old);
2154
2155                                 /* free acquired resources*/
2156                                 if (pipe_ctx_old->stream_res.audio) {
2157                                         /*disable az_endpoint*/
2158                                         pipe_ctx_old->stream_res.audio->funcs->
2159                                                         az_disable(pipe_ctx_old->stream_res.audio);
2160
2161                                         /*free audio*/
2162                                         if (dc->caps.dynamic_audio == true) {
2163                                                 /*we have to dynamic arbitrate the audio endpoints*/
2164                                                 /*we free the resource, need reset is_audio_acquired*/
2165                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2166                                                                 pipe_ctx_old->stream_res.audio, false);
2167                                                 pipe_ctx_old->stream_res.audio = NULL;
2168                                         }
2169                                 }
2170                         }
2171
2172                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2173                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2174                                 dm_error("DC: failed to blank crtc!\n");
2175                                 BREAK_TO_DEBUGGER();
2176                         }
2177                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2178                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2179                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2180
2181                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2182                                                                                 dc->res_pool,
2183                                                                                 old_clk))
2184                                 old_clk->funcs->cs_power_down(old_clk);
2185
2186                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2187
2188                         pipe_ctx_old->stream = NULL;
2189                 }
2190         }
2191 }
2192
2193 static void dce110_setup_audio_dto(
2194                 struct dc *dc,
2195                 struct dc_state *context)
2196 {
2197         int i;
2198
2199         /* program audio wall clock. use HDMI as clock source if HDMI
2200          * audio active. Otherwise, use DP as clock source
2201          * first, loop to find any HDMI audio, if not, loop find DP audio
2202          */
2203         /* Setup audio rate clock source */
2204         /* Issue:
2205         * Audio lag happened on DP monitor when unplug a HDMI monitor
2206         *
2207         * Cause:
2208         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2209         * is set to either dto0 or dto1, audio should work fine.
2210         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2211         * set to dto0 will cause audio lag.
2212         *
2213         * Solution:
2214         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2215         * find first available pipe with audio, setup audio wall DTO per topology
2216         * instead of per pipe.
2217         */
2218         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2219                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2220
2221                 if (pipe_ctx->stream == NULL)
2222                         continue;
2223
2224                 if (pipe_ctx->top_pipe)
2225                         continue;
2226                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2227                         continue;
2228                 if (pipe_ctx->stream_res.audio != NULL) {
2229                         struct audio_output audio_output;
2230
2231                         build_audio_output(context, pipe_ctx, &audio_output);
2232
2233 #if defined(CONFIG_DRM_AMD_DC_DCN)
2234                         /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
2235                         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2236                                 /* disable audio DTBCLK DTO */
2237                                 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2238                                         dc->res_pool->dccg, 0);
2239
2240                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2241                                                 pipe_ctx->stream_res.audio,
2242                                                 pipe_ctx->stream->signal,
2243                                                 &audio_output.crtc_info,
2244                                                 &audio_output.pll_info);
2245                         } else
2246                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2247                                         pipe_ctx->stream_res.audio,
2248                                         pipe_ctx->stream->signal,
2249                                         &audio_output.crtc_info,
2250                                         &audio_output.pll_info);
2251 #else
2252                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2253                                 pipe_ctx->stream_res.audio,
2254                                 pipe_ctx->stream->signal,
2255                                 &audio_output.crtc_info,
2256                                 &audio_output.pll_info);
2257 #endif
2258                         break;
2259                 }
2260         }
2261
2262         /* no HDMI audio is found, try DP audio */
2263         if (i == dc->res_pool->pipe_count) {
2264                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2265                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2266
2267                         if (pipe_ctx->stream == NULL)
2268                                 continue;
2269
2270                         if (pipe_ctx->top_pipe)
2271                                 continue;
2272
2273                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2274                                 continue;
2275
2276                         if (pipe_ctx->stream_res.audio != NULL) {
2277                                 struct audio_output audio_output;
2278
2279                                 build_audio_output(context, pipe_ctx, &audio_output);
2280
2281                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2282                                         pipe_ctx->stream_res.audio,
2283                                         pipe_ctx->stream->signal,
2284                                         &audio_output.crtc_info,
2285                                         &audio_output.pll_info);
2286                                 break;
2287                         }
2288                 }
2289         }
2290 }
2291
2292 enum dc_status dce110_apply_ctx_to_hw(
2293                 struct dc *dc,
2294                 struct dc_state *context)
2295 {
2296         struct dce_hwseq *hws = dc->hwseq;
2297         struct dc_bios *dcb = dc->ctx->dc_bios;
2298         enum dc_status status;
2299         int i;
2300
2301         /* reset syncd pipes from disabled pipes */
2302         if (dc->config.use_pipe_ctx_sync_logic)
2303                 reset_syncd_pipes_from_disabled_pipes(dc, context);
2304
2305         /* Reset old context */
2306         /* look up the targets that have been removed since last commit */
2307         hws->funcs.reset_hw_ctx_wrap(dc, context);
2308
2309         /* Skip applying if no targets */
2310         if (context->stream_count <= 0)
2311                 return DC_OK;
2312
2313         /* Apply new context */
2314         dcb->funcs->set_scratch_critical_state(dcb, true);
2315
2316         /* below is for real asic only */
2317         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2318                 struct pipe_ctx *pipe_ctx_old =
2319                                         &dc->current_state->res_ctx.pipe_ctx[i];
2320                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2321
2322                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2323                         continue;
2324
2325                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2326                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2327                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2328                                                 pipe_ctx->clock_source, i);
2329                         continue;
2330                 }
2331
2332                 hws->funcs.enable_display_power_gating(
2333                                 dc, i, dc->ctx->dc_bios,
2334                                 PIPE_GATING_CONTROL_DISABLE);
2335         }
2336
2337         if (dc->fbc_compressor)
2338                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2339
2340         dce110_setup_audio_dto(dc, context);
2341
2342         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2343                 struct pipe_ctx *pipe_ctx_old =
2344                                         &dc->current_state->res_ctx.pipe_ctx[i];
2345                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2346
2347                 if (pipe_ctx->stream == NULL)
2348                         continue;
2349
2350                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2351                         pipe_ctx->stream->link->link_state_valid) {
2352                         continue;
2353                 }
2354
2355                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2356                         continue;
2357
2358                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2359                         continue;
2360
2361                 status = apply_single_controller_ctx_to_hw(
2362                                 pipe_ctx,
2363                                 context,
2364                                 dc);
2365
2366                 if (DC_OK != status)
2367                         return status;
2368         }
2369
2370         if (dc->fbc_compressor)
2371                 enable_fbc(dc, dc->current_state);
2372
2373         dcb->funcs->set_scratch_critical_state(dcb, false);
2374
2375         return DC_OK;
2376 }
2377
2378 /*******************************************************************************
2379  * Front End programming
2380  ******************************************************************************/
2381 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2382 {
2383         struct default_adjustment default_adjust = { 0 };
2384
2385         default_adjust.force_hw_default = false;
2386         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2387         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2388         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2389         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2390
2391         /* display color depth */
2392         default_adjust.color_depth =
2393                 pipe_ctx->stream->timing.display_color_depth;
2394
2395         /* Lb color depth */
2396         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2397
2398         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2399                                         pipe_ctx->plane_res.xfm, &default_adjust);
2400 }
2401
2402
2403 /*******************************************************************************
2404  * In order to turn on/off specific surface we will program
2405  * Blender + CRTC
2406  *
2407  * In case that we have two surfaces and they have a different visibility
2408  * we can't turn off the CRTC since it will turn off the entire display
2409  *
2410  * |----------------------------------------------- |
2411  * |bottom pipe|curr pipe  |              |         |
2412  * |Surface    |Surface    | Blender      |  CRCT   |
2413  * |visibility |visibility | Configuration|         |
2414  * |------------------------------------------------|
2415  * |   off     |    off    | CURRENT_PIPE | blank   |
2416  * |   off     |    on     | CURRENT_PIPE | unblank |
2417  * |   on      |    off    | OTHER_PIPE   | unblank |
2418  * |   on      |    on     | BLENDING     | unblank |
2419  * -------------------------------------------------|
2420  *
2421  ******************************************************************************/
2422 static void program_surface_visibility(const struct dc *dc,
2423                 struct pipe_ctx *pipe_ctx)
2424 {
2425         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2426         bool blank_target = false;
2427
2428         if (pipe_ctx->bottom_pipe) {
2429
2430                 /* For now we are supporting only two pipes */
2431                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2432
2433                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2434                         if (pipe_ctx->plane_state->visible)
2435                                 blender_mode = BLND_MODE_BLENDING;
2436                         else
2437                                 blender_mode = BLND_MODE_OTHER_PIPE;
2438
2439                 } else if (!pipe_ctx->plane_state->visible)
2440                         blank_target = true;
2441
2442         } else if (!pipe_ctx->plane_state->visible)
2443                 blank_target = true;
2444
2445         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2446         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2447
2448 }
2449
2450 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2451 {
2452         int i = 0;
2453         struct xfm_grph_csc_adjustment adjust;
2454         memset(&adjust, 0, sizeof(adjust));
2455         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2456
2457
2458         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2459                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2460
2461                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2462                         adjust.temperature_matrix[i] =
2463                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2464         }
2465
2466         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2467 }
2468 static void update_plane_addr(const struct dc *dc,
2469                 struct pipe_ctx *pipe_ctx)
2470 {
2471         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2472
2473         if (plane_state == NULL)
2474                 return;
2475
2476         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2477                         pipe_ctx->plane_res.mi,
2478                         &plane_state->address,
2479                         plane_state->flip_immediate);
2480
2481         plane_state->status.requested_address = plane_state->address;
2482 }
2483
2484 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2485 {
2486         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2487
2488         if (plane_state == NULL)
2489                 return;
2490
2491         plane_state->status.is_flip_pending =
2492                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2493                                         pipe_ctx->plane_res.mi);
2494
2495         if (plane_state->status.is_flip_pending && !plane_state->visible)
2496                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2497
2498         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2499         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2500                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2501                 plane_state->status.is_right_eye =\
2502                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2503         }
2504 }
2505
2506 void dce110_power_down(struct dc *dc)
2507 {
2508         power_down_all_hw_blocks(dc);
2509         disable_vga_and_power_gate_all_controllers(dc);
2510 }
2511
2512 static bool wait_for_reset_trigger_to_occur(
2513         struct dc_context *dc_ctx,
2514         struct timing_generator *tg)
2515 {
2516         bool rc = false;
2517
2518         /* To avoid endless loop we wait at most
2519          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2520         const uint32_t frames_to_wait_on_triggered_reset = 10;
2521         uint32_t i;
2522
2523         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2524
2525                 if (!tg->funcs->is_counter_moving(tg)) {
2526                         DC_ERROR("TG counter is not moving!\n");
2527                         break;
2528                 }
2529
2530                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2531                         rc = true;
2532                         /* usually occurs at i=1 */
2533                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2534                                         i);
2535                         break;
2536                 }
2537
2538                 /* Wait for one frame. */
2539                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2540                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2541         }
2542
2543         if (false == rc)
2544                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2545
2546         return rc;
2547 }
2548
2549 /* Enable timing synchronization for a group of Timing Generators. */
2550 static void dce110_enable_timing_synchronization(
2551                 struct dc *dc,
2552                 int group_index,
2553                 int group_size,
2554                 struct pipe_ctx *grouped_pipes[])
2555 {
2556         struct dc_context *dc_ctx = dc->ctx;
2557         struct dcp_gsl_params gsl_params = { 0 };
2558         int i;
2559
2560         DC_SYNC_INFO("GSL: Setting-up...\n");
2561
2562         /* Designate a single TG in the group as a master.
2563          * Since HW doesn't care which one, we always assign
2564          * the 1st one in the group. */
2565         gsl_params.gsl_group = 0;
2566         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2567
2568         for (i = 0; i < group_size; i++)
2569                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2570                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2571
2572         /* Reset slave controllers on master VSync */
2573         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2574
2575         for (i = 1 /* skip the master */; i < group_size; i++)
2576                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2577                                 grouped_pipes[i]->stream_res.tg,
2578                                 gsl_params.gsl_group);
2579
2580         for (i = 1 /* skip the master */; i < group_size; i++) {
2581                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2582                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2583                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2584                                 grouped_pipes[i]->stream_res.tg);
2585         }
2586
2587         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2588          * is that the sync'ed displays will not drift out of sync over time*/
2589         DC_SYNC_INFO("GSL: Restoring register states.\n");
2590         for (i = 0; i < group_size; i++)
2591                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2592
2593         DC_SYNC_INFO("GSL: Set-up complete.\n");
2594 }
2595
2596 static void dce110_enable_per_frame_crtc_position_reset(
2597                 struct dc *dc,
2598                 int group_size,
2599                 struct pipe_ctx *grouped_pipes[])
2600 {
2601         struct dc_context *dc_ctx = dc->ctx;
2602         struct dcp_gsl_params gsl_params = { 0 };
2603         int i;
2604
2605         gsl_params.gsl_group = 0;
2606         gsl_params.gsl_master = 0;
2607
2608         for (i = 0; i < group_size; i++)
2609                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2610                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2611
2612         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2613
2614         for (i = 1; i < group_size; i++)
2615                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2616                                 grouped_pipes[i]->stream_res.tg,
2617                                 gsl_params.gsl_master,
2618                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2619
2620         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2621         for (i = 1; i < group_size; i++)
2622                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2623
2624         for (i = 0; i < group_size; i++)
2625                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2626
2627 }
2628
2629 static void init_pipes(struct dc *dc, struct dc_state *context)
2630 {
2631         // Do nothing
2632 }
2633
2634 static void init_hw(struct dc *dc)
2635 {
2636         int i;
2637         struct dc_bios *bp;
2638         struct transform *xfm;
2639         struct abm *abm;
2640         struct dmcu *dmcu;
2641         struct dce_hwseq *hws = dc->hwseq;
2642         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2643
2644         bp = dc->ctx->dc_bios;
2645         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2646                 xfm = dc->res_pool->transforms[i];
2647                 xfm->funcs->transform_reset(xfm);
2648
2649                 hws->funcs.enable_display_power_gating(
2650                                 dc, i, bp,
2651                                 PIPE_GATING_CONTROL_INIT);
2652                 hws->funcs.enable_display_power_gating(
2653                                 dc, i, bp,
2654                                 PIPE_GATING_CONTROL_DISABLE);
2655                 hws->funcs.enable_display_pipe_clock_gating(
2656                         dc->ctx,
2657                         true);
2658         }
2659
2660         dce_clock_gating_power_up(dc->hwseq, false);
2661         /***************************************/
2662
2663         for (i = 0; i < dc->link_count; i++) {
2664                 /****************************************/
2665                 /* Power up AND update implementation according to the
2666                  * required signal (which may be different from the
2667                  * default signal on connector). */
2668                 struct dc_link *link = dc->links[i];
2669
2670                 link->link_enc->funcs->hw_init(link->link_enc);
2671         }
2672
2673         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2674                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2675
2676                 tg->funcs->disable_vga(tg);
2677
2678                 /* Blank controller using driver code instead of
2679                  * command table. */
2680                 tg->funcs->set_blank(tg, true);
2681                 hwss_wait_for_blank_complete(tg);
2682         }
2683
2684         for (i = 0; i < dc->res_pool->audio_count; i++) {
2685                 struct audio *audio = dc->res_pool->audios[i];
2686                 audio->funcs->hw_init(audio);
2687         }
2688
2689         for (i = 0; i < dc->link_count; i++) {
2690                 struct dc_link *link = dc->links[i];
2691
2692                 if (link->panel_cntl)
2693                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2694         }
2695
2696         abm = dc->res_pool->abm;
2697         if (abm != NULL)
2698                 abm->funcs->abm_init(abm, backlight);
2699
2700         dmcu = dc->res_pool->dmcu;
2701         if (dmcu != NULL && abm != NULL)
2702                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2703
2704         if (dc->fbc_compressor)
2705                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2706
2707 }
2708
2709
2710 void dce110_prepare_bandwidth(
2711                 struct dc *dc,
2712                 struct dc_state *context)
2713 {
2714         struct clk_mgr *dccg = dc->clk_mgr;
2715
2716         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2717
2718         dccg->funcs->update_clocks(
2719                         dccg,
2720                         context,
2721                         false);
2722 }
2723
2724 void dce110_optimize_bandwidth(
2725                 struct dc *dc,
2726                 struct dc_state *context)
2727 {
2728         struct clk_mgr *dccg = dc->clk_mgr;
2729
2730         dce110_set_displaymarks(dc, context);
2731
2732         dccg->funcs->update_clocks(
2733                         dccg,
2734                         context,
2735                         true);
2736 }
2737
2738 static void dce110_program_front_end_for_pipe(
2739                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2740 {
2741         struct mem_input *mi = pipe_ctx->plane_res.mi;
2742         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2743         struct xfm_grph_csc_adjustment adjust;
2744         struct out_csc_color_matrix tbl_entry;
2745         unsigned int i;
2746         struct dce_hwseq *hws = dc->hwseq;
2747
2748         DC_LOGGER_INIT();
2749         memset(&tbl_entry, 0, sizeof(tbl_entry));
2750
2751         memset(&adjust, 0, sizeof(adjust));
2752         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2753
2754         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2755
2756         set_default_colors(pipe_ctx);
2757         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2758                         == true) {
2759                 tbl_entry.color_space =
2760                         pipe_ctx->stream->output_color_space;
2761
2762                 for (i = 0; i < 12; i++)
2763                         tbl_entry.regval[i] =
2764                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2765
2766                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2767                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2768         }
2769
2770         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2771                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2772
2773                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2774                         adjust.temperature_matrix[i] =
2775                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2776         }
2777
2778         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2779
2780         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2781
2782         program_scaler(dc, pipe_ctx);
2783
2784         mi->funcs->mem_input_program_surface_config(
2785                         mi,
2786                         plane_state->format,
2787                         &plane_state->tiling_info,
2788                         &plane_state->plane_size,
2789                         plane_state->rotation,
2790                         NULL,
2791                         false);
2792         if (mi->funcs->set_blank)
2793                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2794
2795         if (dc->config.gpu_vm_support)
2796                 mi->funcs->mem_input_program_pte_vm(
2797                                 pipe_ctx->plane_res.mi,
2798                                 plane_state->format,
2799                                 &plane_state->tiling_info,
2800                                 plane_state->rotation);
2801
2802         /* Moved programming gamma from dc to hwss */
2803         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2804                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2805                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2806                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2807
2808         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2809                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2810
2811         DC_LOG_SURFACE(
2812                         "Pipe:%d %p: addr hi:0x%x, "
2813                         "addr low:0x%x, "
2814                         "src: %d, %d, %d,"
2815                         " %d; dst: %d, %d, %d, %d;"
2816                         "clip: %d, %d, %d, %d\n",
2817                         pipe_ctx->pipe_idx,
2818                         (void *) pipe_ctx->plane_state,
2819                         pipe_ctx->plane_state->address.grph.addr.high_part,
2820                         pipe_ctx->plane_state->address.grph.addr.low_part,
2821                         pipe_ctx->plane_state->src_rect.x,
2822                         pipe_ctx->plane_state->src_rect.y,
2823                         pipe_ctx->plane_state->src_rect.width,
2824                         pipe_ctx->plane_state->src_rect.height,
2825                         pipe_ctx->plane_state->dst_rect.x,
2826                         pipe_ctx->plane_state->dst_rect.y,
2827                         pipe_ctx->plane_state->dst_rect.width,
2828                         pipe_ctx->plane_state->dst_rect.height,
2829                         pipe_ctx->plane_state->clip_rect.x,
2830                         pipe_ctx->plane_state->clip_rect.y,
2831                         pipe_ctx->plane_state->clip_rect.width,
2832                         pipe_ctx->plane_state->clip_rect.height);
2833
2834         DC_LOG_SURFACE(
2835                         "Pipe %d: width, height, x, y\n"
2836                         "viewport:%d, %d, %d, %d\n"
2837                         "recout:  %d, %d, %d, %d\n",
2838                         pipe_ctx->pipe_idx,
2839                         pipe_ctx->plane_res.scl_data.viewport.width,
2840                         pipe_ctx->plane_res.scl_data.viewport.height,
2841                         pipe_ctx->plane_res.scl_data.viewport.x,
2842                         pipe_ctx->plane_res.scl_data.viewport.y,
2843                         pipe_ctx->plane_res.scl_data.recout.width,
2844                         pipe_ctx->plane_res.scl_data.recout.height,
2845                         pipe_ctx->plane_res.scl_data.recout.x,
2846                         pipe_ctx->plane_res.scl_data.recout.y);
2847 }
2848
2849 static void dce110_apply_ctx_for_surface(
2850                 struct dc *dc,
2851                 const struct dc_stream_state *stream,
2852                 int num_planes,
2853                 struct dc_state *context)
2854 {
2855         int i;
2856
2857         if (num_planes == 0)
2858                 return;
2859
2860         if (dc->fbc_compressor)
2861                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2862
2863         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2864                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2865
2866                 if (pipe_ctx->stream != stream)
2867                         continue;
2868
2869                 /* Need to allocate mem before program front end for Fiji */
2870                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2871                                 pipe_ctx->plane_res.mi,
2872                                 pipe_ctx->stream->timing.h_total,
2873                                 pipe_ctx->stream->timing.v_total,
2874                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2875                                 context->stream_count);
2876
2877                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2878
2879                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2880
2881                 program_surface_visibility(dc, pipe_ctx);
2882
2883         }
2884
2885         if (dc->fbc_compressor)
2886                 enable_fbc(dc, context);
2887 }
2888
2889 static void dce110_post_unlock_program_front_end(
2890                 struct dc *dc,
2891                 struct dc_state *context)
2892 {
2893 }
2894
2895 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2896 {
2897         struct dce_hwseq *hws = dc->hwseq;
2898         int fe_idx = pipe_ctx->plane_res.mi ?
2899                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2900
2901         /* Do not power down fe when stream is active on dce*/
2902         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2903                 return;
2904
2905         hws->funcs.enable_display_power_gating(
2906                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2907
2908         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2909                                 dc->res_pool->transforms[fe_idx]);
2910 }
2911
2912 static void dce110_wait_for_mpcc_disconnect(
2913                 struct dc *dc,
2914                 struct resource_pool *res_pool,
2915                 struct pipe_ctx *pipe_ctx)
2916 {
2917         /* do nothing*/
2918 }
2919
2920 static void program_output_csc(struct dc *dc,
2921                 struct pipe_ctx *pipe_ctx,
2922                 enum dc_color_space colorspace,
2923                 uint16_t *matrix,
2924                 int opp_id)
2925 {
2926         int i;
2927         struct out_csc_color_matrix tbl_entry;
2928
2929         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2930                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2931
2932                 for (i = 0; i < 12; i++)
2933                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2934
2935                 tbl_entry.color_space = color_space;
2936
2937                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2938                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2939         }
2940 }
2941
2942 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2943 {
2944         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2945         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2946         struct mem_input *mi = pipe_ctx->plane_res.mi;
2947         struct dc_cursor_mi_param param = {
2948                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2949                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2950                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2951                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2952                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2953                 .rotation = pipe_ctx->plane_state->rotation,
2954                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2955         };
2956
2957         /**
2958          * If the cursor's source viewport is clipped then we need to
2959          * translate the cursor to appear in the correct position on
2960          * the screen.
2961          *
2962          * This translation isn't affected by scaling so it needs to be
2963          * done *after* we adjust the position for the scale factor.
2964          *
2965          * This is only done by opt-in for now since there are still
2966          * some usecases like tiled display that might enable the
2967          * cursor on both streams while expecting dc to clip it.
2968          */
2969         if (pos_cpy.translate_by_source) {
2970                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2971                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2972         }
2973
2974         if (pipe_ctx->plane_state->address.type
2975                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2976                 pos_cpy.enable = false;
2977
2978         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2979                 pos_cpy.enable = false;
2980
2981         if (ipp->funcs->ipp_cursor_set_position)
2982                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2983         if (mi->funcs->set_cursor_position)
2984                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2985 }
2986
2987 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2988 {
2989         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2990
2991         if (pipe_ctx->plane_res.ipp &&
2992             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2993                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2994                                 pipe_ctx->plane_res.ipp, attributes);
2995
2996         if (pipe_ctx->plane_res.mi &&
2997             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2998                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2999                                 pipe_ctx->plane_res.mi, attributes);
3000
3001         if (pipe_ctx->plane_res.xfm &&
3002             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
3003                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
3004                                 pipe_ctx->plane_res.xfm, attributes);
3005 }
3006
3007 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
3008                 uint32_t backlight_pwm_u16_16,
3009                 uint32_t frame_ramp)
3010 {
3011         struct dc_link *link = pipe_ctx->stream->link;
3012         struct dc  *dc = link->ctx->dc;
3013         struct abm *abm = pipe_ctx->stream_res.abm;
3014         struct panel_cntl *panel_cntl = link->panel_cntl;
3015         struct dmcu *dmcu = dc->res_pool->dmcu;
3016         bool fw_set_brightness = true;
3017         /* DMCU -1 for all controller id values,
3018          * therefore +1 here
3019          */
3020         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
3021
3022         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
3023                 return false;
3024
3025         if (dmcu)
3026                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3027
3028         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
3029                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
3030         else
3031                 abm->funcs->set_backlight_level_pwm(
3032                                 abm,
3033                                 backlight_pwm_u16_16,
3034                                 frame_ramp,
3035                                 controller_id,
3036                                 link->panel_cntl->inst);
3037
3038         return true;
3039 }
3040
3041 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
3042 {
3043         struct abm *abm = pipe_ctx->stream_res.abm;
3044         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3045
3046         if (abm)
3047                 abm->funcs->set_abm_immediate_disable(abm,
3048                                 pipe_ctx->stream->link->panel_cntl->inst);
3049
3050         if (panel_cntl)
3051                 panel_cntl->funcs->store_backlight_level(panel_cntl);
3052 }
3053
3054 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3055 {
3056         struct abm *abm = pipe_ctx->stream_res.abm;
3057         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3058         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3059
3060         if (abm && panel_cntl)
3061                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3062 }
3063
3064 static const struct hw_sequencer_funcs dce110_funcs = {
3065         .program_gamut_remap = program_gamut_remap,
3066         .program_output_csc = program_output_csc,
3067         .init_hw = init_hw,
3068         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3069         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3070         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3071         .update_plane_addr = update_plane_addr,
3072         .update_pending_status = dce110_update_pending_status,
3073         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3074         .enable_timing_synchronization = dce110_enable_timing_synchronization,
3075         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3076         .update_info_frame = dce110_update_info_frame,
3077         .enable_stream = dce110_enable_stream,
3078         .disable_stream = dce110_disable_stream,
3079         .unblank_stream = dce110_unblank_stream,
3080         .blank_stream = dce110_blank_stream,
3081         .enable_audio_stream = dce110_enable_audio_stream,
3082         .disable_audio_stream = dce110_disable_audio_stream,
3083         .disable_plane = dce110_power_down_fe,
3084         .pipe_control_lock = dce_pipe_control_lock,
3085         .interdependent_update_lock = NULL,
3086         .cursor_lock = dce_pipe_control_lock,
3087         .prepare_bandwidth = dce110_prepare_bandwidth,
3088         .optimize_bandwidth = dce110_optimize_bandwidth,
3089         .set_drr = set_drr,
3090         .get_position = get_position,
3091         .set_static_screen_control = set_static_screen_control,
3092         .setup_stereo = NULL,
3093         .set_avmute = dce110_set_avmute,
3094         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3095         .edp_backlight_control = dce110_edp_backlight_control,
3096         .edp_power_control = dce110_edp_power_control,
3097         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3098         .set_cursor_position = dce110_set_cursor_position,
3099         .set_cursor_attribute = dce110_set_cursor_attribute,
3100         .set_backlight_level = dce110_set_backlight_level,
3101         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3102         .set_pipe = dce110_set_pipe,
3103 };
3104
3105 static const struct hwseq_private_funcs dce110_private_funcs = {
3106         .init_pipes = init_pipes,
3107         .update_plane_addr = update_plane_addr,
3108         .set_input_transfer_func = dce110_set_input_transfer_func,
3109         .set_output_transfer_func = dce110_set_output_transfer_func,
3110         .power_down = dce110_power_down,
3111         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3112         .enable_display_power_gating = dce110_enable_display_power_gating,
3113         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3114         .enable_stream_timing = dce110_enable_stream_timing,
3115         .disable_stream_gating = NULL,
3116         .enable_stream_gating = NULL,
3117         .edp_backlight_control = dce110_edp_backlight_control,
3118 };
3119
3120 void dce110_hw_sequencer_construct(struct dc *dc)
3121 {
3122         dc->hwss = dce110_funcs;
3123         dc->hwseq->funcs = dce110_private_funcs;
3124 }
3125