drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30 #include "dc_bios_types.h"
  31 #include "core_types.h"
  32 #include "core_status.h"
  33 #include "resource.h"
  34 #include "dm_helpers.h"
  35 #include "dce110_timing_generator.h"
  36 #include "dce/dce_hwseq.h"
  37 #include "gpio_service_interface.h"
  38
  39 #include "dce110_compressor.h"
  40
  41 #include "bios/bios_parser_helper.h"
  42 #include "timing_generator.h"
  43 #include "mem_input.h"
  44 #include "opp.h"
  45 #include "ipp.h"
  46 #include "transform.h"
  47 #include "stream_encoder.h"
  48 #include "link_encoder.h"
  49 #include "link_enc_cfg.h"
  50 #include "link_hwss.h"
  51 #include "dc_link_dp.h"
  52 #if defined(CONFIG_DRM_AMD_DC_DCN)
  53 #include "dccg.h"
  54 #endif
  55 #include "clock_source.h"
  56 #include "clk_mgr.h"
  57 #include "abm.h"
  58 #include "audio.h"
  59 #include "reg_helper.h"
  60 #include "panel_cntl.h"
  61 #include "inc/link_dpcd.h"
  62 #include "dpcd_defs.h"
  63 /* include DCE11 register header files */
  64 #include "dce/dce_11_0_d.h"
  65 #include "dce/dce_11_0_sh_mask.h"
  66 #include "custom_float.h"
  67
  68 #include "atomfirmware.h"
  69
  70 #include "dcn10/dcn10_hw_sequencer.h"
  71
  72 #include "dce110_hw_sequencer.h"
  73
  74 #define GAMMA_HW_POINTS_NUM 256
  75
  76 /*
  77  * All values are in milliseconds;
  78  * For eDP, after power-up/power/down,
  79  * 300/500 msec max. delay from LCDVCC to black video generation
  80  */
  81 #define PANEL_POWER_UP_TIMEOUT 300
  82 #define PANEL_POWER_DOWN_TIMEOUT 500
  83 #define HPD_CHECK_INTERVAL 10
  84 #define OLED_POST_T7_DELAY 100
  85 #define OLED_PRE_T11_DELAY 150
  86
  87 #define CTX \
  88         hws->ctx
  89
  90 #define DC_LOGGER_INIT()
  91
  92 #define REG(reg)\
  93         hws->regs->reg
  94
  95 #undef FN
  96 #define FN(reg_name, field_name) \
  97         hws->shifts->field_name, hws->masks->field_name
  98
  99 struct dce110_hw_seq_reg_offsets {
 100         uint32_t crtc;
 101 };
 102
 103 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
 104 {
 105         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 106 },
 107 {
 108         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 109 },
 110 {
 111         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 112 },
 113 {
 114         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 115 }
 116 };
 117
 118 #define HW_REG_BLND(reg, id)\
 119         (reg + reg_offsets[id].blnd)
 120
 121 #define HW_REG_CRTC(reg, id)\
 122         (reg + reg_offsets[id].crtc)
 123
 124 #define MAX_WATERMARK 0xFFFF
 125 #define SAFE_NBP_MARK 0x7FFF
 126
 127 /*******************************************************************************
 128  * Private definitions
 129  ******************************************************************************/
 130 /***************************PIPE_CONTROL***********************************/
 131 static void dce110_init_pte(struct dc_context *ctx)
 132 {
 133         uint32_t addr;
 134         uint32_t value = 0;
 135         uint32_t chunk_int = 0;
 136         uint32_t chunk_mul = 0;
 137
 138         addr = mmUNP_DVMM_PTE_CONTROL;
 139         value = dm_read_reg(ctx, addr);
 140
 141         set_reg_field_value(
 142                 value,
 143                 0,
 144                 DVMM_PTE_CONTROL,
 145                 DVMM_USE_SINGLE_PTE);
 146
 147         set_reg_field_value(
 148                 value,
 149                 1,
 150                 DVMM_PTE_CONTROL,
 151                 DVMM_PTE_BUFFER_MODE0);
 152
 153         set_reg_field_value(
 154                 value,
 155                 1,
 156                 DVMM_PTE_CONTROL,
 157                 DVMM_PTE_BUFFER_MODE1);
 158
 159         dm_write_reg(ctx, addr, value);
 160
 161         addr = mmDVMM_PTE_REQ;
 162         value = dm_read_reg(ctx, addr);
 163
 164         chunk_int = get_reg_field_value(
 165                 value,
 166                 DVMM_PTE_REQ,
 167                 HFLIP_PTEREQ_PER_CHUNK_INT);
 168
 169         chunk_mul = get_reg_field_value(
 170                 value,
 171                 DVMM_PTE_REQ,
 172                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 173
 174         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 175
 176                 set_reg_field_value(
 177                         value,
 178                         255,
 179                         DVMM_PTE_REQ,
 180                         MAX_PTEREQ_TO_ISSUE);
 181
 182                 set_reg_field_value(
 183                         value,
 184                         4,
 185                         DVMM_PTE_REQ,
 186                         HFLIP_PTEREQ_PER_CHUNK_INT);
 187
 188                 set_reg_field_value(
 189                         value,
 190                         4,
 191                         DVMM_PTE_REQ,
 192                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 193
 194                 dm_write_reg(ctx, addr, value);
 195         }
 196 }
 197 /**************************************************************************/
 198
 199 static void enable_display_pipe_clock_gating(
 200         struct dc_context *ctx,
 201         bool clock_gating)
 202 {
 203         /*TODO*/
 204 }
 205
 206 static bool dce110_enable_display_power_gating(
 207         struct dc *dc,
 208         uint8_t controller_id,
 209         struct dc_bios *dcb,
 210         enum pipe_gating_control power_gating)
 211 {
 212         enum bp_result bp_result = BP_RESULT_OK;
 213         enum bp_pipe_control_action cntl;
 214         struct dc_context *ctx = dc->ctx;
 215         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 216
 217         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 218                 return true;
 219
 220         if (power_gating == PIPE_GATING_CONTROL_INIT)
 221                 cntl = ASIC_PIPE_INIT;
 222         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 223                 cntl = ASIC_PIPE_ENABLE;
 224         else
 225                 cntl = ASIC_PIPE_DISABLE;
 226
 227         if (controller_id == underlay_idx)
 228                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 229
 230         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 231
 232                 bp_result = dcb->funcs->enable_disp_power_gating(
 233                                                 dcb, controller_id + 1, cntl);
 234
 235                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 236                  * by default when command table is called
 237                  *
 238                  * Bios parser accepts controller_id = 6 as indicative of
 239                  * underlay pipe in dce110. But we do not support more
 240                  * than 3.
 241                  */
 242                 if (controller_id < CONTROLLER_ID_MAX - 1)
 243                         dm_write_reg(ctx,
 244                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 245                                 0);
 246         }
 247
 248         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 249                 dce110_init_pte(ctx);
 250
 251         if (bp_result == BP_RESULT_OK)
 252                 return true;
 253         else
 254                 return false;
 255 }
 256
 257 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 258                 const struct dc_plane_state *plane_state)
 259 {
 260         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 261
 262         switch (plane_state->format) {
 263         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 264                 prescale_params->scale = 0x2082;
 265                 break;
 266         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 267         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 268                 prescale_params->scale = 0x2020;
 269                 break;
 270         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 271         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 272                 prescale_params->scale = 0x2008;
 273                 break;
 274         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 275         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 276         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 277                 prescale_params->scale = 0x2000;
 278                 break;
 279         default:
 280                 ASSERT(false);
 281                 break;
 282         }
 283 }
 284
 285 static bool
 286 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 287                                const struct dc_plane_state *plane_state)
 288 {
 289         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 290         const struct dc_transfer_func *tf = NULL;
 291         struct ipp_prescale_params prescale_params = { 0 };
 292         bool result = true;
 293
 294         if (ipp == NULL)
 295                 return false;
 296
 297         if (plane_state->in_transfer_func)
 298                 tf = plane_state->in_transfer_func;
 299
 300         build_prescale_params(&prescale_params, plane_state);
 301         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 302
 303         if (plane_state->gamma_correction &&
 304                         !plane_state->gamma_correction->is_identity &&
 305                         dce_use_lut(plane_state->format))
 306                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 307
 308         if (tf == NULL) {
 309                 /* Default case if no input transfer function specified */
 310                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 311         } else if (tf->type == TF_TYPE_PREDEFINED) {
 312                 switch (tf->tf) {
 313                 case TRANSFER_FUNCTION_SRGB:
 314                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 315                         break;
 316                 case TRANSFER_FUNCTION_BT709:
 317                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 318                         break;
 319                 case TRANSFER_FUNCTION_LINEAR:
 320                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 321                         break;
 322                 case TRANSFER_FUNCTION_PQ:
 323                 default:
 324                         result = false;
 325                         break;
 326                 }
 327         } else if (tf->type == TF_TYPE_BYPASS) {
 328                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 329         } else {
 330                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 331                 result = false;
 332         }
 333
 334         return result;
 335 }
 336
 337 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 338                                     struct curve_points *arr_points,
 339                                     uint32_t hw_points_num)
 340 {
 341         struct custom_float_format fmt;
 342
 343         struct pwl_result_data *rgb = rgb_resulted;
 344
 345         uint32_t i = 0;
 346
 347         fmt.exponenta_bits = 6;
 348         fmt.mantissa_bits = 12;
 349         fmt.sign = true;
 350
 351         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 352                                             &arr_points[0].custom_float_x)) {
 353                 BREAK_TO_DEBUGGER();
 354                 return false;
 355         }
 356
 357         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 358                                             &arr_points[0].custom_float_offset)) {
 359                 BREAK_TO_DEBUGGER();
 360                 return false;
 361         }
 362
 363         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 364                                             &arr_points[0].custom_float_slope)) {
 365                 BREAK_TO_DEBUGGER();
 366                 return false;
 367         }
 368
 369         fmt.mantissa_bits = 10;
 370         fmt.sign = false;
 371
 372         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 373                                             &arr_points[1].custom_float_x)) {
 374                 BREAK_TO_DEBUGGER();
 375                 return false;
 376         }
 377
 378         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 379                                             &arr_points[1].custom_float_y)) {
 380                 BREAK_TO_DEBUGGER();
 381                 return false;
 382         }
 383
 384         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 385                                             &arr_points[1].custom_float_slope)) {
 386                 BREAK_TO_DEBUGGER();
 387                 return false;
 388         }
 389
 390         fmt.mantissa_bits = 12;
 391         fmt.sign = true;
 392
 393         while (i != hw_points_num) {
 394                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 395                                                     &rgb->red_reg)) {
 396                         BREAK_TO_DEBUGGER();
 397                         return false;
 398                 }
 399
 400                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 401                                                     &rgb->green_reg)) {
 402                         BREAK_TO_DEBUGGER();
 403                         return false;
 404                 }
 405
 406                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 407                                                     &rgb->blue_reg)) {
 408                         BREAK_TO_DEBUGGER();
 409                         return false;
 410                 }
 411
 412                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 413                                                     &rgb->delta_red_reg)) {
 414                         BREAK_TO_DEBUGGER();
 415                         return false;
 416                 }
 417
 418                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 419                                                     &rgb->delta_green_reg)) {
 420                         BREAK_TO_DEBUGGER();
 421                         return false;
 422                 }
 423
 424                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 425                                                     &rgb->delta_blue_reg)) {
 426                         BREAK_TO_DEBUGGER();
 427                         return false;
 428                 }
 429
 430                 ++rgb;
 431                 ++i;
 432         }
 433
 434         return true;
 435 }
 436
 437 #define MAX_LOW_POINT      25
 438 #define NUMBER_REGIONS     16
 439 #define NUMBER_SW_SEGMENTS 16
 440
 441 static bool
 442 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 443                                       struct pwl_params *regamma_params)
 444 {
 445         struct curve_points *arr_points;
 446         struct pwl_result_data *rgb_resulted;
 447         struct pwl_result_data *rgb;
 448         struct pwl_result_data *rgb_plus_1;
 449         struct fixed31_32 y_r;
 450         struct fixed31_32 y_g;
 451         struct fixed31_32 y_b;
 452         struct fixed31_32 y1_min;
 453         struct fixed31_32 y3_max;
 454
 455         int32_t region_start, region_end;
 456         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 457
 458         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 459                 return false;
 460
 461         arr_points = regamma_params->arr_points;
 462         rgb_resulted = regamma_params->rgb_resulted;
 463         hw_points = 0;
 464
 465         memset(regamma_params, 0, sizeof(struct pwl_params));
 466
 467         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 468                 /* 16 segments
 469                  * segments are from 2^-11 to 2^5
 470                  */
 471                 region_start = -11;
 472                 region_end = region_start + NUMBER_REGIONS;
 473
 474                 for (i = 0; i < NUMBER_REGIONS; i++)
 475                         seg_distr[i] = 4;
 476
 477         } else {
 478                 /* 10 segments
 479                  * segment is from 2^-10 to 2^1
 480                  * We include an extra segment for range [2^0, 2^1). This is to
 481                  * ensure that colors with normalized values of 1 don't miss the
 482                  * LUT.
 483                  */
 484                 region_start = -10;
 485                 region_end = 1;
 486
 487                 seg_distr[0] = 4;
 488                 seg_distr[1] = 4;
 489                 seg_distr[2] = 4;
 490                 seg_distr[3] = 4;
 491                 seg_distr[4] = 4;
 492                 seg_distr[5] = 4;
 493                 seg_distr[6] = 4;
 494                 seg_distr[7] = 4;
 495                 seg_distr[8] = 4;
 496                 seg_distr[9] = 4;
 497                 seg_distr[10] = 0;
 498                 seg_distr[11] = -1;
 499                 seg_distr[12] = -1;
 500                 seg_distr[13] = -1;
 501                 seg_distr[14] = -1;
 502                 seg_distr[15] = -1;
 503         }
 504
 505         for (k = 0; k < 16; k++) {
 506                 if (seg_distr[k] != -1)
 507                         hw_points += (1 << seg_distr[k]);
 508         }
 509
 510         j = 0;
 511         for (k = 0; k < (region_end - region_start); k++) {
 512                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 513                 start_index = (region_start + k + MAX_LOW_POINT) *
 514                                 NUMBER_SW_SEGMENTS;
 515                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 516                                 i += increment) {
 517                         if (j == hw_points - 1)
 518                                 break;
 519                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 520                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 521                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 522                         j++;
 523                 }
 524         }
 525
 526         /* last point */
 527         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 528         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 529         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 530         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 531
 532         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 533                                              dc_fixpt_from_int(region_start));
 534         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 535                                              dc_fixpt_from_int(region_end));
 536
 537         y_r = rgb_resulted[0].red;
 538         y_g = rgb_resulted[0].green;
 539         y_b = rgb_resulted[0].blue;
 540
 541         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 542
 543         arr_points[0].y = y1_min;
 544         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 545                                                  arr_points[0].x);
 546
 547         y_r = rgb_resulted[hw_points - 1].red;
 548         y_g = rgb_resulted[hw_points - 1].green;
 549         y_b = rgb_resulted[hw_points - 1].blue;
 550
 551         /* see comment above, m_arrPoints[1].y should be the Y value for the
 552          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 553          */
 554         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 555
 556         arr_points[1].y = y3_max;
 557
 558         arr_points[1].slope = dc_fixpt_zero;
 559
 560         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 561                 /* for PQ, we want to have a straight line from last HW X point,
 562                  * and the slope to be such that we hit 1.0 at 10000 nits.
 563                  */
 564                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 565
 566                 arr_points[1].slope = dc_fixpt_div(
 567                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 568                                 dc_fixpt_sub(end_value, arr_points[1].x));
 569         }
 570
 571         regamma_params->hw_points_num = hw_points;
 572
 573         k = 0;
 574         for (i = 1; i < 16; i++) {
 575                 if (seg_distr[k] != -1) {
 576                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 577                         regamma_params->arr_curve_points[i].offset =
 578                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 579                 }
 580                 k++;
 581         }
 582
 583         if (seg_distr[k] != -1)
 584                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 585
 586         rgb = rgb_resulted;
 587         rgb_plus_1 = rgb_resulted + 1;
 588
 589         i = 1;
 590
 591         while (i != hw_points + 1) {
 592                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 593                         rgb_plus_1->red = rgb->red;
 594                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 595                         rgb_plus_1->green = rgb->green;
 596                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 597                         rgb_plus_1->blue = rgb->blue;
 598
 599                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 600                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 601                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 602
 603                 ++rgb_plus_1;
 604                 ++rgb;
 605                 ++i;
 606         }
 607
 608         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 609
 610         return true;
 611 }
 612
 613 static bool
 614 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 615                                 const struct dc_stream_state *stream)
 616 {
 617         struct transform *xfm = pipe_ctx->plane_res.xfm;
 618
 619         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 620         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 621
 622         if (stream->out_transfer_func &&
 623             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 624             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 625                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 626         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 627                                                          &xfm->regamma_params)) {
 628                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 629                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 630         } else {
 631                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 632         }
 633
 634         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 635
 636         return true;
 637 }
 638
 639 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 640 {
 641         bool is_hdmi_tmds;
 642         bool is_dp;
 643
 644         ASSERT(pipe_ctx->stream);
 645
 646         if (pipe_ctx->stream_res.stream_enc == NULL)
 647                 return;  /* this is not root pipe */
 648
 649         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 650         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 651
 652         if (!is_hdmi_tmds && !is_dp)
 653                 return;
 654
 655         if (is_hdmi_tmds)
 656                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 657                         pipe_ctx->stream_res.stream_enc,
 658                         &pipe_ctx->stream_res.encoder_info_frame);
 659         else
 660                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 661                         pipe_ctx->stream_res.stream_enc,
 662                         &pipe_ctx->stream_res.encoder_info_frame);
 663 }
 664
 665 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 666 {
 667         enum dc_lane_count lane_count =
 668                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 669         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 670         struct dc_link *link = pipe_ctx->stream->link;
 671         const struct dc *dc = link->dc;
 672
 673         uint32_t active_total_with_borders;
 674         uint32_t early_control = 0;
 675         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 676
 677         /* For MST, there are multiply stream go to only one link.
 678          * connect DIG back_end to front_end while enable_stream and
 679          * disconnect them during disable_stream
 680          * BY this, it is logic clean to separate stream and link */
 681         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 682                                                     pipe_ctx->stream_res.stream_enc->id, true);
 683
 684         dc->hwss.update_info_frame(pipe_ctx);
 685
 686         /* enable early control to avoid corruption on DP monitor*/
 687         active_total_with_borders =
 688                         timing->h_addressable
 689                                 + timing->h_border_left
 690                                 + timing->h_border_right;
 691
 692         if (lane_count != 0)
 693                 early_control = active_total_with_borders % lane_count;
 694
 695         if (early_control == 0)
 696                 early_control = lane_count;
 697
 698         tg->funcs->set_early_control(tg, early_control);
 699
 700         /* enable audio only within mode set */
 701         if (pipe_ctx->stream_res.audio != NULL) {
 702                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 703                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 704         }
 705
 706
 707
 708
 709 }
 710
 711 static enum bp_result link_transmitter_control(
 712                 struct dc_bios *bios,
 713         struct bp_transmitter_control *cntl)
 714 {
 715         enum bp_result result;
 716
 717         result = bios->funcs->transmitter_control(bios, cntl);
 718
 719         return result;
 720 }
 721
 722 /*
 723  * @brief
 724  * eDP only.
 725  */
 726 void dce110_edp_wait_for_hpd_ready(
 727                 struct dc_link *link,
 728                 bool power_up)
 729 {
 730         struct dc_context *ctx = link->ctx;
 731         struct graphics_object_id connector = link->link_enc->connector;
 732         struct gpio *hpd;
 733         struct dc_sink *sink = link->local_sink;
 734         bool edp_hpd_high = false;
 735         uint32_t time_elapsed = 0;
 736         uint32_t timeout = power_up ?
 737                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 738
 739         if (dal_graphics_object_id_get_connector_id(connector)
 740                         != CONNECTOR_ID_EDP) {
 741                 BREAK_TO_DEBUGGER();
 742                 return;
 743         }
 744
 745         if (!power_up)
 746                 /*
 747                  * From KV, we will not HPD low after turning off VCC -
 748                  * instead, we will check the SW timer in power_up().
 749                  */
 750                 return;
 751
 752         /*
 753          * When we power on/off the eDP panel,
 754          * we need to wait until SENSE bit is high/low.
 755          */
 756
 757         /* obtain HPD */
 758         /* TODO what to do with this? */
 759         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 760
 761         if (!hpd) {
 762                 BREAK_TO_DEBUGGER();
 763                 return;
 764         }
 765
 766         if (sink != NULL) {
 767                 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) {
 768                         int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 769
 770                         msleep(extra_t3_in_ms);
 771                 }
 772         }
 773
 774         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 775
 776         /* wait until timeout or panel detected */
 777
 778         do {
 779                 uint32_t detected = 0;
 780
 781                 dal_gpio_get_value(hpd, &detected);
 782
 783                 if (!(detected ^ power_up)) {
 784                         edp_hpd_high = true;
 785                         break;
 786                 }
 787
 788                 msleep(HPD_CHECK_INTERVAL);
 789
 790                 time_elapsed += HPD_CHECK_INTERVAL;
 791         } while (time_elapsed < timeout);
 792
 793         dal_gpio_close(hpd);
 794
 795         dal_gpio_destroy_irq(&hpd);
 796
 797         if (false == edp_hpd_high) {
 798                 DC_LOG_ERROR(
 799                                 "%s: wait timed out!\n", __func__);
 800         }
 801 }
 802
 803 void dce110_edp_power_control(
 804                 struct dc_link *link,
 805                 bool power_up)
 806 {
 807         struct dc_context *ctx = link->ctx;
 808         struct bp_transmitter_control cntl = { 0 };
 809         enum bp_result bp_result;
 810         uint8_t panel_instance;
 811
 812
 813         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 814                         != CONNECTOR_ID_EDP) {
 815                 BREAK_TO_DEBUGGER();
 816                 return;
 817         }
 818
 819         if (!link->panel_cntl)
 820                 return;
 821         if (power_up !=
 822                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 823
 824                 unsigned long long current_ts = dm_get_timestamp(ctx);
 825                 unsigned long long time_since_edp_poweroff_ms =
 826                                 div64_u64(dm_get_elapse_time_in_ns(
 827                                                 ctx,
 828                                                 current_ts,
 829                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 830                 unsigned long long time_since_edp_poweron_ms =
 831                                 div64_u64(dm_get_elapse_time_in_ns(
 832                                                 ctx,
 833                                                 current_ts,
 834                                                 link->link_trace.time_stamp.edp_poweron), 1000000);
 835                 DC_LOG_HW_RESUME_S3(
 836                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 837                                 __func__,
 838                                 power_up,
 839                                 current_ts,
 840                                 link->link_trace.time_stamp.edp_poweroff,
 841                                 link->link_trace.time_stamp.edp_poweron,
 842                                 time_since_edp_poweroff_ms,
 843                                 time_since_edp_poweron_ms);
 844
 845                 /* Send VBIOS command to prompt eDP panel power */
 846                 if (power_up) {
 847                         /* edp requires a min of 500ms from LCDVDD off to on */
 848                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 849
 850                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 851                         if (link->local_sink != NULL)
 852                                 remaining_min_edp_poweroff_time_ms +=
 853                                         link->local_sink->edid_caps.panel_patch.extra_t12_ms;
 854
 855                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 856                         if (link->link_trace.time_stamp.edp_poweroff != 0) {
 857                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 858                                         remaining_min_edp_poweroff_time_ms =
 859                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 860                                 else
 861                                         remaining_min_edp_poweroff_time_ms = 0;
 862                         }
 863
 864                         if (remaining_min_edp_poweroff_time_ms) {
 865                                 DC_LOG_HW_RESUME_S3(
 866                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 867                                                 __func__, remaining_min_edp_poweroff_time_ms);
 868                                 msleep(remaining_min_edp_poweroff_time_ms);
 869                                 DC_LOG_HW_RESUME_S3(
 870                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 871                                                 __func__, remaining_min_edp_poweroff_time_ms);
 872                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 873                                                 __func__, remaining_min_edp_poweroff_time_ms);
 874                         } else {
 875                                 DC_LOG_HW_RESUME_S3(
 876                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 877                                                 __func__, remaining_min_edp_poweroff_time_ms);
 878                         }
 879                 }
 880
 881                 DC_LOG_HW_RESUME_S3(
 882                                 "%s: BEGIN: Panel Power action: %s\n",
 883                                 __func__, (power_up ? "On":"Off"));
 884
 885                 cntl.action = power_up ?
 886                         TRANSMITTER_CONTROL_POWER_ON :
 887                         TRANSMITTER_CONTROL_POWER_OFF;
 888                 cntl.transmitter = link->link_enc->transmitter;
 889                 cntl.connector_obj_id = link->link_enc->connector;
 890                 cntl.coherent = false;
 891                 cntl.lanes_number = LANE_COUNT_FOUR;
 892                 cntl.hpd_sel = link->link_enc->hpd_source;
 893                 panel_instance = link->panel_cntl->inst;
 894
 895                 if (ctx->dc->ctx->dmub_srv &&
 896                                 ctx->dc->debug.dmub_command_table) {
 897                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
 898                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 899                                                 LVTMA_CONTROL_POWER_ON,
 900                                                 panel_instance);
 901                         else
 902                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 903                                                 LVTMA_CONTROL_POWER_OFF,
 904                                                 panel_instance);
 905                 }
 906
 907                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 908
 909                 DC_LOG_HW_RESUME_S3(
 910                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 911                                 __func__, (power_up ? "On":"Off"),
 912                                 bp_result);
 913
 914                 if (!power_up)
 915                         /*save driver power off time stamp*/
 916                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 917                 else
 918                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 919
 920                 DC_LOG_HW_RESUME_S3(
 921                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 922                                 __func__,
 923                                 link->link_trace.time_stamp.edp_poweroff,
 924                                 link->link_trace.time_stamp.edp_poweron);
 925
 926                 if (bp_result != BP_RESULT_OK)
 927                         DC_LOG_ERROR(
 928                                         "%s: Panel Power bp_result: %d\n",
 929                                         __func__, bp_result);
 930         } else {
 931                 DC_LOG_HW_RESUME_S3(
 932                                 "%s: Skipping Panel Power action: %s\n",
 933                                 __func__, (power_up ? "On":"Off"));
 934         }
 935 }
 936
 937 void dce110_edp_wait_for_T12(
 938                 struct dc_link *link)
 939 {
 940         struct dc_context *ctx = link->ctx;
 941
 942         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 943                         != CONNECTOR_ID_EDP) {
 944                 BREAK_TO_DEBUGGER();
 945                 return;
 946         }
 947
 948         if (!link->panel_cntl)
 949                 return;
 950
 951         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 952                         link->link_trace.time_stamp.edp_poweroff != 0) {
 953                 unsigned int t12_duration = 500; // Default T12 as per spec
 954                 unsigned long long current_ts = dm_get_timestamp(ctx);
 955                 unsigned long long time_since_edp_poweroff_ms =
 956                                 div64_u64(dm_get_elapse_time_in_ns(
 957                                                 ctx,
 958                                                 current_ts,
 959                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 960
 961                 t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
 962
 963                 if (time_since_edp_poweroff_ms < t12_duration)
 964                         msleep(t12_duration - time_since_edp_poweroff_ms);
 965         }
 966 }
 967
 968 /*todo: cloned in stream enc, fix*/
 969 /*
 970  * @brief
 971  * eDP only. Control the backlight of the eDP panel
 972  */
 973 void dce110_edp_backlight_control(
 974                 struct dc_link *link,
 975                 bool enable)
 976 {
 977         struct dc_context *ctx = link->ctx;
 978         struct bp_transmitter_control cntl = { 0 };
 979         uint8_t panel_instance;
 980
 981         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 982                 != CONNECTOR_ID_EDP) {
 983                 BREAK_TO_DEBUGGER();
 984                 return;
 985         }
 986
 987         if (link->panel_cntl) {
 988                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 989
 990                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 991                         DC_LOG_HW_RESUME_S3(
 992                                 "%s: panel already powered up/off. Do nothing.\n",
 993                                 __func__);
 994                         return;
 995                 }
 996         }
 997
 998         /* Send VBIOS command to control eDP panel backlight */
 999
1000         DC_LOG_HW_RESUME_S3(
1001                         "%s: backlight action: %s\n",
1002                         __func__, (enable ? "On":"Off"));
1003
1004         cntl.action = enable ?
1005                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
1006                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
1007
1008         /*cntl.engine_id = ctx->engine;*/
1009         cntl.transmitter = link->link_enc->transmitter;
1010         cntl.connector_obj_id = link->link_enc->connector;
1011         /*todo: unhardcode*/
1012         cntl.lanes_number = LANE_COUNT_FOUR;
1013         cntl.hpd_sel = link->link_enc->hpd_source;
1014         cntl.signal = SIGNAL_TYPE_EDP;
1015
1016         /* For eDP, the following delays might need to be considered
1017          * after link training completed:
1018          * idle period - min. accounts for required BS-Idle pattern,
1019          * max. allows for source frame synchronization);
1020          * 50 msec max. delay from valid video data from source
1021          * to video on dislpay or backlight enable.
1022          *
1023          * Disable the delay for now.
1024          * Enable it in the future if necessary.
1025          */
1026         /* dc_service_sleep_in_milliseconds(50); */
1027                 /*edp 1.2*/
1028         panel_instance = link->panel_cntl->inst;
1029
1030         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1031                 if (!link->dc->config.edp_no_power_sequencing)
1032                 /*
1033                  * Sometimes, DP receiver chip power-controlled externally by an
1034                  * Embedded Controller could be treated and used as eDP,
1035                  * if it drives mobile display. In this case,
1036                  * we shouldn't be doing power-sequencing, hence we can skip
1037                  * waiting for T7-ready.
1038                  */
1039                         edp_receiver_ready_T7(link);
1040                 else
1041                         DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1042         }
1043
1044         if (ctx->dc->ctx->dmub_srv &&
1045                         ctx->dc->debug.dmub_command_table) {
1046                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1047                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1048                                         LVTMA_CONTROL_LCD_BLON,
1049                                         panel_instance);
1050                 else
1051                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1052                                         LVTMA_CONTROL_LCD_BLOFF,
1053                                         panel_instance);
1054         }
1055
1056         link_transmitter_control(ctx->dc_bios, &cntl);
1057
1058         if (enable && link->dpcd_sink_ext_caps.bits.oled)
1059                 msleep(OLED_POST_T7_DELAY);
1060
1061         if (link->dpcd_sink_ext_caps.bits.oled ||
1062                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1063                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1064                 dc_link_backlight_enable_aux(link, enable);
1065
1066         /*edp 1.2*/
1067         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1068                 if (!link->dc->config.edp_no_power_sequencing)
1069                 /*
1070                  * Sometimes, DP receiver chip power-controlled externally by an
1071                  * Embedded Controller could be treated and used as eDP,
1072                  * if it drives mobile display. In this case,
1073                  * we shouldn't be doing power-sequencing, hence we can skip
1074                  * waiting for T9-ready.
1075                  */
1076                         edp_add_delay_for_T9(link);
1077                 else
1078                         DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1079         }
1080
1081         if (!enable && link->dpcd_sink_ext_caps.bits.oled)
1082                 msleep(OLED_PRE_T11_DELAY);
1083 }
1084
1085 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1086 {
1087         /* notify audio driver for audio modes of monitor */
1088         struct dc *dc;
1089         struct clk_mgr *clk_mgr;
1090         unsigned int i, num_audio = 1;
1091
1092         if (!pipe_ctx->stream)
1093                 return;
1094
1095         dc = pipe_ctx->stream->ctx->dc;
1096         clk_mgr = dc->clk_mgr;
1097
1098         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1099                 return;
1100
1101         if (pipe_ctx->stream_res.audio) {
1102                 for (i = 0; i < MAX_PIPES; i++) {
1103                         /*current_state not updated yet*/
1104                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1105                                 num_audio++;
1106                 }
1107
1108                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1109
1110                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1111                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1112                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1113                 /* un-mute audio */
1114                 /* TODO: audio should be per stream rather than per link */
1115 #if defined(CONFIG_DRM_AMD_DC_DCN)
1116                 if (is_dp_128b_132b_signal(pipe_ctx))
1117                         pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
1118                                         pipe_ctx->stream_res.hpo_dp_stream_enc, false);
1119                 else
1120                         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1121                                         pipe_ctx->stream_res.stream_enc, false);
1122 #else
1123                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1124                                 pipe_ctx->stream_res.stream_enc, false);
1125 #endif
1126                 if (pipe_ctx->stream_res.audio)
1127                         pipe_ctx->stream_res.audio->enabled = true;
1128         }
1129
1130         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1131                 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM);
1132 }
1133
1134 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1135 {
1136         struct dc *dc;
1137         struct clk_mgr *clk_mgr;
1138
1139         if (!pipe_ctx || !pipe_ctx->stream)
1140                 return;
1141
1142         dc = pipe_ctx->stream->ctx->dc;
1143         clk_mgr = dc->clk_mgr;
1144
1145         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1146                 return;
1147
1148 #if defined(CONFIG_DRM_AMD_DC_DCN)
1149         if (is_dp_128b_132b_signal(pipe_ctx))
1150                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
1151                                 pipe_ctx->stream_res.hpo_dp_stream_enc, true);
1152         else
1153                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1154                                 pipe_ctx->stream_res.stream_enc, true);
1155 #else
1156         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1157                         pipe_ctx->stream_res.stream_enc, true);
1158 #endif
1159         if (pipe_ctx->stream_res.audio) {
1160                 pipe_ctx->stream_res.audio->enabled = false;
1161
1162                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1163 #if defined(CONFIG_DRM_AMD_DC_DCN)
1164                         if (is_dp_128b_132b_signal(pipe_ctx))
1165                                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(
1166                                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1167                         else
1168                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1169                                                 pipe_ctx->stream_res.stream_enc);
1170 #else
1171                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1172                                         pipe_ctx->stream_res.stream_enc);
1173 #endif
1174                 else
1175                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1176                                         pipe_ctx->stream_res.stream_enc);
1177
1178                 if (clk_mgr->funcs->enable_pme_wa)
1179                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1180                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1181
1182                 /* TODO: notify audio driver for if audio modes list changed
1183                  * add audio mode list change flag */
1184                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1185                  * stream->stream_engine_id);
1186                  */
1187         }
1188
1189         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1190                 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM);
1191 }
1192
1193 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1194 {
1195         struct dc_stream_state *stream = pipe_ctx->stream;
1196         struct dc_link *link = stream->link;
1197         struct dc *dc = pipe_ctx->stream->ctx->dc;
1198         struct link_encoder *link_enc = NULL;
1199
1200         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1201                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1202                         pipe_ctx->stream_res.stream_enc);
1203                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1204                         pipe_ctx->stream_res.stream_enc);
1205         }
1206
1207 #if defined(CONFIG_DRM_AMD_DC_DCN)
1208         if (is_dp_128b_132b_signal(pipe_ctx)) {
1209                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1210                                         pipe_ctx->stream_res.hpo_dp_stream_enc);
1211         } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1212 #else
1213         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1214 #endif
1215                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1216                         pipe_ctx->stream_res.stream_enc);
1217
1218         dc->hwss.disable_audio_stream(pipe_ctx);
1219
1220         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
1221         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
1222                 link_enc = link->link_enc;
1223         else if (dc->res_pool->funcs->link_encs_assign)
1224                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
1225         ASSERT(link_enc);
1226
1227 #if defined(CONFIG_DRM_AMD_DC_DCN)
1228         if (is_dp_128b_132b_signal(pipe_ctx)) {
1229                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable(
1230                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1231                 setup_dp_hpo_stream(pipe_ctx, false);
1232         /* TODO - DP2.0 HW: unmap stream from link encoder here */
1233         } else {
1234                 if (link_enc)
1235                         link_enc->funcs->connect_dig_be_to_fe(
1236                                 link_enc,
1237                                 pipe_ctx->stream_res.stream_enc->id,
1238                                 false);
1239         }
1240 #else
1241         if (link_enc)
1242                 link_enc->funcs->connect_dig_be_to_fe(
1243                         link->link_enc,
1244                         pipe_ctx->stream_res.stream_enc->id,
1245                         false);
1246 #endif
1247         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1248                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
1249
1250 #if defined(CONFIG_DRM_AMD_DC_DCN)
1251         if (dc->hwseq->funcs.setup_hpo_hw_control && is_dp_128b_132b_signal(pipe_ctx))
1252                 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, false);
1253 #endif
1254
1255 }
1256
1257 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1258                 struct dc_link_settings *link_settings)
1259 {
1260         struct encoder_unblank_param params = { { 0 } };
1261         struct dc_stream_state *stream = pipe_ctx->stream;
1262         struct dc_link *link = stream->link;
1263         struct dce_hwseq *hws = link->dc->hwseq;
1264
1265         /* only 3 items below are used by unblank */
1266         params.timing = pipe_ctx->stream->timing;
1267         params.link_settings.link_rate = link_settings->link_rate;
1268
1269         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1270                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1271
1272         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1273                 hws->funcs.edp_backlight_control(link, true);
1274         }
1275 }
1276
1277 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1278 {
1279         struct dc_stream_state *stream = pipe_ctx->stream;
1280         struct dc_link *link = stream->link;
1281         struct dce_hwseq *hws = link->dc->hwseq;
1282
1283         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1284                 hws->funcs.edp_backlight_control(link, false);
1285                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1286         }
1287
1288 #if defined(CONFIG_DRM_AMD_DC_DCN)
1289         if (is_dp_128b_132b_signal(pipe_ctx)) {
1290                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1291                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1292                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1293         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1294 #else
1295         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1296 #endif
1297                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1298
1299                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1300                         /*
1301                          * After output is idle pattern some sinks need time to recognize the stream
1302                          * has changed or they enter protection state and hang.
1303                          */
1304                         msleep(60);
1305                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
1306                         edp_receiver_ready_T9(link);
1307         }
1308
1309 }
1310
1311
1312 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1313 {
1314         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1315                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1316 }
1317
1318 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1319 {
1320         switch (crtc_id) {
1321         case CONTROLLER_ID_D0:
1322                 return DTO_SOURCE_ID0;
1323         case CONTROLLER_ID_D1:
1324                 return DTO_SOURCE_ID1;
1325         case CONTROLLER_ID_D2:
1326                 return DTO_SOURCE_ID2;
1327         case CONTROLLER_ID_D3:
1328                 return DTO_SOURCE_ID3;
1329         case CONTROLLER_ID_D4:
1330                 return DTO_SOURCE_ID4;
1331         case CONTROLLER_ID_D5:
1332                 return DTO_SOURCE_ID5;
1333         default:
1334                 return DTO_SOURCE_UNKNOWN;
1335         }
1336 }
1337
1338 static void build_audio_output(
1339         struct dc_state *state,
1340         const struct pipe_ctx *pipe_ctx,
1341         struct audio_output *audio_output)
1342 {
1343         const struct dc_stream_state *stream = pipe_ctx->stream;
1344         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1345
1346         audio_output->signal = pipe_ctx->stream->signal;
1347
1348         /* audio_crtc_info  */
1349
1350         audio_output->crtc_info.h_total =
1351                 stream->timing.h_total;
1352
1353         /*
1354          * Audio packets are sent during actual CRTC blank physical signal, we
1355          * need to specify actual active signal portion
1356          */
1357         audio_output->crtc_info.h_active =
1358                         stream->timing.h_addressable
1359                         + stream->timing.h_border_left
1360                         + stream->timing.h_border_right;
1361
1362         audio_output->crtc_info.v_active =
1363                         stream->timing.v_addressable
1364                         + stream->timing.v_border_top
1365                         + stream->timing.v_border_bottom;
1366
1367         audio_output->crtc_info.pixel_repetition = 1;
1368
1369         audio_output->crtc_info.interlaced =
1370                         stream->timing.flags.INTERLACE;
1371
1372         audio_output->crtc_info.refresh_rate =
1373                 (stream->timing.pix_clk_100hz*100)/
1374                 (stream->timing.h_total*stream->timing.v_total);
1375
1376         audio_output->crtc_info.color_depth =
1377                 stream->timing.display_color_depth;
1378
1379         audio_output->crtc_info.requested_pixel_clock_100Hz =
1380                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1381
1382         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1383                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1384
1385 /*for HDMI, audio ACR is with deep color ratio factor*/
1386         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1387                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1388                                 (stream->timing.pix_clk_100hz)) {
1389                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1390                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1391                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1392                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1393                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1394
1395                 }
1396         }
1397
1398         if (state->clk_mgr &&
1399                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1400                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1401                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1402                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1403                                                 state->clk_mgr);
1404         }
1405
1406         audio_output->pll_info.feed_back_divider =
1407                         pipe_ctx->pll_settings.feedback_divider;
1408
1409         audio_output->pll_info.dto_source =
1410                 translate_to_dto_source(
1411                         pipe_ctx->stream_res.tg->inst + 1);
1412
1413         /* TODO hard code to enable for now. Need get from stream */
1414         audio_output->pll_info.ss_enabled = true;
1415
1416         audio_output->pll_info.ss_percentage =
1417                         pipe_ctx->pll_settings.ss_percentage;
1418 }
1419
1420 static void program_scaler(const struct dc *dc,
1421                 const struct pipe_ctx *pipe_ctx)
1422 {
1423         struct tg_color color = {0};
1424
1425 #if defined(CONFIG_DRM_AMD_DC_DCN)
1426         /* TOFPGA */
1427         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1428                 return;
1429 #endif
1430
1431         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1432                 get_surface_visual_confirm_color(pipe_ctx, &color);
1433         else
1434                 color_space_to_black_color(dc,
1435                                 pipe_ctx->stream->output_color_space,
1436                                 &color);
1437
1438         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1439                 pipe_ctx->plane_res.xfm,
1440                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1441                 &pipe_ctx->stream->bit_depth_params);
1442
1443         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1444                 /*
1445                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1446                  * alternate between Cb and Cr, so both channels need the pixel
1447                  * value for Y
1448                  */
1449                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1450                         color.color_r_cr = color.color_g_y;
1451
1452                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1453                                 pipe_ctx->stream_res.tg,
1454                                 &color);
1455         }
1456
1457         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1458                 &pipe_ctx->plane_res.scl_data);
1459 }
1460
1461 static enum dc_status dce110_enable_stream_timing(
1462                 struct pipe_ctx *pipe_ctx,
1463                 struct dc_state *context,
1464                 struct dc *dc)
1465 {
1466         struct dc_stream_state *stream = pipe_ctx->stream;
1467         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1468                         pipe_ctx[pipe_ctx->pipe_idx];
1469         struct tg_color black_color = {0};
1470
1471         if (!pipe_ctx_old->stream) {
1472
1473                 /* program blank color */
1474                 color_space_to_black_color(dc,
1475                                 stream->output_color_space, &black_color);
1476                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1477                                 pipe_ctx->stream_res.tg,
1478                                 &black_color);
1479
1480                 /*
1481                  * Must blank CRTC after disabling power gating and before any
1482                  * programming, otherwise CRTC will be hung in bad state
1483                  */
1484                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1485
1486                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1487                                 pipe_ctx->clock_source,
1488                                 &pipe_ctx->stream_res.pix_clk_params,
1489                                 &pipe_ctx->pll_settings)) {
1490                         BREAK_TO_DEBUGGER();
1491                         return DC_ERROR_UNEXPECTED;
1492                 }
1493
1494                 pipe_ctx->stream_res.tg->funcs->program_timing(
1495                                 pipe_ctx->stream_res.tg,
1496                                 &stream->timing,
1497                                 0,
1498                                 0,
1499                                 0,
1500                                 0,
1501                                 pipe_ctx->stream->signal,
1502                                 true);
1503         }
1504
1505         if (!pipe_ctx_old->stream) {
1506                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1507                                 pipe_ctx->stream_res.tg)) {
1508                         BREAK_TO_DEBUGGER();
1509                         return DC_ERROR_UNEXPECTED;
1510                 }
1511         }
1512
1513         return DC_OK;
1514 }
1515
1516 static enum dc_status apply_single_controller_ctx_to_hw(
1517                 struct pipe_ctx *pipe_ctx,
1518                 struct dc_state *context,
1519                 struct dc *dc)
1520 {
1521         struct dc_stream_state *stream = pipe_ctx->stream;
1522         struct dc_link *link = stream->link;
1523         struct drr_params params = {0};
1524         unsigned int event_triggers = 0;
1525         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1526         struct dce_hwseq *hws = dc->hwseq;
1527
1528         if (hws->funcs.disable_stream_gating) {
1529                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1530         }
1531
1532         if (pipe_ctx->stream_res.audio != NULL) {
1533                 struct audio_output audio_output;
1534
1535                 build_audio_output(context, pipe_ctx, &audio_output);
1536
1537                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1538 #if defined(CONFIG_DRM_AMD_DC_DCN)
1539                         if (is_dp_128b_132b_signal(pipe_ctx))
1540                                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(
1541                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1542                                                 pipe_ctx->stream_res.audio->inst,
1543                                                 &pipe_ctx->stream->audio_info);
1544                         else
1545                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1546                                                 pipe_ctx->stream_res.stream_enc,
1547                                                 pipe_ctx->stream_res.audio->inst,
1548                                                 &pipe_ctx->stream->audio_info);
1549 #else
1550                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1551                                         pipe_ctx->stream_res.stream_enc,
1552                                         pipe_ctx->stream_res.audio->inst,
1553                                         &pipe_ctx->stream->audio_info);
1554 #endif
1555                 else
1556                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1557                                         pipe_ctx->stream_res.stream_enc,
1558                                         pipe_ctx->stream_res.audio->inst,
1559                                         &pipe_ctx->stream->audio_info,
1560                                         &audio_output.crtc_info);
1561
1562                 pipe_ctx->stream_res.audio->funcs->az_configure(
1563                                 pipe_ctx->stream_res.audio,
1564                                 pipe_ctx->stream->signal,
1565                                 &audio_output.crtc_info,
1566                                 &pipe_ctx->stream->audio_info);
1567         }
1568
1569         /* make sure no pipes syncd to the pipe being enabled */
1570         if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1571                 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1572
1573 #if defined(CONFIG_DRM_AMD_DC_DCN)
1574         /* DCN3.1 FPGA Workaround
1575          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1576          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1577          * function core_link_enable_stream
1578          */
1579         if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)))
1580 #endif
1581                 /*  */
1582                 /* Do not touch stream timing on seamless boot optimization. */
1583                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1584                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1585
1586         if (hws->funcs.setup_vupdate_interrupt)
1587                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1588
1589         params.vertical_total_min = stream->adjust.v_total_min;
1590         params.vertical_total_max = stream->adjust.v_total_max;
1591         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1592                 pipe_ctx->stream_res.tg->funcs->set_drr(
1593                         pipe_ctx->stream_res.tg, &params);
1594
1595         // DRR should set trigger event to monitor surface update event
1596         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1597                 event_triggers = 0x80;
1598         /* Event triggers and num frames initialized for DRR, but can be
1599          * later updated for PSR use. Note DRR trigger events are generated
1600          * regardless of whether num frames met.
1601          */
1602         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1603                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1604                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1605
1606         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1607                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1608                         pipe_ctx->stream_res.stream_enc,
1609                         pipe_ctx->stream_res.tg->inst);
1610
1611         if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1612                 pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
1613                 pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
1614                         pipe_ctx->stream_res.stream_enc);
1615
1616         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1617                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1618
1619         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1620                         pipe_ctx->stream_res.opp,
1621                         COLOR_SPACE_YCBCR601,
1622                         stream->timing.display_color_depth,
1623                         stream->signal);
1624
1625         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1626                 pipe_ctx->stream_res.opp,
1627                 &stream->bit_depth_params,
1628                 &stream->clamping);
1629         while (odm_pipe) {
1630                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1631                                 odm_pipe->stream_res.opp,
1632                                 COLOR_SPACE_YCBCR601,
1633                                 stream->timing.display_color_depth,
1634                                 stream->signal);
1635
1636                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1637                                 odm_pipe->stream_res.opp,
1638                                 &stream->bit_depth_params,
1639                                 &stream->clamping);
1640                 odm_pipe = odm_pipe->next_odm_pipe;
1641         }
1642
1643         if (!stream->dpms_off)
1644                 core_link_enable_stream(context, pipe_ctx);
1645
1646 #if defined(CONFIG_DRM_AMD_DC_DCN)
1647         /* DCN3.1 FPGA Workaround
1648          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1649          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1650          * function core_link_enable_stream
1651          */
1652         if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) {
1653                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1654                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1655         }
1656 #endif
1657
1658         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1659
1660         pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1661
1662         return DC_OK;
1663 }
1664
1665 /******************************************************************************/
1666
1667 static void power_down_encoders(struct dc *dc)
1668 {
1669         int i;
1670
1671         for (i = 0; i < dc->link_count; i++) {
1672                 enum signal_type signal = dc->links[i]->connector_signal;
1673
1674                 dc_link_blank_dp_stream(dc->links[i], false);
1675
1676                 if (signal != SIGNAL_TYPE_EDP)
1677                         signal = SIGNAL_TYPE_NONE;
1678
1679                 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1680                         dc->links[i]->link_enc->funcs->disable_output(
1681                                         dc->links[i]->link_enc, signal);
1682
1683                 dc->links[i]->link_status.link_active = false;
1684                 memset(&dc->links[i]->cur_link_settings, 0,
1685                                 sizeof(dc->links[i]->cur_link_settings));
1686         }
1687 }
1688
1689 static void power_down_controllers(struct dc *dc)
1690 {
1691         int i;
1692
1693         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1694                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1695                                 dc->res_pool->timing_generators[i]);
1696         }
1697 }
1698
1699 static void power_down_clock_sources(struct dc *dc)
1700 {
1701         int i;
1702
1703         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1704                 dc->res_pool->dp_clock_source) == false)
1705                 dm_error("Failed to power down pll! (dp clk src)\n");
1706
1707         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1708                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1709                                 dc->res_pool->clock_sources[i]) == false)
1710                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1711         }
1712 }
1713
1714 static void power_down_all_hw_blocks(struct dc *dc)
1715 {
1716         power_down_encoders(dc);
1717
1718         power_down_controllers(dc);
1719
1720         power_down_clock_sources(dc);
1721
1722         if (dc->fbc_compressor)
1723                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1724 }
1725
1726 static void disable_vga_and_power_gate_all_controllers(
1727                 struct dc *dc)
1728 {
1729         int i;
1730         struct timing_generator *tg;
1731         struct dc_context *ctx = dc->ctx;
1732
1733         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1734                 tg = dc->res_pool->timing_generators[i];
1735
1736                 if (tg->funcs->disable_vga)
1737                         tg->funcs->disable_vga(tg);
1738         }
1739         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1740                 /* Enable CLOCK gating for each pipe BEFORE controller
1741                  * powergating. */
1742                 enable_display_pipe_clock_gating(ctx,
1743                                 true);
1744
1745                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1746                 dc->hwss.disable_plane(dc,
1747                         &dc->current_state->res_ctx.pipe_ctx[i]);
1748         }
1749 }
1750
1751
1752 static void get_edp_streams(struct dc_state *context,
1753                 struct dc_stream_state **edp_streams,
1754                 int *edp_stream_num)
1755 {
1756         int i;
1757
1758         *edp_stream_num = 0;
1759         for (i = 0; i < context->stream_count; i++) {
1760                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1761                         edp_streams[*edp_stream_num] = context->streams[i];
1762                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1763                                 return;
1764                 }
1765         }
1766 }
1767
1768 static void get_edp_links_with_sink(
1769                 struct dc *dc,
1770                 struct dc_link **edp_links_with_sink,
1771                 int *edp_with_sink_num)
1772 {
1773         int i;
1774
1775         /* check if there is an eDP panel not in use */
1776         *edp_with_sink_num = 0;
1777         for (i = 0; i < dc->link_count; i++) {
1778                 if (dc->links[i]->local_sink &&
1779                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1780                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1781                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1782                                 return;
1783                 }
1784         }
1785 }
1786
1787 /*
1788  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1789  *  1. Power down all DC HW blocks
1790  *  2. Disable VGA engine on all controllers
1791  *  3. Enable power gating for controller
1792  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1793  */
1794 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1795 {
1796         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1797         struct dc_link *edp_links[MAX_NUM_EDP];
1798         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1799         struct dc_link *edp_link_with_sink = NULL;
1800         struct dc_link *edp_link = NULL;
1801         struct dc_stream_state *edp_stream = NULL;
1802         struct dce_hwseq *hws = dc->hwseq;
1803         int edp_with_sink_num;
1804         int edp_num;
1805         int edp_stream_num;
1806         int i;
1807         bool can_apply_edp_fast_boot = false;
1808         bool can_apply_seamless_boot = false;
1809         bool keep_edp_vdd_on = false;
1810         DC_LOGGER_INIT();
1811
1812
1813         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1814         get_edp_links(dc, edp_links, &edp_num);
1815
1816         if (hws->funcs.init_pipes)
1817                 hws->funcs.init_pipes(dc, context);
1818
1819         get_edp_streams(context, edp_streams, &edp_stream_num);
1820
1821         // Check fastboot support, disable on DCE8 because of blank screens
1822         if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1823                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1824                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1825                 for (i = 0; i < edp_num; i++) {
1826                         edp_link = edp_links[i];
1827                         if (edp_link != edp_streams[0]->link)
1828                                 continue;
1829                         // enable fastboot if backend is enabled on eDP
1830                         if (edp_link->link_enc->funcs->is_dig_enabled &&
1831                             edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1832                             edp_link->link_status.link_active) {
1833                                 edp_stream = edp_streams[0];
1834                                 can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing);
1835                                 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1836                                 if (can_apply_edp_fast_boot)
1837                                         DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1838
1839                                 break;
1840                         }
1841                 }
1842                 // We are trying to enable eDP, don't power down VDD
1843                 if (can_apply_edp_fast_boot)
1844                         keep_edp_vdd_on = true;
1845         }
1846
1847         // Check seamless boot support
1848         for (i = 0; i < context->stream_count; i++) {
1849                 if (context->streams[i]->apply_seamless_boot_optimization) {
1850                         can_apply_seamless_boot = true;
1851                         break;
1852                 }
1853         }
1854
1855         /* eDP should not have stream in resume from S4 and so even with VBios post
1856          * it should get turned off
1857          */
1858         if (edp_with_sink_num)
1859                 edp_link_with_sink = edp_links_with_sink[0];
1860
1861         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1862                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1863                         /*turn off backlight before DP_blank and encoder powered down*/
1864                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1865                 }
1866                 /*resume from S3, no vbios posting, no need to power down again*/
1867                 power_down_all_hw_blocks(dc);
1868                 disable_vga_and_power_gate_all_controllers(dc);
1869                 if (edp_link_with_sink && !keep_edp_vdd_on)
1870                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1871         }
1872         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1873 }
1874
1875 static uint32_t compute_pstate_blackout_duration(
1876         struct bw_fixed blackout_duration,
1877         const struct dc_stream_state *stream)
1878 {
1879         uint32_t total_dest_line_time_ns;
1880         uint32_t pstate_blackout_duration_ns;
1881
1882         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1883
1884         total_dest_line_time_ns = 1000000UL *
1885                 (stream->timing.h_total * 10) /
1886                 stream->timing.pix_clk_100hz +
1887                 pstate_blackout_duration_ns;
1888
1889         return total_dest_line_time_ns;
1890 }
1891
1892 static void dce110_set_displaymarks(
1893         const struct dc *dc,
1894         struct dc_state *context)
1895 {
1896         uint8_t i, num_pipes;
1897         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1898
1899         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1900                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1901                 uint32_t total_dest_line_time_ns;
1902
1903                 if (pipe_ctx->stream == NULL)
1904                         continue;
1905
1906                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1907                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1908                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1909                         pipe_ctx->plane_res.mi,
1910                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1911                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1912                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1913                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1914                         total_dest_line_time_ns);
1915                 if (i == underlay_idx) {
1916                         num_pipes++;
1917                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1918                                 pipe_ctx->plane_res.mi,
1919                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1920                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1921                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1922                                 total_dest_line_time_ns);
1923                 }
1924                 num_pipes++;
1925         }
1926 }
1927
1928 void dce110_set_safe_displaymarks(
1929                 struct resource_context *res_ctx,
1930                 const struct resource_pool *pool)
1931 {
1932         int i;
1933         int underlay_idx = pool->underlay_pipe_index;
1934         struct dce_watermarks max_marks = {
1935                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1936         struct dce_watermarks nbp_marks = {
1937                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1938         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1939
1940         for (i = 0; i < MAX_PIPES; i++) {
1941                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1942                         continue;
1943
1944                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1945                                 res_ctx->pipe_ctx[i].plane_res.mi,
1946                                 nbp_marks,
1947                                 max_marks,
1948                                 min_marks,
1949                                 max_marks,
1950                                 MAX_WATERMARK);
1951
1952                 if (i == underlay_idx)
1953                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1954                                 res_ctx->pipe_ctx[i].plane_res.mi,
1955                                 nbp_marks,
1956                                 max_marks,
1957                                 max_marks,
1958                                 MAX_WATERMARK);
1959
1960         }
1961 }
1962
1963 /*******************************************************************************
1964  * Public functions
1965  ******************************************************************************/
1966
1967 static void set_drr(struct pipe_ctx **pipe_ctx,
1968                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1969 {
1970         int i = 0;
1971         struct drr_params params = {0};
1972         // DRR should set trigger event to monitor surface update event
1973         unsigned int event_triggers = 0x80;
1974         // Note DRR trigger events are generated regardless of whether num frames met.
1975         unsigned int num_frames = 2;
1976
1977         params.vertical_total_max = adjust.v_total_max;
1978         params.vertical_total_min = adjust.v_total_min;
1979
1980         /* TODO: If multiple pipes are to be supported, you need
1981          * some GSL stuff. Static screen triggers may be programmed differently
1982          * as well.
1983          */
1984         for (i = 0; i < num_pipes; i++) {
1985                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1986                         pipe_ctx[i]->stream_res.tg, &params);
1987
1988                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1989                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1990                                         pipe_ctx[i]->stream_res.tg,
1991                                         event_triggers, num_frames);
1992         }
1993 }
1994
1995 static void get_position(struct pipe_ctx **pipe_ctx,
1996                 int num_pipes,
1997                 struct crtc_position *position)
1998 {
1999         int i = 0;
2000
2001         /* TODO: handle pipes > 1
2002          */
2003         for (i = 0; i < num_pipes; i++)
2004                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2005 }
2006
2007 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2008                 int num_pipes, const struct dc_static_screen_params *params)
2009 {
2010         unsigned int i;
2011         unsigned int triggers = 0;
2012
2013         if (params->triggers.overlay_update)
2014                 triggers |= 0x100;
2015         if (params->triggers.surface_update)
2016                 triggers |= 0x80;
2017         if (params->triggers.cursor_update)
2018                 triggers |= 0x2;
2019         if (params->triggers.force_trigger)
2020                 triggers |= 0x1;
2021
2022         if (num_pipes) {
2023                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
2024
2025                 if (dc->fbc_compressor)
2026                         triggers |= 0x84;
2027         }
2028
2029         for (i = 0; i < num_pipes; i++)
2030                 pipe_ctx[i]->stream_res.tg->funcs->
2031                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
2032                                         triggers, params->num_frames);
2033 }
2034
2035 /*
2036  *  Check if FBC can be enabled
2037  */
2038 static bool should_enable_fbc(struct dc *dc,
2039                 struct dc_state *context,
2040                 uint32_t *pipe_idx)
2041 {
2042         uint32_t i;
2043         struct pipe_ctx *pipe_ctx = NULL;
2044         struct resource_context *res_ctx = &context->res_ctx;
2045         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2046
2047
2048         ASSERT(dc->fbc_compressor);
2049
2050         /* FBC memory should be allocated */
2051         if (!dc->ctx->fbc_gpu_addr)
2052                 return false;
2053
2054         /* Only supports single display */
2055         if (context->stream_count != 1)
2056                 return false;
2057
2058         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2059                 if (res_ctx->pipe_ctx[i].stream) {
2060
2061                         pipe_ctx = &res_ctx->pipe_ctx[i];
2062
2063                         if (!pipe_ctx)
2064                                 continue;
2065
2066                         /* fbc not applicable on underlay pipe */
2067                         if (pipe_ctx->pipe_idx != underlay_idx) {
2068                                 *pipe_idx = i;
2069                                 break;
2070                         }
2071                 }
2072         }
2073
2074         if (i == dc->res_pool->pipe_count)
2075                 return false;
2076
2077         if (!pipe_ctx->stream->link)
2078                 return false;
2079
2080         /* Only supports eDP */
2081         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2082                 return false;
2083
2084         /* PSR should not be enabled */
2085         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2086                 return false;
2087
2088         /* Nothing to compress */
2089         if (!pipe_ctx->plane_state)
2090                 return false;
2091
2092         /* Only for non-linear tiling */
2093         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2094                 return false;
2095
2096         return true;
2097 }
2098
2099 /*
2100  *  Enable FBC
2101  */
2102 static void enable_fbc(
2103                 struct dc *dc,
2104                 struct dc_state *context)
2105 {
2106         uint32_t pipe_idx = 0;
2107
2108         if (should_enable_fbc(dc, context, &pipe_idx)) {
2109                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2110                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2111                 struct compressor *compr = dc->fbc_compressor;
2112                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2113
2114                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2115                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2116                 params.inst = pipe_ctx->stream_res.tg->inst;
2117                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2118
2119                 compr->funcs->surface_address_and_pitch(compr, &params);
2120                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2121
2122                 compr->funcs->enable_fbc(compr, &params);
2123         }
2124 }
2125
2126 static void dce110_reset_hw_ctx_wrap(
2127                 struct dc *dc,
2128                 struct dc_state *context)
2129 {
2130         int i;
2131
2132         /* Reset old context */
2133         /* look up the targets that have been removed since last commit */
2134         for (i = 0; i < MAX_PIPES; i++) {
2135                 struct pipe_ctx *pipe_ctx_old =
2136                         &dc->current_state->res_ctx.pipe_ctx[i];
2137                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2138
2139                 /* Note: We need to disable output if clock sources change,
2140                  * since bios does optimization and doesn't apply if changing
2141                  * PHY when not already disabled.
2142                  */
2143
2144                 /* Skip underlay pipe since it will be handled in commit surface*/
2145                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2146                         continue;
2147
2148                 if (!pipe_ctx->stream ||
2149                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2150                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2151
2152                         /* Disable if new stream is null. O/w, if stream is
2153                          * disabled already, no need to disable again.
2154                          */
2155                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2156                                 core_link_disable_stream(pipe_ctx_old);
2157
2158                                 /* free acquired resources*/
2159                                 if (pipe_ctx_old->stream_res.audio) {
2160                                         /*disable az_endpoint*/
2161                                         pipe_ctx_old->stream_res.audio->funcs->
2162                                                         az_disable(pipe_ctx_old->stream_res.audio);
2163
2164                                         /*free audio*/
2165                                         if (dc->caps.dynamic_audio == true) {
2166                                                 /*we have to dynamic arbitrate the audio endpoints*/
2167                                                 /*we free the resource, need reset is_audio_acquired*/
2168                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2169                                                                 pipe_ctx_old->stream_res.audio, false);
2170                                                 pipe_ctx_old->stream_res.audio = NULL;
2171                                         }
2172                                 }
2173                         }
2174
2175                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2176                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2177                                 dm_error("DC: failed to blank crtc!\n");
2178                                 BREAK_TO_DEBUGGER();
2179                         }
2180                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2181                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2182                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2183
2184                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2185                                                                                 dc->res_pool,
2186                                                                                 old_clk))
2187                                 old_clk->funcs->cs_power_down(old_clk);
2188
2189                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2190
2191                         pipe_ctx_old->stream = NULL;
2192                 }
2193         }
2194 }
2195
2196 static void dce110_setup_audio_dto(
2197                 struct dc *dc,
2198                 struct dc_state *context)
2199 {
2200         int i;
2201
2202         /* program audio wall clock. use HDMI as clock source if HDMI
2203          * audio active. Otherwise, use DP as clock source
2204          * first, loop to find any HDMI audio, if not, loop find DP audio
2205          */
2206         /* Setup audio rate clock source */
2207         /* Issue:
2208         * Audio lag happened on DP monitor when unplug a HDMI monitor
2209         *
2210         * Cause:
2211         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2212         * is set to either dto0 or dto1, audio should work fine.
2213         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2214         * set to dto0 will cause audio lag.
2215         *
2216         * Solution:
2217         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2218         * find first available pipe with audio, setup audio wall DTO per topology
2219         * instead of per pipe.
2220         */
2221         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2222                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2223
2224                 if (pipe_ctx->stream == NULL)
2225                         continue;
2226
2227                 if (pipe_ctx->top_pipe)
2228                         continue;
2229                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2230                         continue;
2231                 if (pipe_ctx->stream_res.audio != NULL) {
2232                         struct audio_output audio_output;
2233
2234                         build_audio_output(context, pipe_ctx, &audio_output);
2235
2236 #if defined(CONFIG_DRM_AMD_DC_DCN)
2237                         /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
2238                         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2239                                 /* disable audio DTBCLK DTO */
2240                                 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2241                                         dc->res_pool->dccg, 0);
2242
2243                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2244                                                 pipe_ctx->stream_res.audio,
2245                                                 pipe_ctx->stream->signal,
2246                                                 &audio_output.crtc_info,
2247                                                 &audio_output.pll_info);
2248                         } else
2249                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2250                                         pipe_ctx->stream_res.audio,
2251                                         pipe_ctx->stream->signal,
2252                                         &audio_output.crtc_info,
2253                                         &audio_output.pll_info);
2254 #else
2255                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2256                                 pipe_ctx->stream_res.audio,
2257                                 pipe_ctx->stream->signal,
2258                                 &audio_output.crtc_info,
2259                                 &audio_output.pll_info);
2260 #endif
2261                         break;
2262                 }
2263         }
2264
2265         /* no HDMI audio is found, try DP audio */
2266         if (i == dc->res_pool->pipe_count) {
2267                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2268                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2269
2270                         if (pipe_ctx->stream == NULL)
2271                                 continue;
2272
2273                         if (pipe_ctx->top_pipe)
2274                                 continue;
2275
2276                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2277                                 continue;
2278
2279                         if (pipe_ctx->stream_res.audio != NULL) {
2280                                 struct audio_output audio_output;
2281
2282                                 build_audio_output(context, pipe_ctx, &audio_output);
2283
2284                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2285                                         pipe_ctx->stream_res.audio,
2286                                         pipe_ctx->stream->signal,
2287                                         &audio_output.crtc_info,
2288                                         &audio_output.pll_info);
2289                                 break;
2290                         }
2291                 }
2292         }
2293 }
2294
2295 enum dc_status dce110_apply_ctx_to_hw(
2296                 struct dc *dc,
2297                 struct dc_state *context)
2298 {
2299         struct dce_hwseq *hws = dc->hwseq;
2300         struct dc_bios *dcb = dc->ctx->dc_bios;
2301         enum dc_status status;
2302         int i;
2303
2304         /* reset syncd pipes from disabled pipes */
2305         if (dc->config.use_pipe_ctx_sync_logic)
2306                 reset_syncd_pipes_from_disabled_pipes(dc, context);
2307
2308         /* Reset old context */
2309         /* look up the targets that have been removed since last commit */
2310         hws->funcs.reset_hw_ctx_wrap(dc, context);
2311
2312         /* Skip applying if no targets */
2313         if (context->stream_count <= 0)
2314                 return DC_OK;
2315
2316         /* Apply new context */
2317         dcb->funcs->set_scratch_critical_state(dcb, true);
2318
2319         /* below is for real asic only */
2320         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2321                 struct pipe_ctx *pipe_ctx_old =
2322                                         &dc->current_state->res_ctx.pipe_ctx[i];
2323                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2324
2325                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2326                         continue;
2327
2328                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2329                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2330                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2331                                                 pipe_ctx->clock_source, i);
2332                         continue;
2333                 }
2334
2335                 hws->funcs.enable_display_power_gating(
2336                                 dc, i, dc->ctx->dc_bios,
2337                                 PIPE_GATING_CONTROL_DISABLE);
2338         }
2339
2340         if (dc->fbc_compressor)
2341                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2342
2343         dce110_setup_audio_dto(dc, context);
2344
2345         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2346                 struct pipe_ctx *pipe_ctx_old =
2347                                         &dc->current_state->res_ctx.pipe_ctx[i];
2348                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2349
2350                 if (pipe_ctx->stream == NULL)
2351                         continue;
2352
2353                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2354                         pipe_ctx->stream->link->link_state_valid) {
2355                         continue;
2356                 }
2357
2358                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2359                         continue;
2360
2361                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2362                         continue;
2363
2364                 status = apply_single_controller_ctx_to_hw(
2365                                 pipe_ctx,
2366                                 context,
2367                                 dc);
2368
2369                 if (DC_OK != status)
2370                         return status;
2371         }
2372
2373         if (dc->fbc_compressor)
2374                 enable_fbc(dc, dc->current_state);
2375
2376         dcb->funcs->set_scratch_critical_state(dcb, false);
2377
2378         return DC_OK;
2379 }
2380
2381 /*******************************************************************************
2382  * Front End programming
2383  ******************************************************************************/
2384 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2385 {
2386         struct default_adjustment default_adjust = { 0 };
2387
2388         default_adjust.force_hw_default = false;
2389         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2390         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2391         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2392         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2393
2394         /* display color depth */
2395         default_adjust.color_depth =
2396                 pipe_ctx->stream->timing.display_color_depth;
2397
2398         /* Lb color depth */
2399         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2400
2401         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2402                                         pipe_ctx->plane_res.xfm, &default_adjust);
2403 }
2404
2405
2406 /*******************************************************************************
2407  * In order to turn on/off specific surface we will program
2408  * Blender + CRTC
2409  *
2410  * In case that we have two surfaces and they have a different visibility
2411  * we can't turn off the CRTC since it will turn off the entire display
2412  *
2413  * |----------------------------------------------- |
2414  * |bottom pipe|curr pipe  |              |         |
2415  * |Surface    |Surface    | Blender      |  CRCT   |
2416  * |visibility |visibility | Configuration|         |
2417  * |------------------------------------------------|
2418  * |   off     |    off    | CURRENT_PIPE | blank   |
2419  * |   off     |    on     | CURRENT_PIPE | unblank |
2420  * |   on      |    off    | OTHER_PIPE   | unblank |
2421  * |   on      |    on     | BLENDING     | unblank |
2422  * -------------------------------------------------|
2423  *
2424  ******************************************************************************/
2425 static void program_surface_visibility(const struct dc *dc,
2426                 struct pipe_ctx *pipe_ctx)
2427 {
2428         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2429         bool blank_target = false;
2430
2431         if (pipe_ctx->bottom_pipe) {
2432
2433                 /* For now we are supporting only two pipes */
2434                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2435
2436                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2437                         if (pipe_ctx->plane_state->visible)
2438                                 blender_mode = BLND_MODE_BLENDING;
2439                         else
2440                                 blender_mode = BLND_MODE_OTHER_PIPE;
2441
2442                 } else if (!pipe_ctx->plane_state->visible)
2443                         blank_target = true;
2444
2445         } else if (!pipe_ctx->plane_state->visible)
2446                 blank_target = true;
2447
2448         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2449         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2450
2451 }
2452
2453 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2454 {
2455         int i = 0;
2456         struct xfm_grph_csc_adjustment adjust;
2457         memset(&adjust, 0, sizeof(adjust));
2458         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2459
2460
2461         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2462                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2463
2464                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2465                         adjust.temperature_matrix[i] =
2466                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2467         }
2468
2469         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2470 }
2471 static void update_plane_addr(const struct dc *dc,
2472                 struct pipe_ctx *pipe_ctx)
2473 {
2474         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2475
2476         if (plane_state == NULL)
2477                 return;
2478
2479         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2480                         pipe_ctx->plane_res.mi,
2481                         &plane_state->address,
2482                         plane_state->flip_immediate);
2483
2484         plane_state->status.requested_address = plane_state->address;
2485 }
2486
2487 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2488 {
2489         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2490
2491         if (plane_state == NULL)
2492                 return;
2493
2494         plane_state->status.is_flip_pending =
2495                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2496                                         pipe_ctx->plane_res.mi);
2497
2498         if (plane_state->status.is_flip_pending && !plane_state->visible)
2499                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2500
2501         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2502         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2503                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2504                 plane_state->status.is_right_eye =\
2505                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2506         }
2507 }
2508
2509 void dce110_power_down(struct dc *dc)
2510 {
2511         power_down_all_hw_blocks(dc);
2512         disable_vga_and_power_gate_all_controllers(dc);
2513 }
2514
2515 static bool wait_for_reset_trigger_to_occur(
2516         struct dc_context *dc_ctx,
2517         struct timing_generator *tg)
2518 {
2519         bool rc = false;
2520
2521         /* To avoid endless loop we wait at most
2522          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2523         const uint32_t frames_to_wait_on_triggered_reset = 10;
2524         uint32_t i;
2525
2526         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2527
2528                 if (!tg->funcs->is_counter_moving(tg)) {
2529                         DC_ERROR("TG counter is not moving!\n");
2530                         break;
2531                 }
2532
2533                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2534                         rc = true;
2535                         /* usually occurs at i=1 */
2536                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2537                                         i);
2538                         break;
2539                 }
2540
2541                 /* Wait for one frame. */
2542                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2543                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2544         }
2545
2546         if (false == rc)
2547                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2548
2549         return rc;
2550 }
2551
2552 /* Enable timing synchronization for a group of Timing Generators. */
2553 static void dce110_enable_timing_synchronization(
2554                 struct dc *dc,
2555                 int group_index,
2556                 int group_size,
2557                 struct pipe_ctx *grouped_pipes[])
2558 {
2559         struct dc_context *dc_ctx = dc->ctx;
2560         struct dcp_gsl_params gsl_params = { 0 };
2561         int i;
2562
2563         DC_SYNC_INFO("GSL: Setting-up...\n");
2564
2565         /* Designate a single TG in the group as a master.
2566          * Since HW doesn't care which one, we always assign
2567          * the 1st one in the group. */
2568         gsl_params.gsl_group = 0;
2569         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2570
2571         for (i = 0; i < group_size; i++)
2572                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2573                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2574
2575         /* Reset slave controllers on master VSync */
2576         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2577
2578         for (i = 1 /* skip the master */; i < group_size; i++)
2579                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2580                                 grouped_pipes[i]->stream_res.tg,
2581                                 gsl_params.gsl_group);
2582
2583         for (i = 1 /* skip the master */; i < group_size; i++) {
2584                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2585                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2586                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2587                                 grouped_pipes[i]->stream_res.tg);
2588         }
2589
2590         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2591          * is that the sync'ed displays will not drift out of sync over time*/
2592         DC_SYNC_INFO("GSL: Restoring register states.\n");
2593         for (i = 0; i < group_size; i++)
2594                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2595
2596         DC_SYNC_INFO("GSL: Set-up complete.\n");
2597 }
2598
2599 static void dce110_enable_per_frame_crtc_position_reset(
2600                 struct dc *dc,
2601                 int group_size,
2602                 struct pipe_ctx *grouped_pipes[])
2603 {
2604         struct dc_context *dc_ctx = dc->ctx;
2605         struct dcp_gsl_params gsl_params = { 0 };
2606         int i;
2607
2608         gsl_params.gsl_group = 0;
2609         gsl_params.gsl_master = 0;
2610
2611         for (i = 0; i < group_size; i++)
2612                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2613                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2614
2615         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2616
2617         for (i = 1; i < group_size; i++)
2618                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2619                                 grouped_pipes[i]->stream_res.tg,
2620                                 gsl_params.gsl_master,
2621                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2622
2623         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2624         for (i = 1; i < group_size; i++)
2625                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2626
2627         for (i = 0; i < group_size; i++)
2628                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2629
2630 }
2631
2632 static void init_pipes(struct dc *dc, struct dc_state *context)
2633 {
2634         // Do nothing
2635 }
2636
2637 static void init_hw(struct dc *dc)
2638 {
2639         int i;
2640         struct dc_bios *bp;
2641         struct transform *xfm;
2642         struct abm *abm;
2643         struct dmcu *dmcu;
2644         struct dce_hwseq *hws = dc->hwseq;
2645         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2646
2647         bp = dc->ctx->dc_bios;
2648         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2649                 xfm = dc->res_pool->transforms[i];
2650                 xfm->funcs->transform_reset(xfm);
2651
2652                 hws->funcs.enable_display_power_gating(
2653                                 dc, i, bp,
2654                                 PIPE_GATING_CONTROL_INIT);
2655                 hws->funcs.enable_display_power_gating(
2656                                 dc, i, bp,
2657                                 PIPE_GATING_CONTROL_DISABLE);
2658                 hws->funcs.enable_display_pipe_clock_gating(
2659                         dc->ctx,
2660                         true);
2661         }
2662
2663         dce_clock_gating_power_up(dc->hwseq, false);
2664         /***************************************/
2665
2666         for (i = 0; i < dc->link_count; i++) {
2667                 /****************************************/
2668                 /* Power up AND update implementation according to the
2669                  * required signal (which may be different from the
2670                  * default signal on connector). */
2671                 struct dc_link *link = dc->links[i];
2672
2673                 link->link_enc->funcs->hw_init(link->link_enc);
2674         }
2675
2676         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2677                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2678
2679                 tg->funcs->disable_vga(tg);
2680
2681                 /* Blank controller using driver code instead of
2682                  * command table. */
2683                 tg->funcs->set_blank(tg, true);
2684                 hwss_wait_for_blank_complete(tg);
2685         }
2686
2687         for (i = 0; i < dc->res_pool->audio_count; i++) {
2688                 struct audio *audio = dc->res_pool->audios[i];
2689                 audio->funcs->hw_init(audio);
2690         }
2691
2692         for (i = 0; i < dc->link_count; i++) {
2693                 struct dc_link *link = dc->links[i];
2694
2695                 if (link->panel_cntl)
2696                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2697         }
2698
2699         abm = dc->res_pool->abm;
2700         if (abm != NULL)
2701                 abm->funcs->abm_init(abm, backlight);
2702
2703         dmcu = dc->res_pool->dmcu;
2704         if (dmcu != NULL && abm != NULL)
2705                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2706
2707         if (dc->fbc_compressor)
2708                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2709
2710 }
2711
2712
2713 void dce110_prepare_bandwidth(
2714                 struct dc *dc,
2715                 struct dc_state *context)
2716 {
2717         struct clk_mgr *dccg = dc->clk_mgr;
2718
2719         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2720
2721         dccg->funcs->update_clocks(
2722                         dccg,
2723                         context,
2724                         false);
2725 }
2726
2727 void dce110_optimize_bandwidth(
2728                 struct dc *dc,
2729                 struct dc_state *context)
2730 {
2731         struct clk_mgr *dccg = dc->clk_mgr;
2732
2733         dce110_set_displaymarks(dc, context);
2734
2735         dccg->funcs->update_clocks(
2736                         dccg,
2737                         context,
2738                         true);
2739 }
2740
2741 static void dce110_program_front_end_for_pipe(
2742                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2743 {
2744         struct mem_input *mi = pipe_ctx->plane_res.mi;
2745         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2746         struct xfm_grph_csc_adjustment adjust;
2747         struct out_csc_color_matrix tbl_entry;
2748         unsigned int i;
2749         struct dce_hwseq *hws = dc->hwseq;
2750
2751         DC_LOGGER_INIT();
2752         memset(&tbl_entry, 0, sizeof(tbl_entry));
2753
2754         memset(&adjust, 0, sizeof(adjust));
2755         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2756
2757         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2758
2759         set_default_colors(pipe_ctx);
2760         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2761                         == true) {
2762                 tbl_entry.color_space =
2763                         pipe_ctx->stream->output_color_space;
2764
2765                 for (i = 0; i < 12; i++)
2766                         tbl_entry.regval[i] =
2767                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2768
2769                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2770                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2771         }
2772
2773         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2774                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2775
2776                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2777                         adjust.temperature_matrix[i] =
2778                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2779         }
2780
2781         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2782
2783         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2784
2785         program_scaler(dc, pipe_ctx);
2786
2787         mi->funcs->mem_input_program_surface_config(
2788                         mi,
2789                         plane_state->format,
2790                         &plane_state->tiling_info,
2791                         &plane_state->plane_size,
2792                         plane_state->rotation,
2793                         NULL,
2794                         false);
2795         if (mi->funcs->set_blank)
2796                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2797
2798         if (dc->config.gpu_vm_support)
2799                 mi->funcs->mem_input_program_pte_vm(
2800                                 pipe_ctx->plane_res.mi,
2801                                 plane_state->format,
2802                                 &plane_state->tiling_info,
2803                                 plane_state->rotation);
2804
2805         /* Moved programming gamma from dc to hwss */
2806         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2807                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2808                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2809                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2810
2811         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2812                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2813
2814         DC_LOG_SURFACE(
2815                         "Pipe:%d %p: addr hi:0x%x, "
2816                         "addr low:0x%x, "
2817                         "src: %d, %d, %d,"
2818                         " %d; dst: %d, %d, %d, %d;"
2819                         "clip: %d, %d, %d, %d\n",
2820                         pipe_ctx->pipe_idx,
2821                         (void *) pipe_ctx->plane_state,
2822                         pipe_ctx->plane_state->address.grph.addr.high_part,
2823                         pipe_ctx->plane_state->address.grph.addr.low_part,
2824                         pipe_ctx->plane_state->src_rect.x,
2825                         pipe_ctx->plane_state->src_rect.y,
2826                         pipe_ctx->plane_state->src_rect.width,
2827                         pipe_ctx->plane_state->src_rect.height,
2828                         pipe_ctx->plane_state->dst_rect.x,
2829                         pipe_ctx->plane_state->dst_rect.y,
2830                         pipe_ctx->plane_state->dst_rect.width,
2831                         pipe_ctx->plane_state->dst_rect.height,
2832                         pipe_ctx->plane_state->clip_rect.x,
2833                         pipe_ctx->plane_state->clip_rect.y,
2834                         pipe_ctx->plane_state->clip_rect.width,
2835                         pipe_ctx->plane_state->clip_rect.height);
2836
2837         DC_LOG_SURFACE(
2838                         "Pipe %d: width, height, x, y\n"
2839                         "viewport:%d, %d, %d, %d\n"
2840                         "recout:  %d, %d, %d, %d\n",
2841                         pipe_ctx->pipe_idx,
2842                         pipe_ctx->plane_res.scl_data.viewport.width,
2843                         pipe_ctx->plane_res.scl_data.viewport.height,
2844                         pipe_ctx->plane_res.scl_data.viewport.x,
2845                         pipe_ctx->plane_res.scl_data.viewport.y,
2846                         pipe_ctx->plane_res.scl_data.recout.width,
2847                         pipe_ctx->plane_res.scl_data.recout.height,
2848                         pipe_ctx->plane_res.scl_data.recout.x,
2849                         pipe_ctx->plane_res.scl_data.recout.y);
2850 }
2851
2852 static void dce110_apply_ctx_for_surface(
2853                 struct dc *dc,
2854                 const struct dc_stream_state *stream,
2855                 int num_planes,
2856                 struct dc_state *context)
2857 {
2858         int i;
2859
2860         if (num_planes == 0)
2861                 return;
2862
2863         if (dc->fbc_compressor)
2864                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2865
2866         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2867                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2868
2869                 if (pipe_ctx->stream != stream)
2870                         continue;
2871
2872                 /* Need to allocate mem before program front end for Fiji */
2873                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2874                                 pipe_ctx->plane_res.mi,
2875                                 pipe_ctx->stream->timing.h_total,
2876                                 pipe_ctx->stream->timing.v_total,
2877                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2878                                 context->stream_count);
2879
2880                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2881
2882                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2883
2884                 program_surface_visibility(dc, pipe_ctx);
2885
2886         }
2887
2888         if (dc->fbc_compressor)
2889                 enable_fbc(dc, context);
2890 }
2891
2892 static void dce110_post_unlock_program_front_end(
2893                 struct dc *dc,
2894                 struct dc_state *context)
2895 {
2896 }
2897
2898 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2899 {
2900         struct dce_hwseq *hws = dc->hwseq;
2901         int fe_idx = pipe_ctx->plane_res.mi ?
2902                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2903
2904         /* Do not power down fe when stream is active on dce*/
2905         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2906                 return;
2907
2908         hws->funcs.enable_display_power_gating(
2909                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2910
2911         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2912                                 dc->res_pool->transforms[fe_idx]);
2913 }
2914
2915 static void dce110_wait_for_mpcc_disconnect(
2916                 struct dc *dc,
2917                 struct resource_pool *res_pool,
2918                 struct pipe_ctx *pipe_ctx)
2919 {
2920         /* do nothing*/
2921 }
2922
2923 static void program_output_csc(struct dc *dc,
2924                 struct pipe_ctx *pipe_ctx,
2925                 enum dc_color_space colorspace,
2926                 uint16_t *matrix,
2927                 int opp_id)
2928 {
2929         int i;
2930         struct out_csc_color_matrix tbl_entry;
2931
2932         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2933                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2934
2935                 for (i = 0; i < 12; i++)
2936                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2937
2938                 tbl_entry.color_space = color_space;
2939
2940                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2941                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2942         }
2943 }
2944
2945 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2946 {
2947         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2948         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2949         struct mem_input *mi = pipe_ctx->plane_res.mi;
2950         struct dc_cursor_mi_param param = {
2951                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2952                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2953                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2954                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2955                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2956                 .rotation = pipe_ctx->plane_state->rotation,
2957                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2958         };
2959
2960         /**
2961          * If the cursor's source viewport is clipped then we need to
2962          * translate the cursor to appear in the correct position on
2963          * the screen.
2964          *
2965          * This translation isn't affected by scaling so it needs to be
2966          * done *after* we adjust the position for the scale factor.
2967          *
2968          * This is only done by opt-in for now since there are still
2969          * some usecases like tiled display that might enable the
2970          * cursor on both streams while expecting dc to clip it.
2971          */
2972         if (pos_cpy.translate_by_source) {
2973                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2974                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2975         }
2976
2977         if (pipe_ctx->plane_state->address.type
2978                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2979                 pos_cpy.enable = false;
2980
2981         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2982                 pos_cpy.enable = false;
2983
2984         if (ipp->funcs->ipp_cursor_set_position)
2985                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2986         if (mi->funcs->set_cursor_position)
2987                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2988 }
2989
2990 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2991 {
2992         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2993
2994         if (pipe_ctx->plane_res.ipp &&
2995             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2996                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2997                                 pipe_ctx->plane_res.ipp, attributes);
2998
2999         if (pipe_ctx->plane_res.mi &&
3000             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
3001                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
3002                                 pipe_ctx->plane_res.mi, attributes);
3003
3004         if (pipe_ctx->plane_res.xfm &&
3005             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
3006                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
3007                                 pipe_ctx->plane_res.xfm, attributes);
3008 }
3009
3010 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
3011                 uint32_t backlight_pwm_u16_16,
3012                 uint32_t frame_ramp)
3013 {
3014         struct dc_link *link = pipe_ctx->stream->link;
3015         struct dc  *dc = link->ctx->dc;
3016         struct abm *abm = pipe_ctx->stream_res.abm;
3017         struct panel_cntl *panel_cntl = link->panel_cntl;
3018         struct dmcu *dmcu = dc->res_pool->dmcu;
3019         bool fw_set_brightness = true;
3020         /* DMCU -1 for all controller id values,
3021          * therefore +1 here
3022          */
3023         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
3024
3025         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
3026                 return false;
3027
3028         if (dmcu)
3029                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3030
3031         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
3032                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
3033         else
3034                 abm->funcs->set_backlight_level_pwm(
3035                                 abm,
3036                                 backlight_pwm_u16_16,
3037                                 frame_ramp,
3038                                 controller_id,
3039                                 link->panel_cntl->inst);
3040
3041         return true;
3042 }
3043
3044 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
3045 {
3046         struct abm *abm = pipe_ctx->stream_res.abm;
3047         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3048
3049         if (abm)
3050                 abm->funcs->set_abm_immediate_disable(abm,
3051                                 pipe_ctx->stream->link->panel_cntl->inst);
3052
3053         if (panel_cntl)
3054                 panel_cntl->funcs->store_backlight_level(panel_cntl);
3055 }
3056
3057 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3058 {
3059         struct abm *abm = pipe_ctx->stream_res.abm;
3060         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3061         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3062
3063         if (abm && panel_cntl)
3064                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3065 }
3066
3067 static const struct hw_sequencer_funcs dce110_funcs = {
3068         .program_gamut_remap = program_gamut_remap,
3069         .program_output_csc = program_output_csc,
3070         .init_hw = init_hw,
3071         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3072         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3073         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3074         .update_plane_addr = update_plane_addr,
3075         .update_pending_status = dce110_update_pending_status,
3076         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3077         .enable_timing_synchronization = dce110_enable_timing_synchronization,
3078         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3079         .update_info_frame = dce110_update_info_frame,
3080         .enable_stream = dce110_enable_stream,
3081         .disable_stream = dce110_disable_stream,
3082         .unblank_stream = dce110_unblank_stream,
3083         .blank_stream = dce110_blank_stream,
3084         .enable_audio_stream = dce110_enable_audio_stream,
3085         .disable_audio_stream = dce110_disable_audio_stream,
3086         .disable_plane = dce110_power_down_fe,
3087         .pipe_control_lock = dce_pipe_control_lock,
3088         .interdependent_update_lock = NULL,
3089         .cursor_lock = dce_pipe_control_lock,
3090         .prepare_bandwidth = dce110_prepare_bandwidth,
3091         .optimize_bandwidth = dce110_optimize_bandwidth,
3092         .set_drr = set_drr,
3093         .get_position = get_position,
3094         .set_static_screen_control = set_static_screen_control,
3095         .setup_stereo = NULL,
3096         .set_avmute = dce110_set_avmute,
3097         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3098         .edp_backlight_control = dce110_edp_backlight_control,
3099         .edp_power_control = dce110_edp_power_control,
3100         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3101         .set_cursor_position = dce110_set_cursor_position,
3102         .set_cursor_attribute = dce110_set_cursor_attribute,
3103         .set_backlight_level = dce110_set_backlight_level,
3104         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3105         .set_pipe = dce110_set_pipe,
3106 };
3107
3108 static const struct hwseq_private_funcs dce110_private_funcs = {
3109         .init_pipes = init_pipes,
3110         .update_plane_addr = update_plane_addr,
3111         .set_input_transfer_func = dce110_set_input_transfer_func,
3112         .set_output_transfer_func = dce110_set_output_transfer_func,
3113         .power_down = dce110_power_down,
3114         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3115         .enable_display_power_gating = dce110_enable_display_power_gating,
3116         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3117         .enable_stream_timing = dce110_enable_stream_timing,
3118         .disable_stream_gating = NULL,
3119         .enable_stream_gating = NULL,
3120         .edp_backlight_control = dce110_edp_backlight_control,
3121 };
3122
3123 void dce110_hw_sequencer_construct(struct dc *dc)
3124 {
3125         dc->hwss = dce110_funcs;
3126         dc->hwseq->funcs = dce110_private_funcs;
3127 }
3128