drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28 #include "dc_bios_types.h"
  29 #include "core_types.h"
  30 #include "core_status.h"
  31 #include "resource.h"
  32 #include "dm_helpers.h"
  33 #include "dce110_timing_generator.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "gpio_service_interface.h"
  36
  37 #include "dce110_compressor.h"
  38
  39 #include "bios/bios_parser_helper.h"
  40 #include "timing_generator.h"
  41 #include "mem_input.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "transform.h"
  45 #include "stream_encoder.h"
  46 #include "link_encoder.h"
  47 #include "link_enc_cfg.h"
  48 #include "link_hwss.h"
  49 #include "link.h"
  50 #include "dccg.h"
  51 #include "clock_source.h"
  52 #include "clk_mgr.h"
  53 #include "abm.h"
  54 #include "audio.h"
  55 #include "reg_helper.h"
  56 #include "panel_cntl.h"
  57 #include "dpcd_defs.h"
  58 /* include DCE11 register header files */
  59 #include "dce/dce_11_0_d.h"
  60 #include "dce/dce_11_0_sh_mask.h"
  61 #include "custom_float.h"
  62
  63 #include "atomfirmware.h"
  64
  65 #include "dcn10/dcn10_hw_sequencer.h"
  66
  67 #include "dce110_hw_sequencer.h"
  68
  69 #define GAMMA_HW_POINTS_NUM 256
  70
  71 /*
  72  * All values are in milliseconds;
  73  * For eDP, after power-up/power/down,
  74  * 300/500 msec max. delay from LCDVCC to black video generation
  75  */
  76 #define PANEL_POWER_UP_TIMEOUT 300
  77 #define PANEL_POWER_DOWN_TIMEOUT 500
  78 #define HPD_CHECK_INTERVAL 10
  79 #define OLED_POST_T7_DELAY 100
  80 #define OLED_PRE_T11_DELAY 150
  81
  82 #define CTX \
  83         hws->ctx
  84
  85 #define DC_LOGGER_INIT()
  86
  87 #define REG(reg)\
  88         hws->regs->reg
  89
  90 #undef FN
  91 #define FN(reg_name, field_name) \
  92         hws->shifts->field_name, hws->masks->field_name
  93
  94 struct dce110_hw_seq_reg_offsets {
  95         uint32_t crtc;
  96 };
  97
  98 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  99 {
 100         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 101 },
 102 {
 103         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 104 },
 105 {
 106         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 107 },
 108 {
 109         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 110 }
 111 };
 112
 113 #define HW_REG_BLND(reg, id)\
 114         (reg + reg_offsets[id].blnd)
 115
 116 #define HW_REG_CRTC(reg, id)\
 117         (reg + reg_offsets[id].crtc)
 118
 119 #define MAX_WATERMARK 0xFFFF
 120 #define SAFE_NBP_MARK 0x7FFF
 121
 122 /*******************************************************************************
 123  * Private definitions
 124  ******************************************************************************/
 125 /***************************PIPE_CONTROL***********************************/
 126 static void dce110_init_pte(struct dc_context *ctx)
 127 {
 128         uint32_t addr;
 129         uint32_t value = 0;
 130         uint32_t chunk_int = 0;
 131         uint32_t chunk_mul = 0;
 132
 133         addr = mmUNP_DVMM_PTE_CONTROL;
 134         value = dm_read_reg(ctx, addr);
 135
 136         set_reg_field_value(
 137                 value,
 138                 0,
 139                 DVMM_PTE_CONTROL,
 140                 DVMM_USE_SINGLE_PTE);
 141
 142         set_reg_field_value(
 143                 value,
 144                 1,
 145                 DVMM_PTE_CONTROL,
 146                 DVMM_PTE_BUFFER_MODE0);
 147
 148         set_reg_field_value(
 149                 value,
 150                 1,
 151                 DVMM_PTE_CONTROL,
 152                 DVMM_PTE_BUFFER_MODE1);
 153
 154         dm_write_reg(ctx, addr, value);
 155
 156         addr = mmDVMM_PTE_REQ;
 157         value = dm_read_reg(ctx, addr);
 158
 159         chunk_int = get_reg_field_value(
 160                 value,
 161                 DVMM_PTE_REQ,
 162                 HFLIP_PTEREQ_PER_CHUNK_INT);
 163
 164         chunk_mul = get_reg_field_value(
 165                 value,
 166                 DVMM_PTE_REQ,
 167                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 168
 169         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 170
 171                 set_reg_field_value(
 172                         value,
 173                         255,
 174                         DVMM_PTE_REQ,
 175                         MAX_PTEREQ_TO_ISSUE);
 176
 177                 set_reg_field_value(
 178                         value,
 179                         4,
 180                         DVMM_PTE_REQ,
 181                         HFLIP_PTEREQ_PER_CHUNK_INT);
 182
 183                 set_reg_field_value(
 184                         value,
 185                         4,
 186                         DVMM_PTE_REQ,
 187                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 188
 189                 dm_write_reg(ctx, addr, value);
 190         }
 191 }
 192 /**************************************************************************/
 193
 194 static void enable_display_pipe_clock_gating(
 195         struct dc_context *ctx,
 196         bool clock_gating)
 197 {
 198         /*TODO*/
 199 }
 200
 201 static bool dce110_enable_display_power_gating(
 202         struct dc *dc,
 203         uint8_t controller_id,
 204         struct dc_bios *dcb,
 205         enum pipe_gating_control power_gating)
 206 {
 207         enum bp_result bp_result = BP_RESULT_OK;
 208         enum bp_pipe_control_action cntl;
 209         struct dc_context *ctx = dc->ctx;
 210         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 211
 212         if (power_gating == PIPE_GATING_CONTROL_INIT)
 213                 cntl = ASIC_PIPE_INIT;
 214         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 215                 cntl = ASIC_PIPE_ENABLE;
 216         else
 217                 cntl = ASIC_PIPE_DISABLE;
 218
 219         if (controller_id == underlay_idx)
 220                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 221
 222         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
 223
 224                 bp_result = dcb->funcs->enable_disp_power_gating(
 225                                                 dcb, controller_id + 1, cntl);
 226
 227                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 228                  * by default when command table is called
 229                  *
 230                  * Bios parser accepts controller_id = 6 as indicative of
 231                  * underlay pipe in dce110. But we do not support more
 232                  * than 3.
 233                  */
 234                 if (controller_id < CONTROLLER_ID_MAX - 1)
 235                         dm_write_reg(ctx,
 236                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 237                                 0);
 238         }
 239
 240         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 241                 dce110_init_pte(ctx);
 242
 243         if (bp_result == BP_RESULT_OK)
 244                 return true;
 245         else
 246                 return false;
 247 }
 248
 249 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 250                 const struct dc_plane_state *plane_state)
 251 {
 252         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 253
 254         switch (plane_state->format) {
 255         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 256                 prescale_params->scale = 0x2082;
 257                 break;
 258         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 259         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 260                 prescale_params->scale = 0x2020;
 261                 break;
 262         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 263         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 264                 prescale_params->scale = 0x2008;
 265                 break;
 266         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 267         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 268         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 269                 prescale_params->scale = 0x2000;
 270                 break;
 271         default:
 272                 ASSERT(false);
 273                 break;
 274         }
 275 }
 276
 277 static bool
 278 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 279                                const struct dc_plane_state *plane_state)
 280 {
 281         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 282         const struct dc_transfer_func *tf = NULL;
 283         struct ipp_prescale_params prescale_params = { 0 };
 284         bool result = true;
 285
 286         if (ipp == NULL)
 287                 return false;
 288
 289         if (plane_state->in_transfer_func)
 290                 tf = plane_state->in_transfer_func;
 291
 292         build_prescale_params(&prescale_params, plane_state);
 293         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 294
 295         if (plane_state->gamma_correction &&
 296                         !plane_state->gamma_correction->is_identity &&
 297                         dce_use_lut(plane_state->format))
 298                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 299
 300         if (tf == NULL) {
 301                 /* Default case if no input transfer function specified */
 302                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 303         } else if (tf->type == TF_TYPE_PREDEFINED) {
 304                 switch (tf->tf) {
 305                 case TRANSFER_FUNCTION_SRGB:
 306                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 307                         break;
 308                 case TRANSFER_FUNCTION_BT709:
 309                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 310                         break;
 311                 case TRANSFER_FUNCTION_LINEAR:
 312                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 313                         break;
 314                 case TRANSFER_FUNCTION_PQ:
 315                 default:
 316                         result = false;
 317                         break;
 318                 }
 319         } else if (tf->type == TF_TYPE_BYPASS) {
 320                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 321         } else {
 322                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 323                 result = false;
 324         }
 325
 326         return result;
 327 }
 328
 329 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 330                                     struct curve_points *arr_points,
 331                                     uint32_t hw_points_num)
 332 {
 333         struct custom_float_format fmt;
 334
 335         struct pwl_result_data *rgb = rgb_resulted;
 336
 337         uint32_t i = 0;
 338
 339         fmt.exponenta_bits = 6;
 340         fmt.mantissa_bits = 12;
 341         fmt.sign = true;
 342
 343         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 344                                             &arr_points[0].custom_float_x)) {
 345                 BREAK_TO_DEBUGGER();
 346                 return false;
 347         }
 348
 349         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 350                                             &arr_points[0].custom_float_offset)) {
 351                 BREAK_TO_DEBUGGER();
 352                 return false;
 353         }
 354
 355         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 356                                             &arr_points[0].custom_float_slope)) {
 357                 BREAK_TO_DEBUGGER();
 358                 return false;
 359         }
 360
 361         fmt.mantissa_bits = 10;
 362         fmt.sign = false;
 363
 364         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 365                                             &arr_points[1].custom_float_x)) {
 366                 BREAK_TO_DEBUGGER();
 367                 return false;
 368         }
 369
 370         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 371                                             &arr_points[1].custom_float_y)) {
 372                 BREAK_TO_DEBUGGER();
 373                 return false;
 374         }
 375
 376         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 377                                             &arr_points[1].custom_float_slope)) {
 378                 BREAK_TO_DEBUGGER();
 379                 return false;
 380         }
 381
 382         fmt.mantissa_bits = 12;
 383         fmt.sign = true;
 384
 385         while (i != hw_points_num) {
 386                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 387                                                     &rgb->red_reg)) {
 388                         BREAK_TO_DEBUGGER();
 389                         return false;
 390                 }
 391
 392                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 393                                                     &rgb->green_reg)) {
 394                         BREAK_TO_DEBUGGER();
 395                         return false;
 396                 }
 397
 398                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 399                                                     &rgb->blue_reg)) {
 400                         BREAK_TO_DEBUGGER();
 401                         return false;
 402                 }
 403
 404                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 405                                                     &rgb->delta_red_reg)) {
 406                         BREAK_TO_DEBUGGER();
 407                         return false;
 408                 }
 409
 410                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 411                                                     &rgb->delta_green_reg)) {
 412                         BREAK_TO_DEBUGGER();
 413                         return false;
 414                 }
 415
 416                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 417                                                     &rgb->delta_blue_reg)) {
 418                         BREAK_TO_DEBUGGER();
 419                         return false;
 420                 }
 421
 422                 ++rgb;
 423                 ++i;
 424         }
 425
 426         return true;
 427 }
 428
 429 #define MAX_LOW_POINT      25
 430 #define NUMBER_REGIONS     16
 431 #define NUMBER_SW_SEGMENTS 16
 432
 433 static bool
 434 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 435                                       struct pwl_params *regamma_params)
 436 {
 437         struct curve_points *arr_points;
 438         struct pwl_result_data *rgb_resulted;
 439         struct pwl_result_data *rgb;
 440         struct pwl_result_data *rgb_plus_1;
 441         struct fixed31_32 y_r;
 442         struct fixed31_32 y_g;
 443         struct fixed31_32 y_b;
 444         struct fixed31_32 y1_min;
 445         struct fixed31_32 y3_max;
 446
 447         int32_t region_start, region_end;
 448         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 449
 450         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 451                 return false;
 452
 453         arr_points = regamma_params->arr_points;
 454         rgb_resulted = regamma_params->rgb_resulted;
 455         hw_points = 0;
 456
 457         memset(regamma_params, 0, sizeof(struct pwl_params));
 458
 459         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 460                 /* 16 segments
 461                  * segments are from 2^-11 to 2^5
 462                  */
 463                 region_start = -11;
 464                 region_end = region_start + NUMBER_REGIONS;
 465
 466                 for (i = 0; i < NUMBER_REGIONS; i++)
 467                         seg_distr[i] = 4;
 468
 469         } else {
 470                 /* 10 segments
 471                  * segment is from 2^-10 to 2^1
 472                  * We include an extra segment for range [2^0, 2^1). This is to
 473                  * ensure that colors with normalized values of 1 don't miss the
 474                  * LUT.
 475                  */
 476                 region_start = -10;
 477                 region_end = 1;
 478
 479                 seg_distr[0] = 4;
 480                 seg_distr[1] = 4;
 481                 seg_distr[2] = 4;
 482                 seg_distr[3] = 4;
 483                 seg_distr[4] = 4;
 484                 seg_distr[5] = 4;
 485                 seg_distr[6] = 4;
 486                 seg_distr[7] = 4;
 487                 seg_distr[8] = 4;
 488                 seg_distr[9] = 4;
 489                 seg_distr[10] = 0;
 490                 seg_distr[11] = -1;
 491                 seg_distr[12] = -1;
 492                 seg_distr[13] = -1;
 493                 seg_distr[14] = -1;
 494                 seg_distr[15] = -1;
 495         }
 496
 497         for (k = 0; k < 16; k++) {
 498                 if (seg_distr[k] != -1)
 499                         hw_points += (1 << seg_distr[k]);
 500         }
 501
 502         j = 0;
 503         for (k = 0; k < (region_end - region_start); k++) {
 504                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 505                 start_index = (region_start + k + MAX_LOW_POINT) *
 506                                 NUMBER_SW_SEGMENTS;
 507                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 508                                 i += increment) {
 509                         if (j == hw_points - 1)
 510                                 break;
 511                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 512                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 513                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 514                         j++;
 515                 }
 516         }
 517
 518         /* last point */
 519         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 520         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 521         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 522         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 523
 524         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 525                                              dc_fixpt_from_int(region_start));
 526         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 527                                              dc_fixpt_from_int(region_end));
 528
 529         y_r = rgb_resulted[0].red;
 530         y_g = rgb_resulted[0].green;
 531         y_b = rgb_resulted[0].blue;
 532
 533         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 534
 535         arr_points[0].y = y1_min;
 536         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 537                                                  arr_points[0].x);
 538
 539         y_r = rgb_resulted[hw_points - 1].red;
 540         y_g = rgb_resulted[hw_points - 1].green;
 541         y_b = rgb_resulted[hw_points - 1].blue;
 542
 543         /* see comment above, m_arrPoints[1].y should be the Y value for the
 544          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 545          */
 546         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 547
 548         arr_points[1].y = y3_max;
 549
 550         arr_points[1].slope = dc_fixpt_zero;
 551
 552         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 553                 /* for PQ, we want to have a straight line from last HW X point,
 554                  * and the slope to be such that we hit 1.0 at 10000 nits.
 555                  */
 556                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 557
 558                 arr_points[1].slope = dc_fixpt_div(
 559                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 560                                 dc_fixpt_sub(end_value, arr_points[1].x));
 561         }
 562
 563         regamma_params->hw_points_num = hw_points;
 564
 565         k = 0;
 566         for (i = 1; i < 16; i++) {
 567                 if (seg_distr[k] != -1) {
 568                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 569                         regamma_params->arr_curve_points[i].offset =
 570                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 571                 }
 572                 k++;
 573         }
 574
 575         if (seg_distr[k] != -1)
 576                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 577
 578         rgb = rgb_resulted;
 579         rgb_plus_1 = rgb_resulted + 1;
 580
 581         i = 1;
 582
 583         while (i != hw_points + 1) {
 584                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 585                         rgb_plus_1->red = rgb->red;
 586                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 587                         rgb_plus_1->green = rgb->green;
 588                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 589                         rgb_plus_1->blue = rgb->blue;
 590
 591                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 592                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 593                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 594
 595                 ++rgb_plus_1;
 596                 ++rgb;
 597                 ++i;
 598         }
 599
 600         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 601
 602         return true;
 603 }
 604
 605 static bool
 606 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 607                                 const struct dc_stream_state *stream)
 608 {
 609         struct transform *xfm = pipe_ctx->plane_res.xfm;
 610
 611         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 612         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 613
 614         if (stream->out_transfer_func &&
 615             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 616             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 617                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 618         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 619                                                          &xfm->regamma_params)) {
 620                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 621                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 622         } else {
 623                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 624         }
 625
 626         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 627
 628         return true;
 629 }
 630
 631 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 632 {
 633         bool is_hdmi_tmds;
 634         bool is_dp;
 635
 636         ASSERT(pipe_ctx->stream);
 637
 638         if (pipe_ctx->stream_res.stream_enc == NULL)
 639                 return;  /* this is not root pipe */
 640
 641         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 642         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 643
 644         if (!is_hdmi_tmds && !is_dp)
 645                 return;
 646
 647         if (is_hdmi_tmds)
 648                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 649                         pipe_ctx->stream_res.stream_enc,
 650                         &pipe_ctx->stream_res.encoder_info_frame);
 651         else {
 652                 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
 653                         pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
 654                                 pipe_ctx->stream_res.stream_enc,
 655                                 &pipe_ctx->stream_res.encoder_info_frame);
 656
 657                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 658                         pipe_ctx->stream_res.stream_enc,
 659                         &pipe_ctx->stream_res.encoder_info_frame);
 660         }
 661 }
 662
 663 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 664 {
 665         enum dc_lane_count lane_count =
 666                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 667         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 668         struct dc_link *link = pipe_ctx->stream->link;
 669         const struct dc *dc = link->dc;
 670         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
 671         uint32_t active_total_with_borders;
 672         uint32_t early_control = 0;
 673         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 674
 675         link_hwss->setup_stream_encoder(pipe_ctx);
 676
 677         dc->hwss.update_info_frame(pipe_ctx);
 678
 679         /* enable early control to avoid corruption on DP monitor*/
 680         active_total_with_borders =
 681                         timing->h_addressable
 682                                 + timing->h_border_left
 683                                 + timing->h_border_right;
 684
 685         if (lane_count != 0)
 686                 early_control = active_total_with_borders % lane_count;
 687
 688         if (early_control == 0)
 689                 early_control = lane_count;
 690
 691         tg->funcs->set_early_control(tg, early_control);
 692 }
 693
 694 static enum bp_result link_transmitter_control(
 695                 struct dc_bios *bios,
 696         struct bp_transmitter_control *cntl)
 697 {
 698         enum bp_result result;
 699
 700         result = bios->funcs->transmitter_control(bios, cntl);
 701
 702         return result;
 703 }
 704
 705 /*
 706  * @brief
 707  * eDP only.
 708  */
 709 void dce110_edp_wait_for_hpd_ready(
 710                 struct dc_link *link,
 711                 bool power_up)
 712 {
 713         struct dc_context *ctx = link->ctx;
 714         struct graphics_object_id connector = link->link_enc->connector;
 715         struct gpio *hpd;
 716         bool edp_hpd_high = false;
 717         uint32_t time_elapsed = 0;
 718         uint32_t timeout = power_up ?
 719                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 720
 721         if (dal_graphics_object_id_get_connector_id(connector)
 722                         != CONNECTOR_ID_EDP) {
 723                 BREAK_TO_DEBUGGER();
 724                 return;
 725         }
 726
 727         if (!power_up)
 728                 /*
 729                  * From KV, we will not HPD low after turning off VCC -
 730                  * instead, we will check the SW timer in power_up().
 731                  */
 732                 return;
 733
 734         /*
 735          * When we power on/off the eDP panel,
 736          * we need to wait until SENSE bit is high/low.
 737          */
 738
 739         /* obtain HPD */
 740         /* TODO what to do with this? */
 741         hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 742
 743         if (!hpd) {
 744                 BREAK_TO_DEBUGGER();
 745                 return;
 746         }
 747
 748         if (link != NULL) {
 749                 if (link->panel_config.pps.extra_t3_ms > 0) {
 750                         int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
 751
 752                         msleep(extra_t3_in_ms);
 753                 }
 754         }
 755
 756         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 757
 758         /* wait until timeout or panel detected */
 759
 760         do {
 761                 uint32_t detected = 0;
 762
 763                 dal_gpio_get_value(hpd, &detected);
 764
 765                 if (!(detected ^ power_up)) {
 766                         edp_hpd_high = true;
 767                         break;
 768                 }
 769
 770                 msleep(HPD_CHECK_INTERVAL);
 771
 772                 time_elapsed += HPD_CHECK_INTERVAL;
 773         } while (time_elapsed < timeout);
 774
 775         dal_gpio_close(hpd);
 776
 777         dal_gpio_destroy_irq(&hpd);
 778
 779         /* ensure that the panel is detected */
 780         if (!edp_hpd_high)
 781                 DC_LOG_DC("%s: wait timed out!\n", __func__);
 782 }
 783
 784 void dce110_edp_power_control(
 785                 struct dc_link *link,
 786                 bool power_up)
 787 {
 788         struct dc_context *ctx = link->ctx;
 789         struct bp_transmitter_control cntl = { 0 };
 790         enum bp_result bp_result;
 791         uint8_t panel_instance;
 792
 793
 794         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 795                         != CONNECTOR_ID_EDP) {
 796                 BREAK_TO_DEBUGGER();
 797                 return;
 798         }
 799
 800         if (!link->panel_cntl)
 801                 return;
 802         if (power_up !=
 803                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 804
 805                 unsigned long long current_ts = dm_get_timestamp(ctx);
 806                 unsigned long long time_since_edp_poweroff_ms =
 807                                 div64_u64(dm_get_elapse_time_in_ns(
 808                                                 ctx,
 809                                                 current_ts,
 810                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 811                 unsigned long long time_since_edp_poweron_ms =
 812                                 div64_u64(dm_get_elapse_time_in_ns(
 813                                                 ctx,
 814                                                 current_ts,
 815                                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);
 816                 DC_LOG_HW_RESUME_S3(
 817                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 818                                 __func__,
 819                                 power_up,
 820                                 current_ts,
 821                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 822                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),
 823                                 time_since_edp_poweroff_ms,
 824                                 time_since_edp_poweron_ms);
 825
 826                 /* Send VBIOS command to prompt eDP panel power */
 827                 if (power_up) {
 828                         /* edp requires a min of 500ms from LCDVDD off to on */
 829                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 830
 831                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 832                         if (link->local_sink != NULL)
 833                                 remaining_min_edp_poweroff_time_ms +=
 834                                         link->panel_config.pps.extra_t12_ms;
 835
 836                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 837                         if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 838                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 839                                         remaining_min_edp_poweroff_time_ms =
 840                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 841                                 else
 842                                         remaining_min_edp_poweroff_time_ms = 0;
 843                         }
 844
 845                         if (remaining_min_edp_poweroff_time_ms) {
 846                                 DC_LOG_HW_RESUME_S3(
 847                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 848                                                 __func__, remaining_min_edp_poweroff_time_ms);
 849                                 msleep(remaining_min_edp_poweroff_time_ms);
 850                                 DC_LOG_HW_RESUME_S3(
 851                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 852                                                 __func__, remaining_min_edp_poweroff_time_ms);
 853                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 854                                                 __func__, remaining_min_edp_poweroff_time_ms);
 855                         } else {
 856                                 DC_LOG_HW_RESUME_S3(
 857                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 858                                                 __func__, remaining_min_edp_poweroff_time_ms);
 859                         }
 860                 }
 861
 862                 DC_LOG_HW_RESUME_S3(
 863                                 "%s: BEGIN: Panel Power action: %s\n",
 864                                 __func__, (power_up ? "On":"Off"));
 865
 866                 cntl.action = power_up ?
 867                         TRANSMITTER_CONTROL_POWER_ON :
 868                         TRANSMITTER_CONTROL_POWER_OFF;
 869                 cntl.transmitter = link->link_enc->transmitter;
 870                 cntl.connector_obj_id = link->link_enc->connector;
 871                 cntl.coherent = false;
 872                 cntl.lanes_number = LANE_COUNT_FOUR;
 873                 cntl.hpd_sel = link->link_enc->hpd_source;
 874                 panel_instance = link->panel_cntl->inst;
 875
 876                 if (ctx->dc->ctx->dmub_srv &&
 877                                 ctx->dc->debug.dmub_command_table) {
 878
 879                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {
 880                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 881                                                 LVTMA_CONTROL_POWER_ON,
 882                                                 panel_instance, link->link_powered_externally);
 883                         } else {
 884                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 885                                                 LVTMA_CONTROL_POWER_OFF,
 886                                                 panel_instance, link->link_powered_externally);
 887                         }
 888                 }
 889
 890                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 891
 892                 DC_LOG_HW_RESUME_S3(
 893                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 894                                 __func__, (power_up ? "On":"Off"),
 895                                 bp_result);
 896
 897                 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);
 898
 899                 DC_LOG_HW_RESUME_S3(
 900                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 901                                 __func__,
 902                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 903                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));
 904
 905                 if (bp_result != BP_RESULT_OK)
 906                         DC_LOG_ERROR(
 907                                         "%s: Panel Power bp_result: %d\n",
 908                                         __func__, bp_result);
 909         } else {
 910                 DC_LOG_HW_RESUME_S3(
 911                                 "%s: Skipping Panel Power action: %s\n",
 912                                 __func__, (power_up ? "On":"Off"));
 913         }
 914 }
 915
 916 void dce110_edp_wait_for_T12(
 917                 struct dc_link *link)
 918 {
 919         struct dc_context *ctx = link->ctx;
 920
 921         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 922                         != CONNECTOR_ID_EDP) {
 923                 BREAK_TO_DEBUGGER();
 924                 return;
 925         }
 926
 927         if (!link->panel_cntl)
 928                 return;
 929
 930         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 931                         ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 932                 unsigned int t12_duration = 500; // Default T12 as per spec
 933                 unsigned long long current_ts = dm_get_timestamp(ctx);
 934                 unsigned long long time_since_edp_poweroff_ms =
 935                                 div64_u64(dm_get_elapse_time_in_ns(
 936                                                 ctx,
 937                                                 current_ts,
 938                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 939
 940                 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
 941
 942                 if (time_since_edp_poweroff_ms < t12_duration)
 943                         msleep(t12_duration - time_since_edp_poweroff_ms);
 944         }
 945 }
 946 /*todo: cloned in stream enc, fix*/
 947 /*
 948  * @brief
 949  * eDP only. Control the backlight of the eDP panel
 950  */
 951 void dce110_edp_backlight_control(
 952                 struct dc_link *link,
 953                 bool enable)
 954 {
 955         struct dc_context *ctx = link->ctx;
 956         struct bp_transmitter_control cntl = { 0 };
 957         uint8_t panel_instance;
 958         unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
 959         unsigned int post_T7_delay = OLED_POST_T7_DELAY;
 960
 961         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 962                 != CONNECTOR_ID_EDP) {
 963                 BREAK_TO_DEBUGGER();
 964                 return;
 965         }
 966
 967         if (link->panel_cntl) {
 968                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 969
 970                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 971                         DC_LOG_HW_RESUME_S3(
 972                                 "%s: panel already powered up/off. Do nothing.\n",
 973                                 __func__);
 974                         return;
 975                 }
 976         }
 977
 978         /* Send VBIOS command to control eDP panel backlight */
 979
 980         DC_LOG_HW_RESUME_S3(
 981                         "%s: backlight action: %s\n",
 982                         __func__, (enable ? "On":"Off"));
 983
 984         cntl.action = enable ?
 985                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 986                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 987
 988         /*cntl.engine_id = ctx->engine;*/
 989         cntl.transmitter = link->link_enc->transmitter;
 990         cntl.connector_obj_id = link->link_enc->connector;
 991         /*todo: unhardcode*/
 992         cntl.lanes_number = LANE_COUNT_FOUR;
 993         cntl.hpd_sel = link->link_enc->hpd_source;
 994         cntl.signal = SIGNAL_TYPE_EDP;
 995
 996         /* For eDP, the following delays might need to be considered
 997          * after link training completed:
 998          * idle period - min. accounts for required BS-Idle pattern,
 999          * max. allows for source frame synchronization);
1000          * 50 msec max. delay from valid video data from source
1001          * to video on dislpay or backlight enable.
1002          *
1003          * Disable the delay for now.
1004          * Enable it in the future if necessary.
1005          */
1006         /* dc_service_sleep_in_milliseconds(50); */
1007                 /*edp 1.2*/
1008         panel_instance = link->panel_cntl->inst;
1009
1010         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1011                 if (!link->dc->config.edp_no_power_sequencing)
1012                 /*
1013                  * Sometimes, DP receiver chip power-controlled externally by an
1014                  * Embedded Controller could be treated and used as eDP,
1015                  * if it drives mobile display. In this case,
1016                  * we shouldn't be doing power-sequencing, hence we can skip
1017                  * waiting for T7-ready.
1018                  */
1019                         ctx->dc->link_srv->edp_receiver_ready_T7(link);
1020                 else
1021                         DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1022         }
1023
1024         /* Setting link_powered_externally will bypass delays in the backlight
1025          * as they are not required if the link is being powered by a different
1026          * source.
1027          */
1028         if (ctx->dc->ctx->dmub_srv &&
1029                         ctx->dc->debug.dmub_command_table) {
1030                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1031                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1032                                         LVTMA_CONTROL_LCD_BLON,
1033                                         panel_instance, link->link_powered_externally);
1034                 else
1035                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1036                                         LVTMA_CONTROL_LCD_BLOFF,
1037                                         panel_instance, link->link_powered_externally);
1038         }
1039
1040         link_transmitter_control(ctx->dc_bios, &cntl);
1041
1042         if (enable && link->dpcd_sink_ext_caps.bits.oled) {
1043                 post_T7_delay += link->panel_config.pps.extra_post_t7_ms;
1044                 msleep(post_T7_delay);
1045         }
1046
1047         if (link->dpcd_sink_ext_caps.bits.oled ||
1048                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1049                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1050                 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);
1051
1052         /*edp 1.2*/
1053         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1054                 if (!link->dc->config.edp_no_power_sequencing)
1055                 /*
1056                  * Sometimes, DP receiver chip power-controlled externally by an
1057                  * Embedded Controller could be treated and used as eDP,
1058                  * if it drives mobile display. In this case,
1059                  * we shouldn't be doing power-sequencing, hence we can skip
1060                  * waiting for T9-ready.
1061                  */
1062                         ctx->dc->link_srv->edp_add_delay_for_T9(link);
1063                 else
1064                         DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1065         }
1066
1067         if (!enable && link->dpcd_sink_ext_caps.bits.oled) {
1068                 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;
1069                 msleep(pre_T11_delay);
1070         }
1071 }
1072
1073 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1074 {
1075         /* notify audio driver for audio modes of monitor */
1076         struct dc *dc;
1077         struct clk_mgr *clk_mgr;
1078         unsigned int i, num_audio = 1;
1079         const struct link_hwss *link_hwss;
1080
1081         if (!pipe_ctx->stream)
1082                 return;
1083
1084         dc = pipe_ctx->stream->ctx->dc;
1085         clk_mgr = dc->clk_mgr;
1086         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1087
1088         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1089                 return;
1090
1091         if (pipe_ctx->stream_res.audio) {
1092                 for (i = 0; i < MAX_PIPES; i++) {
1093                         /*current_state not updated yet*/
1094                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1095                                 num_audio++;
1096                 }
1097
1098                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1099
1100                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1101                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1102                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1103
1104                 link_hwss->enable_audio_packet(pipe_ctx);
1105
1106                 if (pipe_ctx->stream_res.audio)
1107                         pipe_ctx->stream_res.audio->enabled = true;
1108         }
1109 }
1110
1111 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1112 {
1113         struct dc *dc;
1114         struct clk_mgr *clk_mgr;
1115         const struct link_hwss *link_hwss;
1116
1117         if (!pipe_ctx || !pipe_ctx->stream)
1118                 return;
1119
1120         dc = pipe_ctx->stream->ctx->dc;
1121         clk_mgr = dc->clk_mgr;
1122         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1123
1124         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1125                 return;
1126
1127         link_hwss->disable_audio_packet(pipe_ctx);
1128
1129         if (pipe_ctx->stream_res.audio) {
1130                 pipe_ctx->stream_res.audio->enabled = false;
1131
1132                 if (clk_mgr->funcs->enable_pme_wa)
1133                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1134                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1135
1136                 /* TODO: notify audio driver for if audio modes list changed
1137                  * add audio mode list change flag */
1138                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1139                  * stream->stream_engine_id);
1140                  */
1141         }
1142 }
1143
1144 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1145 {
1146         struct dc_stream_state *stream = pipe_ctx->stream;
1147         struct dc_link *link = stream->link;
1148         struct dc *dc = pipe_ctx->stream->ctx->dc;
1149         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1150         struct dccg *dccg = dc->res_pool->dccg;
1151         struct timing_generator *tg = pipe_ctx->stream_res.tg;
1152         struct dtbclk_dto_params dto_params = {0};
1153         int dp_hpo_inst;
1154         struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
1155         struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
1156
1157         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1158                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1159                         pipe_ctx->stream_res.stream_enc);
1160                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1161                         pipe_ctx->stream_res.stream_enc);
1162         }
1163
1164         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1165                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1166                                         pipe_ctx->stream_res.hpo_dp_stream_enc);
1167         } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1168                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1169                         pipe_ctx->stream_res.stream_enc);
1170
1171         dc->hwss.disable_audio_stream(pipe_ctx);
1172
1173         link_hwss->reset_stream_encoder(pipe_ctx);
1174
1175         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1176                 dto_params.otg_inst = tg->inst;
1177                 dto_params.timing = &pipe_ctx->stream->timing;
1178                 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
1179                 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
1180                 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
1181                 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
1182         } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se)
1183                 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
1184                                 link_enc->transmitter - TRANSMITTER_UNIPHY_A);
1185
1186         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1187                 /* TODO: This looks like a bug to me as we are disabling HPO IO when
1188                  * we are just disabling a single HPO stream. Shouldn't we disable HPO
1189                  * HW control only when HPOs for all streams are disabled?
1190                  */
1191                 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control)
1192                         pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control(
1193                                         pipe_ctx->stream->ctx->dc->hwseq, false);
1194         }
1195 }
1196
1197 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1198                 struct dc_link_settings *link_settings)
1199 {
1200         struct encoder_unblank_param params = { { 0 } };
1201         struct dc_stream_state *stream = pipe_ctx->stream;
1202         struct dc_link *link = stream->link;
1203         struct dce_hwseq *hws = link->dc->hwseq;
1204
1205         /* only 3 items below are used by unblank */
1206         params.timing = pipe_ctx->stream->timing;
1207         params.link_settings.link_rate = link_settings->link_rate;
1208
1209         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1210                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1211
1212         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1213                 hws->funcs.edp_backlight_control(link, true);
1214         }
1215 }
1216
1217 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1218 {
1219         struct dc_stream_state *stream = pipe_ctx->stream;
1220         struct dc_link *link = stream->link;
1221         struct dce_hwseq *hws = link->dc->hwseq;
1222
1223         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1224                 if (!stream->skip_edp_power_down)
1225                         hws->funcs.edp_backlight_control(link, false);
1226                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1227         }
1228
1229         if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1230                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1231                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1232                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1233         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1234                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1235
1236                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1237                         /*
1238                          * After output is idle pattern some sinks need time to recognize the stream
1239                          * has changed or they enter protection state and hang.
1240                          */
1241                         msleep(60);
1242                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1243                         if (!link->dc->config.edp_no_power_sequencing) {
1244                                 /*
1245                                  * Sometimes, DP receiver chip power-controlled externally by an
1246                                  * Embedded Controller could be treated and used as eDP,
1247                                  * if it drives mobile display. In this case,
1248                                  * we shouldn't be doing power-sequencing, hence we can skip
1249                                  * waiting for T9-ready.
1250                                  */
1251                                 link->dc->link_srv->edp_receiver_ready_T9(link);
1252                         }
1253                 }
1254         }
1255
1256 }
1257
1258
1259 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1260 {
1261         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1262                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1263 }
1264
1265 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1266 {
1267         switch (crtc_id) {
1268         case CONTROLLER_ID_D0:
1269                 return DTO_SOURCE_ID0;
1270         case CONTROLLER_ID_D1:
1271                 return DTO_SOURCE_ID1;
1272         case CONTROLLER_ID_D2:
1273                 return DTO_SOURCE_ID2;
1274         case CONTROLLER_ID_D3:
1275                 return DTO_SOURCE_ID3;
1276         case CONTROLLER_ID_D4:
1277                 return DTO_SOURCE_ID4;
1278         case CONTROLLER_ID_D5:
1279                 return DTO_SOURCE_ID5;
1280         default:
1281                 return DTO_SOURCE_UNKNOWN;
1282         }
1283 }
1284
1285 static void build_audio_output(
1286         struct dc_state *state,
1287         const struct pipe_ctx *pipe_ctx,
1288         struct audio_output *audio_output)
1289 {
1290         const struct dc_stream_state *stream = pipe_ctx->stream;
1291         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1292
1293         audio_output->signal = pipe_ctx->stream->signal;
1294
1295         /* audio_crtc_info  */
1296
1297         audio_output->crtc_info.h_total =
1298                 stream->timing.h_total;
1299
1300         /*
1301          * Audio packets are sent during actual CRTC blank physical signal, we
1302          * need to specify actual active signal portion
1303          */
1304         audio_output->crtc_info.h_active =
1305                         stream->timing.h_addressable
1306                         + stream->timing.h_border_left
1307                         + stream->timing.h_border_right;
1308
1309         audio_output->crtc_info.v_active =
1310                         stream->timing.v_addressable
1311                         + stream->timing.v_border_top
1312                         + stream->timing.v_border_bottom;
1313
1314         audio_output->crtc_info.pixel_repetition = 1;
1315
1316         audio_output->crtc_info.interlaced =
1317                         stream->timing.flags.INTERLACE;
1318
1319         audio_output->crtc_info.refresh_rate =
1320                 (stream->timing.pix_clk_100hz*100)/
1321                 (stream->timing.h_total*stream->timing.v_total);
1322
1323         audio_output->crtc_info.color_depth =
1324                 stream->timing.display_color_depth;
1325
1326         audio_output->crtc_info.requested_pixel_clock_100Hz =
1327                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1328
1329         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1330                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1331
1332 /*for HDMI, audio ACR is with deep color ratio factor*/
1333         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1334                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1335                                 (stream->timing.pix_clk_100hz)) {
1336                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1337                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1338                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1339                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1340                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1341
1342                 }
1343         }
1344
1345         if (state->clk_mgr &&
1346                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1347                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1348                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1349                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1350                                                 state->clk_mgr);
1351         }
1352
1353         audio_output->pll_info.feed_back_divider =
1354                         pipe_ctx->pll_settings.feedback_divider;
1355
1356         audio_output->pll_info.dto_source =
1357                 translate_to_dto_source(
1358                         pipe_ctx->stream_res.tg->inst + 1);
1359
1360         /* TODO hard code to enable for now. Need get from stream */
1361         audio_output->pll_info.ss_enabled = true;
1362
1363         audio_output->pll_info.ss_percentage =
1364                         pipe_ctx->pll_settings.ss_percentage;
1365 }
1366
1367 static void program_scaler(const struct dc *dc,
1368                 const struct pipe_ctx *pipe_ctx)
1369 {
1370         struct tg_color color = {0};
1371
1372         /* TOFPGA */
1373         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1374                 return;
1375
1376         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1377                 get_surface_visual_confirm_color(pipe_ctx, &color);
1378         else
1379                 color_space_to_black_color(dc,
1380                                 pipe_ctx->stream->output_color_space,
1381                                 &color);
1382
1383         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1384                 pipe_ctx->plane_res.xfm,
1385                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1386                 &pipe_ctx->stream->bit_depth_params);
1387
1388         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1389                 /*
1390                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1391                  * alternate between Cb and Cr, so both channels need the pixel
1392                  * value for Y
1393                  */
1394                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1395                         color.color_r_cr = color.color_g_y;
1396
1397                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1398                                 pipe_ctx->stream_res.tg,
1399                                 &color);
1400         }
1401
1402         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1403                 &pipe_ctx->plane_res.scl_data);
1404 }
1405
1406 static enum dc_status dce110_enable_stream_timing(
1407                 struct pipe_ctx *pipe_ctx,
1408                 struct dc_state *context,
1409                 struct dc *dc)
1410 {
1411         struct dc_stream_state *stream = pipe_ctx->stream;
1412         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1413                         pipe_ctx[pipe_ctx->pipe_idx];
1414         struct tg_color black_color = {0};
1415
1416         if (!pipe_ctx_old->stream) {
1417
1418                 /* program blank color */
1419                 color_space_to_black_color(dc,
1420                                 stream->output_color_space, &black_color);
1421                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1422                                 pipe_ctx->stream_res.tg,
1423                                 &black_color);
1424
1425                 /*
1426                  * Must blank CRTC after disabling power gating and before any
1427                  * programming, otherwise CRTC will be hung in bad state
1428                  */
1429                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1430
1431                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1432                                 pipe_ctx->clock_source,
1433                                 &pipe_ctx->stream_res.pix_clk_params,
1434                                 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1435                                 &pipe_ctx->pll_settings)) {
1436                         BREAK_TO_DEBUGGER();
1437                         return DC_ERROR_UNEXPECTED;
1438                 }
1439
1440                 if (dc_is_hdmi_tmds_signal(stream->signal)) {
1441                         stream->link->phy_state.symclk_ref_cnts.otg = 1;
1442                         if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
1443                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1444                         else
1445                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
1446                 }
1447
1448                 pipe_ctx->stream_res.tg->funcs->program_timing(
1449                                 pipe_ctx->stream_res.tg,
1450                                 &stream->timing,
1451                                 0,
1452                                 0,
1453                                 0,
1454                                 0,
1455                                 pipe_ctx->stream->signal,
1456                                 true);
1457         }
1458
1459         if (!pipe_ctx_old->stream) {
1460                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1461                                 pipe_ctx->stream_res.tg)) {
1462                         BREAK_TO_DEBUGGER();
1463                         return DC_ERROR_UNEXPECTED;
1464                 }
1465         }
1466
1467         return DC_OK;
1468 }
1469
1470 static enum dc_status apply_single_controller_ctx_to_hw(
1471                 struct pipe_ctx *pipe_ctx,
1472                 struct dc_state *context,
1473                 struct dc *dc)
1474 {
1475         struct dc_stream_state *stream = pipe_ctx->stream;
1476         struct dc_link *link = stream->link;
1477         struct drr_params params = {0};
1478         unsigned int event_triggers = 0;
1479         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1480         struct dce_hwseq *hws = dc->hwseq;
1481         const struct link_hwss *link_hwss = get_link_hwss(
1482                         link, &pipe_ctx->link_res);
1483
1484
1485         if (hws->funcs.disable_stream_gating) {
1486                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1487         }
1488
1489         if (pipe_ctx->stream_res.audio != NULL) {
1490                 struct audio_output audio_output;
1491
1492                 build_audio_output(context, pipe_ctx, &audio_output);
1493
1494                 link_hwss->setup_audio_output(pipe_ctx, &audio_output,
1495                                 pipe_ctx->stream_res.audio->inst);
1496
1497                 pipe_ctx->stream_res.audio->funcs->az_configure(
1498                                 pipe_ctx->stream_res.audio,
1499                                 pipe_ctx->stream->signal,
1500                                 &audio_output.crtc_info,
1501                                 &pipe_ctx->stream->audio_info);
1502         }
1503
1504         /* make sure no pipes syncd to the pipe being enabled */
1505         if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1506                 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1507
1508         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1509                 pipe_ctx->stream_res.opp,
1510                 &stream->bit_depth_params,
1511                 &stream->clamping);
1512
1513         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1514                         pipe_ctx->stream_res.opp,
1515                         COLOR_SPACE_YCBCR601,
1516                         stream->timing.display_color_depth,
1517                         stream->signal);
1518
1519         while (odm_pipe) {
1520                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1521                                 odm_pipe->stream_res.opp,
1522                                 COLOR_SPACE_YCBCR601,
1523                                 stream->timing.display_color_depth,
1524                                 stream->signal);
1525
1526                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1527                                 odm_pipe->stream_res.opp,
1528                                 &stream->bit_depth_params,
1529                                 &stream->clamping);
1530                 odm_pipe = odm_pipe->next_odm_pipe;
1531         }
1532
1533         /* DCN3.1 FPGA Workaround
1534          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1535          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1536          * function core_link_enable_stream
1537          */
1538         if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))
1539                 /*  */
1540                 /* Do not touch stream timing on seamless boot optimization. */
1541                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1542                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1543
1544         if (hws->funcs.setup_vupdate_interrupt)
1545                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1546
1547         params.vertical_total_min = stream->adjust.v_total_min;
1548         params.vertical_total_max = stream->adjust.v_total_max;
1549         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1550                 pipe_ctx->stream_res.tg->funcs->set_drr(
1551                         pipe_ctx->stream_res.tg, &params);
1552
1553         // DRR should set trigger event to monitor surface update event
1554         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1555                 event_triggers = 0x80;
1556         /* Event triggers and num frames initialized for DRR, but can be
1557          * later updated for PSR use. Note DRR trigger events are generated
1558          * regardless of whether num frames met.
1559          */
1560         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1561                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1562                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1563
1564         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1565                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1566                         pipe_ctx->stream_res.stream_enc,
1567                         pipe_ctx->stream_res.tg->inst);
1568
1569         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1570                 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1571
1572         if (!stream->dpms_off)
1573                 dc->link_srv->set_dpms_on(context, pipe_ctx);
1574
1575         /* DCN3.1 FPGA Workaround
1576          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1577          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1578          * function core_link_enable_stream
1579          */
1580         if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1581                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1582                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1583         }
1584
1585         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
1586
1587         /* Phantom and main stream share the same link (because the stream
1588          * is constructed with the same sink). Make sure not to override
1589          * and link programming on the main.
1590          */
1591         if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1592                 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1593                 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
1594         }
1595         return DC_OK;
1596 }
1597
1598 /******************************************************************************/
1599
1600 static void power_down_encoders(struct dc *dc)
1601 {
1602         int i;
1603
1604         for (i = 0; i < dc->link_count; i++) {
1605                 enum signal_type signal = dc->links[i]->connector_signal;
1606
1607                 dc->link_srv->blank_dp_stream(dc->links[i], false);
1608
1609                 if (signal != SIGNAL_TYPE_EDP)
1610                         signal = SIGNAL_TYPE_NONE;
1611
1612                 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1613                         dc->links[i]->link_enc->funcs->disable_output(
1614                                         dc->links[i]->link_enc, signal);
1615
1616                 dc->links[i]->link_status.link_active = false;
1617                 memset(&dc->links[i]->cur_link_settings, 0,
1618                                 sizeof(dc->links[i]->cur_link_settings));
1619         }
1620 }
1621
1622 static void power_down_controllers(struct dc *dc)
1623 {
1624         int i;
1625
1626         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1627                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1628                                 dc->res_pool->timing_generators[i]);
1629         }
1630 }
1631
1632 static void power_down_clock_sources(struct dc *dc)
1633 {
1634         int i;
1635
1636         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1637                 dc->res_pool->dp_clock_source) == false)
1638                 dm_error("Failed to power down pll! (dp clk src)\n");
1639
1640         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1641                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1642                                 dc->res_pool->clock_sources[i]) == false)
1643                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1644         }
1645 }
1646
1647 static void power_down_all_hw_blocks(struct dc *dc)
1648 {
1649         power_down_encoders(dc);
1650
1651         power_down_controllers(dc);
1652
1653         power_down_clock_sources(dc);
1654
1655         if (dc->fbc_compressor)
1656                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1657 }
1658
1659 static void disable_vga_and_power_gate_all_controllers(
1660                 struct dc *dc)
1661 {
1662         int i;
1663         struct timing_generator *tg;
1664         struct dc_context *ctx = dc->ctx;
1665
1666         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1667                 tg = dc->res_pool->timing_generators[i];
1668
1669                 if (tg->funcs->disable_vga)
1670                         tg->funcs->disable_vga(tg);
1671         }
1672         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1673                 /* Enable CLOCK gating for each pipe BEFORE controller
1674                  * powergating. */
1675                 enable_display_pipe_clock_gating(ctx,
1676                                 true);
1677
1678                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1679                 dc->hwss.disable_plane(dc,
1680                         &dc->current_state->res_ctx.pipe_ctx[i]);
1681         }
1682 }
1683
1684
1685 static void get_edp_streams(struct dc_state *context,
1686                 struct dc_stream_state **edp_streams,
1687                 int *edp_stream_num)
1688 {
1689         int i;
1690
1691         *edp_stream_num = 0;
1692         for (i = 0; i < context->stream_count; i++) {
1693                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1694                         edp_streams[*edp_stream_num] = context->streams[i];
1695                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1696                                 return;
1697                 }
1698         }
1699 }
1700
1701 static void get_edp_links_with_sink(
1702                 struct dc *dc,
1703                 struct dc_link **edp_links_with_sink,
1704                 int *edp_with_sink_num)
1705 {
1706         int i;
1707
1708         /* check if there is an eDP panel not in use */
1709         *edp_with_sink_num = 0;
1710         for (i = 0; i < dc->link_count; i++) {
1711                 if (dc->links[i]->local_sink &&
1712                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1713                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1714                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1715                                 return;
1716                 }
1717         }
1718 }
1719
1720 /*
1721  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1722  *  1. Power down all DC HW blocks
1723  *  2. Disable VGA engine on all controllers
1724  *  3. Enable power gating for controller
1725  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1726  */
1727 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1728 {
1729         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1730         struct dc_link *edp_links[MAX_NUM_EDP];
1731         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1732         struct dc_link *edp_link_with_sink = NULL;
1733         struct dc_link *edp_link = NULL;
1734         struct dce_hwseq *hws = dc->hwseq;
1735         int edp_with_sink_num;
1736         int edp_num;
1737         int edp_stream_num;
1738         int i;
1739         bool can_apply_edp_fast_boot = false;
1740         bool can_apply_seamless_boot = false;
1741         bool keep_edp_vdd_on = false;
1742         DC_LOGGER_INIT();
1743
1744
1745         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1746         dc_get_edp_links(dc, edp_links, &edp_num);
1747
1748         if (hws->funcs.init_pipes)
1749                 hws->funcs.init_pipes(dc, context);
1750
1751         get_edp_streams(context, edp_streams, &edp_stream_num);
1752
1753         // Check fastboot support, disable on DCE8 because of blank screens
1754         if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1755                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1756                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1757                 for (i = 0; i < edp_num; i++) {
1758                         edp_link = edp_links[i];
1759                         if (edp_link != edp_streams[0]->link)
1760                                 continue;
1761                         // enable fastboot if backend is enabled on eDP
1762                         if (edp_link->link_enc->funcs->is_dig_enabled &&
1763                             edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1764                             edp_link->link_status.link_active) {
1765                                 struct dc_stream_state *edp_stream = edp_streams[0];
1766
1767                                 can_apply_edp_fast_boot = dc_validate_boot_timing(dc,
1768                                         edp_stream->sink, &edp_stream->timing);
1769                                 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1770                                 if (can_apply_edp_fast_boot)
1771                                         DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1772
1773                                 break;
1774                         }
1775                 }
1776                 // We are trying to enable eDP, don't power down VDD
1777                 if (can_apply_edp_fast_boot)
1778                         keep_edp_vdd_on = true;
1779         }
1780
1781         // Check seamless boot support
1782         for (i = 0; i < context->stream_count; i++) {
1783                 if (context->streams[i]->apply_seamless_boot_optimization) {
1784                         can_apply_seamless_boot = true;
1785                         break;
1786                 }
1787         }
1788
1789         /* eDP should not have stream in resume from S4 and so even with VBios post
1790          * it should get turned off
1791          */
1792         if (edp_with_sink_num)
1793                 edp_link_with_sink = edp_links_with_sink[0];
1794
1795         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1796                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1797                         /*turn off backlight before DP_blank and encoder powered down*/
1798                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1799                 }
1800                 /*resume from S3, no vbios posting, no need to power down again*/
1801                 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1802
1803                 power_down_all_hw_blocks(dc);
1804                 disable_vga_and_power_gate_all_controllers(dc);
1805                 if (edp_link_with_sink && !keep_edp_vdd_on)
1806                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1807                 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1808         }
1809         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1810 }
1811
1812 static uint32_t compute_pstate_blackout_duration(
1813         struct bw_fixed blackout_duration,
1814         const struct dc_stream_state *stream)
1815 {
1816         uint32_t total_dest_line_time_ns;
1817         uint32_t pstate_blackout_duration_ns;
1818
1819         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1820
1821         total_dest_line_time_ns = 1000000UL *
1822                 (stream->timing.h_total * 10) /
1823                 stream->timing.pix_clk_100hz +
1824                 pstate_blackout_duration_ns;
1825
1826         return total_dest_line_time_ns;
1827 }
1828
1829 static void dce110_set_displaymarks(
1830         const struct dc *dc,
1831         struct dc_state *context)
1832 {
1833         uint8_t i, num_pipes;
1834         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1835
1836         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1837                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1838                 uint32_t total_dest_line_time_ns;
1839
1840                 if (pipe_ctx->stream == NULL)
1841                         continue;
1842
1843                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1844                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1845                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1846                         pipe_ctx->plane_res.mi,
1847                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1848                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1849                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1850                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1851                         total_dest_line_time_ns);
1852                 if (i == underlay_idx) {
1853                         num_pipes++;
1854                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1855                                 pipe_ctx->plane_res.mi,
1856                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1857                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1858                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1859                                 total_dest_line_time_ns);
1860                 }
1861                 num_pipes++;
1862         }
1863 }
1864
1865 void dce110_set_safe_displaymarks(
1866                 struct resource_context *res_ctx,
1867                 const struct resource_pool *pool)
1868 {
1869         int i;
1870         int underlay_idx = pool->underlay_pipe_index;
1871         struct dce_watermarks max_marks = {
1872                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1873         struct dce_watermarks nbp_marks = {
1874                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1875         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1876
1877         for (i = 0; i < MAX_PIPES; i++) {
1878                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1879                         continue;
1880
1881                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1882                                 res_ctx->pipe_ctx[i].plane_res.mi,
1883                                 nbp_marks,
1884                                 max_marks,
1885                                 min_marks,
1886                                 max_marks,
1887                                 MAX_WATERMARK);
1888
1889                 if (i == underlay_idx)
1890                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1891                                 res_ctx->pipe_ctx[i].plane_res.mi,
1892                                 nbp_marks,
1893                                 max_marks,
1894                                 max_marks,
1895                                 MAX_WATERMARK);
1896
1897         }
1898 }
1899
1900 /*******************************************************************************
1901  * Public functions
1902  ******************************************************************************/
1903
1904 static void set_drr(struct pipe_ctx **pipe_ctx,
1905                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1906 {
1907         int i = 0;
1908         struct drr_params params = {0};
1909         // DRR should set trigger event to monitor surface update event
1910         unsigned int event_triggers = 0x80;
1911         // Note DRR trigger events are generated regardless of whether num frames met.
1912         unsigned int num_frames = 2;
1913
1914         params.vertical_total_max = adjust.v_total_max;
1915         params.vertical_total_min = adjust.v_total_min;
1916
1917         /* TODO: If multiple pipes are to be supported, you need
1918          * some GSL stuff. Static screen triggers may be programmed differently
1919          * as well.
1920          */
1921         for (i = 0; i < num_pipes; i++) {
1922                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1923                         pipe_ctx[i]->stream_res.tg, &params);
1924
1925                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1926                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1927                                         pipe_ctx[i]->stream_res.tg,
1928                                         event_triggers, num_frames);
1929         }
1930 }
1931
1932 static void get_position(struct pipe_ctx **pipe_ctx,
1933                 int num_pipes,
1934                 struct crtc_position *position)
1935 {
1936         int i = 0;
1937
1938         /* TODO: handle pipes > 1
1939          */
1940         for (i = 0; i < num_pipes; i++)
1941                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1942 }
1943
1944 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1945                 int num_pipes, const struct dc_static_screen_params *params)
1946 {
1947         unsigned int i;
1948         unsigned int triggers = 0;
1949
1950         if (params->triggers.overlay_update)
1951                 triggers |= 0x100;
1952         if (params->triggers.surface_update)
1953                 triggers |= 0x80;
1954         if (params->triggers.cursor_update)
1955                 triggers |= 0x2;
1956         if (params->triggers.force_trigger)
1957                 triggers |= 0x1;
1958
1959         if (num_pipes) {
1960                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1961
1962                 if (dc->fbc_compressor)
1963                         triggers |= 0x84;
1964         }
1965
1966         for (i = 0; i < num_pipes; i++)
1967                 pipe_ctx[i]->stream_res.tg->funcs->
1968                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1969                                         triggers, params->num_frames);
1970 }
1971
1972 /*
1973  *  Check if FBC can be enabled
1974  */
1975 static bool should_enable_fbc(struct dc *dc,
1976                 struct dc_state *context,
1977                 uint32_t *pipe_idx)
1978 {
1979         uint32_t i;
1980         struct pipe_ctx *pipe_ctx = NULL;
1981         struct resource_context *res_ctx = &context->res_ctx;
1982         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1983
1984
1985         ASSERT(dc->fbc_compressor);
1986
1987         /* FBC memory should be allocated */
1988         if (!dc->ctx->fbc_gpu_addr)
1989                 return false;
1990
1991         /* Only supports single display */
1992         if (context->stream_count != 1)
1993                 return false;
1994
1995         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1996                 if (res_ctx->pipe_ctx[i].stream) {
1997
1998                         pipe_ctx = &res_ctx->pipe_ctx[i];
1999
2000                         if (!pipe_ctx)
2001                                 continue;
2002
2003                         /* fbc not applicable on underlay pipe */
2004                         if (pipe_ctx->pipe_idx != underlay_idx) {
2005                                 *pipe_idx = i;
2006                                 break;
2007                         }
2008                 }
2009         }
2010
2011         if (i == dc->res_pool->pipe_count)
2012                 return false;
2013
2014         if (!pipe_ctx->stream->link)
2015                 return false;
2016
2017         /* Only supports eDP */
2018         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2019                 return false;
2020
2021         /* PSR should not be enabled */
2022         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2023                 return false;
2024
2025         /* Replay should not be enabled */
2026         if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)
2027                 return false;
2028
2029         /* Nothing to compress */
2030         if (!pipe_ctx->plane_state)
2031                 return false;
2032
2033         /* Only for non-linear tiling */
2034         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2035                 return false;
2036
2037         return true;
2038 }
2039
2040 /*
2041  *  Enable FBC
2042  */
2043 static void enable_fbc(
2044                 struct dc *dc,
2045                 struct dc_state *context)
2046 {
2047         uint32_t pipe_idx = 0;
2048
2049         if (should_enable_fbc(dc, context, &pipe_idx)) {
2050                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2051                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2052                 struct compressor *compr = dc->fbc_compressor;
2053                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2054
2055                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2056                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2057                 params.inst = pipe_ctx->stream_res.tg->inst;
2058                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2059
2060                 compr->funcs->surface_address_and_pitch(compr, &params);
2061                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2062
2063                 compr->funcs->enable_fbc(compr, &params);
2064         }
2065 }
2066
2067 static void dce110_reset_hw_ctx_wrap(
2068                 struct dc *dc,
2069                 struct dc_state *context)
2070 {
2071         int i;
2072
2073         /* Reset old context */
2074         /* look up the targets that have been removed since last commit */
2075         for (i = 0; i < MAX_PIPES; i++) {
2076                 struct pipe_ctx *pipe_ctx_old =
2077                         &dc->current_state->res_ctx.pipe_ctx[i];
2078                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2079
2080                 /* Note: We need to disable output if clock sources change,
2081                  * since bios does optimization and doesn't apply if changing
2082                  * PHY when not already disabled.
2083                  */
2084
2085                 /* Skip underlay pipe since it will be handled in commit surface*/
2086                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2087                         continue;
2088
2089                 if (!pipe_ctx->stream ||
2090                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2091                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2092
2093                         /* Disable if new stream is null. O/w, if stream is
2094                          * disabled already, no need to disable again.
2095                          */
2096                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2097                                 dc->link_srv->set_dpms_off(pipe_ctx_old);
2098
2099                                 /* free acquired resources*/
2100                                 if (pipe_ctx_old->stream_res.audio) {
2101                                         /*disable az_endpoint*/
2102                                         pipe_ctx_old->stream_res.audio->funcs->
2103                                                         az_disable(pipe_ctx_old->stream_res.audio);
2104
2105                                         /*free audio*/
2106                                         if (dc->caps.dynamic_audio == true) {
2107                                                 /*we have to dynamic arbitrate the audio endpoints*/
2108                                                 /*we free the resource, need reset is_audio_acquired*/
2109                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2110                                                                 pipe_ctx_old->stream_res.audio, false);
2111                                                 pipe_ctx_old->stream_res.audio = NULL;
2112                                         }
2113                                 }
2114                         }
2115
2116                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2117                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2118                                 dm_error("DC: failed to blank crtc!\n");
2119                                 BREAK_TO_DEBUGGER();
2120                         }
2121                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2122                         pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
2123                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2124                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2125
2126                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2127                                                                                 dc->res_pool,
2128                                                                                 old_clk))
2129                                 old_clk->funcs->cs_power_down(old_clk);
2130
2131                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2132
2133                         pipe_ctx_old->stream = NULL;
2134                 }
2135         }
2136 }
2137
2138 static void dce110_setup_audio_dto(
2139                 struct dc *dc,
2140                 struct dc_state *context)
2141 {
2142         int i;
2143
2144         /* program audio wall clock. use HDMI as clock source if HDMI
2145          * audio active. Otherwise, use DP as clock source
2146          * first, loop to find any HDMI audio, if not, loop find DP audio
2147          */
2148         /* Setup audio rate clock source */
2149         /* Issue:
2150         * Audio lag happened on DP monitor when unplug a HDMI monitor
2151         *
2152         * Cause:
2153         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2154         * is set to either dto0 or dto1, audio should work fine.
2155         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2156         * set to dto0 will cause audio lag.
2157         *
2158         * Solution:
2159         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2160         * find first available pipe with audio, setup audio wall DTO per topology
2161         * instead of per pipe.
2162         */
2163         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2164                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2165
2166                 if (pipe_ctx->stream == NULL)
2167                         continue;
2168
2169                 if (pipe_ctx->top_pipe)
2170                         continue;
2171                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2172                         continue;
2173                 if (pipe_ctx->stream_res.audio != NULL) {
2174                         struct audio_output audio_output;
2175
2176                         build_audio_output(context, pipe_ctx, &audio_output);
2177
2178                         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2179                                 struct dtbclk_dto_params dto_params = {0};
2180
2181                                 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2182                                         dc->res_pool->dccg, &dto_params);
2183
2184                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2185                                                 pipe_ctx->stream_res.audio,
2186                                                 pipe_ctx->stream->signal,
2187                                                 &audio_output.crtc_info,
2188                                                 &audio_output.pll_info);
2189                         } else
2190                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2191                                         pipe_ctx->stream_res.audio,
2192                                         pipe_ctx->stream->signal,
2193                                         &audio_output.crtc_info,
2194                                         &audio_output.pll_info);
2195                         break;
2196                 }
2197         }
2198
2199         /* no HDMI audio is found, try DP audio */
2200         if (i == dc->res_pool->pipe_count) {
2201                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2202                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2203
2204                         if (pipe_ctx->stream == NULL)
2205                                 continue;
2206
2207                         if (pipe_ctx->top_pipe)
2208                                 continue;
2209
2210                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2211                                 continue;
2212
2213                         if (pipe_ctx->stream_res.audio != NULL) {
2214                                 struct audio_output audio_output;
2215
2216                                 build_audio_output(context, pipe_ctx, &audio_output);
2217
2218                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2219                                         pipe_ctx->stream_res.audio,
2220                                         pipe_ctx->stream->signal,
2221                                         &audio_output.crtc_info,
2222                                         &audio_output.pll_info);
2223                                 break;
2224                         }
2225                 }
2226         }
2227 }
2228
2229 enum dc_status dce110_apply_ctx_to_hw(
2230                 struct dc *dc,
2231                 struct dc_state *context)
2232 {
2233         struct dce_hwseq *hws = dc->hwseq;
2234         struct dc_bios *dcb = dc->ctx->dc_bios;
2235         enum dc_status status;
2236         int i;
2237
2238         /* reset syncd pipes from disabled pipes */
2239         if (dc->config.use_pipe_ctx_sync_logic)
2240                 reset_syncd_pipes_from_disabled_pipes(dc, context);
2241
2242         /* Reset old context */
2243         /* look up the targets that have been removed since last commit */
2244         hws->funcs.reset_hw_ctx_wrap(dc, context);
2245
2246         /* Skip applying if no targets */
2247         if (context->stream_count <= 0)
2248                 return DC_OK;
2249
2250         /* Apply new context */
2251         dcb->funcs->set_scratch_critical_state(dcb, true);
2252
2253         /* below is for real asic only */
2254         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2255                 struct pipe_ctx *pipe_ctx_old =
2256                                         &dc->current_state->res_ctx.pipe_ctx[i];
2257                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2258
2259                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2260                         continue;
2261
2262                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2263                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2264                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2265                                                 pipe_ctx->clock_source, i);
2266                         continue;
2267                 }
2268
2269                 hws->funcs.enable_display_power_gating(
2270                                 dc, i, dc->ctx->dc_bios,
2271                                 PIPE_GATING_CONTROL_DISABLE);
2272         }
2273
2274         if (dc->fbc_compressor)
2275                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2276
2277         dce110_setup_audio_dto(dc, context);
2278
2279         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2280                 struct pipe_ctx *pipe_ctx_old =
2281                                         &dc->current_state->res_ctx.pipe_ctx[i];
2282                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2283
2284                 if (pipe_ctx->stream == NULL)
2285                         continue;
2286
2287                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2288                         pipe_ctx->stream->link->link_state_valid) {
2289                         continue;
2290                 }
2291
2292                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2293                         continue;
2294
2295                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2296                         continue;
2297
2298                 status = apply_single_controller_ctx_to_hw(
2299                                 pipe_ctx,
2300                                 context,
2301                                 dc);
2302
2303                 if (DC_OK != status)
2304                         return status;
2305
2306 #ifdef CONFIG_DRM_AMD_DC_FP
2307                 if (hws->funcs.resync_fifo_dccg_dio)
2308                         hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
2309 #endif
2310         }
2311
2312         if (dc->fbc_compressor)
2313                 enable_fbc(dc, dc->current_state);
2314
2315         dcb->funcs->set_scratch_critical_state(dcb, false);
2316
2317         return DC_OK;
2318 }
2319
2320 /*******************************************************************************
2321  * Front End programming
2322  ******************************************************************************/
2323 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2324 {
2325         struct default_adjustment default_adjust = { 0 };
2326
2327         default_adjust.force_hw_default = false;
2328         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2329         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2330         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2331         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2332
2333         /* display color depth */
2334         default_adjust.color_depth =
2335                 pipe_ctx->stream->timing.display_color_depth;
2336
2337         /* Lb color depth */
2338         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2339
2340         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2341                                         pipe_ctx->plane_res.xfm, &default_adjust);
2342 }
2343
2344
2345 /*******************************************************************************
2346  * In order to turn on/off specific surface we will program
2347  * Blender + CRTC
2348  *
2349  * In case that we have two surfaces and they have a different visibility
2350  * we can't turn off the CRTC since it will turn off the entire display
2351  *
2352  * |----------------------------------------------- |
2353  * |bottom pipe|curr pipe  |              |         |
2354  * |Surface    |Surface    | Blender      |  CRCT   |
2355  * |visibility |visibility | Configuration|         |
2356  * |------------------------------------------------|
2357  * |   off     |    off    | CURRENT_PIPE | blank   |
2358  * |   off     |    on     | CURRENT_PIPE | unblank |
2359  * |   on      |    off    | OTHER_PIPE   | unblank |
2360  * |   on      |    on     | BLENDING     | unblank |
2361  * -------------------------------------------------|
2362  *
2363  ******************************************************************************/
2364 static void program_surface_visibility(const struct dc *dc,
2365                 struct pipe_ctx *pipe_ctx)
2366 {
2367         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2368         bool blank_target = false;
2369
2370         if (pipe_ctx->bottom_pipe) {
2371
2372                 /* For now we are supporting only two pipes */
2373                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2374
2375                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2376                         if (pipe_ctx->plane_state->visible)
2377                                 blender_mode = BLND_MODE_BLENDING;
2378                         else
2379                                 blender_mode = BLND_MODE_OTHER_PIPE;
2380
2381                 } else if (!pipe_ctx->plane_state->visible)
2382                         blank_target = true;
2383
2384         } else if (!pipe_ctx->plane_state->visible)
2385                 blank_target = true;
2386
2387         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2388         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2389
2390 }
2391
2392 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2393 {
2394         int i = 0;
2395         struct xfm_grph_csc_adjustment adjust;
2396         memset(&adjust, 0, sizeof(adjust));
2397         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2398
2399
2400         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2401                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2402
2403                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2404                         adjust.temperature_matrix[i] =
2405                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2406         }
2407
2408         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2409 }
2410 static void update_plane_addr(const struct dc *dc,
2411                 struct pipe_ctx *pipe_ctx)
2412 {
2413         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2414
2415         if (plane_state == NULL)
2416                 return;
2417
2418         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2419                         pipe_ctx->plane_res.mi,
2420                         &plane_state->address,
2421                         plane_state->flip_immediate);
2422
2423         plane_state->status.requested_address = plane_state->address;
2424 }
2425
2426 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2427 {
2428         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2429
2430         if (plane_state == NULL)
2431                 return;
2432
2433         plane_state->status.is_flip_pending =
2434                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2435                                         pipe_ctx->plane_res.mi);
2436
2437         if (plane_state->status.is_flip_pending && !plane_state->visible)
2438                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2439
2440         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2441         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2442                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2443                 plane_state->status.is_right_eye =\
2444                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2445         }
2446 }
2447
2448 void dce110_power_down(struct dc *dc)
2449 {
2450         power_down_all_hw_blocks(dc);
2451         disable_vga_and_power_gate_all_controllers(dc);
2452 }
2453
2454 static bool wait_for_reset_trigger_to_occur(
2455         struct dc_context *dc_ctx,
2456         struct timing_generator *tg)
2457 {
2458         bool rc = false;
2459
2460         /* To avoid endless loop we wait at most
2461          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2462         const uint32_t frames_to_wait_on_triggered_reset = 10;
2463         uint32_t i;
2464
2465         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2466
2467                 if (!tg->funcs->is_counter_moving(tg)) {
2468                         DC_ERROR("TG counter is not moving!\n");
2469                         break;
2470                 }
2471
2472                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2473                         rc = true;
2474                         /* usually occurs at i=1 */
2475                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2476                                         i);
2477                         break;
2478                 }
2479
2480                 /* Wait for one frame. */
2481                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2482                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2483         }
2484
2485         if (false == rc)
2486                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2487
2488         return rc;
2489 }
2490
2491 /* Enable timing synchronization for a group of Timing Generators. */
2492 static void dce110_enable_timing_synchronization(
2493                 struct dc *dc,
2494                 int group_index,
2495                 int group_size,
2496                 struct pipe_ctx *grouped_pipes[])
2497 {
2498         struct dc_context *dc_ctx = dc->ctx;
2499         struct dcp_gsl_params gsl_params = { 0 };
2500         int i;
2501
2502         DC_SYNC_INFO("GSL: Setting-up...\n");
2503
2504         /* Designate a single TG in the group as a master.
2505          * Since HW doesn't care which one, we always assign
2506          * the 1st one in the group. */
2507         gsl_params.gsl_group = 0;
2508         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2509
2510         for (i = 0; i < group_size; i++)
2511                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2512                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2513
2514         /* Reset slave controllers on master VSync */
2515         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2516
2517         for (i = 1 /* skip the master */; i < group_size; i++)
2518                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2519                                 grouped_pipes[i]->stream_res.tg,
2520                                 gsl_params.gsl_group);
2521
2522         for (i = 1 /* skip the master */; i < group_size; i++) {
2523                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2524                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2525                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2526                                 grouped_pipes[i]->stream_res.tg);
2527         }
2528
2529         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2530          * is that the sync'ed displays will not drift out of sync over time*/
2531         DC_SYNC_INFO("GSL: Restoring register states.\n");
2532         for (i = 0; i < group_size; i++)
2533                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2534
2535         DC_SYNC_INFO("GSL: Set-up complete.\n");
2536 }
2537
2538 static void dce110_enable_per_frame_crtc_position_reset(
2539                 struct dc *dc,
2540                 int group_size,
2541                 struct pipe_ctx *grouped_pipes[])
2542 {
2543         struct dc_context *dc_ctx = dc->ctx;
2544         struct dcp_gsl_params gsl_params = { 0 };
2545         int i;
2546
2547         gsl_params.gsl_group = 0;
2548         gsl_params.gsl_master = 0;
2549
2550         for (i = 0; i < group_size; i++)
2551                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2552                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2553
2554         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2555
2556         for (i = 1; i < group_size; i++)
2557                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2558                                 grouped_pipes[i]->stream_res.tg,
2559                                 gsl_params.gsl_master,
2560                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2561
2562         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2563         for (i = 1; i < group_size; i++)
2564                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2565
2566         for (i = 0; i < group_size; i++)
2567                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2568
2569 }
2570
2571 static void init_pipes(struct dc *dc, struct dc_state *context)
2572 {
2573         // Do nothing
2574 }
2575
2576 static void init_hw(struct dc *dc)
2577 {
2578         int i;
2579         struct dc_bios *bp;
2580         struct transform *xfm;
2581         struct abm *abm;
2582         struct dmcu *dmcu;
2583         struct dce_hwseq *hws = dc->hwseq;
2584         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2585
2586         bp = dc->ctx->dc_bios;
2587         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2588                 xfm = dc->res_pool->transforms[i];
2589                 xfm->funcs->transform_reset(xfm);
2590
2591                 hws->funcs.enable_display_power_gating(
2592                                 dc, i, bp,
2593                                 PIPE_GATING_CONTROL_INIT);
2594                 hws->funcs.enable_display_power_gating(
2595                                 dc, i, bp,
2596                                 PIPE_GATING_CONTROL_DISABLE);
2597                 hws->funcs.enable_display_pipe_clock_gating(
2598                         dc->ctx,
2599                         true);
2600         }
2601
2602         dce_clock_gating_power_up(dc->hwseq, false);
2603         /***************************************/
2604
2605         for (i = 0; i < dc->link_count; i++) {
2606                 /****************************************/
2607                 /* Power up AND update implementation according to the
2608                  * required signal (which may be different from the
2609                  * default signal on connector). */
2610                 struct dc_link *link = dc->links[i];
2611
2612                 link->link_enc->funcs->hw_init(link->link_enc);
2613         }
2614
2615         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2616                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2617
2618                 tg->funcs->disable_vga(tg);
2619
2620                 /* Blank controller using driver code instead of
2621                  * command table. */
2622                 tg->funcs->set_blank(tg, true);
2623                 hwss_wait_for_blank_complete(tg);
2624         }
2625
2626         for (i = 0; i < dc->res_pool->audio_count; i++) {
2627                 struct audio *audio = dc->res_pool->audios[i];
2628                 audio->funcs->hw_init(audio);
2629         }
2630
2631         for (i = 0; i < dc->link_count; i++) {
2632                 struct dc_link *link = dc->links[i];
2633
2634                 if (link->panel_cntl)
2635                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2636         }
2637
2638         abm = dc->res_pool->abm;
2639         if (abm != NULL)
2640                 abm->funcs->abm_init(abm, backlight);
2641
2642         dmcu = dc->res_pool->dmcu;
2643         if (dmcu != NULL && abm != NULL)
2644                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2645
2646         if (dc->fbc_compressor)
2647                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2648
2649 }
2650
2651
2652 void dce110_prepare_bandwidth(
2653                 struct dc *dc,
2654                 struct dc_state *context)
2655 {
2656         struct clk_mgr *dccg = dc->clk_mgr;
2657
2658         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2659
2660         dccg->funcs->update_clocks(
2661                         dccg,
2662                         context,
2663                         false);
2664 }
2665
2666 void dce110_optimize_bandwidth(
2667                 struct dc *dc,
2668                 struct dc_state *context)
2669 {
2670         struct clk_mgr *dccg = dc->clk_mgr;
2671
2672         dce110_set_displaymarks(dc, context);
2673
2674         dccg->funcs->update_clocks(
2675                         dccg,
2676                         context,
2677                         true);
2678 }
2679
2680 static void dce110_program_front_end_for_pipe(
2681                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2682 {
2683         struct mem_input *mi = pipe_ctx->plane_res.mi;
2684         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2685         struct xfm_grph_csc_adjustment adjust;
2686         struct out_csc_color_matrix tbl_entry;
2687         unsigned int i;
2688         struct dce_hwseq *hws = dc->hwseq;
2689
2690         DC_LOGGER_INIT();
2691         memset(&tbl_entry, 0, sizeof(tbl_entry));
2692
2693         memset(&adjust, 0, sizeof(adjust));
2694         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2695
2696         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2697
2698         set_default_colors(pipe_ctx);
2699         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2700                         == true) {
2701                 tbl_entry.color_space =
2702                         pipe_ctx->stream->output_color_space;
2703
2704                 for (i = 0; i < 12; i++)
2705                         tbl_entry.regval[i] =
2706                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2707
2708                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2709                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2710         }
2711
2712         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2713                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2714
2715                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2716                         adjust.temperature_matrix[i] =
2717                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2718         }
2719
2720         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2721
2722         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
2723
2724         program_scaler(dc, pipe_ctx);
2725
2726         mi->funcs->mem_input_program_surface_config(
2727                         mi,
2728                         plane_state->format,
2729                         &plane_state->tiling_info,
2730                         &plane_state->plane_size,
2731                         plane_state->rotation,
2732                         NULL,
2733                         false);
2734         if (mi->funcs->set_blank)
2735                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2736
2737         if (dc->config.gpu_vm_support)
2738                 mi->funcs->mem_input_program_pte_vm(
2739                                 pipe_ctx->plane_res.mi,
2740                                 plane_state->format,
2741                                 &plane_state->tiling_info,
2742                                 plane_state->rotation);
2743
2744         /* Moved programming gamma from dc to hwss */
2745         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2746                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2747                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2748                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2749
2750         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2751                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2752
2753         DC_LOG_SURFACE(
2754                         "Pipe:%d %p: addr hi:0x%x, "
2755                         "addr low:0x%x, "
2756                         "src: %d, %d, %d,"
2757                         " %d; dst: %d, %d, %d, %d;"
2758                         "clip: %d, %d, %d, %d\n",
2759                         pipe_ctx->pipe_idx,
2760                         (void *) pipe_ctx->plane_state,
2761                         pipe_ctx->plane_state->address.grph.addr.high_part,
2762                         pipe_ctx->plane_state->address.grph.addr.low_part,
2763                         pipe_ctx->plane_state->src_rect.x,
2764                         pipe_ctx->plane_state->src_rect.y,
2765                         pipe_ctx->plane_state->src_rect.width,
2766                         pipe_ctx->plane_state->src_rect.height,
2767                         pipe_ctx->plane_state->dst_rect.x,
2768                         pipe_ctx->plane_state->dst_rect.y,
2769                         pipe_ctx->plane_state->dst_rect.width,
2770                         pipe_ctx->plane_state->dst_rect.height,
2771                         pipe_ctx->plane_state->clip_rect.x,
2772                         pipe_ctx->plane_state->clip_rect.y,
2773                         pipe_ctx->plane_state->clip_rect.width,
2774                         pipe_ctx->plane_state->clip_rect.height);
2775
2776         DC_LOG_SURFACE(
2777                         "Pipe %d: width, height, x, y\n"
2778                         "viewport:%d, %d, %d, %d\n"
2779                         "recout:  %d, %d, %d, %d\n",
2780                         pipe_ctx->pipe_idx,
2781                         pipe_ctx->plane_res.scl_data.viewport.width,
2782                         pipe_ctx->plane_res.scl_data.viewport.height,
2783                         pipe_ctx->plane_res.scl_data.viewport.x,
2784                         pipe_ctx->plane_res.scl_data.viewport.y,
2785                         pipe_ctx->plane_res.scl_data.recout.width,
2786                         pipe_ctx->plane_res.scl_data.recout.height,
2787                         pipe_ctx->plane_res.scl_data.recout.x,
2788                         pipe_ctx->plane_res.scl_data.recout.y);
2789 }
2790
2791 static void dce110_apply_ctx_for_surface(
2792                 struct dc *dc,
2793                 const struct dc_stream_state *stream,
2794                 int num_planes,
2795                 struct dc_state *context)
2796 {
2797         int i;
2798
2799         if (num_planes == 0)
2800                 return;
2801
2802         if (dc->fbc_compressor)
2803                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2804
2805         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2806                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2807
2808                 if (pipe_ctx->stream != stream)
2809                         continue;
2810
2811                 /* Need to allocate mem before program front end for Fiji */
2812                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2813                                 pipe_ctx->plane_res.mi,
2814                                 pipe_ctx->stream->timing.h_total,
2815                                 pipe_ctx->stream->timing.v_total,
2816                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2817                                 context->stream_count);
2818
2819                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2820
2821                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2822
2823                 program_surface_visibility(dc, pipe_ctx);
2824
2825         }
2826
2827         if (dc->fbc_compressor)
2828                 enable_fbc(dc, context);
2829 }
2830
2831 static void dce110_post_unlock_program_front_end(
2832                 struct dc *dc,
2833                 struct dc_state *context)
2834 {
2835 }
2836
2837 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2838 {
2839         struct dce_hwseq *hws = dc->hwseq;
2840         int fe_idx = pipe_ctx->plane_res.mi ?
2841                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2842
2843         /* Do not power down fe when stream is active on dce*/
2844         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2845                 return;
2846
2847         hws->funcs.enable_display_power_gating(
2848                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2849
2850         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2851                                 dc->res_pool->transforms[fe_idx]);
2852 }
2853
2854 static void dce110_wait_for_mpcc_disconnect(
2855                 struct dc *dc,
2856                 struct resource_pool *res_pool,
2857                 struct pipe_ctx *pipe_ctx)
2858 {
2859         /* do nothing*/
2860 }
2861
2862 static void program_output_csc(struct dc *dc,
2863                 struct pipe_ctx *pipe_ctx,
2864                 enum dc_color_space colorspace,
2865                 uint16_t *matrix,
2866                 int opp_id)
2867 {
2868         int i;
2869         struct out_csc_color_matrix tbl_entry;
2870
2871         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2872                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2873
2874                 for (i = 0; i < 12; i++)
2875                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2876
2877                 tbl_entry.color_space = color_space;
2878
2879                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2880                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2881         }
2882 }
2883
2884 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2885 {
2886         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2887         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2888         struct mem_input *mi = pipe_ctx->plane_res.mi;
2889         struct dc_cursor_mi_param param = {
2890                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2891                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2892                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2893                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2894                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2895                 .rotation = pipe_ctx->plane_state->rotation,
2896                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2897         };
2898
2899         /**
2900          * If the cursor's source viewport is clipped then we need to
2901          * translate the cursor to appear in the correct position on
2902          * the screen.
2903          *
2904          * This translation isn't affected by scaling so it needs to be
2905          * done *after* we adjust the position for the scale factor.
2906          *
2907          * This is only done by opt-in for now since there are still
2908          * some usecases like tiled display that might enable the
2909          * cursor on both streams while expecting dc to clip it.
2910          */
2911         if (pos_cpy.translate_by_source) {
2912                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2913                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2914         }
2915
2916         if (pipe_ctx->plane_state->address.type
2917                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2918                 pos_cpy.enable = false;
2919
2920         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2921                 pos_cpy.enable = false;
2922
2923         if (ipp->funcs->ipp_cursor_set_position)
2924                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2925         if (mi->funcs->set_cursor_position)
2926                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2927 }
2928
2929 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2930 {
2931         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2932
2933         if (pipe_ctx->plane_res.ipp &&
2934             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2935                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2936                                 pipe_ctx->plane_res.ipp, attributes);
2937
2938         if (pipe_ctx->plane_res.mi &&
2939             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2940                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2941                                 pipe_ctx->plane_res.mi, attributes);
2942
2943         if (pipe_ctx->plane_res.xfm &&
2944             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2945                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2946                                 pipe_ctx->plane_res.xfm, attributes);
2947 }
2948
2949 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
2950                 uint32_t backlight_pwm_u16_16,
2951                 uint32_t frame_ramp)
2952 {
2953         struct dc_link *link = pipe_ctx->stream->link;
2954         struct dc  *dc = link->ctx->dc;
2955         struct abm *abm = pipe_ctx->stream_res.abm;
2956         struct panel_cntl *panel_cntl = link->panel_cntl;
2957         struct dmcu *dmcu = dc->res_pool->dmcu;
2958         bool fw_set_brightness = true;
2959         /* DMCU -1 for all controller id values,
2960          * therefore +1 here
2961          */
2962         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
2963
2964         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2965                 return false;
2966
2967         if (dmcu)
2968                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2969
2970         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
2971                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
2972         else
2973                 abm->funcs->set_backlight_level_pwm(
2974                                 abm,
2975                                 backlight_pwm_u16_16,
2976                                 frame_ramp,
2977                                 controller_id,
2978                                 link->panel_cntl->inst);
2979
2980         return true;
2981 }
2982
2983 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
2984 {
2985         struct abm *abm = pipe_ctx->stream_res.abm;
2986         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2987
2988         if (abm)
2989                 abm->funcs->set_abm_immediate_disable(abm,
2990                                 pipe_ctx->stream->link->panel_cntl->inst);
2991
2992         if (panel_cntl)
2993                 panel_cntl->funcs->store_backlight_level(panel_cntl);
2994 }
2995
2996 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
2997 {
2998         struct abm *abm = pipe_ctx->stream_res.abm;
2999         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3000         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3001
3002         if (abm && panel_cntl)
3003                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3004 }
3005
3006 void dce110_enable_lvds_link_output(struct dc_link *link,
3007                 const struct link_resource *link_res,
3008                 enum clock_source_id clock_source,
3009                 uint32_t pixel_clock)
3010 {
3011         link->link_enc->funcs->enable_lvds_output(
3012                         link->link_enc,
3013                         clock_source,
3014                         pixel_clock);
3015         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3016 }
3017
3018 void dce110_enable_tmds_link_output(struct dc_link *link,
3019                 const struct link_resource *link_res,
3020                 enum signal_type signal,
3021                 enum clock_source_id clock_source,
3022                 enum dc_color_depth color_depth,
3023                 uint32_t pixel_clock)
3024 {
3025         link->link_enc->funcs->enable_tmds_output(
3026                         link->link_enc,
3027                         clock_source,
3028                         color_depth,
3029                         signal,
3030                         pixel_clock);
3031         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3032 }
3033
3034 void dce110_enable_dp_link_output(
3035                 struct dc_link *link,
3036                 const struct link_resource *link_res,
3037                 enum signal_type signal,
3038                 enum clock_source_id clock_source,
3039                 const struct dc_link_settings *link_settings)
3040 {
3041         struct dc  *dc = link->ctx->dc;
3042         struct dmcu *dmcu = dc->res_pool->dmcu;
3043         struct pipe_ctx *pipes =
3044                         link->dc->current_state->res_ctx.pipe_ctx;
3045         struct clock_source *dp_cs =
3046                         link->dc->res_pool->dp_clock_source;
3047         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3048         unsigned int i;
3049
3050         /*
3051          * Add the logic to extract BOTH power up and power down sequences
3052          * from enable/disable link output and only call edp panel control
3053          * in enable_link_dp and disable_link_dp once.
3054          */
3055         if (link->connector_signal == SIGNAL_TYPE_EDP) {
3056                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
3057         }
3058
3059         /* If the current pixel clock source is not DTO(happens after
3060          * switching from HDMI passive dongle to DP on the same connector),
3061          * switch the pixel clock source to DTO.
3062          */
3063
3064         for (i = 0; i < MAX_PIPES; i++) {
3065                 if (pipes[i].stream != NULL &&
3066                                 pipes[i].stream->link == link) {
3067                         if (pipes[i].clock_source != NULL &&
3068                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
3069                                 pipes[i].clock_source = dp_cs;
3070                                 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
3071                                                 pipes[i].stream->timing.pix_clk_100hz;
3072                                 pipes[i].clock_source->funcs->program_pix_clk(
3073                                                 pipes[i].clock_source,
3074                                                 &pipes[i].stream_res.pix_clk_params,
3075                                                 dc->link_srv->dp_get_encoding_format(link_settings),
3076                                                 &pipes[i].pll_settings);
3077                         }
3078                 }
3079         }
3080
3081         if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
3082                 if (dc->clk_mgr->funcs->notify_link_rate_change)
3083                         dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
3084         }
3085
3086         if (dmcu != NULL && dmcu->funcs->lock_phy)
3087                 dmcu->funcs->lock_phy(dmcu);
3088
3089         if (link_hwss->ext.enable_dp_link_output)
3090                 link_hwss->ext.enable_dp_link_output(link, link_res, signal,
3091                                 clock_source, link_settings);
3092
3093         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3094
3095         if (dmcu != NULL && dmcu->funcs->unlock_phy)
3096                 dmcu->funcs->unlock_phy(dmcu);
3097
3098         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
3099 }
3100
3101 void dce110_disable_link_output(struct dc_link *link,
3102                 const struct link_resource *link_res,
3103                 enum signal_type signal)
3104 {
3105         struct dc *dc = link->ctx->dc;
3106         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3107         struct dmcu *dmcu = dc->res_pool->dmcu;
3108
3109         if (signal == SIGNAL_TYPE_EDP &&
3110                         link->dc->hwss.edp_backlight_control)
3111                 link->dc->hwss.edp_backlight_control(link, false);
3112         else if (dmcu != NULL && dmcu->funcs->lock_phy)
3113                 dmcu->funcs->lock_phy(dmcu);
3114
3115         link_hwss->disable_link_output(link, link_res, signal);
3116         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
3117         /*
3118          * Add the logic to extract BOTH power up and power down sequences
3119          * from enable/disable link output and only call edp panel control
3120          * in enable_link_dp and disable_link_dp once.
3121          */
3122         if (dmcu != NULL && dmcu->funcs->lock_phy)
3123                 dmcu->funcs->unlock_phy(dmcu);
3124         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
3125 }
3126
3127 static const struct hw_sequencer_funcs dce110_funcs = {
3128         .program_gamut_remap = program_gamut_remap,
3129         .program_output_csc = program_output_csc,
3130         .init_hw = init_hw,
3131         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3132         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3133         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3134         .update_plane_addr = update_plane_addr,
3135         .update_pending_status = dce110_update_pending_status,
3136         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3137         .enable_timing_synchronization = dce110_enable_timing_synchronization,
3138         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3139         .update_info_frame = dce110_update_info_frame,
3140         .enable_stream = dce110_enable_stream,
3141         .disable_stream = dce110_disable_stream,
3142         .unblank_stream = dce110_unblank_stream,
3143         .blank_stream = dce110_blank_stream,
3144         .enable_audio_stream = dce110_enable_audio_stream,
3145         .disable_audio_stream = dce110_disable_audio_stream,
3146         .disable_plane = dce110_power_down_fe,
3147         .pipe_control_lock = dce_pipe_control_lock,
3148         .interdependent_update_lock = NULL,
3149         .cursor_lock = dce_pipe_control_lock,
3150         .prepare_bandwidth = dce110_prepare_bandwidth,
3151         .optimize_bandwidth = dce110_optimize_bandwidth,
3152         .set_drr = set_drr,
3153         .get_position = get_position,
3154         .set_static_screen_control = set_static_screen_control,
3155         .setup_stereo = NULL,
3156         .set_avmute = dce110_set_avmute,
3157         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3158         .edp_backlight_control = dce110_edp_backlight_control,
3159         .edp_power_control = dce110_edp_power_control,
3160         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3161         .set_cursor_position = dce110_set_cursor_position,
3162         .set_cursor_attribute = dce110_set_cursor_attribute,
3163         .set_backlight_level = dce110_set_backlight_level,
3164         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3165         .set_pipe = dce110_set_pipe,
3166         .enable_lvds_link_output = dce110_enable_lvds_link_output,
3167         .enable_tmds_link_output = dce110_enable_tmds_link_output,
3168         .enable_dp_link_output = dce110_enable_dp_link_output,
3169         .disable_link_output = dce110_disable_link_output,
3170 };
3171
3172 static const struct hwseq_private_funcs dce110_private_funcs = {
3173         .init_pipes = init_pipes,
3174         .update_plane_addr = update_plane_addr,
3175         .set_input_transfer_func = dce110_set_input_transfer_func,
3176         .set_output_transfer_func = dce110_set_output_transfer_func,
3177         .power_down = dce110_power_down,
3178         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3179         .enable_display_power_gating = dce110_enable_display_power_gating,
3180         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3181         .enable_stream_timing = dce110_enable_stream_timing,
3182         .disable_stream_gating = NULL,
3183         .enable_stream_gating = NULL,
3184         .edp_backlight_control = dce110_edp_backlight_control,
3185 };
3186
3187 void dce110_hw_sequencer_construct(struct dc *dc)
3188 {
3189         dc->hwss = dce110_funcs;
3190         dc->hwseq->funcs = dce110_private_funcs;
3191 }
3192