drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "reg_helper.h"
  27
  28 #include "core_types.h"
  29 #include "link_encoder.h"
  30 #include "dce_link_encoder.h"
  31 #include "stream_encoder.h"
  32 #include "i2caux_interface.h"
  33 #include "dc_bios_types.h"
  34
  35 #include "gpio_service_interface.h"
  36
  37 #include "dce/dce_11_0_d.h"
  38 #include "dce/dce_11_0_sh_mask.h"
  39 #include "dce/dce_11_0_enum.h"
  40
  41 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
  42 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
  43 #endif
  44
  45 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
  46 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
  47 #endif
  48
  49 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
  50 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK  0x10000000L
  51 #endif
  52
  53 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
  54 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT  0x1c
  55 #endif
  56
  57 #define CTX \
  58         enc110->base.ctx
  59
  60 #define REG(reg)\
  61         (enc110->link_regs->reg)
  62
  63 #define AUX_REG(reg)\
  64         (enc110->aux_regs->reg)
  65
  66 #define HPD_REG(reg)\
  67         (enc110->hpd_regs->reg)
  68
  69 #define DEFAULT_AUX_MAX_DATA_SIZE 16
  70 #define AUX_MAX_DEFER_WRITE_RETRY 20
  71 /*
  72  * @brief
  73  * Trigger Source Select
  74  * ASIC-dependent, actual values for register programming
  75  */
  76 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
  77 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
  78 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
  79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
  80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
  81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
  82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
  83
  84 /* all values are in milliseconds */
  85 /* For eDP, after power-up/power/down,
  86  * 300/500 msec max. delay from LCDVCC to black video generation */
  87 #define PANEL_POWER_UP_TIMEOUT 300
  88 #define PANEL_POWER_DOWN_TIMEOUT 500
  89 #define HPD_CHECK_INTERVAL 10
  90
  91 /* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
  92 #define TMDS_MIN_PIXEL_CLOCK 25000
  93 /* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
  94 #define TMDS_MAX_PIXEL_CLOCK 165000
  95 /* For current ASICs pixel clock - 600MHz */
  96 #define MAX_ENCODER_CLOCK 600000
  97
  98 enum {
  99         DP_MST_UPDATE_MAX_RETRY = 50
 100 };
 101
 102 #define DIG_REG(reg)\
 103         (reg + enc110->offsets.dig)
 104
 105 #define DP_REG(reg)\
 106         (reg + enc110->offsets.dp)
 107
 108 static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
 109         .validate_output_with_stream =
 110                 dce110_link_encoder_validate_output_with_stream,
 111         .hw_init = dce110_link_encoder_hw_init,
 112         .setup = dce110_link_encoder_setup,
 113         .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
 114         .enable_dp_output = dce110_link_encoder_enable_dp_output,
 115         .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
 116         .disable_output = dce110_link_encoder_disable_output,
 117         .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
 118         .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
 119         .update_mst_stream_allocation_table =
 120                 dce110_link_encoder_update_mst_stream_allocation_table,
 121         .psr_program_dp_dphy_fast_training =
 122                         dce110_psr_program_dp_dphy_fast_training,
 123         .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
 124         .backlight_control = dce110_link_encoder_edp_backlight_control,
 125         .power_control = dce110_link_encoder_edp_power_control,
 126         .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
 127         .enable_hpd = dce110_link_encoder_enable_hpd,
 128         .disable_hpd = dce110_link_encoder_disable_hpd,
 129         .destroy = dce110_link_encoder_destroy
 130 };
 131
 132 static enum bp_result link_transmitter_control(
 133         struct dce110_link_encoder *enc110,
 134         struct bp_transmitter_control *cntl)
 135 {
 136         enum bp_result result;
 137         struct dc_bios *bp = enc110->base.ctx->dc_bios;
 138
 139         result = bp->funcs->transmitter_control(bp, cntl);
 140
 141         return result;
 142 }
 143
 144 static void enable_phy_bypass_mode(
 145         struct dce110_link_encoder *enc110,
 146         bool enable)
 147 {
 148         /* This register resides in DP back end block;
 149          * transmitter is used for the offset */
 150
 151         REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
 152
 153 }
 154
 155 static void disable_prbs_symbols(
 156         struct dce110_link_encoder *enc110,
 157         bool disable)
 158 {
 159         /* This register resides in DP back end block;
 160          * transmitter is used for the offset */
 161
 162         REG_UPDATE_4(DP_DPHY_CNTL,
 163                         DPHY_ATEST_SEL_LANE0, disable,
 164                         DPHY_ATEST_SEL_LANE1, disable,
 165                         DPHY_ATEST_SEL_LANE2, disable,
 166                         DPHY_ATEST_SEL_LANE3, disable);
 167 }
 168
 169 static void disable_prbs_mode(
 170         struct dce110_link_encoder *enc110)
 171 {
 172         REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
 173 }
 174
 175 static void program_pattern_symbols(
 176         struct dce110_link_encoder *enc110,
 177         uint16_t pattern_symbols[8])
 178 {
 179         /* This register resides in DP back end block;
 180          * transmitter is used for the offset */
 181
 182         REG_SET_3(DP_DPHY_SYM0, 0,
 183                         DPHY_SYM1, pattern_symbols[0],
 184                         DPHY_SYM2, pattern_symbols[1],
 185                         DPHY_SYM3, pattern_symbols[2]);
 186
 187         /* This register resides in DP back end block;
 188          * transmitter is used for the offset */
 189
 190         REG_SET_3(DP_DPHY_SYM1, 0,
 191                         DPHY_SYM4, pattern_symbols[3],
 192                         DPHY_SYM5, pattern_symbols[4],
 193                         DPHY_SYM6, pattern_symbols[5]);
 194
 195         /* This register resides in DP back end block;
 196          * transmitter is used for the offset */
 197
 198         REG_SET_2(DP_DPHY_SYM2, 0,
 199                         DPHY_SYM7, pattern_symbols[6],
 200                         DPHY_SYM8, pattern_symbols[7]);
 201 }
 202
 203 static void set_dp_phy_pattern_d102(
 204         struct dce110_link_encoder *enc110)
 205 {
 206         /* Disable PHY Bypass mode to setup the test pattern */
 207         enable_phy_bypass_mode(enc110, false);
 208
 209         /* For 10-bit PRBS or debug symbols
 210          * please use the following sequence: */
 211
 212         /* Enable debug symbols on the lanes */
 213
 214         disable_prbs_symbols(enc110, true);
 215
 216         /* Disable PRBS mode */
 217         disable_prbs_mode(enc110);
 218
 219         /* Program debug symbols to be output */
 220         {
 221                 uint16_t pattern_symbols[8] = {
 222                         0x2AA, 0x2AA, 0x2AA, 0x2AA,
 223                         0x2AA, 0x2AA, 0x2AA, 0x2AA
 224                 };
 225
 226                 program_pattern_symbols(enc110, pattern_symbols);
 227         }
 228
 229         /* Enable phy bypass mode to enable the test pattern */
 230
 231         enable_phy_bypass_mode(enc110, true);
 232 }
 233
 234 static void set_link_training_complete(
 235         struct dce110_link_encoder *enc110,
 236         bool complete)
 237 {
 238         /* This register resides in DP back end block;
 239          * transmitter is used for the offset */
 240
 241         REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
 242
 243 }
 244
 245 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
 246         struct link_encoder *enc,
 247         uint32_t index)
 248 {
 249         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 250         /* Write Training Pattern */
 251
 252         REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
 253
 254         /* Set HW Register Training Complete to false */
 255
 256         set_link_training_complete(enc110, false);
 257
 258         /* Disable PHY Bypass mode to output Training Pattern */
 259
 260         enable_phy_bypass_mode(enc110, false);
 261
 262         /* Disable PRBS mode */
 263         disable_prbs_mode(enc110);
 264 }
 265
 266 static void setup_panel_mode(
 267         struct dce110_link_encoder *enc110,
 268         enum dp_panel_mode panel_mode)
 269 {
 270         uint32_t value;
 271
 272         ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
 273         value = REG_READ(DP_DPHY_INTERNAL_CTRL);
 274
 275         switch (panel_mode) {
 276         case DP_PANEL_MODE_EDP:
 277                 value = 0x1;
 278                 break;
 279         case DP_PANEL_MODE_SPECIAL:
 280                 value = 0x11;
 281                 break;
 282         default:
 283                 value = 0x0;
 284                 break;
 285         }
 286
 287         REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
 288 }
 289
 290 static void set_dp_phy_pattern_symbol_error(
 291         struct dce110_link_encoder *enc110)
 292 {
 293         /* Disable PHY Bypass mode to setup the test pattern */
 294         enable_phy_bypass_mode(enc110, false);
 295
 296         /* program correct panel mode*/
 297         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 298
 299         /* A PRBS23 pattern is used for most DP electrical measurements. */
 300
 301         /* Enable PRBS symbols on the lanes */
 302         disable_prbs_symbols(enc110, false);
 303
 304         /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
 305         REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
 306                         DPHY_PRBS_SEL, 1,
 307                         DPHY_PRBS_EN, 1);
 308
 309         /* Enable phy bypass mode to enable the test pattern */
 310         enable_phy_bypass_mode(enc110, true);
 311 }
 312
 313 static void set_dp_phy_pattern_prbs7(
 314         struct dce110_link_encoder *enc110)
 315 {
 316         /* Disable PHY Bypass mode to setup the test pattern */
 317         enable_phy_bypass_mode(enc110, false);
 318
 319         /* A PRBS7 pattern is used for most DP electrical measurements. */
 320
 321         /* Enable PRBS symbols on the lanes */
 322         disable_prbs_symbols(enc110, false);
 323
 324         /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
 325         REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
 326                         DPHY_PRBS_SEL, 0,
 327                         DPHY_PRBS_EN, 1);
 328
 329         /* Enable phy bypass mode to enable the test pattern */
 330         enable_phy_bypass_mode(enc110, true);
 331 }
 332
 333 static void set_dp_phy_pattern_80bit_custom(
 334         struct dce110_link_encoder *enc110,
 335         const uint8_t *pattern)
 336 {
 337         /* Disable PHY Bypass mode to setup the test pattern */
 338         enable_phy_bypass_mode(enc110, false);
 339
 340         /* Enable debug symbols on the lanes */
 341
 342         disable_prbs_symbols(enc110, true);
 343
 344         /* Enable PHY bypass mode to enable the test pattern */
 345         /* TODO is it really needed ? */
 346
 347         enable_phy_bypass_mode(enc110, true);
 348
 349         /* Program 80 bit custom pattern */
 350         {
 351                 uint16_t pattern_symbols[8];
 352
 353                 pattern_symbols[0] =
 354                         ((pattern[1] & 0x03) << 8) | pattern[0];
 355                 pattern_symbols[1] =
 356                         ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
 357                 pattern_symbols[2] =
 358                         ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
 359                 pattern_symbols[3] =
 360                         (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
 361                 pattern_symbols[4] =
 362                         ((pattern[6] & 0x03) << 8) | pattern[5];
 363                 pattern_symbols[5] =
 364                         ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
 365                 pattern_symbols[6] =
 366                         ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
 367                 pattern_symbols[7] =
 368                         (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
 369
 370                 program_pattern_symbols(enc110, pattern_symbols);
 371         }
 372
 373         /* Enable phy bypass mode to enable the test pattern */
 374
 375         enable_phy_bypass_mode(enc110, true);
 376 }
 377
 378 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
 379         struct dce110_link_encoder *enc110,
 380         unsigned int cp2520_pattern)
 381 {
 382
 383         /* previously there is a register DP_HBR2_EYE_PATTERN
 384          * that is enabled to get the pattern.
 385          * But it does not work with the latest spec change,
 386          * so we are programming the following registers manually.
 387          *
 388          * The following settings have been confirmed
 389          * by Nick Chorney and Sandra Liu */
 390
 391         /* Disable PHY Bypass mode to setup the test pattern */
 392
 393         enable_phy_bypass_mode(enc110, false);
 394
 395         /* Setup DIG encoder in DP SST mode */
 396         enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
 397
 398         /* ensure normal panel mode. */
 399         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 400
 401         /* no vbid after BS (SR)
 402          * DP_LINK_FRAMING_CNTL changed history Sandra Liu
 403          * 11000260 / 11000104 / 110000FC */
 404         REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
 405                         DP_IDLE_BS_INTERVAL, 0xFC,
 406                         DP_VBID_DISABLE, 1,
 407                         DP_VID_ENHANCED_FRAME_MODE, 1);
 408
 409         /* swap every BS with SR */
 410         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
 411
 412         /* select cp2520 patterns */
 413         if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
 414                 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
 415                                 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
 416         else
 417                 /* pre-DCE11 can only generate CP2520 pattern 2 */
 418                 ASSERT(cp2520_pattern == 2);
 419
 420         /* set link training complete */
 421         set_link_training_complete(enc110, true);
 422
 423         /* disable video stream */
 424         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 425
 426         /* Disable PHY Bypass mode to setup the test pattern */
 427         enable_phy_bypass_mode(enc110, false);
 428 }
 429
 430 static void set_dp_phy_pattern_passthrough_mode(
 431         struct dce110_link_encoder *enc110,
 432         enum dp_panel_mode panel_mode)
 433 {
 434         /* program correct panel mode */
 435         setup_panel_mode(enc110, panel_mode);
 436
 437         /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
 438          * in case we were doing HBR2 compliance pattern before
 439          */
 440         REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
 441                         DP_IDLE_BS_INTERVAL, 0x2000,
 442                         DP_VBID_DISABLE, 0,
 443                         DP_VID_ENHANCED_FRAME_MODE, 1);
 444
 445         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
 446
 447         /* set link training complete */
 448         set_link_training_complete(enc110, true);
 449
 450         /* Disable PHY Bypass mode to setup the test pattern */
 451         enable_phy_bypass_mode(enc110, false);
 452
 453         /* Disable PRBS mode */
 454         disable_prbs_mode(enc110);
 455 }
 456
 457 /* return value is bit-vector */
 458 static uint8_t get_frontend_source(
 459         enum engine_id engine)
 460 {
 461         switch (engine) {
 462         case ENGINE_ID_DIGA:
 463                 return DCE110_DIG_FE_SOURCE_SELECT_DIGA;
 464         case ENGINE_ID_DIGB:
 465                 return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
 466         case ENGINE_ID_DIGC:
 467                 return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
 468         case ENGINE_ID_DIGD:
 469                 return DCE110_DIG_FE_SOURCE_SELECT_DIGD;
 470         case ENGINE_ID_DIGE:
 471                 return DCE110_DIG_FE_SOURCE_SELECT_DIGE;
 472         case ENGINE_ID_DIGF:
 473                 return DCE110_DIG_FE_SOURCE_SELECT_DIGF;
 474         default:
 475                 ASSERT_CRITICAL(false);
 476                 return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
 477         }
 478 }
 479
 480 static void configure_encoder(
 481         struct dce110_link_encoder *enc110,
 482         const struct dc_link_settings *link_settings)
 483 {
 484         /* set number of lanes */
 485
 486         REG_SET(DP_CONFIG, 0,
 487                         DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
 488
 489         /* setup scrambler */
 490         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
 491 }
 492
 493 static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
 494 {
 495         bool ret;
 496         uint32_t value;
 497
 498         REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value);
 499         ret = value;
 500
 501         return ret == 1;
 502 }
 503
 504
 505 /* TODO duplicate of dc_link.c version */
 506 static struct gpio *get_hpd_gpio(const struct link_encoder *enc)
 507 {
 508         enum bp_result bp_result;
 509         struct dc_bios *dcb = enc->ctx->dc_bios;
 510         struct graphics_object_hpd_info hpd_info;
 511         struct gpio_pin_info pin_info;
 512
 513         if (dcb->funcs->get_hpd_info(dcb, enc->connector, &hpd_info) != BP_RESULT_OK)
 514                 return NULL;
 515
 516         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 517                 hpd_info.hpd_int_gpio_uid, &pin_info);
 518
 519         if (bp_result != BP_RESULT_OK) {
 520                 ASSERT(bp_result == BP_RESULT_NORECORD);
 521                 return NULL;
 522         }
 523
 524         return dal_gpio_service_create_irq(
 525                 enc->ctx->gpio_service,
 526                 pin_info.offset,
 527                 pin_info.mask);
 528 }
 529
 530 /*
 531  * @brief
 532  * eDP only.
 533  */
 534 static void link_encoder_edp_wait_for_hpd_ready(
 535         struct dce110_link_encoder *enc110,
 536         bool power_up)
 537 {
 538         struct dc_context *ctx = enc110->base.ctx;
 539         struct graphics_object_id connector = enc110->base.connector;
 540         struct gpio *hpd;
 541         bool edp_hpd_high = false;
 542         uint32_t time_elapsed = 0;
 543         uint32_t timeout = power_up ?
 544                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 545
 546         if (dal_graphics_object_id_get_connector_id(connector) !=
 547                 CONNECTOR_ID_EDP) {
 548                 BREAK_TO_DEBUGGER();
 549                 return;
 550         }
 551
 552         if (!power_up)
 553                 /* from KV, we will not HPD low after turning off VCC -
 554                  * instead, we will check the SW timer in power_up(). */
 555                 return;
 556
 557         /* when we power on/off the eDP panel,
 558          * we need to wait until SENSE bit is high/low */
 559
 560         /* obtain HPD */
 561         /* TODO what to do with this? */
 562         hpd = get_hpd_gpio(&enc110->base);
 563
 564         if (!hpd) {
 565                 BREAK_TO_DEBUGGER();
 566                 return;
 567         }
 568
 569         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 570
 571         /* wait until timeout or panel detected */
 572
 573         do {
 574                 uint32_t detected = 0;
 575
 576                 dal_gpio_get_value(hpd, &detected);
 577
 578                 if (!(detected ^ power_up)) {
 579                         edp_hpd_high = true;
 580                         break;
 581                 }
 582
 583                 msleep(HPD_CHECK_INTERVAL);
 584
 585                 time_elapsed += HPD_CHECK_INTERVAL;
 586         } while (time_elapsed < timeout);
 587
 588         dal_gpio_close(hpd);
 589
 590         dal_gpio_destroy_irq(&hpd);
 591
 592         if (false == edp_hpd_high) {
 593                 dm_logger_write(ctx->logger, LOG_ERROR,
 594                                 "%s: wait timed out!\n", __func__);
 595         }
 596 }
 597
 598 /*
 599  * @brief
 600  * eDP only. Control the power of the eDP panel.
 601  */
 602 void dce110_link_encoder_edp_power_control(
 603         struct link_encoder *enc,
 604         bool power_up)
 605 {
 606         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 607         struct dc_context *ctx = enc110->base.ctx;
 608         struct bp_transmitter_control cntl = { 0 };
 609         enum bp_result bp_result;
 610
 611         if (dal_graphics_object_id_get_connector_id(enc110->base.connector) !=
 612                 CONNECTOR_ID_EDP) {
 613                 BREAK_TO_DEBUGGER();
 614                 return;
 615         }
 616
 617         if ((power_up && !is_panel_powered_on(enc110)) ||
 618                 (!power_up && is_panel_powered_on(enc110))) {
 619
 620                 /* Send VBIOS command to prompt eDP panel power */
 621
 622                 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 623                                 "%s: Panel Power action: %s\n",
 624                                 __func__, (power_up ? "On":"Off"));
 625
 626                 cntl.action = power_up ?
 627                         TRANSMITTER_CONTROL_POWER_ON :
 628                         TRANSMITTER_CONTROL_POWER_OFF;
 629                 cntl.transmitter = enc110->base.transmitter;
 630                 cntl.connector_obj_id = enc110->base.connector;
 631                 cntl.coherent = false;
 632                 cntl.lanes_number = LANE_COUNT_FOUR;
 633                 cntl.hpd_sel = enc110->base.hpd_source;
 634
 635                 bp_result = link_transmitter_control(enc110, &cntl);
 636
 637                 if (BP_RESULT_OK != bp_result) {
 638
 639                         dm_logger_write(ctx->logger, LOG_ERROR,
 640                                         "%s: Panel Power bp_result: %d\n",
 641                                         __func__, bp_result);
 642                 }
 643         } else {
 644                 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 645                                 "%s: Skipping Panel Power action: %s\n",
 646                                 __func__, (power_up ? "On":"Off"));
 647         }
 648
 649         link_encoder_edp_wait_for_hpd_ready(enc110, true);
 650 }
 651
 652 static void aux_initialize(
 653         struct dce110_link_encoder *enc110)
 654 {
 655         struct dc_context *ctx = enc110->base.ctx;
 656         enum hpd_source_id hpd_source = enc110->base.hpd_source;
 657         uint32_t addr = AUX_REG(AUX_CONTROL);
 658         uint32_t value = dm_read_reg(ctx, addr);
 659
 660         set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
 661         set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
 662         dm_write_reg(ctx, addr, value);
 663
 664         addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
 665         value = dm_read_reg(ctx, addr);
 666
 667         /* 1/4 window (the maximum allowed) */
 668         set_reg_field_value(value, 1,
 669                         AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
 670         dm_write_reg(ctx, addr, value);
 671
 672 }
 673
 674 /*todo: cloned in stream enc, fix*/
 675 static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
 676 {
 677         uint32_t value;
 678
 679         REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
 680
 681         return value;
 682 }
 683
 684 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
 685                         bool exit_link_training_required)
 686 {
 687         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 688
 689         if (exit_link_training_required)
 690                 REG_UPDATE(DP_DPHY_FAST_TRAINING,
 691                                 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
 692         else {
 693                 REG_UPDATE(DP_DPHY_FAST_TRAINING,
 694                                 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
 695                 /*In DCE 11, we are able to pre-program a Force SR register
 696                  * to be able to trigger SR symbol after 5 idle patterns
 697                  * transmitted. Upon PSR Exit, DMCU can trigger
 698                  * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
 699                  * DPHY_LOAD_BS_COUNT_START and the internal counter
 700                  * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
 701                  * replaced by SR symbol once.
 702                  */
 703
 704                 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
 705         }
 706 }
 707
 708 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
 709                         unsigned int sdp_transmit_line_num_deadline)
 710 {
 711         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 712
 713         REG_UPDATE_2(DP_SEC_CNTL1,
 714                 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
 715                 DP_SEC_GSP0_PRIORITY, 1);
 716 }
 717
 718 /*todo: cloned in stream enc, fix*/
 719 /*
 720  * @brief
 721  * eDP only. Control the backlight of the eDP panel
 722  */
 723 void dce110_link_encoder_edp_backlight_control(
 724         struct link_encoder *enc,
 725         bool enable)
 726 {
 727         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 728         struct dc_context *ctx = enc110->base.ctx;
 729         struct bp_transmitter_control cntl = { 0 };
 730
 731         if (dal_graphics_object_id_get_connector_id(enc110->base.connector)
 732                 != CONNECTOR_ID_EDP) {
 733                 BREAK_TO_DEBUGGER();
 734                 return;
 735         }
 736
 737         if (enable && is_panel_backlight_on(enc110)) {
 738                 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 739                                 "%s: panel already powered up. Do nothing.\n",
 740                                 __func__);
 741                 return;
 742         }
 743
 744         if (!enable && !is_panel_powered_on(enc110)) {
 745                 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 746                                 "%s: panel already powered down. Do nothing.\n",
 747                                 __func__);
 748                 return;
 749         }
 750
 751         /* Send VBIOS command to control eDP panel backlight */
 752
 753         dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 754                         "%s: backlight action: %s\n",
 755                         __func__, (enable ? "On":"Off"));
 756
 757         cntl.action = enable ?
 758                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 759                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 760         /*cntl.engine_id = ctx->engine;*/
 761         cntl.transmitter = enc110->base.transmitter;
 762         cntl.connector_obj_id = enc110->base.connector;
 763         /*todo: unhardcode*/
 764         cntl.lanes_number = LANE_COUNT_FOUR;
 765         cntl.hpd_sel = enc110->base.hpd_source;
 766
 767         /* For eDP, the following delays might need to be considered
 768          * after link training completed:
 769          * idle period - min. accounts for required BS-Idle pattern,
 770          * max. allows for source frame synchronization);
 771          * 50 msec max. delay from valid video data from source
 772          * to video on dislpay or backlight enable.
 773          *
 774          * Disable the delay for now.
 775          * Enable it in the future if necessary.
 776          */
 777         /* dc_service_sleep_in_milliseconds(50); */
 778         link_transmitter_control(enc110, &cntl);
 779 }
 780
 781 static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
 782 {
 783         uint32_t value;
 784
 785         REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
 786         return value;
 787 }
 788
 789 static void link_encoder_disable(struct dce110_link_encoder *enc110)
 790 {
 791         /* reset training pattern */
 792         REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
 793                         DPHY_TRAINING_PATTERN_SEL, 0);
 794
 795         /* reset training complete */
 796         REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
 797
 798         /* reset panel mode */
 799         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 800 }
 801
 802 static void hpd_initialize(
 803         struct dce110_link_encoder *enc110)
 804 {
 805         /* Associate HPD with DIG_BE */
 806         enum hpd_source_id hpd_source = enc110->base.hpd_source;
 807
 808         REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
 809 }
 810
 811 bool dce110_link_encoder_validate_dvi_output(
 812         const struct dce110_link_encoder *enc110,
 813         enum signal_type connector_signal,
 814         enum signal_type signal,
 815         const struct dc_crtc_timing *crtc_timing)
 816 {
 817         uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
 818
 819         if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
 820                 max_pixel_clock *= 2;
 821
 822         /* This handles the case of HDMI downgrade to DVI we don't want to
 823          * we don't want to cap the pixel clock if the DDI is not DVI.
 824          */
 825         if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
 826                         connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
 827                 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
 828
 829         /* DVI only support RGB pixel encoding */
 830         if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
 831                 return false;
 832
 833         /*connect DVI via adpater's HDMI connector*/
 834         if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
 835                 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
 836                 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
 837                 crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
 838                 return false;
 839         if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
 840                 return false;
 841
 842         if (crtc_timing->pix_clk_khz > max_pixel_clock)
 843                 return false;
 844
 845         /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
 846         switch (crtc_timing->display_color_depth) {
 847         case COLOR_DEPTH_666:
 848         case COLOR_DEPTH_888:
 849         break;
 850         case COLOR_DEPTH_101010:
 851         case COLOR_DEPTH_161616:
 852                 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
 853                         return false;
 854         break;
 855         default:
 856                 return false;
 857         }
 858
 859         return true;
 860 }
 861
 862 static bool dce110_link_encoder_validate_hdmi_output(
 863         const struct dce110_link_encoder *enc110,
 864         const struct dc_crtc_timing *crtc_timing,
 865         int adjusted_pix_clk_khz)
 866 {
 867         enum dc_color_depth max_deep_color =
 868                         enc110->base.features.max_hdmi_deep_color;
 869
 870         if (max_deep_color < crtc_timing->display_color_depth)
 871                 return false;
 872
 873         if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
 874                 return false;
 875         if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
 876                 return false;
 877
 878         if ((adjusted_pix_clk_khz == 0) ||
 879                 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
 880                 return false;
 881
 882         /* DCE11 HW does not support 420 */
 883         if (!enc110->base.features.ycbcr420_supported &&
 884                         crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 885                 return false;
 886
 887         return true;
 888 }
 889
 890 bool dce110_link_encoder_validate_dp_output(
 891         const struct dce110_link_encoder *enc110,
 892         const struct dc_crtc_timing *crtc_timing)
 893 {
 894         /* default RGB only */
 895         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
 896                 return true;
 897
 898         if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
 899                 return true;
 900
 901         /* for DCE 8.x or later DP Y-only feature,
 902          * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
 903         if (crtc_timing->flags.Y_ONLY &&
 904                 enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
 905                 crtc_timing->display_color_depth != COLOR_DEPTH_666)
 906                 return true;
 907
 908         return false;
 909 }
 910
 911 bool dce110_link_encoder_construct(
 912         struct dce110_link_encoder *enc110,
 913         const struct encoder_init_data *init_data,
 914         const struct encoder_feature_support *enc_features,
 915         const struct dce110_link_enc_registers *link_regs,
 916         const struct dce110_link_enc_aux_registers *aux_regs,
 917         const struct dce110_link_enc_hpd_registers *hpd_regs)
 918 {
 919         struct bp_encoder_cap_info bp_cap_info = {0};
 920         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 921
 922         enc110->base.funcs = &dce110_lnk_enc_funcs;
 923         enc110->base.ctx = init_data->ctx;
 924         enc110->base.id = init_data->encoder;
 925
 926         enc110->base.hpd_source = init_data->hpd_source;
 927         enc110->base.connector = init_data->connector;
 928
 929         enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
 930
 931         enc110->base.features = *enc_features;
 932
 933         enc110->base.transmitter = init_data->transmitter;
 934
 935         /* set the flag to indicate whether driver poll the I2C data pin
 936          * while doing the DP sink detect
 937          */
 938
 939 /*      if (dal_adapter_service_is_feature_supported(as,
 940                 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 941                 enc110->base.features.flags.bits.
 942                         DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 943
 944         enc110->base.output_signals =
 945                 SIGNAL_TYPE_DVI_SINGLE_LINK |
 946                 SIGNAL_TYPE_DVI_DUAL_LINK |
 947                 SIGNAL_TYPE_LVDS |
 948                 SIGNAL_TYPE_DISPLAY_PORT |
 949                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 950                 SIGNAL_TYPE_EDP |
 951                 SIGNAL_TYPE_HDMI_TYPE_A;
 952
 953         /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 954          * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 955          * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 956          * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 957          * Prefer DIG assignment is decided by board design.
 958          * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 959          * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 960          * By this, adding DIGG should not hurt DCE 8.0.
 961          * This will let DCE 8.1 share DCE 8.0 as much as possible
 962          */
 963
 964         enc110->link_regs = link_regs;
 965         enc110->aux_regs = aux_regs;
 966         enc110->hpd_regs = hpd_regs;
 967
 968         switch (enc110->base.transmitter) {
 969         case TRANSMITTER_UNIPHY_A:
 970                 enc110->base.preferred_engine = ENGINE_ID_DIGA;
 971         break;
 972         case TRANSMITTER_UNIPHY_B:
 973                 enc110->base.preferred_engine = ENGINE_ID_DIGB;
 974         break;
 975         case TRANSMITTER_UNIPHY_C:
 976                 enc110->base.preferred_engine = ENGINE_ID_DIGC;
 977         break;
 978         case TRANSMITTER_UNIPHY_D:
 979                 enc110->base.preferred_engine = ENGINE_ID_DIGD;
 980         break;
 981         case TRANSMITTER_UNIPHY_E:
 982                 enc110->base.preferred_engine = ENGINE_ID_DIGE;
 983         break;
 984         case TRANSMITTER_UNIPHY_F:
 985                 enc110->base.preferred_engine = ENGINE_ID_DIGF;
 986         break;
 987         default:
 988                 ASSERT_CRITICAL(false);
 989                 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
 990         }
 991
 992         dm_logger_write(init_data->ctx->logger, LOG_I2C_AUX,
 993                         "Using channel: %s [%d]\n",
 994                         DECODE_CHANNEL_ID(init_data->channel),
 995                         init_data->channel);
 996
 997         /* Override features with DCE-specific values */
 998         if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
 999                         enc110->base.ctx->dc_bios, enc110->base.id,
1000                         &bp_cap_info)) {
1001                 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
1002                                 bp_cap_info.DP_HBR2_EN;
1003                 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
1004                                 bp_cap_info.DP_HBR3_EN;
1005         }
1006
1007         return true;
1008 }
1009
1010 bool dce110_link_encoder_validate_output_with_stream(
1011         struct link_encoder *enc,
1012         const struct dc_stream_state *stream)
1013 {
1014         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1015         bool is_valid;
1016
1017         switch (stream->signal) {
1018         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1019         case SIGNAL_TYPE_DVI_DUAL_LINK:
1020                 is_valid = dce110_link_encoder_validate_dvi_output(
1021                         enc110,
1022                         stream->sink->link->connector_signal,
1023                         stream->signal,
1024                         &stream->timing);
1025         break;
1026         case SIGNAL_TYPE_HDMI_TYPE_A:
1027                 is_valid = dce110_link_encoder_validate_hdmi_output(
1028                                 enc110,
1029                                 &stream->timing,
1030                                 stream->phy_pix_clk);
1031         break;
1032         case SIGNAL_TYPE_DISPLAY_PORT:
1033         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1034                 is_valid = dce110_link_encoder_validate_dp_output(
1035                                         enc110, &stream->timing);
1036         break;
1037         case SIGNAL_TYPE_EDP:
1038                 is_valid =
1039                         (stream->timing.
1040                                 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
1041         break;
1042         case SIGNAL_TYPE_VIRTUAL:
1043                 is_valid = true;
1044                 break;
1045         default:
1046                 is_valid = false;
1047         break;
1048         }
1049
1050         return is_valid;
1051 }
1052
1053 void dce110_link_encoder_hw_init(
1054         struct link_encoder *enc)
1055 {
1056         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1057         struct dc_context *ctx = enc110->base.ctx;
1058         struct bp_transmitter_control cntl = { 0 };
1059         enum bp_result result;
1060
1061         cntl.action = TRANSMITTER_CONTROL_INIT;
1062         cntl.engine_id = ENGINE_ID_UNKNOWN;
1063         cntl.transmitter = enc110->base.transmitter;
1064         cntl.connector_obj_id = enc110->base.connector;
1065         cntl.lanes_number = LANE_COUNT_FOUR;
1066         cntl.coherent = false;
1067         cntl.hpd_sel = enc110->base.hpd_source;
1068
1069         result = link_transmitter_control(enc110, &cntl);
1070
1071         if (result != BP_RESULT_OK) {
1072                 dm_logger_write(ctx->logger, LOG_ERROR,
1073                         "%s: Failed to execute VBIOS command table!\n",
1074                         __func__);
1075                 BREAK_TO_DEBUGGER();
1076                 return;
1077         }
1078
1079         if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
1080                 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
1081
1082                 result = link_transmitter_control(enc110, &cntl);
1083
1084                 ASSERT(result == BP_RESULT_OK);
1085
1086         } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
1087                 enc->funcs->power_control(&enc110->base, true);
1088         }
1089         aux_initialize(enc110);
1090
1091         /* reinitialize HPD.
1092          * hpd_initialize() will pass DIG_FE id to HW context.
1093          * All other routine within HW context will use fe_engine_offset
1094          * as DIG_FE id even caller pass DIG_FE id.
1095          * So this routine must be called first. */
1096         hpd_initialize(enc110);
1097 }
1098
1099 void dce110_link_encoder_destroy(struct link_encoder **enc)
1100 {
1101         dm_free(TO_DCE110_LINK_ENC(*enc));
1102         *enc = NULL;
1103 }
1104
1105 void dce110_link_encoder_setup(
1106         struct link_encoder *enc,
1107         enum signal_type signal)
1108 {
1109         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1110
1111         switch (signal) {
1112         case SIGNAL_TYPE_EDP:
1113         case SIGNAL_TYPE_DISPLAY_PORT:
1114                 /* DP SST */
1115                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
1116                 break;
1117         case SIGNAL_TYPE_LVDS:
1118                 /* LVDS */
1119                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
1120                 break;
1121         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1122         case SIGNAL_TYPE_DVI_DUAL_LINK:
1123                 /* TMDS-DVI */
1124                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
1125                 break;
1126         case SIGNAL_TYPE_HDMI_TYPE_A:
1127                 /* TMDS-HDMI */
1128                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
1129                 break;
1130         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1131                 /* DP MST */
1132                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
1133                 break;
1134         default:
1135                 ASSERT_CRITICAL(false);
1136                 /* invalid mode ! */
1137                 break;
1138         }
1139
1140 }
1141
1142 /* TODO: still need depth or just pass in adjusted pixel clock? */
1143 void dce110_link_encoder_enable_tmds_output(
1144         struct link_encoder *enc,
1145         enum clock_source_id clock_source,
1146         enum dc_color_depth color_depth,
1147         bool hdmi,
1148         bool dual_link,
1149         uint32_t pixel_clock)
1150 {
1151         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1152         struct dc_context *ctx = enc110->base.ctx;
1153         struct bp_transmitter_control cntl = { 0 };
1154         enum bp_result result;
1155
1156         /* Enable the PHY */
1157
1158         cntl.action = TRANSMITTER_CONTROL_ENABLE;
1159         cntl.engine_id = enc->preferred_engine;
1160         cntl.transmitter = enc110->base.transmitter;
1161         cntl.pll_id = clock_source;
1162         if (hdmi) {
1163                 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1164                 cntl.lanes_number = 4;
1165         } else if (dual_link) {
1166                 cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1167                 cntl.lanes_number = 8;
1168         } else {
1169                 cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1170                 cntl.lanes_number = 4;
1171         }
1172         cntl.hpd_sel = enc110->base.hpd_source;
1173
1174         cntl.pixel_clock = pixel_clock;
1175         cntl.color_depth = color_depth;
1176
1177         result = link_transmitter_control(enc110, &cntl);
1178
1179         if (result != BP_RESULT_OK) {
1180                 dm_logger_write(ctx->logger, LOG_ERROR,
1181                         "%s: Failed to execute VBIOS command table!\n",
1182                         __func__);
1183                 BREAK_TO_DEBUGGER();
1184         }
1185 }
1186
1187 /* enables DP PHY output */
1188 void dce110_link_encoder_enable_dp_output(
1189         struct link_encoder *enc,
1190         const struct dc_link_settings *link_settings,
1191         enum clock_source_id clock_source)
1192 {
1193         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1194         struct dc_context *ctx = enc110->base.ctx;
1195         struct bp_transmitter_control cntl = { 0 };
1196         enum bp_result result;
1197
1198         /* Enable the PHY */
1199
1200         /* number_of_lanes is used for pixel clock adjust,
1201          * but it's not passed to asic_control.
1202          * We need to set number of lanes manually.
1203          */
1204         configure_encoder(enc110, link_settings);
1205
1206         cntl.action = TRANSMITTER_CONTROL_ENABLE;
1207         cntl.engine_id = enc->preferred_engine;
1208         cntl.transmitter = enc110->base.transmitter;
1209         cntl.pll_id = clock_source;
1210         cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
1211         cntl.lanes_number = link_settings->lane_count;
1212         cntl.hpd_sel = enc110->base.hpd_source;
1213         cntl.pixel_clock = link_settings->link_rate
1214                                                 * LINK_RATE_REF_FREQ_IN_KHZ;
1215         /* TODO: check if undefined works */
1216         cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1217
1218         result = link_transmitter_control(enc110, &cntl);
1219
1220         if (result != BP_RESULT_OK) {
1221                 dm_logger_write(ctx->logger, LOG_ERROR,
1222                         "%s: Failed to execute VBIOS command table!\n",
1223                         __func__);
1224                 BREAK_TO_DEBUGGER();
1225         }
1226 }
1227
1228 /* enables DP PHY output in MST mode */
1229 void dce110_link_encoder_enable_dp_mst_output(
1230         struct link_encoder *enc,
1231         const struct dc_link_settings *link_settings,
1232         enum clock_source_id clock_source)
1233 {
1234         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1235         struct dc_context *ctx = enc110->base.ctx;
1236         struct bp_transmitter_control cntl = { 0 };
1237         enum bp_result result;
1238
1239         /* Enable the PHY */
1240
1241         /* number_of_lanes is used for pixel clock adjust,
1242          * but it's not passed to asic_control.
1243          * We need to set number of lanes manually.
1244          */
1245         configure_encoder(enc110, link_settings);
1246
1247         cntl.action = TRANSMITTER_CONTROL_ENABLE;
1248         cntl.engine_id = ENGINE_ID_UNKNOWN;
1249         cntl.transmitter = enc110->base.transmitter;
1250         cntl.pll_id = clock_source;
1251         cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1252         cntl.lanes_number = link_settings->lane_count;
1253         cntl.hpd_sel = enc110->base.hpd_source;
1254         cntl.pixel_clock = link_settings->link_rate
1255                                                 * LINK_RATE_REF_FREQ_IN_KHZ;
1256         /* TODO: check if undefined works */
1257         cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1258
1259         result = link_transmitter_control(enc110, &cntl);
1260
1261         if (result != BP_RESULT_OK) {
1262                 dm_logger_write(ctx->logger, LOG_ERROR,
1263                         "%s: Failed to execute VBIOS command table!\n",
1264                         __func__);
1265                 BREAK_TO_DEBUGGER();
1266         }
1267 }
1268 /*
1269  * @brief
1270  * Disable transmitter and its encoder
1271  */
1272 void dce110_link_encoder_disable_output(
1273         struct link_encoder *enc,
1274         enum signal_type signal)
1275 {
1276         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1277         struct dc_context *ctx = enc110->base.ctx;
1278         struct bp_transmitter_control cntl = { 0 };
1279         enum bp_result result;
1280
1281         if (!is_dig_enabled(enc110)) {
1282                 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1283                 return;
1284         }
1285         /* Power-down RX and disable GPU PHY should be paired.
1286          * Disabling PHY without powering down RX may cause
1287          * symbol lock loss, on which we will get DP Sink interrupt. */
1288
1289         /* There is a case for the DP active dongles
1290          * where we want to disable the PHY but keep RX powered,
1291          * for those we need to ignore DP Sink interrupt
1292          * by checking lane count that has been set
1293          * on the last do_enable_output(). */
1294
1295         /* disable transmitter */
1296         cntl.action = TRANSMITTER_CONTROL_DISABLE;
1297         cntl.transmitter = enc110->base.transmitter;
1298         cntl.hpd_sel = enc110->base.hpd_source;
1299         cntl.signal = signal;
1300         cntl.connector_obj_id = enc110->base.connector;
1301
1302         result = link_transmitter_control(enc110, &cntl);
1303
1304         if (result != BP_RESULT_OK) {
1305                 dm_logger_write(ctx->logger, LOG_ERROR,
1306                         "%s: Failed to execute VBIOS command table!\n",
1307                         __func__);
1308                 BREAK_TO_DEBUGGER();
1309                 return;
1310         }
1311
1312         /* disable encoder */
1313         if (dc_is_dp_signal(signal))
1314                 link_encoder_disable(enc110);
1315
1316         if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
1317                 /* power down eDP panel */
1318                 /* TODO: Power control cause regression, we should implement
1319                  * it properly, for now just comment it.
1320                  *
1321                  * link_encoder_edp_wait_for_hpd_ready(
1322                         link_enc,
1323                         link_enc->connector,
1324                         false);
1325
1326                  * link_encoder_edp_power_control(
1327                                 link_enc, false); */
1328         }
1329 }
1330
1331 void dce110_link_encoder_dp_set_lane_settings(
1332         struct link_encoder *enc,
1333         const struct link_training_settings *link_settings)
1334 {
1335         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1336         union dpcd_training_lane_set training_lane_set = { { 0 } };
1337         int32_t lane = 0;
1338         struct bp_transmitter_control cntl = { 0 };
1339
1340         if (!link_settings) {
1341                 BREAK_TO_DEBUGGER();
1342                 return;
1343         }
1344
1345         cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1346         cntl.transmitter = enc110->base.transmitter;
1347         cntl.connector_obj_id = enc110->base.connector;
1348         cntl.lanes_number = link_settings->link_settings.lane_count;
1349         cntl.hpd_sel = enc110->base.hpd_source;
1350         cntl.pixel_clock = link_settings->link_settings.link_rate *
1351                                                 LINK_RATE_REF_FREQ_IN_KHZ;
1352
1353         for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1354                 /* translate lane settings */
1355
1356                 training_lane_set.bits.VOLTAGE_SWING_SET =
1357                         link_settings->lane_settings[lane].VOLTAGE_SWING;
1358                 training_lane_set.bits.PRE_EMPHASIS_SET =
1359                         link_settings->lane_settings[lane].PRE_EMPHASIS;
1360
1361                 /* post cursor 2 setting only applies to HBR2 link rate */
1362                 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1363                         /* this is passed to VBIOS
1364                          * to program post cursor 2 level */
1365
1366                         training_lane_set.bits.POST_CURSOR2_SET =
1367                                 link_settings->lane_settings[lane].POST_CURSOR2;
1368                 }
1369
1370                 cntl.lane_select = lane;
1371                 cntl.lane_settings = training_lane_set.raw;
1372
1373                 /* call VBIOS table to set voltage swing and pre-emphasis */
1374                 link_transmitter_control(enc110, &cntl);
1375         }
1376 }
1377
1378 /* set DP PHY test and training patterns */
1379 void dce110_link_encoder_dp_set_phy_pattern(
1380         struct link_encoder *enc,
1381         const struct encoder_set_dp_phy_pattern_param *param)
1382 {
1383         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1384
1385         switch (param->dp_phy_pattern) {
1386         case DP_TEST_PATTERN_TRAINING_PATTERN1:
1387                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1388                 break;
1389         case DP_TEST_PATTERN_TRAINING_PATTERN2:
1390                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1391                 break;
1392         case DP_TEST_PATTERN_TRAINING_PATTERN3:
1393                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1394                 break;
1395         case DP_TEST_PATTERN_TRAINING_PATTERN4:
1396                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1397                 break;
1398         case DP_TEST_PATTERN_D102:
1399                 set_dp_phy_pattern_d102(enc110);
1400                 break;
1401         case DP_TEST_PATTERN_SYMBOL_ERROR:
1402                 set_dp_phy_pattern_symbol_error(enc110);
1403                 break;
1404         case DP_TEST_PATTERN_PRBS7:
1405                 set_dp_phy_pattern_prbs7(enc110);
1406                 break;
1407         case DP_TEST_PATTERN_80BIT_CUSTOM:
1408                 set_dp_phy_pattern_80bit_custom(
1409                         enc110, param->custom_pattern);
1410                 break;
1411         case DP_TEST_PATTERN_CP2520_1:
1412                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
1413                 break;
1414         case DP_TEST_PATTERN_CP2520_2:
1415                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
1416                 break;
1417         case DP_TEST_PATTERN_CP2520_3:
1418                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
1419                 break;
1420         case DP_TEST_PATTERN_VIDEO_MODE: {
1421                 set_dp_phy_pattern_passthrough_mode(
1422                         enc110, param->dp_panel_mode);
1423                 break;
1424         }
1425
1426         default:
1427                 /* invalid phy pattern */
1428                 ASSERT_CRITICAL(false);
1429                 break;
1430         }
1431 }
1432
1433 static void fill_stream_allocation_row_info(
1434         const struct link_mst_stream_allocation *stream_allocation,
1435         uint32_t *src,
1436         uint32_t *slots)
1437 {
1438         const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1439
1440         if (stream_enc) {
1441                 *src = stream_enc->id;
1442                 *slots = stream_allocation->slot_count;
1443         } else {
1444                 *src = 0;
1445                 *slots = 0;
1446         }
1447 }
1448
1449 /* programs DP MST VC payload allocation */
1450 void dce110_link_encoder_update_mst_stream_allocation_table(
1451         struct link_encoder *enc,
1452         const struct link_mst_stream_allocation_table *table)
1453 {
1454         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1455         uint32_t value0 = 0;
1456         uint32_t value1 = 0;
1457         uint32_t value2 = 0;
1458         uint32_t slots = 0;
1459         uint32_t src = 0;
1460         uint32_t retries = 0;
1461
1462         /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1463
1464         /* --- Set MSE Stream Attribute -
1465          * Setup VC Payload Table on Tx Side,
1466          * Issue allocation change trigger
1467          * to commit payload on both tx and rx side */
1468
1469         /* we should clean-up table each time */
1470
1471         if (table->stream_count >= 1) {
1472                 fill_stream_allocation_row_info(
1473                         &table->stream_allocations[0],
1474                         &src,
1475                         &slots);
1476         } else {
1477                 src = 0;
1478                 slots = 0;
1479         }
1480
1481         REG_UPDATE_2(DP_MSE_SAT0,
1482                         DP_MSE_SAT_SRC0, src,
1483                         DP_MSE_SAT_SLOT_COUNT0, slots);
1484
1485         if (table->stream_count >= 2) {
1486                 fill_stream_allocation_row_info(
1487                         &table->stream_allocations[1],
1488                         &src,
1489                         &slots);
1490         } else {
1491                 src = 0;
1492                 slots = 0;
1493         }
1494
1495         REG_UPDATE_2(DP_MSE_SAT0,
1496                         DP_MSE_SAT_SRC1, src,
1497                         DP_MSE_SAT_SLOT_COUNT1, slots);
1498
1499         if (table->stream_count >= 3) {
1500                 fill_stream_allocation_row_info(
1501                         &table->stream_allocations[2],
1502                         &src,
1503                         &slots);
1504         } else {
1505                 src = 0;
1506                 slots = 0;
1507         }
1508
1509         REG_UPDATE_2(DP_MSE_SAT1,
1510                         DP_MSE_SAT_SRC2, src,
1511                         DP_MSE_SAT_SLOT_COUNT2, slots);
1512
1513         if (table->stream_count >= 4) {
1514                 fill_stream_allocation_row_info(
1515                         &table->stream_allocations[3],
1516                         &src,
1517                         &slots);
1518         } else {
1519                 src = 0;
1520                 slots = 0;
1521         }
1522
1523         REG_UPDATE_2(DP_MSE_SAT1,
1524                         DP_MSE_SAT_SRC3, src,
1525                         DP_MSE_SAT_SLOT_COUNT3, slots);
1526
1527         /* --- wait for transaction finish */
1528
1529         /* send allocation change trigger (ACT) ?
1530          * this step first sends the ACT,
1531          * then double buffers the SAT into the hardware
1532          * making the new allocation active on the DP MST mode link */
1533
1534
1535         /* DP_MSE_SAT_UPDATE:
1536          * 0 - No Action
1537          * 1 - Update SAT with trigger
1538          * 2 - Update SAT without trigger */
1539
1540         REG_UPDATE(DP_MSE_SAT_UPDATE,
1541                         DP_MSE_SAT_UPDATE, 1);
1542
1543         /* wait for update to complete
1544          * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1545          * then wait for the transmission
1546          * of at least 16 MTP headers on immediate local link.
1547          * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1548          * a value of 1 indicates that DP MST mode
1549          * is in the 16 MTP keepout region after a VC has been added.
1550          * MST stream bandwidth (VC rate) can be configured
1551          * after this bit is cleared */
1552
1553         do {
1554                 udelay(10);
1555
1556                 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1557
1558                 REG_GET(DP_MSE_SAT_UPDATE,
1559                                 DP_MSE_SAT_UPDATE, &value1);
1560
1561                 REG_GET(DP_MSE_SAT_UPDATE,
1562                                 DP_MSE_16_MTP_KEEPOUT, &value2);
1563
1564                 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1565                 if (!value1 && !value2)
1566                         break;
1567                 ++retries;
1568         } while (retries < DP_MST_UPDATE_MAX_RETRY);
1569 }
1570
1571 void dce110_link_encoder_connect_dig_be_to_fe(
1572         struct link_encoder *enc,
1573         enum engine_id engine,
1574         bool connect)
1575 {
1576         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1577         uint32_t field;
1578
1579         if (engine != ENGINE_ID_UNKNOWN) {
1580
1581                 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1582
1583                 if (connect)
1584                         field |= get_frontend_source(engine);
1585                 else
1586                         field &= ~get_frontend_source(engine);
1587
1588                 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1589         }
1590 }
1591
1592 void dce110_link_encoder_enable_hpd(struct link_encoder *enc)
1593 {
1594         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1595         struct dc_context *ctx = enc110->base.ctx;
1596         uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1597         uint32_t hpd_enable = 0;
1598         uint32_t value = dm_read_reg(ctx, addr);
1599
1600         get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
1601
1602         if (hpd_enable == 0)
1603                 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN);
1604 }
1605
1606 void dce110_link_encoder_disable_hpd(struct link_encoder *enc)
1607 {
1608         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1609         struct dc_context *ctx = enc110->base.ctx;
1610         uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1611         uint32_t value = dm_read_reg(ctx, addr);
1612
1613         set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
1614 }