drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc.h"
  27 #include "dc_dmub_srv.h"
  28 #include "../dmub/dmub_srv.h"
  29 #include "dm_helpers.h"
  30 #include "dc_hw_types.h"
  31 #include "core_types.h"
  32 #include "../basics/conversion.h"
  33 #include "cursor_reg_cache.h"
  34 #include "resource.h"
  35 #include "clk_mgr.h"
  36
  37 #define CTX dc_dmub_srv->ctx
  38 #define DC_LOGGER CTX->logger
  39
  40 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
  41                                   struct dmub_srv *dmub)
  42 {
  43         dc_srv->dmub = dmub;
  44         dc_srv->ctx = dc->ctx;
  45 }
  46
  47 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
  48 {
  49         struct dc_dmub_srv *dc_srv =
  50                 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
  51
  52         if (dc_srv == NULL) {
  53                 BREAK_TO_DEBUGGER();
  54                 return NULL;
  55         }
  56
  57         dc_dmub_srv_construct(dc_srv, dc, dmub);
  58
  59         return dc_srv;
  60 }
  61
  62 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
  63 {
  64         if (*dmub_srv) {
  65                 kfree(*dmub_srv);
  66                 *dmub_srv = NULL;
  67         }
  68 }
  69
  70 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
  71 {
  72         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  73         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  74         enum dmub_status status;
  75
  76         status = dmub_srv_wait_for_idle(dmub, 100000);
  77         if (status != DMUB_STATUS_OK) {
  78                 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
  79                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  80         }
  81 }
  82
  83 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  84 {
  85         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  86         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  87         enum dmub_status status = DMUB_STATUS_OK;
  88
  89         status = dmub_srv_clear_inbox0_ack(dmub);
  90         if (status != DMUB_STATUS_OK) {
  91                 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
  92                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  93         }
  94 }
  95
  96 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  97 {
  98         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  99         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 100         enum dmub_status status = DMUB_STATUS_OK;
 101
 102         status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
 103         if (status != DMUB_STATUS_OK) {
 104                 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
 105                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 106         }
 107 }
 108
 109 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv,
 110                                  union dmub_inbox0_data_register data)
 111 {
 112         struct dmub_srv *dmub = dc_dmub_srv->dmub;
 113         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 114         enum dmub_status status = DMUB_STATUS_OK;
 115
 116         status = dmub_srv_send_inbox0_cmd(dmub, data);
 117         if (status != DMUB_STATUS_OK) {
 118                 DC_ERROR("Error sending INBOX0 cmd\n");
 119                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 120         }
 121 }
 122
 123 bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
 124                 unsigned int count,
 125                 union dmub_rb_cmd *cmd_list)
 126 {
 127         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 128         struct dmub_srv *dmub;
 129         enum dmub_status status;
 130         int i;
 131
 132         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 133                 return false;
 134
 135         dmub = dc_dmub_srv->dmub;
 136
 137         for (i = 0 ; i < count; i++) {
 138                 // Queue command
 139                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 140
 141                 if (status == DMUB_STATUS_QUEUE_FULL) {
 142                         /* Execute and wait for queue to become empty again. */
 143                         dmub_srv_cmd_execute(dmub);
 144                         dmub_srv_wait_for_idle(dmub, 100000);
 145
 146                         /* Requeue the command. */
 147                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 148                 }
 149
 150                 if (status != DMUB_STATUS_OK) {
 151                         DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 152                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 153                         return false;
 154                 }
 155         }
 156
 157         status = dmub_srv_cmd_execute(dmub);
 158         if (status != DMUB_STATUS_OK) {
 159                 DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 160                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 161                 return false;
 162         }
 163
 164         return true;
 165 }
 166
 167 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
 168                 enum dm_dmub_wait_type wait_type,
 169                 union dmub_rb_cmd *cmd_list)
 170 {
 171         struct dmub_srv *dmub;
 172         enum dmub_status status;
 173
 174         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 175                 return false;
 176
 177         dmub = dc_dmub_srv->dmub;
 178
 179         // Wait for DMUB to process command
 180         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 181                 status = dmub_srv_wait_for_idle(dmub, 100000);
 182
 183                 if (status != DMUB_STATUS_OK) {
 184                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 185                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 186                         return false;
 187                 }
 188
 189                 // Copy data back from ring buffer into command
 190                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 191                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 192         }
 193
 194         return true;
 195 }
 196
 197 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
 198 {
 199         return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);
 200 }
 201
 202 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
 203 {
 204         struct dc_context *dc_ctx;
 205         struct dmub_srv *dmub;
 206         enum dmub_status status;
 207         int i;
 208
 209         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 210                 return false;
 211
 212         dc_ctx = dc_dmub_srv->ctx;
 213         dmub = dc_dmub_srv->dmub;
 214
 215         for (i = 0 ; i < count; i++) {
 216                 // Queue command
 217                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 218
 219                 if (status == DMUB_STATUS_QUEUE_FULL) {
 220                         /* Execute and wait for queue to become empty again. */
 221                         dmub_srv_cmd_execute(dmub);
 222                         dmub_srv_wait_for_idle(dmub, 100000);
 223
 224                         /* Requeue the command. */
 225                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 226                 }
 227
 228                 if (status != DMUB_STATUS_OK) {
 229                         DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 230                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 231                         return false;
 232                 }
 233         }
 234
 235         status = dmub_srv_cmd_execute(dmub);
 236         if (status != DMUB_STATUS_OK) {
 237                 DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 238                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 239                 return false;
 240         }
 241
 242         // Wait for DMUB to process command
 243         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 244                 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {
 245                         do {
 246                                 status = dmub_srv_wait_for_idle(dmub, 100000);
 247                         } while (status != DMUB_STATUS_OK);
 248                 } else
 249                         status = dmub_srv_wait_for_idle(dmub, 100000);
 250
 251                 if (status != DMUB_STATUS_OK) {
 252                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 253                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 254                         return false;
 255                 }
 256
 257                 // Copy data back from ring buffer into command
 258                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 259                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 260         }
 261
 262         return true;
 263 }
 264
 265 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
 266 {
 267         struct dmub_srv *dmub;
 268         struct dc_context *dc_ctx;
 269         union dmub_fw_boot_status boot_status;
 270         enum dmub_status status;
 271
 272         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 273                 return false;
 274
 275         dmub = dc_dmub_srv->dmub;
 276         dc_ctx = dc_dmub_srv->ctx;
 277
 278         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 279         if (status != DMUB_STATUS_OK) {
 280                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 281                 return false;
 282         }
 283
 284         return boot_status.bits.optimized_init_done;
 285 }
 286
 287 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 288                                     unsigned int stream_mask)
 289 {
 290         struct dmub_srv *dmub;
 291         const uint32_t timeout = 30;
 292
 293         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 294                 return false;
 295
 296         dmub = dc_dmub_srv->dmub;
 297
 298         return dmub_srv_send_gpint_command(
 299                        dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
 300                        stream_mask, timeout) == DMUB_STATUS_OK;
 301 }
 302
 303 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
 304 {
 305         struct dmub_srv *dmub;
 306         struct dc_context *dc_ctx;
 307         union dmub_fw_boot_status boot_status;
 308         enum dmub_status status;
 309
 310         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 311                 return false;
 312
 313         dmub = dc_dmub_srv->dmub;
 314         dc_ctx = dc_dmub_srv->ctx;
 315
 316         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 317         if (status != DMUB_STATUS_OK) {
 318                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 319                 return false;
 320         }
 321
 322         return boot_status.bits.restore_required;
 323 }
 324
 325 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
 326 {
 327         struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
 328         return dmub_srv_get_outbox0_msg(dmub, entry);
 329 }
 330
 331 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
 332 {
 333         dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
 334 }
 335
 336 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
 337 {
 338         union dmub_rb_cmd cmd = { 0 };
 339
 340         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 341         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
 342         cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
 343         cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
 344         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 345
 346         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 347
 348         // Send the command to the DMCUB.
 349         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 350 }
 351
 352 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
 353 {
 354         union dmub_rb_cmd cmd = { 0 };
 355
 356         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 357         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
 358         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 359
 360         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 361
 362         // Send the command to the DMCUB.
 363         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 364 }
 365
 366 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
 367 {
 368         uint8_t pipes = 0;
 369         int i = 0;
 370
 371         for (i = 0; i < MAX_PIPES; i++) {
 372                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 373
 374                 if (pipe->stream == stream && pipe->stream_res.tg)
 375                         pipes = i;
 376         }
 377         return pipes;
 378 }
 379
 380 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
 381                 struct pipe_ctx *head_pipe,
 382                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
 383 {
 384         int j;
 385         int pipe_idx = 0;
 386
 387         fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
 388         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 389                 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
 390
 391                 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
 392                         fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
 393                 }
 394         }
 395         fams_pipe_data->pipe_count = pipe_idx;
 396 }
 397
 398 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
 399 {
 400         union dmub_rb_cmd cmd = { 0 };
 401         struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
 402         int i = 0, k = 0;
 403         int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
 404         uint8_t visual_confirm_enabled;
 405         int pipe_idx = 0;
 406
 407         if (dc == NULL)
 408                 return false;
 409
 410         visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
 411
 412         // Format command.
 413         cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 414         cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
 415         cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
 416         cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
 417
 418         if (should_manage_pstate) {
 419                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 420                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 421
 422                         if (!pipe->stream)
 423                                 continue;
 424
 425                         /* If FAMS is being used to support P-State and there is a stream
 426                          * that does not use FAMS, we are in an FPO + VActive scenario.
 427                          * Assign vactive stretch margin in this case.
 428                          */
 429                         if (!pipe->stream->fpo_in_use) {
 430                                 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
 431                                 break;
 432                         }
 433                         pipe_idx++;
 434                 }
 435         }
 436
 437         for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
 438                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 439
 440                 if (resource_is_pipe_type(pipe, OTG_MASTER) && pipe->stream->fpo_in_use) {
 441                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 442                         uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
 443
 444                         config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
 445                         config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
 446                         config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
 447                         config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
 448                         dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
 449                         k++;
 450                 }
 451         }
 452         cmd.fw_assisted_mclk_switch.header.payload_bytes =
 453                 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
 454
 455         // Send the command to the DMCUB.
 456         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 457
 458         return true;
 459 }
 460
 461 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
 462 {
 463         union dmub_rb_cmd cmd = { 0 };
 464
 465         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
 466                 return;
 467
 468         memset(&cmd, 0, sizeof(cmd));
 469
 470         /* Prepare fw command */
 471         cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
 472         cmd.query_feature_caps.header.sub_type = 0;
 473         cmd.query_feature_caps.header.ret_status = 1;
 474         cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
 475
 476         /* If command was processed, copy feature caps to dmub srv */
 477         if (dm_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 478             cmd.query_feature_caps.header.ret_status == 0) {
 479                 memcpy(&dc_dmub_srv->dmub->feature_caps,
 480                        &cmd.query_feature_caps.query_feature_caps_data,
 481                        sizeof(struct dmub_feature_caps));
 482         }
 483 }
 484
 485 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
 486 {
 487         union dmub_rb_cmd cmd = { 0 };
 488         unsigned int panel_inst = 0;
 489
 490         dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
 491
 492         memset(&cmd, 0, sizeof(cmd));
 493
 494         // Prepare fw command
 495         cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
 496         cmd.visual_confirm_color.header.sub_type = 0;
 497         cmd.visual_confirm_color.header.ret_status = 1;
 498         cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
 499         cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
 500
 501         // If command was processed, copy feature caps to dmub srv
 502         if (dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 503                 cmd.visual_confirm_color.header.ret_status == 0) {
 504                 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
 505                         &cmd.visual_confirm_color.visual_confirm_color_data,
 506                         sizeof(struct dmub_visual_confirm_color));
 507         }
 508 }
 509
 510 /**
 511  * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
 512  *
 513  * @dc: [in] current dc state
 514  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 515  * @vblank_pipe: [in] pipe_ctx for the DRR pipe
 516  * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
 517  *
 518  * Populate the DMCUB SubVP command with DRR pipe info. All the information
 519  * required for calculating the SubVP + DRR microschedule is populated here.
 520  *
 521  * High level algorithm:
 522  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 523  * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
 524  * 3. Populate the drr_info with the min and max supported vtotal values
 525  */
 526 static void populate_subvp_cmd_drr_info(struct dc *dc,
 527                 struct pipe_ctx *subvp_pipe,
 528                 struct pipe_ctx *vblank_pipe,
 529                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
 530 {
 531         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 532         struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 533         struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
 534         uint16_t drr_frame_us = 0;
 535         uint16_t min_drr_supported_us = 0;
 536         uint16_t max_drr_supported_us = 0;
 537         uint16_t max_drr_vblank_us = 0;
 538         uint16_t max_drr_mallregion_us = 0;
 539         uint16_t mall_region_us = 0;
 540         uint16_t prefetch_us = 0;
 541         uint16_t subvp_active_us = 0;
 542         uint16_t drr_active_us = 0;
 543         uint16_t min_vtotal_supported = 0;
 544         uint16_t max_vtotal_supported = 0;
 545
 546         pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
 547         pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
 548         pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
 549
 550         drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
 551                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 552         // P-State allow width and FW delays already included phantom_timing->v_addressable
 553         mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
 554                         (((uint64_t)phantom_timing->pix_clk_100hz * 100)));
 555         min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 556         min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
 557                         (((uint64_t)drr_timing->h_total * 1000000)));
 558
 559         prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
 560                         (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 561         subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
 562                         (((uint64_t)main_timing->pix_clk_100hz * 100)));
 563         drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
 564                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 565         max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
 566                         dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
 567         max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
 568         max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
 569         max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
 570                         (((uint64_t)drr_timing->h_total * 1000000)));
 571
 572         /* When calculating the max vtotal supported for SubVP + DRR cases, add
 573          * margin due to possible rounding errors (being off by 1 line in the
 574          * FW calculation can incorrectly push the P-State switch to wait 1 frame
 575          * longer).
 576          */
 577         max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
 578
 579         pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
 580         pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
 581         pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
 582 }
 583
 584 /**
 585  * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
 586  *
 587  * @dc: [in] current dc state
 588  * @context: [in] new dc state
 589  * @cmd: [in] DMUB cmd to be populated with SubVP info
 590  * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
 591  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 592  *
 593  * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
 594  * required to calculate the microschedule for SubVP + VBLANK case is stored in
 595  * the pipe_data (subvp_data and vblank_data).  Also check if the VBLANK pipe
 596  * is a DRR display -- if it is make a call to populate drr_info.
 597  */
 598 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
 599                 struct dc_state *context,
 600                 union dmub_rb_cmd *cmd,
 601                 struct pipe_ctx *vblank_pipe,
 602                 uint8_t cmd_pipe_index)
 603 {
 604         uint32_t i;
 605         struct pipe_ctx *pipe = NULL;
 606         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 607                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 608
 609         // Find the SubVP pipe
 610         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 611                 pipe = &context->res_ctx.pipe_ctx[i];
 612
 613                 // We check for master pipe, but it shouldn't matter since we only need
 614                 // the pipe for timing info (stream should be same for any pipe splits)
 615                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 616                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 617                         continue;
 618
 619                 // Find the SubVP pipe
 620                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 621                         break;
 622         }
 623
 624         pipe_data->mode = VBLANK;
 625         pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
 626         pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
 627                                                         vblank_pipe->stream->timing.v_front_porch;
 628         pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
 629         pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
 630         pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
 631         pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
 632         pipe_data->pipe_config.vblank_data.vblank_end =
 633                         vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
 634
 635         if (vblank_pipe->stream->ignore_msa_timing_param &&
 636                 (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))
 637                 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
 638 }
 639
 640 /**
 641  * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
 642  *
 643  * @dc: [in] current dc state
 644  * @context: [in] new dc state
 645  * @cmd: [in] DMUB cmd to be populated with SubVP info
 646  * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
 647  *
 648  * For SubVP + SubVP, we use a single vertical interrupt to start the
 649  * microschedule for both SubVP pipes. In order for this to work correctly, the
 650  * MALL REGION of both SubVP pipes must start at the same time. This function
 651  * lengthens the prefetch end to mall start delay of the SubVP pipe that has
 652  * the shorter prefetch so that both MALL REGION's will start at the same time.
 653  */
 654 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 655                 struct dc_state *context,
 656                 union dmub_rb_cmd *cmd,
 657                 struct pipe_ctx *subvp_pipes[])
 658 {
 659         uint32_t subvp0_prefetch_us = 0;
 660         uint32_t subvp1_prefetch_us = 0;
 661         uint32_t prefetch_delta_us = 0;
 662         struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing;
 663         struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
 664         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
 665
 666         subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
 667                         (uint64_t)phantom_timing0->h_total * 1000000),
 668                         (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 669         subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
 670                         (uint64_t)phantom_timing1->h_total * 1000000),
 671                         (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 672
 673         // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
 674         // should increase it's prefetch time to match the other
 675         if (subvp0_prefetch_us > subvp1_prefetch_us) {
 676                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
 677                 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
 678                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 679                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 680                                         ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
 681                                         ((uint64_t)phantom_timing1->h_total * 1000000));
 682
 683         } else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
 684                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
 685                 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
 686                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 687                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 688                                         ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
 689                                         ((uint64_t)phantom_timing0->h_total * 1000000));
 690         }
 691 }
 692
 693 /**
 694  * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
 695  *
 696  * @dc: [in] current dc state
 697  * @context: [in] new dc state
 698  * @cmd: [in] DMUB cmd to be populated with SubVP info
 699  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 700  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 701  *
 702  * Populate the DMCUB SubVP command with SubVP pipe info. All the information
 703  * required to calculate the microschedule for the SubVP pipe is stored in the
 704  * pipe_data of the DMCUB SubVP command.
 705  */
 706 static void populate_subvp_cmd_pipe_info(struct dc *dc,
 707                 struct dc_state *context,
 708                 union dmub_rb_cmd *cmd,
 709                 struct pipe_ctx *subvp_pipe,
 710                 uint8_t cmd_pipe_index)
 711 {
 712         uint32_t j;
 713         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 714                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 715         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 716         struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 717         uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
 718
 719         pipe_data->mode = SUBVP;
 720         pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
 721         pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
 722         pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
 723         pipe_data->pipe_config.subvp_data.main_vblank_start =
 724                         main_timing->v_total - main_timing->v_front_porch;
 725         pipe_data->pipe_config.subvp_data.main_vblank_end =
 726                         main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
 727         pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
 728         pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
 729         pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
 730                 (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
 731
 732         /* Calculate the scaling factor from the src and dst height.
 733          * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
 734          * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
 735          *
 736          * Make sure to combine stream and plane scaling together.
 737          */
 738         reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
 739                         &out_num_stream, &out_den_stream);
 740         reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
 741                         &out_num_plane, &out_den_plane);
 742         reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
 743         pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
 744         pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
 745
 746         // Prefetch lines is equal to VACTIVE + BP + VSYNC
 747         pipe_data->pipe_config.subvp_data.prefetch_lines =
 748                         phantom_timing->v_total - phantom_timing->v_front_porch;
 749
 750         // Round up
 751         pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 752                         div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 753                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 754         pipe_data->pipe_config.subvp_data.processing_delay_lines =
 755                         div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 756                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 757
 758         if (subvp_pipe->bottom_pipe) {
 759                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
 760         } else if (subvp_pipe->next_odm_pipe) {
 761                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
 762         } else {
 763                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
 764         }
 765
 766         // Find phantom pipe index based on phantom stream
 767         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 768                 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
 769
 770                 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) {
 771                         pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
 772                         if (phantom_pipe->bottom_pipe) {
 773                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
 774                         } else if (phantom_pipe->next_odm_pipe) {
 775                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
 776                         } else {
 777                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
 778                         }
 779                         break;
 780                 }
 781         }
 782 }
 783
 784 /**
 785  * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
 786  *
 787  * @dc: [in] current dc state
 788  * @context: [in] new dc state
 789  * @enable: [in] if true enables the pipes population
 790  *
 791  * This function loops through each pipe and populates the DMUB SubVP CMD info
 792  * based on the pipe (e.g. SubVP, VBLANK).
 793  */
 794 void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
 795                 struct dc_state *context,
 796                 bool enable)
 797 {
 798         uint8_t cmd_pipe_index = 0;
 799         uint32_t i, pipe_idx;
 800         uint8_t subvp_count = 0;
 801         union dmub_rb_cmd cmd;
 802         struct pipe_ctx *subvp_pipes[2];
 803         uint32_t wm_val_refclk = 0;
 804
 805         memset(&cmd, 0, sizeof(cmd));
 806         // FW command for SUBVP
 807         cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 808         cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
 809         cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
 810                         sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
 811
 812         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 813                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 814
 815                 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe
 816                  */
 817                 if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 818                                 resource_is_pipe_type(pipe, DPP_PIPE) &&
 819                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 820                         subvp_pipes[subvp_count++] = pipe;
 821         }
 822
 823         if (enable) {
 824                 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
 825                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 826                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 827
 828                         if (!pipe->stream)
 829                                 continue;
 830
 831                         /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
 832                          * Any ODM or MPC splits being used in SubVP will be handled internally in
 833                          * populate_subvp_cmd_pipe_info
 834                          */
 835                         if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 836                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 837                                         pipe->stream->mall_stream_config.paired_stream &&
 838                                         pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 839                                 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 840                         } else if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 841                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 842                                         pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 843                                 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
 844                                 // we run through DML without calculating "natural" P-state support
 845                                 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 846
 847                         }
 848                         pipe_idx++;
 849                 }
 850                 if (subvp_count == 2) {
 851                         update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
 852                 }
 853                 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
 854                 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
 855
 856                 // Store the original watermark value for this SubVP config so we can lower it when the
 857                 // MCLK switch starts
 858                 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
 859                                 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
 860
 861                 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
 862         }
 863
 864         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 865 }
 866
 867 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
 868 {
 869         if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
 870                 return false;
 871         return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
 872 }
 873
 874 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
 875 {
 876         struct dmub_diagnostic_data diag_data = {0};
 877
 878         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
 879                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
 880                 return;
 881         }
 882
 883         if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
 884                 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
 885                 return;
 886         }
 887
 888         DC_LOG_DEBUG("DMCUB STATE:");
 889         DC_LOG_DEBUG("    dmcub_version      : %08x", diag_data.dmcub_version);
 890         DC_LOG_DEBUG("    scratch  [0]       : %08x", diag_data.scratch[0]);
 891         DC_LOG_DEBUG("    scratch  [1]       : %08x", diag_data.scratch[1]);
 892         DC_LOG_DEBUG("    scratch  [2]       : %08x", diag_data.scratch[2]);
 893         DC_LOG_DEBUG("    scratch  [3]       : %08x", diag_data.scratch[3]);
 894         DC_LOG_DEBUG("    scratch  [4]       : %08x", diag_data.scratch[4]);
 895         DC_LOG_DEBUG("    scratch  [5]       : %08x", diag_data.scratch[5]);
 896         DC_LOG_DEBUG("    scratch  [6]       : %08x", diag_data.scratch[6]);
 897         DC_LOG_DEBUG("    scratch  [7]       : %08x", diag_data.scratch[7]);
 898         DC_LOG_DEBUG("    scratch  [8]       : %08x", diag_data.scratch[8]);
 899         DC_LOG_DEBUG("    scratch  [9]       : %08x", diag_data.scratch[9]);
 900         DC_LOG_DEBUG("    scratch [10]       : %08x", diag_data.scratch[10]);
 901         DC_LOG_DEBUG("    scratch [11]       : %08x", diag_data.scratch[11]);
 902         DC_LOG_DEBUG("    scratch [12]       : %08x", diag_data.scratch[12]);
 903         DC_LOG_DEBUG("    scratch [13]       : %08x", diag_data.scratch[13]);
 904         DC_LOG_DEBUG("    scratch [14]       : %08x", diag_data.scratch[14]);
 905         DC_LOG_DEBUG("    scratch [15]       : %08x", diag_data.scratch[15]);
 906         DC_LOG_DEBUG("    pc                 : %08x", diag_data.pc);
 907         DC_LOG_DEBUG("    unk_fault_addr     : %08x", diag_data.undefined_address_fault_addr);
 908         DC_LOG_DEBUG("    inst_fault_addr    : %08x", diag_data.inst_fetch_fault_addr);
 909         DC_LOG_DEBUG("    data_fault_addr    : %08x", diag_data.data_write_fault_addr);
 910         DC_LOG_DEBUG("    inbox1_rptr        : %08x", diag_data.inbox1_rptr);
 911         DC_LOG_DEBUG("    inbox1_wptr        : %08x", diag_data.inbox1_wptr);
 912         DC_LOG_DEBUG("    inbox1_size        : %08x", diag_data.inbox1_size);
 913         DC_LOG_DEBUG("    inbox0_rptr        : %08x", diag_data.inbox0_rptr);
 914         DC_LOG_DEBUG("    inbox0_wptr        : %08x", diag_data.inbox0_wptr);
 915         DC_LOG_DEBUG("    inbox0_size        : %08x", diag_data.inbox0_size);
 916         DC_LOG_DEBUG("    is_enabled         : %d", diag_data.is_dmcub_enabled);
 917         DC_LOG_DEBUG("    is_soft_reset      : %d", diag_data.is_dmcub_soft_reset);
 918         DC_LOG_DEBUG("    is_secure_reset    : %d", diag_data.is_dmcub_secure_reset);
 919         DC_LOG_DEBUG("    is_traceport_en    : %d", diag_data.is_traceport_en);
 920         DC_LOG_DEBUG("    is_cw0_en          : %d", diag_data.is_cw0_enabled);
 921         DC_LOG_DEBUG("    is_cw6_en          : %d", diag_data.is_cw6_enabled);
 922 }
 923
 924 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 925 {
 926         struct pipe_ctx *test_pipe, *split_pipe;
 927         const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
 928         struct rect r1 = scl_data->recout, r2, r2_half;
 929         int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
 930         int cur_layer = pipe_ctx->plane_state->layer_index;
 931
 932         /**
 933          * Disable the cursor if there's another pipe above this with a
 934          * plane that contains this pipe's viewport to prevent double cursor
 935          * and incorrect scaling artifacts.
 936          */
 937         for (test_pipe = pipe_ctx->top_pipe; test_pipe;
 938              test_pipe = test_pipe->top_pipe) {
 939                 // Skip invisible layer and pipe-split plane on same layer
 940                 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
 941                         continue;
 942
 943                 r2 = test_pipe->plane_res.scl_data.recout;
 944                 r2_r = r2.x + r2.width;
 945                 r2_b = r2.y + r2.height;
 946                 split_pipe = test_pipe;
 947
 948                 /**
 949                  * There is another half plane on same layer because of
 950                  * pipe-split, merge together per same height.
 951                  */
 952                 for (split_pipe = pipe_ctx->top_pipe; split_pipe;
 953                      split_pipe = split_pipe->top_pipe)
 954                         if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
 955                                 r2_half = split_pipe->plane_res.scl_data.recout;
 956                                 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
 957                                 r2.width = r2.width + r2_half.width;
 958                                 r2_r = r2.x + r2.width;
 959                                 break;
 960                         }
 961
 962                 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
 963                         return true;
 964         }
 965
 966         return false;
 967 }
 968
 969 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
 970 {
 971         if (pipe_ctx->plane_state != NULL) {
 972                 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
 973                         return false;
 974
 975                 if (dc_can_pipe_disable_cursor(pipe_ctx))
 976                         return false;
 977         }
 978
 979         if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
 980                 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
 981                 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
 982                 return true;
 983
 984         if (pipe_ctx->stream->link->replay_settings.config.replay_supported)
 985                 return true;
 986
 987         return false;
 988 }
 989
 990 static void dc_build_cursor_update_payload0(
 991                 struct pipe_ctx *pipe_ctx, uint8_t p_idx,
 992                 struct dmub_cmd_update_cursor_payload0 *payload)
 993 {
 994         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 995         unsigned int panel_inst = 0;
 996
 997         if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
 998                 pipe_ctx->stream->link, &panel_inst))
 999                 return;
1000
1001         /* Payload: Cursor Rect is built from position & attribute
1002          * x & y are obtained from postion
1003          */
1004         payload->cursor_rect.x = hubp->cur_rect.x;
1005         payload->cursor_rect.y = hubp->cur_rect.y;
1006         /* w & h are obtained from attribute */
1007         payload->cursor_rect.width  = hubp->cur_rect.w;
1008         payload->cursor_rect.height = hubp->cur_rect.h;
1009
1010         payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
1011         payload->pipe_idx    = p_idx;
1012         payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
1013         payload->panel_inst  = panel_inst;
1014 }
1015
1016 static void dc_build_cursor_position_update_payload0(
1017                 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
1018                 const struct hubp *hubp, const struct dpp *dpp)
1019 {
1020         /* Hubp */
1021         pl->position_cfg.pHubp.cur_ctl.raw  = hubp->pos.cur_ctl.raw;
1022         pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
1023         pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
1024         pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
1025
1026         /* dpp */
1027         pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
1028         pl->position_cfg.pipe_idx = p_idx;
1029 }
1030
1031 static void dc_build_cursor_attribute_update_payload1(
1032                 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
1033                 const struct hubp *hubp, const struct dpp *dpp)
1034 {
1035         /* Hubp */
1036         pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
1037         pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
1038         pl_A->aHubp.cur_ctl.raw  = hubp->att.cur_ctl.raw;
1039         pl_A->aHubp.size.raw     = hubp->att.size.raw;
1040         pl_A->aHubp.settings.raw = hubp->att.settings.raw;
1041
1042         /* dpp */
1043         pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
1044 }
1045
1046 /**
1047  * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
1048  *
1049  * @pCtx: [in] pipe context
1050  * @pipe_idx: [in] pipe index
1051  *
1052  * This function would store the cursor related information and pass it into
1053  * dmub
1054  */
1055 void dc_send_update_cursor_info_to_dmu(
1056                 struct pipe_ctx *pCtx, uint8_t pipe_idx)
1057 {
1058         union dmub_rb_cmd cmd[2];
1059         union dmub_cmd_update_cursor_info_data *update_cursor_info_0 =
1060                                         &cmd[0].update_cursor_info.update_cursor_info_data;
1061
1062         memset(cmd, 0, sizeof(cmd));
1063
1064         if (!dc_dmub_should_update_cursor_data(pCtx))
1065                 return;
1066         /*
1067          * Since we use multi_cmd_pending for dmub command, the 2nd command is
1068          * only assigned to store cursor attributes info.
1069          * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
1070          * is to store cursor position info.
1071          *
1072          * Command heaer type must be the same type if using  multi_cmd_pending.
1073          * Besides, while process 2nd command in DMU, the sub type is useless.
1074          * So it's meanless to pass the sub type header with different type.
1075          */
1076
1077         {
1078                 /* Build Payload#0 Header */
1079                 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1080                 cmd[0].update_cursor_info.header.payload_bytes =
1081                                 sizeof(cmd[0].update_cursor_info.update_cursor_info_data);
1082                 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd
1083
1084                 /* Prepare Payload */
1085                 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0);
1086
1087                 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx,
1088                                 pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1089                 }
1090         {
1091                 /* Build Payload#1 Header */
1092                 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1093                 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1094                 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command.
1095
1096                 dc_build_cursor_attribute_update_payload1(
1097                                 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1098                                 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1099
1100                 /* Combine 2nd cmds update_curosr_info to DMU */
1101                 dm_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);
1102         }
1103 }
1104
1105 bool dc_dmub_check_min_version(struct dmub_srv *srv)
1106 {
1107         if (!srv->hw_funcs.is_psrsu_supported)
1108                 return true;
1109         return srv->hw_funcs.is_psrsu_supported(srv);
1110 }
1111
1112 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)
1113 {
1114         struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1115         struct dmub_srv *dmub;
1116         enum dmub_status status;
1117         static const uint32_t timeout_us = 30;
1118
1119         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
1120                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
1121                 return;
1122         }
1123
1124         dmub = dc_dmub_srv->dmub;
1125
1126         status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 0x0010, timeout_us);
1127         if (status != DMUB_STATUS_OK) {
1128                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1129                 return;
1130         }
1131
1132         status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 0x0000, timeout_us);
1133         if (status != DMUB_STATUS_OK) {
1134                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1135                 return;
1136         }
1137
1138         DC_LOG_DEBUG("Enabled DPIA trace\n");
1139 }
1140
1141 void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index)
1142 {
1143         dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index);
1144 }
1145
1146 bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)
1147 {
1148         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
1149         enum dmub_status status;
1150
1151         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
1152                 return true;
1153
1154         if (wait) {
1155                 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {
1156                         do {
1157                                 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);
1158                         } while (status != DMUB_STATUS_OK);
1159                 } else {
1160                         status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);
1161                         if (status != DMUB_STATUS_OK) {
1162                                 DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status);
1163                                 return false;
1164                         }
1165                 }
1166         } else
1167                 return dmub_srv_is_hw_pwr_up(dc_dmub_srv->dmub);
1168
1169         return true;
1170 }
1171
1172 void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
1173 {
1174         union dmub_rb_cmd cmd = {0};
1175
1176         if (dc->debug.dmcub_emulation)
1177                 return;
1178
1179         memset(&cmd, 0, sizeof(cmd));
1180         cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
1181         cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE;
1182         cmd.idle_opt_notify_idle.header.payload_bytes =
1183                 sizeof(cmd.idle_opt_notify_idle) -
1184                 sizeof(cmd.idle_opt_notify_idle.header);
1185
1186         cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
1187
1188         if (allow_idle) {
1189                 if (dc->hwss.set_idle_state)
1190                         dc->hwss.set_idle_state(dc, true);
1191         }
1192
1193         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
1194 }
1195
1196 void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
1197 {
1198         const uint32_t max_num_polls = 10000;
1199         uint32_t allow_state = 0;
1200         uint32_t commit_state = 0;
1201         int i;
1202
1203         if (dc->debug.dmcub_emulation)
1204                 return;
1205
1206         if (!dc->idle_optimizations_allowed)
1207                 return;
1208
1209         if (dc->hwss.get_idle_state &&
1210                 dc->hwss.set_idle_state &&
1211                 dc->clk_mgr->funcs->exit_low_power_state) {
1212
1213                 allow_state = dc->hwss.get_idle_state(dc);
1214                 dc->hwss.set_idle_state(dc, false);
1215
1216                 if (!(allow_state & DMUB_IPS2_ALLOW_MASK)) {
1217                         // Wait for evaluation time
1218                         udelay(dc->debug.ips2_eval_delay_us);
1219                         commit_state = dc->hwss.get_idle_state(dc);
1220                         if (!(commit_state & DMUB_IPS2_COMMIT_MASK)) {
1221                                 // Tell PMFW to exit low power state
1222                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1223
1224                                 // Wait for IPS2 entry upper bound
1225                                 udelay(dc->debug.ips2_entry_delay_us);
1226                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1227
1228                                 for (i = 0; i < max_num_polls; ++i) {
1229                                         commit_state = dc->hwss.get_idle_state(dc);
1230                                         if (commit_state & DMUB_IPS2_COMMIT_MASK)
1231                                                 break;
1232
1233                                         udelay(1);
1234
1235                                         if (dc->debug.disable_timeout)
1236                                                 i--;
1237                                 }
1238                                 ASSERT(i < max_num_polls);
1239
1240                                 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1241                                         ASSERT(0);
1242
1243                                 /* TODO: See if we can return early here - IPS2 should go
1244                                  * back directly to IPS0 and clear the flags, but it will
1245                                  * be safer to directly notify DMCUB of this.
1246                                  */
1247                                 allow_state = dc->hwss.get_idle_state(dc);
1248                         }
1249                 }
1250
1251                 dc_dmub_srv_notify_idle(dc, false);
1252                 if (!(allow_state & DMUB_IPS1_ALLOW_MASK)) {
1253                         for (i = 0; i < max_num_polls; ++i) {
1254                                 commit_state = dc->hwss.get_idle_state(dc);
1255                                 if (commit_state & DMUB_IPS1_COMMIT_MASK)
1256                                         break;
1257
1258                                 udelay(1);
1259
1260                                 if (dc->debug.disable_timeout)
1261                                         i--;
1262                         }
1263                         ASSERT(i < max_num_polls);
1264                 }
1265         }
1266
1267         if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1268                 ASSERT(0);
1269 }
1270