drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc.h"
  27 #include "dc_dmub_srv.h"
  28 #include "../dmub/dmub_srv.h"
  29 #include "dm_helpers.h"
  30 #include "dc_hw_types.h"
  31 #include "core_types.h"
  32 #include "../basics/conversion.h"
  33 #include "cursor_reg_cache.h"
  34 #include "resource.h"
  35 #include "clk_mgr.h"
  36
  37 #define CTX dc_dmub_srv->ctx
  38 #define DC_LOGGER CTX->logger
  39
  40 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
  41                                   struct dmub_srv *dmub)
  42 {
  43         dc_srv->dmub = dmub;
  44         dc_srv->ctx = dc->ctx;
  45 }
  46
  47 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
  48 {
  49         struct dc_dmub_srv *dc_srv =
  50                 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
  51
  52         if (dc_srv == NULL) {
  53                 BREAK_TO_DEBUGGER();
  54                 return NULL;
  55         }
  56
  57         dc_dmub_srv_construct(dc_srv, dc, dmub);
  58
  59         return dc_srv;
  60 }
  61
  62 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
  63 {
  64         if (*dmub_srv) {
  65                 kfree(*dmub_srv);
  66                 *dmub_srv = NULL;
  67         }
  68 }
  69
  70 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
  71 {
  72         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  73         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  74         enum dmub_status status;
  75
  76         status = dmub_srv_wait_for_idle(dmub, 100000);
  77         if (status != DMUB_STATUS_OK) {
  78                 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
  79                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  80         }
  81 }
  82
  83 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  84 {
  85         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  86         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  87         enum dmub_status status = DMUB_STATUS_OK;
  88
  89         status = dmub_srv_clear_inbox0_ack(dmub);
  90         if (status != DMUB_STATUS_OK) {
  91                 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
  92                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  93         }
  94 }
  95
  96 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  97 {
  98         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  99         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 100         enum dmub_status status = DMUB_STATUS_OK;
 101
 102         status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
 103         if (status != DMUB_STATUS_OK) {
 104                 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
 105                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 106         }
 107 }
 108
 109 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv,
 110                                  union dmub_inbox0_data_register data)
 111 {
 112         struct dmub_srv *dmub = dc_dmub_srv->dmub;
 113         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 114         enum dmub_status status = DMUB_STATUS_OK;
 115
 116         status = dmub_srv_send_inbox0_cmd(dmub, data);
 117         if (status != DMUB_STATUS_OK) {
 118                 DC_ERROR("Error sending INBOX0 cmd\n");
 119                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 120         }
 121 }
 122
 123 bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
 124                 unsigned int count,
 125                 union dmub_rb_cmd *cmd_list)
 126 {
 127         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 128         struct dmub_srv *dmub;
 129         enum dmub_status status;
 130         int i;
 131
 132         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 133                 return false;
 134
 135         dmub = dc_dmub_srv->dmub;
 136
 137         for (i = 0 ; i < count; i++) {
 138                 // Queue command
 139                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 140
 141                 if (status == DMUB_STATUS_QUEUE_FULL) {
 142                         /* Execute and wait for queue to become empty again. */
 143                         dmub_srv_cmd_execute(dmub);
 144                         dmub_srv_wait_for_idle(dmub, 100000);
 145
 146                         /* Requeue the command. */
 147                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 148                 }
 149
 150                 if (status != DMUB_STATUS_OK) {
 151                         DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 152                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 153                         return false;
 154                 }
 155         }
 156
 157         status = dmub_srv_cmd_execute(dmub);
 158         if (status != DMUB_STATUS_OK) {
 159                 DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 160                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 161                 return false;
 162         }
 163
 164         return true;
 165 }
 166
 167 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
 168                 enum dm_dmub_wait_type wait_type,
 169                 union dmub_rb_cmd *cmd_list)
 170 {
 171         struct dmub_srv *dmub;
 172         enum dmub_status status;
 173
 174         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 175                 return false;
 176
 177         dmub = dc_dmub_srv->dmub;
 178
 179         // Wait for DMUB to process command
 180         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 181                 status = dmub_srv_wait_for_idle(dmub, 100000);
 182
 183                 if (status != DMUB_STATUS_OK) {
 184                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 185                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 186                         return false;
 187                 }
 188
 189                 // Copy data back from ring buffer into command
 190                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 191                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 192         }
 193
 194         return true;
 195 }
 196
 197 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
 198 {
 199         return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);
 200 }
 201
 202 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
 203 {
 204         struct dc_context *dc_ctx;
 205         struct dmub_srv *dmub;
 206         enum dmub_status status;
 207         int i;
 208
 209         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 210                 return false;
 211
 212         dc_ctx = dc_dmub_srv->ctx;
 213         dmub = dc_dmub_srv->dmub;
 214
 215         for (i = 0 ; i < count; i++) {
 216                 // Queue command
 217                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 218
 219                 if (status == DMUB_STATUS_QUEUE_FULL) {
 220                         /* Execute and wait for queue to become empty again. */
 221                         dmub_srv_cmd_execute(dmub);
 222                         dmub_srv_wait_for_idle(dmub, 100000);
 223
 224                         /* Requeue the command. */
 225                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 226                 }
 227
 228                 if (status != DMUB_STATUS_OK) {
 229                         DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 230                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 231                         return false;
 232                 }
 233         }
 234
 235         status = dmub_srv_cmd_execute(dmub);
 236         if (status != DMUB_STATUS_OK) {
 237                 DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 238                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 239                 return false;
 240         }
 241
 242         // Wait for DMUB to process command
 243         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 244                 status = dmub_srv_wait_for_idle(dmub, 100000);
 245
 246                 if (status != DMUB_STATUS_OK) {
 247                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 248                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 249                         return false;
 250                 }
 251
 252                 // Copy data back from ring buffer into command
 253                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 254                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 255         }
 256
 257         return true;
 258 }
 259
 260 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
 261 {
 262         struct dmub_srv *dmub;
 263         struct dc_context *dc_ctx;
 264         union dmub_fw_boot_status boot_status;
 265         enum dmub_status status;
 266
 267         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 268                 return false;
 269
 270         dmub = dc_dmub_srv->dmub;
 271         dc_ctx = dc_dmub_srv->ctx;
 272
 273         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 274         if (status != DMUB_STATUS_OK) {
 275                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 276                 return false;
 277         }
 278
 279         return boot_status.bits.optimized_init_done;
 280 }
 281
 282 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 283                                     unsigned int stream_mask)
 284 {
 285         struct dmub_srv *dmub;
 286         const uint32_t timeout = 30;
 287
 288         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 289                 return false;
 290
 291         dmub = dc_dmub_srv->dmub;
 292
 293         return dmub_srv_send_gpint_command(
 294                        dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
 295                        stream_mask, timeout) == DMUB_STATUS_OK;
 296 }
 297
 298 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
 299 {
 300         struct dmub_srv *dmub;
 301         struct dc_context *dc_ctx;
 302         union dmub_fw_boot_status boot_status;
 303         enum dmub_status status;
 304
 305         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 306                 return false;
 307
 308         dmub = dc_dmub_srv->dmub;
 309         dc_ctx = dc_dmub_srv->ctx;
 310
 311         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 312         if (status != DMUB_STATUS_OK) {
 313                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 314                 return false;
 315         }
 316
 317         return boot_status.bits.restore_required;
 318 }
 319
 320 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
 321 {
 322         struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
 323         return dmub_srv_get_outbox0_msg(dmub, entry);
 324 }
 325
 326 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
 327 {
 328         dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
 329 }
 330
 331 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
 332 {
 333         union dmub_rb_cmd cmd = { 0 };
 334
 335         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 336         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
 337         cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
 338         cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
 339         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 340
 341         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 342
 343         // Send the command to the DMCUB.
 344         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 345 }
 346
 347 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
 348 {
 349         union dmub_rb_cmd cmd = { 0 };
 350
 351         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 352         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
 353         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 354
 355         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 356
 357         // Send the command to the DMCUB.
 358         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 359 }
 360
 361 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
 362 {
 363         uint8_t pipes = 0;
 364         int i = 0;
 365
 366         for (i = 0; i < MAX_PIPES; i++) {
 367                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 368
 369                 if (pipe->stream == stream && pipe->stream_res.tg)
 370                         pipes = i;
 371         }
 372         return pipes;
 373 }
 374
 375 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
 376                 struct pipe_ctx *head_pipe,
 377                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
 378 {
 379         int j;
 380         int pipe_idx = 0;
 381
 382         fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
 383         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 384                 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
 385
 386                 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
 387                         fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
 388                 }
 389         }
 390         fams_pipe_data->pipe_count = pipe_idx;
 391 }
 392
 393 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
 394 {
 395         union dmub_rb_cmd cmd = { 0 };
 396         struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
 397         int i = 0, k = 0;
 398         int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
 399         uint8_t visual_confirm_enabled;
 400         int pipe_idx = 0;
 401
 402         if (dc == NULL)
 403                 return false;
 404
 405         visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
 406
 407         // Format command.
 408         cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 409         cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
 410         cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
 411         cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
 412
 413         if (should_manage_pstate) {
 414                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 415                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 416
 417                         if (!pipe->stream)
 418                                 continue;
 419
 420                         /* If FAMS is being used to support P-State and there is a stream
 421                          * that does not use FAMS, we are in an FPO + VActive scenario.
 422                          * Assign vactive stretch margin in this case.
 423                          */
 424                         if (!pipe->stream->fpo_in_use) {
 425                                 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
 426                                 break;
 427                         }
 428                         pipe_idx++;
 429                 }
 430         }
 431
 432         for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
 433                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 434
 435                 if (resource_is_pipe_type(pipe, OTG_MASTER) && pipe->stream->fpo_in_use) {
 436                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 437                         uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
 438
 439                         config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
 440                         config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
 441                         config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
 442                         config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
 443                         dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
 444                         k++;
 445                 }
 446         }
 447         cmd.fw_assisted_mclk_switch.header.payload_bytes =
 448                 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
 449
 450         // Send the command to the DMCUB.
 451         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 452
 453         return true;
 454 }
 455
 456 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
 457 {
 458         union dmub_rb_cmd cmd = { 0 };
 459
 460         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
 461                 return;
 462
 463         memset(&cmd, 0, sizeof(cmd));
 464
 465         /* Prepare fw command */
 466         cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
 467         cmd.query_feature_caps.header.sub_type = 0;
 468         cmd.query_feature_caps.header.ret_status = 1;
 469         cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
 470
 471         /* If command was processed, copy feature caps to dmub srv */
 472         if (dm_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 473             cmd.query_feature_caps.header.ret_status == 0) {
 474                 memcpy(&dc_dmub_srv->dmub->feature_caps,
 475                        &cmd.query_feature_caps.query_feature_caps_data,
 476                        sizeof(struct dmub_feature_caps));
 477         }
 478 }
 479
 480 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
 481 {
 482         union dmub_rb_cmd cmd = { 0 };
 483         unsigned int panel_inst = 0;
 484
 485         dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
 486
 487         memset(&cmd, 0, sizeof(cmd));
 488
 489         // Prepare fw command
 490         cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
 491         cmd.visual_confirm_color.header.sub_type = 0;
 492         cmd.visual_confirm_color.header.ret_status = 1;
 493         cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
 494         cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
 495
 496         // If command was processed, copy feature caps to dmub srv
 497         if (dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 498                 cmd.visual_confirm_color.header.ret_status == 0) {
 499                 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
 500                         &cmd.visual_confirm_color.visual_confirm_color_data,
 501                         sizeof(struct dmub_visual_confirm_color));
 502         }
 503 }
 504
 505 /**
 506  * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
 507  *
 508  * @dc: [in] current dc state
 509  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 510  * @vblank_pipe: [in] pipe_ctx for the DRR pipe
 511  * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
 512  *
 513  * Populate the DMCUB SubVP command with DRR pipe info. All the information
 514  * required for calculating the SubVP + DRR microschedule is populated here.
 515  *
 516  * High level algorithm:
 517  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 518  * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
 519  * 3. Populate the drr_info with the min and max supported vtotal values
 520  */
 521 static void populate_subvp_cmd_drr_info(struct dc *dc,
 522                 struct pipe_ctx *subvp_pipe,
 523                 struct pipe_ctx *vblank_pipe,
 524                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
 525 {
 526         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 527         struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 528         struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
 529         uint16_t drr_frame_us = 0;
 530         uint16_t min_drr_supported_us = 0;
 531         uint16_t max_drr_supported_us = 0;
 532         uint16_t max_drr_vblank_us = 0;
 533         uint16_t max_drr_mallregion_us = 0;
 534         uint16_t mall_region_us = 0;
 535         uint16_t prefetch_us = 0;
 536         uint16_t subvp_active_us = 0;
 537         uint16_t drr_active_us = 0;
 538         uint16_t min_vtotal_supported = 0;
 539         uint16_t max_vtotal_supported = 0;
 540
 541         pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
 542         pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
 543         pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
 544
 545         drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
 546                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 547         // P-State allow width and FW delays already included phantom_timing->v_addressable
 548         mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
 549                         (((uint64_t)phantom_timing->pix_clk_100hz * 100)));
 550         min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 551         min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
 552                         (((uint64_t)drr_timing->h_total * 1000000)));
 553
 554         prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
 555                         (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 556         subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
 557                         (((uint64_t)main_timing->pix_clk_100hz * 100)));
 558         drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
 559                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 560         max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
 561                         dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
 562         max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
 563         max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
 564         max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
 565                         (((uint64_t)drr_timing->h_total * 1000000)));
 566
 567         /* When calculating the max vtotal supported for SubVP + DRR cases, add
 568          * margin due to possible rounding errors (being off by 1 line in the
 569          * FW calculation can incorrectly push the P-State switch to wait 1 frame
 570          * longer).
 571          */
 572         max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
 573
 574         pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
 575         pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
 576         pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
 577 }
 578
 579 /**
 580  * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
 581  *
 582  * @dc: [in] current dc state
 583  * @context: [in] new dc state
 584  * @cmd: [in] DMUB cmd to be populated with SubVP info
 585  * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
 586  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 587  *
 588  * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
 589  * required to calculate the microschedule for SubVP + VBLANK case is stored in
 590  * the pipe_data (subvp_data and vblank_data).  Also check if the VBLANK pipe
 591  * is a DRR display -- if it is make a call to populate drr_info.
 592  */
 593 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
 594                 struct dc_state *context,
 595                 union dmub_rb_cmd *cmd,
 596                 struct pipe_ctx *vblank_pipe,
 597                 uint8_t cmd_pipe_index)
 598 {
 599         uint32_t i;
 600         struct pipe_ctx *pipe = NULL;
 601         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 602                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 603
 604         // Find the SubVP pipe
 605         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 606                 pipe = &context->res_ctx.pipe_ctx[i];
 607
 608                 // We check for master pipe, but it shouldn't matter since we only need
 609                 // the pipe for timing info (stream should be same for any pipe splits)
 610                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 611                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 612                         continue;
 613
 614                 // Find the SubVP pipe
 615                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 616                         break;
 617         }
 618
 619         pipe_data->mode = VBLANK;
 620         pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
 621         pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
 622                                                         vblank_pipe->stream->timing.v_front_porch;
 623         pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
 624         pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
 625         pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
 626         pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
 627         pipe_data->pipe_config.vblank_data.vblank_end =
 628                         vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
 629
 630         if (vblank_pipe->stream->ignore_msa_timing_param &&
 631                 (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))
 632                 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
 633 }
 634
 635 /**
 636  * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
 637  *
 638  * @dc: [in] current dc state
 639  * @context: [in] new dc state
 640  * @cmd: [in] DMUB cmd to be populated with SubVP info
 641  * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
 642  *
 643  * For SubVP + SubVP, we use a single vertical interrupt to start the
 644  * microschedule for both SubVP pipes. In order for this to work correctly, the
 645  * MALL REGION of both SubVP pipes must start at the same time. This function
 646  * lengthens the prefetch end to mall start delay of the SubVP pipe that has
 647  * the shorter prefetch so that both MALL REGION's will start at the same time.
 648  */
 649 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 650                 struct dc_state *context,
 651                 union dmub_rb_cmd *cmd,
 652                 struct pipe_ctx *subvp_pipes[])
 653 {
 654         uint32_t subvp0_prefetch_us = 0;
 655         uint32_t subvp1_prefetch_us = 0;
 656         uint32_t prefetch_delta_us = 0;
 657         struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing;
 658         struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
 659         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
 660
 661         subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
 662                         (uint64_t)phantom_timing0->h_total * 1000000),
 663                         (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 664         subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
 665                         (uint64_t)phantom_timing1->h_total * 1000000),
 666                         (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 667
 668         // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
 669         // should increase it's prefetch time to match the other
 670         if (subvp0_prefetch_us > subvp1_prefetch_us) {
 671                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
 672                 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
 673                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 674                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 675                                         ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
 676                                         ((uint64_t)phantom_timing1->h_total * 1000000));
 677
 678         } else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
 679                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
 680                 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
 681                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 682                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 683                                         ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
 684                                         ((uint64_t)phantom_timing0->h_total * 1000000));
 685         }
 686 }
 687
 688 /**
 689  * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
 690  *
 691  * @dc: [in] current dc state
 692  * @context: [in] new dc state
 693  * @cmd: [in] DMUB cmd to be populated with SubVP info
 694  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 695  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 696  *
 697  * Populate the DMCUB SubVP command with SubVP pipe info. All the information
 698  * required to calculate the microschedule for the SubVP pipe is stored in the
 699  * pipe_data of the DMCUB SubVP command.
 700  */
 701 static void populate_subvp_cmd_pipe_info(struct dc *dc,
 702                 struct dc_state *context,
 703                 union dmub_rb_cmd *cmd,
 704                 struct pipe_ctx *subvp_pipe,
 705                 uint8_t cmd_pipe_index)
 706 {
 707         uint32_t j;
 708         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 709                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 710         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 711         struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 712         uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
 713
 714         pipe_data->mode = SUBVP;
 715         pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
 716         pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
 717         pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
 718         pipe_data->pipe_config.subvp_data.main_vblank_start =
 719                         main_timing->v_total - main_timing->v_front_porch;
 720         pipe_data->pipe_config.subvp_data.main_vblank_end =
 721                         main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
 722         pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
 723         pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
 724         pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
 725                 (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
 726
 727         /* Calculate the scaling factor from the src and dst height.
 728          * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
 729          * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
 730          *
 731          * Make sure to combine stream and plane scaling together.
 732          */
 733         reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
 734                         &out_num_stream, &out_den_stream);
 735         reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
 736                         &out_num_plane, &out_den_plane);
 737         reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
 738         pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
 739         pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
 740
 741         // Prefetch lines is equal to VACTIVE + BP + VSYNC
 742         pipe_data->pipe_config.subvp_data.prefetch_lines =
 743                         phantom_timing->v_total - phantom_timing->v_front_porch;
 744
 745         // Round up
 746         pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 747                         div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 748                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 749         pipe_data->pipe_config.subvp_data.processing_delay_lines =
 750                         div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 751                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 752
 753         if (subvp_pipe->bottom_pipe) {
 754                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
 755         } else if (subvp_pipe->next_odm_pipe) {
 756                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
 757         } else {
 758                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
 759         }
 760
 761         // Find phantom pipe index based on phantom stream
 762         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 763                 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
 764
 765                 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) {
 766                         pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
 767                         if (phantom_pipe->bottom_pipe) {
 768                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
 769                         } else if (phantom_pipe->next_odm_pipe) {
 770                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
 771                         } else {
 772                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
 773                         }
 774                         break;
 775                 }
 776         }
 777 }
 778
 779 /**
 780  * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
 781  *
 782  * @dc: [in] current dc state
 783  * @context: [in] new dc state
 784  * @enable: [in] if true enables the pipes population
 785  *
 786  * This function loops through each pipe and populates the DMUB SubVP CMD info
 787  * based on the pipe (e.g. SubVP, VBLANK).
 788  */
 789 void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
 790                 struct dc_state *context,
 791                 bool enable)
 792 {
 793         uint8_t cmd_pipe_index = 0;
 794         uint32_t i, pipe_idx;
 795         uint8_t subvp_count = 0;
 796         union dmub_rb_cmd cmd;
 797         struct pipe_ctx *subvp_pipes[2];
 798         uint32_t wm_val_refclk = 0;
 799
 800         memset(&cmd, 0, sizeof(cmd));
 801         // FW command for SUBVP
 802         cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 803         cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
 804         cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
 805                         sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
 806
 807         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 808                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 809
 810                 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe
 811                  */
 812                 if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 813                                 resource_is_pipe_type(pipe, DPP_PIPE) &&
 814                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 815                         subvp_pipes[subvp_count++] = pipe;
 816         }
 817
 818         if (enable) {
 819                 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
 820                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 821                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 822
 823                         if (!pipe->stream)
 824                                 continue;
 825
 826                         /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
 827                          * Any ODM or MPC splits being used in SubVP will be handled internally in
 828                          * populate_subvp_cmd_pipe_info
 829                          */
 830                         if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 831                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 832                                         pipe->stream->mall_stream_config.paired_stream &&
 833                                         pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 834                                 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 835                         } else if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 836                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 837                                         pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 838                                 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
 839                                 // we run through DML without calculating "natural" P-state support
 840                                 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 841
 842                         }
 843                         pipe_idx++;
 844                 }
 845                 if (subvp_count == 2) {
 846                         update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
 847                 }
 848                 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
 849                 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
 850
 851                 // Store the original watermark value for this SubVP config so we can lower it when the
 852                 // MCLK switch starts
 853                 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
 854                                 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
 855
 856                 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
 857         }
 858
 859         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 860 }
 861
 862 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
 863 {
 864         if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
 865                 return false;
 866         return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
 867 }
 868
 869 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
 870 {
 871         struct dmub_diagnostic_data diag_data = {0};
 872
 873         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
 874                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
 875                 return;
 876         }
 877
 878         if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
 879                 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
 880                 return;
 881         }
 882
 883         DC_LOG_DEBUG("DMCUB STATE:");
 884         DC_LOG_DEBUG("    dmcub_version      : %08x", diag_data.dmcub_version);
 885         DC_LOG_DEBUG("    scratch  [0]       : %08x", diag_data.scratch[0]);
 886         DC_LOG_DEBUG("    scratch  [1]       : %08x", diag_data.scratch[1]);
 887         DC_LOG_DEBUG("    scratch  [2]       : %08x", diag_data.scratch[2]);
 888         DC_LOG_DEBUG("    scratch  [3]       : %08x", diag_data.scratch[3]);
 889         DC_LOG_DEBUG("    scratch  [4]       : %08x", diag_data.scratch[4]);
 890         DC_LOG_DEBUG("    scratch  [5]       : %08x", diag_data.scratch[5]);
 891         DC_LOG_DEBUG("    scratch  [6]       : %08x", diag_data.scratch[6]);
 892         DC_LOG_DEBUG("    scratch  [7]       : %08x", diag_data.scratch[7]);
 893         DC_LOG_DEBUG("    scratch  [8]       : %08x", diag_data.scratch[8]);
 894         DC_LOG_DEBUG("    scratch  [9]       : %08x", diag_data.scratch[9]);
 895         DC_LOG_DEBUG("    scratch [10]       : %08x", diag_data.scratch[10]);
 896         DC_LOG_DEBUG("    scratch [11]       : %08x", diag_data.scratch[11]);
 897         DC_LOG_DEBUG("    scratch [12]       : %08x", diag_data.scratch[12]);
 898         DC_LOG_DEBUG("    scratch [13]       : %08x", diag_data.scratch[13]);
 899         DC_LOG_DEBUG("    scratch [14]       : %08x", diag_data.scratch[14]);
 900         DC_LOG_DEBUG("    scratch [15]       : %08x", diag_data.scratch[15]);
 901         DC_LOG_DEBUG("    pc                 : %08x", diag_data.pc);
 902         DC_LOG_DEBUG("    unk_fault_addr     : %08x", diag_data.undefined_address_fault_addr);
 903         DC_LOG_DEBUG("    inst_fault_addr    : %08x", diag_data.inst_fetch_fault_addr);
 904         DC_LOG_DEBUG("    data_fault_addr    : %08x", diag_data.data_write_fault_addr);
 905         DC_LOG_DEBUG("    inbox1_rptr        : %08x", diag_data.inbox1_rptr);
 906         DC_LOG_DEBUG("    inbox1_wptr        : %08x", diag_data.inbox1_wptr);
 907         DC_LOG_DEBUG("    inbox1_size        : %08x", diag_data.inbox1_size);
 908         DC_LOG_DEBUG("    inbox0_rptr        : %08x", diag_data.inbox0_rptr);
 909         DC_LOG_DEBUG("    inbox0_wptr        : %08x", diag_data.inbox0_wptr);
 910         DC_LOG_DEBUG("    inbox0_size        : %08x", diag_data.inbox0_size);
 911         DC_LOG_DEBUG("    is_enabled         : %d", diag_data.is_dmcub_enabled);
 912         DC_LOG_DEBUG("    is_soft_reset      : %d", diag_data.is_dmcub_soft_reset);
 913         DC_LOG_DEBUG("    is_secure_reset    : %d", diag_data.is_dmcub_secure_reset);
 914         DC_LOG_DEBUG("    is_traceport_en    : %d", diag_data.is_traceport_en);
 915         DC_LOG_DEBUG("    is_cw0_en          : %d", diag_data.is_cw0_enabled);
 916         DC_LOG_DEBUG("    is_cw6_en          : %d", diag_data.is_cw6_enabled);
 917 }
 918
 919 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 920 {
 921         struct pipe_ctx *test_pipe, *split_pipe;
 922         const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
 923         struct rect r1 = scl_data->recout, r2, r2_half;
 924         int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
 925         int cur_layer = pipe_ctx->plane_state->layer_index;
 926
 927         /**
 928          * Disable the cursor if there's another pipe above this with a
 929          * plane that contains this pipe's viewport to prevent double cursor
 930          * and incorrect scaling artifacts.
 931          */
 932         for (test_pipe = pipe_ctx->top_pipe; test_pipe;
 933              test_pipe = test_pipe->top_pipe) {
 934                 // Skip invisible layer and pipe-split plane on same layer
 935                 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
 936                         continue;
 937
 938                 r2 = test_pipe->plane_res.scl_data.recout;
 939                 r2_r = r2.x + r2.width;
 940                 r2_b = r2.y + r2.height;
 941                 split_pipe = test_pipe;
 942
 943                 /**
 944                  * There is another half plane on same layer because of
 945                  * pipe-split, merge together per same height.
 946                  */
 947                 for (split_pipe = pipe_ctx->top_pipe; split_pipe;
 948                      split_pipe = split_pipe->top_pipe)
 949                         if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
 950                                 r2_half = split_pipe->plane_res.scl_data.recout;
 951                                 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
 952                                 r2.width = r2.width + r2_half.width;
 953                                 r2_r = r2.x + r2.width;
 954                                 break;
 955                         }
 956
 957                 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
 958                         return true;
 959         }
 960
 961         return false;
 962 }
 963
 964 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
 965 {
 966         if (pipe_ctx->plane_state != NULL) {
 967                 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
 968                         return false;
 969
 970                 if (dc_can_pipe_disable_cursor(pipe_ctx))
 971                         return false;
 972         }
 973
 974         if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
 975                 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
 976                 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
 977                 return true;
 978
 979         if (pipe_ctx->stream->link->replay_settings.config.replay_supported)
 980                 return true;
 981
 982         return false;
 983 }
 984
 985 static void dc_build_cursor_update_payload0(
 986                 struct pipe_ctx *pipe_ctx, uint8_t p_idx,
 987                 struct dmub_cmd_update_cursor_payload0 *payload)
 988 {
 989         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 990         unsigned int panel_inst = 0;
 991
 992         if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
 993                 pipe_ctx->stream->link, &panel_inst))
 994                 return;
 995
 996         /* Payload: Cursor Rect is built from position & attribute
 997          * x & y are obtained from postion
 998          */
 999         payload->cursor_rect.x = hubp->cur_rect.x;
1000         payload->cursor_rect.y = hubp->cur_rect.y;
1001         /* w & h are obtained from attribute */
1002         payload->cursor_rect.width  = hubp->cur_rect.w;
1003         payload->cursor_rect.height = hubp->cur_rect.h;
1004
1005         payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
1006         payload->pipe_idx    = p_idx;
1007         payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
1008         payload->panel_inst  = panel_inst;
1009 }
1010
1011 static void dc_build_cursor_position_update_payload0(
1012                 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
1013                 const struct hubp *hubp, const struct dpp *dpp)
1014 {
1015         /* Hubp */
1016         pl->position_cfg.pHubp.cur_ctl.raw  = hubp->pos.cur_ctl.raw;
1017         pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
1018         pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
1019         pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
1020
1021         /* dpp */
1022         pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
1023         pl->position_cfg.pipe_idx = p_idx;
1024 }
1025
1026 static void dc_build_cursor_attribute_update_payload1(
1027                 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
1028                 const struct hubp *hubp, const struct dpp *dpp)
1029 {
1030         /* Hubp */
1031         pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
1032         pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
1033         pl_A->aHubp.cur_ctl.raw  = hubp->att.cur_ctl.raw;
1034         pl_A->aHubp.size.raw     = hubp->att.size.raw;
1035         pl_A->aHubp.settings.raw = hubp->att.settings.raw;
1036
1037         /* dpp */
1038         pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
1039 }
1040
1041 /**
1042  * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
1043  *
1044  * @pCtx: [in] pipe context
1045  * @pipe_idx: [in] pipe index
1046  *
1047  * This function would store the cursor related information and pass it into
1048  * dmub
1049  */
1050 void dc_send_update_cursor_info_to_dmu(
1051                 struct pipe_ctx *pCtx, uint8_t pipe_idx)
1052 {
1053         union dmub_rb_cmd cmd[2];
1054         union dmub_cmd_update_cursor_info_data *update_cursor_info_0 =
1055                                         &cmd[0].update_cursor_info.update_cursor_info_data;
1056
1057         memset(cmd, 0, sizeof(cmd));
1058
1059         if (!dc_dmub_should_update_cursor_data(pCtx))
1060                 return;
1061         /*
1062          * Since we use multi_cmd_pending for dmub command, the 2nd command is
1063          * only assigned to store cursor attributes info.
1064          * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
1065          * is to store cursor position info.
1066          *
1067          * Command heaer type must be the same type if using  multi_cmd_pending.
1068          * Besides, while process 2nd command in DMU, the sub type is useless.
1069          * So it's meanless to pass the sub type header with different type.
1070          */
1071
1072         {
1073                 /* Build Payload#0 Header */
1074                 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1075                 cmd[0].update_cursor_info.header.payload_bytes =
1076                                 sizeof(cmd[0].update_cursor_info.update_cursor_info_data);
1077                 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd
1078
1079                 /* Prepare Payload */
1080                 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0);
1081
1082                 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx,
1083                                 pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1084                 }
1085         {
1086                 /* Build Payload#1 Header */
1087                 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1088                 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1089                 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command.
1090
1091                 dc_build_cursor_attribute_update_payload1(
1092                                 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1093                                 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1094
1095                 /* Combine 2nd cmds update_curosr_info to DMU */
1096                 dm_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);
1097         }
1098 }
1099
1100 bool dc_dmub_check_min_version(struct dmub_srv *srv)
1101 {
1102         if (!srv->hw_funcs.is_psrsu_supported)
1103                 return true;
1104         return srv->hw_funcs.is_psrsu_supported(srv);
1105 }
1106
1107 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)
1108 {
1109         struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1110         struct dmub_srv *dmub;
1111         enum dmub_status status;
1112         static const uint32_t timeout_us = 30;
1113
1114         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
1115                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
1116                 return;
1117         }
1118
1119         dmub = dc_dmub_srv->dmub;
1120
1121         status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 0x0010, timeout_us);
1122         if (status != DMUB_STATUS_OK) {
1123                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1124                 return;
1125         }
1126
1127         status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 0x0000, timeout_us);
1128         if (status != DMUB_STATUS_OK) {
1129                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1130                 return;
1131         }
1132
1133         DC_LOG_DEBUG("Enabled DPIA trace\n");
1134 }
1135
1136 void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index)
1137 {
1138         dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index);
1139 }
1140
1141 bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)
1142 {
1143         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
1144         enum dmub_status status;
1145
1146         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
1147                 return true;
1148
1149         if (wait) {
1150                 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);
1151                 if (status != DMUB_STATUS_OK) {
1152                         DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status);
1153                         return false;
1154                 }
1155         } else
1156                 return dmub_srv_is_hw_pwr_up(dc_dmub_srv->dmub);
1157
1158         return true;
1159 }
1160
1161 void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
1162 {
1163         union dmub_rb_cmd cmd = {0};
1164
1165         if (dc->debug.dmcub_emulation)
1166                 return;
1167
1168         memset(&cmd, 0, sizeof(cmd));
1169         cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
1170         cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE;
1171         cmd.idle_opt_notify_idle.header.payload_bytes =
1172                 sizeof(cmd.idle_opt_notify_idle) -
1173                 sizeof(cmd.idle_opt_notify_idle.header);
1174
1175         cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
1176
1177         if (allow_idle) {
1178                 if (dc->hwss.set_idle_state)
1179                         dc->hwss.set_idle_state(dc, true);
1180         }
1181
1182         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
1183 }
1184
1185 void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
1186 {
1187         const uint32_t max_num_polls = 10000;
1188         uint32_t allow_state = 0;
1189         uint32_t commit_state = 0;
1190         uint32_t i;
1191
1192         if (dc->debug.dmcub_emulation)
1193                 return;
1194
1195         if (!dc->idle_optimizations_allowed)
1196                 return;
1197
1198         if (dc->hwss.get_idle_state &&
1199                 dc->hwss.set_idle_state &&
1200                 dc->clk_mgr->funcs->exit_low_power_state) {
1201
1202                 allow_state = dc->hwss.get_idle_state(dc);
1203                 dc->hwss.set_idle_state(dc, false);
1204
1205                 if (!(allow_state & DMUB_IPS2_ALLOW_MASK)) {
1206                         // Wait for evaluation time
1207                         udelay(dc->debug.ips2_eval_delay_us);
1208                         commit_state = dc->hwss.get_idle_state(dc);
1209                         if (!(commit_state & DMUB_IPS2_COMMIT_MASK)) {
1210                                 // Tell PMFW to exit low power state
1211                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1212
1213                                 // Wait for IPS2 entry upper bound
1214                                 udelay(dc->debug.ips2_entry_delay_us);
1215                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1216
1217                                 for (i = 0; i < max_num_polls; ++i) {
1218                                         commit_state = dc->hwss.get_idle_state(dc);
1219                                         if (commit_state & DMUB_IPS2_COMMIT_MASK)
1220                                                 break;
1221
1222                                         udelay(1);
1223                                 }
1224                                 ASSERT(i < max_num_polls);
1225
1226                                 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1227                                         ASSERT(0);
1228
1229                                 /* TODO: See if we can return early here - IPS2 should go
1230                                  * back directly to IPS0 and clear the flags, but it will
1231                                  * be safer to directly notify DMCUB of this.
1232                                  */
1233                                 allow_state = dc->hwss.get_idle_state(dc);
1234                         }
1235                 }
1236
1237                 dc_dmub_srv_notify_idle(dc, false);
1238                 if (!(allow_state & DMUB_IPS1_ALLOW_MASK)) {
1239                         for (i = 0; i < max_num_polls; ++i) {
1240                                 commit_state = dc->hwss.get_idle_state(dc);
1241                                 if (commit_state & DMUB_IPS1_COMMIT_MASK)
1242                                         break;
1243
1244                                 udelay(1);
1245                         }
1246                         ASSERT(i < max_num_polls);
1247                 }
1248         }
1249
1250         if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1251                 ASSERT(0);
1252 }
1253