2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dc_dmub_srv.h"
28 #include "../dmub/dmub_srv.h"
29 #include "dm_helpers.h"
30 #include "dc_hw_types.h"
31 #include "core_types.h"
32 #include "../basics/conversion.h"
33 #include "cursor_reg_cache.h"
35 #define CTX dc_dmub_srv->ctx
36 #define DC_LOGGER CTX->logger
38 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
39 struct dmub_srv *dmub)
42 dc_srv->ctx = dc->ctx;
45 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
47 struct dc_dmub_srv *dc_srv =
48 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
55 dc_dmub_srv_construct(dc_srv, dc, dmub);
60 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
68 void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
69 union dmub_rb_cmd *cmd)
71 struct dmub_srv *dmub = dc_dmub_srv->dmub;
72 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
73 enum dmub_status status;
75 status = dmub_srv_cmd_queue(dmub, cmd);
76 if (status == DMUB_STATUS_OK)
79 if (status != DMUB_STATUS_QUEUE_FULL)
82 /* Execute and wait for queue to become empty again. */
83 dc_dmub_srv_cmd_execute(dc_dmub_srv);
84 dc_dmub_srv_wait_idle(dc_dmub_srv);
86 /* Requeue the command. */
87 status = dmub_srv_cmd_queue(dmub, cmd);
88 if (status == DMUB_STATUS_OK)
92 DC_ERROR("Error queuing DMUB command: status=%d\n", status);
93 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
96 void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
98 struct dmub_srv *dmub = dc_dmub_srv->dmub;
99 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
100 enum dmub_status status;
102 status = dmub_srv_cmd_execute(dmub);
103 if (status != DMUB_STATUS_OK) {
104 DC_ERROR("Error starting DMUB execution: status=%d\n", status);
105 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
109 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
111 struct dmub_srv *dmub = dc_dmub_srv->dmub;
112 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
113 enum dmub_status status;
115 status = dmub_srv_wait_for_idle(dmub, 100000);
116 if (status != DMUB_STATUS_OK) {
117 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
118 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
122 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv)
124 struct dmub_srv *dmub = dmub_srv->dmub;
125 struct dc_context *dc_ctx = dmub_srv->ctx;
126 enum dmub_status status = DMUB_STATUS_OK;
128 status = dmub_srv_clear_inbox0_ack(dmub);
129 if (status != DMUB_STATUS_OK) {
130 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
131 dc_dmub_srv_log_diagnostic_data(dmub_srv);
135 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv)
137 struct dmub_srv *dmub = dmub_srv->dmub;
138 struct dc_context *dc_ctx = dmub_srv->ctx;
139 enum dmub_status status = DMUB_STATUS_OK;
141 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
142 if (status != DMUB_STATUS_OK) {
143 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
144 dc_dmub_srv_log_diagnostic_data(dmub_srv);
148 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
149 union dmub_inbox0_data_register data)
151 struct dmub_srv *dmub = dmub_srv->dmub;
152 struct dc_context *dc_ctx = dmub_srv->ctx;
153 enum dmub_status status = DMUB_STATUS_OK;
155 status = dmub_srv_send_inbox0_cmd(dmub, data);
156 if (status != DMUB_STATUS_OK) {
157 DC_ERROR("Error sending INBOX0 cmd\n");
158 dc_dmub_srv_log_diagnostic_data(dmub_srv);
162 bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd)
164 struct dmub_srv *dmub;
165 enum dmub_status status;
167 if (!dc_dmub_srv || !dc_dmub_srv->dmub)
170 dmub = dc_dmub_srv->dmub;
172 status = dmub_srv_cmd_with_reply_data(dmub, cmd);
173 if (status != DMUB_STATUS_OK) {
174 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
181 void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
183 struct dmub_srv *dmub = dc_dmub_srv->dmub;
184 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
185 enum dmub_status status;
188 /* Wait up to a second for PHY init. */
189 status = dmub_srv_wait_for_phy_init(dmub, 1000000);
190 if (status == DMUB_STATUS_OK)
191 /* Initialization OK */
194 DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
197 if (status != DMUB_STATUS_TIMEOUT)
199 * Server likely initialized or we don't have
200 * DMCUB HW support - this won't end.
204 /* Continue spinning so we don't hang the ASIC. */
208 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
209 unsigned int stream_mask)
211 struct dmub_srv *dmub;
212 const uint32_t timeout = 30;
214 if (!dc_dmub_srv || !dc_dmub_srv->dmub)
217 dmub = dc_dmub_srv->dmub;
219 return dmub_srv_send_gpint_command(
220 dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
221 stream_mask, timeout) == DMUB_STATUS_OK;
224 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
226 struct dmub_srv *dmub;
227 struct dc_context *dc_ctx;
228 union dmub_fw_boot_status boot_status;
229 enum dmub_status status;
231 if (!dc_dmub_srv || !dc_dmub_srv->dmub)
234 dmub = dc_dmub_srv->dmub;
235 dc_ctx = dc_dmub_srv->ctx;
237 status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
238 if (status != DMUB_STATUS_OK) {
239 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
243 return boot_status.bits.restore_required;
246 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
248 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
249 return dmub_srv_get_outbox0_msg(dmub, entry);
252 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
254 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
257 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
259 union dmub_rb_cmd cmd = { 0 };
261 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
262 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
263 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
264 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
265 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
267 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
269 // Send the command to the DMCUB.
270 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
271 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
272 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
275 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
277 union dmub_rb_cmd cmd = { 0 };
279 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
280 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
281 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
283 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
285 // Send the command to the DMCUB.
286 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
287 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
288 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
291 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
296 for (i = 0; i < MAX_PIPES; i++) {
297 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
299 if (pipe->stream == stream && pipe->stream_res.tg)
305 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
306 struct pipe_ctx *head_pipe,
307 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
312 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
313 for (j = 0; j < dc->res_pool->pipe_count; j++) {
314 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
316 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
317 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
320 fams_pipe_data->pipe_count = pipe_idx;
323 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
325 union dmub_rb_cmd cmd = { 0 };
326 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
328 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
329 uint8_t visual_confirm_enabled;
335 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
338 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
339 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
340 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
341 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
343 if (should_manage_pstate) {
344 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
345 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
350 /* If FAMS is being used to support P-State and there is a stream
351 * that does not use FAMS, we are in an FPO + VActive scenario.
352 * Assign vactive stretch margin in this case.
354 if (!pipe->stream->fpo_in_use) {
355 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
362 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
363 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
365 if (!pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream && pipe->stream->fpo_in_use) {
366 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
367 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
369 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
370 config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
371 config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
372 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
373 dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
377 cmd.fw_assisted_mclk_switch.header.payload_bytes =
378 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
380 // Send the command to the DMCUB.
381 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
382 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
383 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
388 void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
390 union dmub_rb_cmd cmd = { 0 };
391 enum dmub_status status;
397 memset(&cmd, 0, sizeof(cmd));
399 /* Prepare fw command */
400 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
401 cmd.query_feature_caps.header.sub_type = 0;
402 cmd.query_feature_caps.header.ret_status = 1;
403 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
405 /* Send command to fw */
406 status = dmub_srv_cmd_with_reply_data(dmub, &cmd);
408 ASSERT(status == DMUB_STATUS_OK);
410 /* If command was processed, copy feature caps to dmub srv */
411 if (status == DMUB_STATUS_OK &&
412 cmd.query_feature_caps.header.ret_status == 0) {
413 memcpy(&dmub->feature_caps,
414 &cmd.query_feature_caps.query_feature_caps_data,
415 sizeof(struct dmub_feature_caps));
419 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
421 union dmub_rb_cmd cmd = { 0 };
422 enum dmub_status status;
423 unsigned int panel_inst = 0;
425 dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
427 memset(&cmd, 0, sizeof(cmd));
429 // Prepare fw command
430 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
431 cmd.visual_confirm_color.header.sub_type = 0;
432 cmd.visual_confirm_color.header.ret_status = 1;
433 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
434 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
436 // Send command to fw
437 status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd);
439 ASSERT(status == DMUB_STATUS_OK);
441 // If command was processed, copy feature caps to dmub srv
442 if (status == DMUB_STATUS_OK &&
443 cmd.visual_confirm_color.header.ret_status == 0) {
444 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
445 &cmd.visual_confirm_color.visual_confirm_color_data,
446 sizeof(struct dmub_visual_confirm_color));
451 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
453 * @dc: [in] current dc state
454 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
455 * @vblank_pipe: [in] pipe_ctx for the DRR pipe
456 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
458 * Populate the DMCUB SubVP command with DRR pipe info. All the information
459 * required for calculating the SubVP + DRR microschedule is populated here.
461 * High level algorithm:
462 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
463 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
464 * 3. Populate the drr_info with the min and max supported vtotal values
466 static void populate_subvp_cmd_drr_info(struct dc *dc,
467 struct pipe_ctx *subvp_pipe,
468 struct pipe_ctx *vblank_pipe,
469 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
471 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
472 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
473 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
474 uint16_t drr_frame_us = 0;
475 uint16_t min_drr_supported_us = 0;
476 uint16_t max_drr_supported_us = 0;
477 uint16_t max_drr_vblank_us = 0;
478 uint16_t max_drr_mallregion_us = 0;
479 uint16_t mall_region_us = 0;
480 uint16_t prefetch_us = 0;
481 uint16_t subvp_active_us = 0;
482 uint16_t drr_active_us = 0;
483 uint16_t min_vtotal_supported = 0;
484 uint16_t max_vtotal_supported = 0;
486 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
487 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
488 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
490 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
491 (((uint64_t)drr_timing->pix_clk_100hz * 100)));
492 // P-State allow width and FW delays already included phantom_timing->v_addressable
493 mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
494 (((uint64_t)phantom_timing->pix_clk_100hz * 100)));
495 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
496 min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
497 (((uint64_t)drr_timing->h_total * 1000000)));
499 prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
500 (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
501 subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
502 (((uint64_t)main_timing->pix_clk_100hz * 100)));
503 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
504 (((uint64_t)drr_timing->pix_clk_100hz * 100)));
505 max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
506 dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
507 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
508 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
509 max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
510 (((uint64_t)drr_timing->h_total * 1000000)));
512 /* When calculating the max vtotal supported for SubVP + DRR cases, add
513 * margin due to possible rounding errors (being off by 1 line in the
514 * FW calculation can incorrectly push the P-State switch to wait 1 frame
517 max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
519 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
520 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
521 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
525 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
527 * @dc: [in] current dc state
528 * @context: [in] new dc state
529 * @cmd: [in] DMUB cmd to be populated with SubVP info
530 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
531 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
533 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
534 * required to calculate the microschedule for SubVP + VBLANK case is stored in
535 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe
536 * is a DRR display -- if it is make a call to populate drr_info.
538 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
539 struct dc_state *context,
540 union dmub_rb_cmd *cmd,
541 struct pipe_ctx *vblank_pipe,
542 uint8_t cmd_pipe_index)
545 struct pipe_ctx *pipe = NULL;
546 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
547 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
549 // Find the SubVP pipe
550 for (i = 0; i < dc->res_pool->pipe_count; i++) {
551 pipe = &context->res_ctx.pipe_ctx[i];
553 // We check for master pipe, but it shouldn't matter since we only need
554 // the pipe for timing info (stream should be same for any pipe splits)
555 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
558 // Find the SubVP pipe
559 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
563 pipe_data->mode = VBLANK;
564 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
565 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
566 vblank_pipe->stream->timing.v_front_porch;
567 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
568 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
569 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
570 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
571 pipe_data->pipe_config.vblank_data.vblank_end =
572 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
574 if (vblank_pipe->stream->ignore_msa_timing_param)
575 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
579 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
581 * @dc: [in] current dc state
582 * @context: [in] new dc state
583 * @cmd: [in] DMUB cmd to be populated with SubVP info
584 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
586 * For SubVP + SubVP, we use a single vertical interrupt to start the
587 * microschedule for both SubVP pipes. In order for this to work correctly, the
588 * MALL REGION of both SubVP pipes must start at the same time. This function
589 * lengthens the prefetch end to mall start delay of the SubVP pipe that has
590 * the shorter prefetch so that both MALL REGION's will start at the same time.
592 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
593 struct dc_state *context,
594 union dmub_rb_cmd *cmd,
595 struct pipe_ctx *subvp_pipes[])
597 uint32_t subvp0_prefetch_us = 0;
598 uint32_t subvp1_prefetch_us = 0;
599 uint32_t prefetch_delta_us = 0;
600 struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing;
601 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
602 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
604 subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
605 (uint64_t)phantom_timing0->h_total * 1000000),
606 (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
607 subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
608 (uint64_t)phantom_timing1->h_total * 1000000),
609 (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
611 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
612 // should increase it's prefetch time to match the other
613 if (subvp0_prefetch_us > subvp1_prefetch_us) {
614 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
615 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
616 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
617 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
618 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
619 ((uint64_t)phantom_timing1->h_total * 1000000));
621 } else if (subvp1_prefetch_us > subvp0_prefetch_us) {
622 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
623 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
624 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
625 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
626 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
627 ((uint64_t)phantom_timing0->h_total * 1000000));
632 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
634 * @dc: [in] current dc state
635 * @context: [in] new dc state
636 * @cmd: [in] DMUB cmd to be populated with SubVP info
637 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
638 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
640 * Populate the DMCUB SubVP command with SubVP pipe info. All the information
641 * required to calculate the microschedule for the SubVP pipe is stored in the
642 * pipe_data of the DMCUB SubVP command.
644 static void populate_subvp_cmd_pipe_info(struct dc *dc,
645 struct dc_state *context,
646 union dmub_rb_cmd *cmd,
647 struct pipe_ctx *subvp_pipe,
648 uint8_t cmd_pipe_index)
651 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
652 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
653 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
654 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
655 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
657 pipe_data->mode = SUBVP;
658 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
659 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
660 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
661 pipe_data->pipe_config.subvp_data.main_vblank_start =
662 main_timing->v_total - main_timing->v_front_porch;
663 pipe_data->pipe_config.subvp_data.main_vblank_end =
664 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
665 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
666 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
667 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param;
669 /* Calculate the scaling factor from the src and dst height.
670 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
671 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
673 * Make sure to combine stream and plane scaling together.
675 reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
676 &out_num_stream, &out_den_stream);
677 reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
678 &out_num_plane, &out_den_plane);
679 reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
680 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
681 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
683 // Prefetch lines is equal to VACTIVE + BP + VSYNC
684 pipe_data->pipe_config.subvp_data.prefetch_lines =
685 phantom_timing->v_total - phantom_timing->v_front_porch;
688 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
689 div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
690 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
691 pipe_data->pipe_config.subvp_data.processing_delay_lines =
692 div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
693 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
695 if (subvp_pipe->bottom_pipe) {
696 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
697 } else if (subvp_pipe->next_odm_pipe) {
698 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
700 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
703 // Find phantom pipe index based on phantom stream
704 for (j = 0; j < dc->res_pool->pipe_count; j++) {
705 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
707 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) {
708 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
709 if (phantom_pipe->bottom_pipe) {
710 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
711 } else if (phantom_pipe->next_odm_pipe) {
712 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
714 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
722 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
724 * @dc: [in] current dc state
725 * @context: [in] new dc state
726 * @enable: [in] if true enables the pipes population
728 * This function loops through each pipe and populates the DMUB SubVP CMD info
729 * based on the pipe (e.g. SubVP, VBLANK).
731 void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
732 struct dc_state *context,
735 uint8_t cmd_pipe_index = 0;
736 uint32_t i, pipe_idx;
737 uint8_t subvp_count = 0;
738 union dmub_rb_cmd cmd;
739 struct pipe_ctx *subvp_pipes[2];
740 uint32_t wm_val_refclk = 0;
742 memset(&cmd, 0, sizeof(cmd));
743 // FW command for SUBVP
744 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
745 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
746 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
747 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
749 for (i = 0; i < dc->res_pool->pipe_count; i++) {
750 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
755 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe
757 if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe &&
758 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
759 subvp_pipes[subvp_count++] = pipe;
763 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
764 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
765 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
770 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
771 * Any ODM or MPC splits being used in SubVP will be handled internally in
772 * populate_subvp_cmd_pipe_info
774 if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream &&
775 !pipe->top_pipe && !pipe->prev_odm_pipe &&
776 pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
777 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
778 } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE &&
779 !pipe->top_pipe && !pipe->prev_odm_pipe) {
780 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
781 // we run through DML without calculating "natural" P-state support
782 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
787 if (subvp_count == 2) {
788 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
790 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
791 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
793 // Store the original watermark value for this SubVP config so we can lower it when the
794 // MCLK switch starts
795 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
796 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
798 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
800 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
801 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
802 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
805 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
807 if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
809 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
812 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
814 struct dmub_diagnostic_data diag_data = {0};
816 if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
817 DC_LOG_ERROR("%s: invalid parameters.", __func__);
821 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
822 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
828 " dmcub_version : %08x\n"
829 " scratch [0] : %08x\n"
830 " scratch [1] : %08x\n"
831 " scratch [2] : %08x\n"
832 " scratch [3] : %08x\n"
833 " scratch [4] : %08x\n"
834 " scratch [5] : %08x\n"
835 " scratch [6] : %08x\n"
836 " scratch [7] : %08x\n"
837 " scratch [8] : %08x\n"
838 " scratch [9] : %08x\n"
839 " scratch [10] : %08x\n"
840 " scratch [11] : %08x\n"
841 " scratch [12] : %08x\n"
842 " scratch [13] : %08x\n"
843 " scratch [14] : %08x\n"
844 " scratch [15] : %08x\n"
846 " unk_fault_addr : %08x\n"
847 " inst_fault_addr : %08x\n"
848 " data_fault_addr : %08x\n"
849 " inbox1_rptr : %08x\n"
850 " inbox1_wptr : %08x\n"
851 " inbox1_size : %08x\n"
852 " inbox0_rptr : %08x\n"
853 " inbox0_wptr : %08x\n"
854 " inbox0_size : %08x\n"
856 " is_soft_reset : %d\n"
857 " is_secure_reset : %d\n"
858 " is_traceport_en : %d\n"
861 diag_data.dmcub_version,
862 diag_data.scratch[0],
863 diag_data.scratch[1],
864 diag_data.scratch[2],
865 diag_data.scratch[3],
866 diag_data.scratch[4],
867 diag_data.scratch[5],
868 diag_data.scratch[6],
869 diag_data.scratch[7],
870 diag_data.scratch[8],
871 diag_data.scratch[9],
872 diag_data.scratch[10],
873 diag_data.scratch[11],
874 diag_data.scratch[12],
875 diag_data.scratch[13],
876 diag_data.scratch[14],
877 diag_data.scratch[15],
879 diag_data.undefined_address_fault_addr,
880 diag_data.inst_fetch_fault_addr,
881 diag_data.data_write_fault_addr,
882 diag_data.inbox1_rptr,
883 diag_data.inbox1_wptr,
884 diag_data.inbox1_size,
885 diag_data.inbox0_rptr,
886 diag_data.inbox0_wptr,
887 diag_data.inbox0_size,
888 diag_data.is_dmcub_enabled,
889 diag_data.is_dmcub_soft_reset,
890 diag_data.is_dmcub_secure_reset,
891 diag_data.is_traceport_en,
892 diag_data.is_cw0_enabled,
893 diag_data.is_cw6_enabled);
896 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
898 struct pipe_ctx *test_pipe, *split_pipe;
899 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
900 struct rect r1 = scl_data->recout, r2, r2_half;
901 int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
902 int cur_layer = pipe_ctx->plane_state->layer_index;
905 * Disable the cursor if there's another pipe above this with a
906 * plane that contains this pipe's viewport to prevent double cursor
907 * and incorrect scaling artifacts.
909 for (test_pipe = pipe_ctx->top_pipe; test_pipe;
910 test_pipe = test_pipe->top_pipe) {
911 // Skip invisible layer and pipe-split plane on same layer
912 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
915 r2 = test_pipe->plane_res.scl_data.recout;
916 r2_r = r2.x + r2.width;
917 r2_b = r2.y + r2.height;
918 split_pipe = test_pipe;
921 * There is another half plane on same layer because of
922 * pipe-split, merge together per same height.
924 for (split_pipe = pipe_ctx->top_pipe; split_pipe;
925 split_pipe = split_pipe->top_pipe)
926 if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
927 r2_half = split_pipe->plane_res.scl_data.recout;
928 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
929 r2.width = r2.width + r2_half.width;
930 r2_r = r2.x + r2.width;
934 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
941 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
943 if (pipe_ctx->plane_state != NULL) {
944 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
947 if (dc_can_pipe_disable_cursor(pipe_ctx))
951 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
952 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
953 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
959 static void dc_build_cursor_update_payload0(
960 struct pipe_ctx *pipe_ctx, uint8_t p_idx,
961 struct dmub_cmd_update_cursor_payload0 *payload)
963 struct hubp *hubp = pipe_ctx->plane_res.hubp;
964 unsigned int panel_inst = 0;
966 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
967 pipe_ctx->stream->link, &panel_inst))
970 /* Payload: Cursor Rect is built from position & attribute
971 * x & y are obtained from postion
973 payload->cursor_rect.x = hubp->cur_rect.x;
974 payload->cursor_rect.y = hubp->cur_rect.y;
975 /* w & h are obtained from attribute */
976 payload->cursor_rect.width = hubp->cur_rect.w;
977 payload->cursor_rect.height = hubp->cur_rect.h;
979 payload->enable = hubp->pos.cur_ctl.bits.cur_enable;
980 payload->pipe_idx = p_idx;
981 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
982 payload->panel_inst = panel_inst;
985 static void dc_send_cmd_to_dmu(struct dc_dmub_srv *dmub_srv,
986 union dmub_rb_cmd *cmd)
988 dc_dmub_srv_cmd_queue(dmub_srv, cmd);
989 dc_dmub_srv_cmd_execute(dmub_srv);
990 dc_dmub_srv_wait_idle(dmub_srv);
993 static void dc_build_cursor_position_update_payload0(
994 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
995 const struct hubp *hubp, const struct dpp *dpp)
998 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw;
999 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
1000 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
1001 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
1004 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
1005 pl->position_cfg.pipe_idx = p_idx;
1008 static void dc_build_cursor_attribute_update_payload1(
1009 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
1010 const struct hubp *hubp, const struct dpp *dpp)
1013 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
1014 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
1015 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw;
1016 pl_A->aHubp.size.raw = hubp->att.size.raw;
1017 pl_A->aHubp.settings.raw = hubp->att.settings.raw;
1020 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
1024 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
1026 * @pCtx: [in] pipe context
1027 * @pipe_idx: [in] pipe index
1029 * This function would store the cursor related information and pass it into
1032 void dc_send_update_cursor_info_to_dmu(
1033 struct pipe_ctx *pCtx, uint8_t pipe_idx)
1035 union dmub_rb_cmd cmd = { 0 };
1036 union dmub_cmd_update_cursor_info_data *update_cursor_info =
1037 &cmd.update_cursor_info.update_cursor_info_data;
1039 if (!dc_dmub_should_update_cursor_data(pCtx))
1042 * Since we use multi_cmd_pending for dmub command, the 2nd command is
1043 * only assigned to store cursor attributes info.
1044 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
1045 * is to store cursor position info.
1047 * Command heaer type must be the same type if using multi_cmd_pending.
1048 * Besides, while process 2nd command in DMU, the sub type is useless.
1049 * So it's meanless to pass the sub type header with different type.
1053 /* Build Payload#0 Header */
1054 cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1055 cmd.update_cursor_info.header.payload_bytes =
1056 sizeof(cmd.update_cursor_info.update_cursor_info_data);
1057 cmd.update_cursor_info.header.multi_cmd_pending = 1; /* To combine multi dmu cmd, 1st cmd */
1059 /* Prepare Payload */
1060 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info->payload0);
1062 dc_build_cursor_position_update_payload0(&update_cursor_info->payload0, pipe_idx,
1063 pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1064 /* Send update_curosr_info to queue */
1065 dc_dmub_srv_cmd_queue(pCtx->stream->ctx->dmub_srv, &cmd);
1068 /* Build Payload#1 Header */
1069 memset(update_cursor_info, 0, sizeof(union dmub_cmd_update_cursor_info_data));
1070 cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1071 cmd.update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1072 cmd.update_cursor_info.header.multi_cmd_pending = 0; /* Indicate it's the last command. */
1074 dc_build_cursor_attribute_update_payload1(
1075 &cmd.update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1076 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1078 /* Combine 2nd cmds update_curosr_info to DMU */
1079 dc_send_cmd_to_dmu(pCtx->stream->ctx->dmub_srv, &cmd);