2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "hdcp_msg_types.h"
33 #include "gpio_types.h"
34 #include "link_service_types.h"
35 #include "grph_object_ctrl_defs.h"
36 #include <inc/hw/opp.h>
38 #include "inc/hw_sequencer.h"
39 #include "inc/compressor.h"
40 #include "inc/hw/dmcu.h"
41 #include "dml/display_mode_lib.h"
43 /* forward declaration */
45 struct set_config_cmd_payload;
46 struct dmub_notification;
48 #define DC_VER "3.2.229"
50 #define MAX_SURFACES 3
53 #define MIN_VIEWPORT_SIZE 12
56 /* Display Core Interfaces */
59 struct dmcu_version dmcu_version;
62 enum dp_protocol_version {
67 DC_PLANE_TYPE_INVALID,
68 DC_PLANE_TYPE_DCE_RGB,
69 DC_PLANE_TYPE_DCE_UNDERLAY,
70 DC_PLANE_TYPE_DCN_UNIVERSAL,
73 // Sizes defined as multiples of 64KB
84 enum dc_plane_type type;
85 uint32_t per_pixel_alpha : 1;
87 uint32_t argb8888 : 1;
92 } pixel_format_support;
93 // max upscaling factor x1000
94 // upscaling factors are always >= 1
95 // for example, 1080p -> 8K is 4.0, or 4000 raw value
100 } max_upscale_factor;
101 // max downscale factor x1000
102 // downscale factors are always <= 1
103 // for example, 8K -> 1080p is 0.25, or 250 raw value
108 } max_downscale_factor;
109 // minimal width/height
115 * DOC: color-management-caps
117 * **Color management caps (DPP and MPC)**
119 * Modules/color calculates various color operations which are translated to
120 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
121 * DCN1, every new generation comes with fairly major differences in color
122 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
123 * decide mapping to HW block based on logical capabilities.
127 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
128 * @srgb: RGB color space transfer func
129 * @bt2020: BT.2020 transfer func
130 * @gamma2_2: standard gamma
131 * @pq: perceptual quantizer transfer function
132 * @hlg: hybrid log–gamma transfer function
134 struct rom_curve_caps {
137 uint16_t gamma2_2 : 1;
143 * struct dpp_color_caps - color pipeline capabilities for display pipe and
146 * @dcn_arch: all DCE generations treated the same
147 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
148 * just plain 256-entry lookup
149 * @icsc: input color space conversion
150 * @dgam_ram: programmable degamma LUT
151 * @post_csc: post color space conversion, before gamut remap
152 * @gamma_corr: degamma correction
153 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
154 * with MPC by setting mpc:shared_3d_lut flag
155 * @ogam_ram: programmable out/blend gamma LUT
156 * @ocsc: output color space conversion
157 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
158 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
159 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
161 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
163 struct dpp_color_caps {
164 uint16_t dcn_arch : 1;
165 uint16_t input_lut_shared : 1;
167 uint16_t dgam_ram : 1;
168 uint16_t post_csc : 1;
169 uint16_t gamma_corr : 1;
170 uint16_t hw_3d_lut : 1;
171 uint16_t ogam_ram : 1;
173 uint16_t dgam_rom_for_yuv : 1;
174 struct rom_curve_caps dgam_rom_caps;
175 struct rom_curve_caps ogam_rom_caps;
179 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
180 * plane combined blocks
182 * @gamut_remap: color transformation matrix
183 * @ogam_ram: programmable out gamma LUT
184 * @ocsc: output color space conversion matrix
185 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
186 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
188 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
190 struct mpc_color_caps {
191 uint16_t gamut_remap : 1;
192 uint16_t ogam_ram : 1;
194 uint16_t num_3dluts : 3;
195 uint16_t shared_3d_lut:1;
196 struct rom_curve_caps ogam_rom_caps;
200 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
201 * @dpp: color pipes caps for DPP
202 * @mpc: color pipes caps for MPC
204 struct dc_color_caps {
205 struct dpp_color_caps dpp;
206 struct mpc_color_caps mpc;
209 struct dc_dmub_caps {
215 uint32_t max_streams;
218 uint32_t max_slave_planes;
219 uint32_t max_slave_yuv_planes;
220 uint32_t max_slave_rgb_planes;
222 uint32_t max_downscale_ratio;
223 uint32_t i2c_speed_in_khz;
224 uint32_t i2c_speed_in_khz_hdcp;
225 uint32_t dmdata_alloc_size;
226 unsigned int max_cursor_size;
227 unsigned int max_video_width;
228 unsigned int min_horizontal_blanking_period;
229 int linear_pitch_alignment;
230 bool dcc_const_color;
234 bool post_blend_color_processing;
235 bool force_dp_tps4_for_cp2520;
236 bool disable_dp_clk_share;
237 bool psp_setup_panel_mode;
238 bool extended_aux_timeout_support;
241 uint32_t num_of_internal_disp;
242 enum dp_protocol_version max_dp_protocol_version;
243 unsigned int mall_size_per_mem_channel;
244 unsigned int mall_size_total;
245 unsigned int cursor_cache_size;
246 struct dc_plane_cap planes[MAX_PLANES];
247 struct dc_color_caps color;
248 struct dc_dmub_caps dmub_caps;
250 bool dp_hdmi21_pcon_support;
251 bool edp_dsc_support;
252 bool vbios_lttpr_aware;
253 bool vbios_lttpr_enable;
254 uint32_t max_otg_num;
255 uint32_t max_cab_allocation_bytes;
256 uint32_t cache_line_size;
257 uint32_t cache_num_ways;
258 uint16_t subvp_fw_processing_delay_us;
259 uint8_t subvp_drr_max_vblank_margin_us;
260 uint16_t subvp_prefetch_end_to_mall_start_us;
261 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
262 uint16_t subvp_pstate_allow_width_us;
263 uint16_t subvp_vertical_int_margin_us;
265 uint8_t subvp_drr_vblank_start_margin_us;
269 bool no_connect_phy_config;
271 bool skip_clock_update;
272 bool lt_early_cr_pattern;
275 struct dc_dcc_surface_param {
276 struct dc_size surface_size;
277 enum surface_pixel_format format;
278 enum swizzle_mode_values swizzle_mode;
279 enum dc_scan_direction scan;
282 struct dc_dcc_setting {
283 unsigned int max_compressed_blk_size;
284 unsigned int max_uncompressed_blk_size;
285 bool independent_64b_blks;
286 //These bitfields to be used starting with DCN
288 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
289 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN
290 uint32_t dcc_256_128_128 : 1; //available starting with DCN
291 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
295 struct dc_surface_dcc_cap {
298 struct dc_dcc_setting rgb;
302 struct dc_dcc_setting luma;
303 struct dc_dcc_setting chroma;
308 bool const_color_support;
311 struct dc_static_screen_params {
318 unsigned int num_frames;
322 /* Surface update type is used by dc_update_surfaces_and_stream
323 * The update type is determined at the very beginning of the function based
324 * on parameters passed in and decides how much programming (or updating) is
325 * going to be done during the call.
327 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
328 * logical calculations or hardware register programming. This update MUST be
329 * ISR safe on windows. Currently fast update will only be used to flip surface
332 * UPDATE_TYPE_MED is used for slower updates which require significant hw
333 * re-programming however do not affect bandwidth consumption or clock
334 * requirements. At present, this is the level at which front end updates
335 * that do not require us to run bw_calcs happen. These are in/out transfer func
336 * updates, viewport offset changes, recout size changes and pixel depth changes.
337 * This update can be done at ISR, but we want to minimize how often this happens.
339 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
340 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
341 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
342 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
343 * a full update. This cannot be done at ISR level and should be a rare event.
344 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
345 * underscan we don't expect to see this call at all.
348 enum surface_update_type {
349 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
350 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
351 UPDATE_TYPE_FULL, /* may need to shuffle resources */
354 /* Forward declaration*/
356 struct dc_plane_state;
360 struct dc_cap_funcs {
361 bool (*get_dcc_compression_cap)(const struct dc *dc,
362 const struct dc_dcc_surface_param *input,
363 struct dc_surface_dcc_cap *output);
366 struct link_training_settings;
368 union allow_lttpr_non_transparent_mode {
376 /* Structure to hold configuration flags set by dm at dc creation. */
379 bool disable_disp_pll_sharing;
381 bool disable_fractional_pwm;
382 bool allow_seamless_boot_optimization;
383 bool seamless_boot_edp_requested;
384 bool edp_not_connected;
385 bool edp_no_power_sequencing;
388 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
389 bool multi_mon_pp_mclk_switch;
392 bool enable_windowed_mpo_odm;
393 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
394 uint32_t allow_edp_hotplug_detection;
395 bool clamp_min_dcfclk;
396 uint64_t vblank_alignment_dto_params;
397 uint8_t vblank_alignment_max_frame_time_diff;
398 bool is_asymmetric_memory;
399 bool is_single_rank_dimm;
400 bool is_vmin_only_asic;
401 bool use_pipe_ctx_sync_logic;
402 bool ignore_dpref_ss;
403 bool enable_mipi_converter_optimization;
404 bool use_default_clock_table;
405 bool force_bios_enable_lttpr;
406 uint8_t force_bios_fixed_vs;
407 int sdpif_request_limit_words_per_umc;
408 bool disable_subvp_drr;
411 enum visual_confirm {
412 VISUAL_CONFIRM_DISABLE = 0,
413 VISUAL_CONFIRM_SURFACE = 1,
414 VISUAL_CONFIRM_HDR = 2,
415 VISUAL_CONFIRM_MPCTREE = 4,
416 VISUAL_CONFIRM_PSR = 5,
417 VISUAL_CONFIRM_SWAPCHAIN = 6,
418 VISUAL_CONFIRM_FAMS = 7,
419 VISUAL_CONFIRM_SWIZZLE = 9,
420 VISUAL_CONFIRM_SUBVP = 14,
423 enum dc_psr_power_opts {
424 psr_power_opt_invalid = 0x0,
425 psr_power_opt_smu_opt_static_screen = 0x1,
426 psr_power_opt_z10_static_screen = 0x10,
427 psr_power_opt_ds_disable_allow = 0x100,
430 enum dml_hostvm_override_opts {
431 DML_HOSTVM_NO_OVERRIDE = 0x0,
432 DML_HOSTVM_OVERRIDE_FALSE = 0x1,
433 DML_HOSTVM_OVERRIDE_TRUE = 0x2,
439 DCC_HALF_REQ_DISALBE = 2,
443 * enum pipe_split_policy - Pipe split strategy supported by DCN
445 * This enum is used to define the pipe split policy supported by DCN. By
446 * default, DC favors MPC_SPLIT_DYNAMIC.
448 enum pipe_split_policy {
450 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
451 * pipe in order to bring the best trade-off between performance and
452 * power consumption. This is the recommended option.
454 MPC_SPLIT_DYNAMIC = 0,
457 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
458 * try any sort of split optimization.
463 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
464 * optimize the pipe utilization when using a single display; if the
465 * user connects to a second display, DC will avoid pipe split.
467 MPC_SPLIT_AVOID_MULT_DISP = 2,
470 enum wm_report_mode {
471 WM_REPORT_DEFAULT = 0,
472 WM_REPORT_OVERRIDE = 1,
475 dtm_level_p0 = 0,/*highest voltage*/
479 dtm_level_p4,/*when active_display_count = 0*/
483 DCN_PWR_STATE_UNKNOWN = -1,
484 DCN_PWR_STATE_MISSION_MODE = 0,
485 DCN_PWR_STATE_LOW_POWER = 3,
488 enum dcn_zstate_support_state {
489 DCN_ZSTATE_SUPPORT_UNKNOWN,
490 DCN_ZSTATE_SUPPORT_ALLOW,
491 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
492 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
493 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
494 DCN_ZSTATE_SUPPORT_DISALLOW,
498 * struct dc_clocks - DC pipe clocks
500 * For any clocks that may differ per pipe only the max is stored in this
505 int actual_dispclk_khz;
507 int actual_dppclk_khz;
508 int disp_dpp_voltage_level_khz;
511 int dcfclk_deep_sleep_khz;
515 bool p_state_change_support;
516 enum dcn_zstate_support_state zstate_support;
519 bool fclk_p_state_change_support;
520 enum dcn_pwr_state pwr_state;
522 * Elements below are not compared for the purposes of
523 * optimization required
525 bool prev_p_state_change_support;
526 bool fclk_prev_p_state_change_support;
530 * @fw_based_mclk_switching
532 * DC has a mechanism that leverage the variable refresh rate to switch
533 * memory clock in cases that we have a large latency to achieve the
534 * memory clock change and a short vblank window. DC has some
535 * requirements to enable this feature, and this field describes if the
536 * system support or not such a feature.
538 bool fw_based_mclk_switching;
539 bool fw_based_mclk_switching_shut_down;
541 enum dtm_pstate dtm_level;
542 int max_supported_dppclk_khz;
543 int max_supported_dispclk_khz;
544 int bw_dppclk_khz; /*a copy of dppclk_khz*/
548 struct dc_bw_validation_profile {
551 unsigned long long total_ticks;
552 unsigned long long voltage_level_ticks;
553 unsigned long long watermark_ticks;
554 unsigned long long rq_dlg_ticks;
556 unsigned long long total_count;
557 unsigned long long skip_fast_count;
558 unsigned long long skip_pass_count;
559 unsigned long long skip_fail_count;
562 #define BW_VAL_TRACE_SETUP() \
563 unsigned long long end_tick = 0; \
564 unsigned long long voltage_level_tick = 0; \
565 unsigned long long watermark_tick = 0; \
566 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
567 dm_get_timestamp(dc->ctx) : 0
569 #define BW_VAL_TRACE_COUNT() \
570 if (dc->debug.bw_val_profile.enable) \
571 dc->debug.bw_val_profile.total_count++
573 #define BW_VAL_TRACE_SKIP(status) \
574 if (dc->debug.bw_val_profile.enable) { \
575 if (!voltage_level_tick) \
576 voltage_level_tick = dm_get_timestamp(dc->ctx); \
577 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
580 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
581 if (dc->debug.bw_val_profile.enable) \
582 voltage_level_tick = dm_get_timestamp(dc->ctx)
584 #define BW_VAL_TRACE_END_WATERMARKS() \
585 if (dc->debug.bw_val_profile.enable) \
586 watermark_tick = dm_get_timestamp(dc->ctx)
588 #define BW_VAL_TRACE_FINISH() \
589 if (dc->debug.bw_val_profile.enable) { \
590 end_tick = dm_get_timestamp(dc->ctx); \
591 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
592 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
593 if (watermark_tick) { \
594 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
595 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
599 union mem_low_power_enable_options {
614 union root_clock_optimization_options {
626 uint32_t reserved: 22;
631 union dpia_debug_options {
633 uint32_t disable_dpia:1; /* bit 0 */
634 uint32_t force_non_lttpr:1; /* bit 1 */
635 uint32_t extend_aux_rd_interval:1; /* bit 2 */
636 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
637 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
638 uint32_t reserved:27;
643 /* AUX wake work around options
644 * 0: enable/disable work around
645 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
647 * 31-16: timeout in ms
649 union aux_wake_wa_options {
651 uint32_t enable_wa : 1;
652 uint32_t use_default_timeout : 1;
654 uint32_t timeout_ms : 16;
659 struct dc_debug_data {
660 uint32_t ltFailCount;
661 uint32_t i2cErrorCount;
662 uint32_t auxErrorCount;
665 struct dc_phy_addr_space_config {
678 uint64_t page_table_start_addr;
679 uint64_t page_table_end_addr;
680 uint64_t page_table_base_addr;
681 bool base_addr_is_mc_addr;
686 uint64_t page_table_default_page_addr;
689 struct dc_virtual_addr_space_config {
690 uint64_t page_table_base_addr;
691 uint64_t page_table_start_addr;
692 uint64_t page_table_end_addr;
693 uint32_t page_table_block_size_in_bytes;
694 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
697 struct dc_bounding_box_overrides {
699 int sr_enter_plus_exit_time_ns;
700 int urgent_latency_ns;
701 int percent_of_ideal_drambw;
702 int dram_clock_change_latency_ns;
703 int dummy_clock_change_latency_ns;
704 int fclk_clock_change_latency_ns;
705 /* This forces a hard min on the DCFCLK we use
706 * for DML. Unlike the debug option for forcing
707 * DCFCLK, this override affects watermark calculations
713 struct resource_pool;
718 * struct dc_debug_options - DC debug struct
720 * This struct provides a simple mechanism for developers to change some
721 * configurations, enable/disable features, and activate extra debug options.
722 * This can be very handy to narrow down whether some specific feature is
723 * causing an issue or not.
725 struct dc_debug_options {
726 bool native422_support;
728 enum visual_confirm visual_confirm;
729 int visual_confirm_rect_height;
736 bool validation_trace;
737 bool bandwidth_calcs_trace;
738 int max_downscale_src_width;
740 /* stutter efficiency related */
741 bool disable_stutter;
743 enum dcc_option disable_dcc;
746 * @pipe_split_policy: Define which pipe split policy is used by the
749 enum pipe_split_policy pipe_split_policy;
750 bool force_single_disp_pipe_split;
751 bool voltage_align_fclk;
752 bool disable_min_fclk;
754 bool disable_dfs_bypass;
755 bool disable_dpp_power_gate;
756 bool disable_hubp_power_gate;
757 bool disable_dsc_power_gate;
758 int dsc_min_slice_height_override;
759 int dsc_bpp_increment_div;
760 bool disable_pplib_wm_range;
761 enum wm_report_mode pplib_wm_report_mode;
762 unsigned int min_disp_clk_khz;
763 unsigned int min_dpp_clk_khz;
764 unsigned int min_dram_clk_khz;
765 int sr_exit_time_dpm0_ns;
766 int sr_enter_plus_exit_time_dpm0_ns;
768 int sr_enter_plus_exit_time_ns;
769 int urgent_latency_ns;
770 uint32_t underflow_assert_delay_us;
771 int percent_of_ideal_drambw;
772 int dram_clock_change_latency_ns;
773 bool optimized_watermark;
775 bool disable_pplib_clock_request;
776 bool disable_clock_gate;
777 bool disable_mem_low_power;
780 bool force_abm_enable;
781 bool disable_stereo_support;
783 bool performance_trace;
784 bool az_endpoint_mute_only;
785 bool always_use_regamma;
786 bool recovery_enabled;
787 bool avoid_vbios_exec_table;
788 bool scl_reset_length10;
790 bool skip_detection_link_training;
791 uint32_t edid_read_retry_times;
792 unsigned int force_odm_combine; //bit vector based on otg inst
793 unsigned int seamless_boot_odm_combine;
794 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
795 int minimum_z8_residency_time;
797 unsigned int force_fclk_khz;
799 bool dmub_offload_enabled;
800 bool dmcub_emulation;
801 bool disable_idle_power_optimizations;
802 unsigned int mall_size_override;
803 unsigned int mall_additional_timer_percent;
804 bool mall_error_as_fatal;
805 bool dmub_command_table; /* for testing only */
806 struct dc_bw_validation_profile bw_val_profile;
808 bool disable_48mhz_pwrdwn;
809 /* This forces a hard min on the DCFCLK requested to SMU/PP
810 * watermarks are not affected.
812 unsigned int force_min_dcfclk_mhz;
814 bool disable_timing_sync;
816 int force_clock_mode;/*every mode change.*/
818 bool disable_dram_clock_change_vactive_support;
819 bool validate_dml_output;
820 bool enable_dmcub_surface_flip;
821 bool usbc_combo_phy_reset_wa;
822 bool enable_dram_clock_change_one_display_vactive;
823 /* TODO - remove once tested */
825 bool set_mst_en_for_sst;
827 bool force_dp2_lt_fallback_method;
828 bool ignore_cable_id;
829 union mem_low_power_enable_options enable_mem_low_power;
830 union root_clock_optimization_options root_clock_optimization;
831 bool hpo_optimization;
832 bool force_vblank_alignment;
834 /* Enable dmub aux for legacy ddc */
835 bool enable_dmub_aux_for_legacy_ddc;
837 /* FEC/PSR1 sequence enable delay in 100us */
838 uint8_t fec_enable_delay_in100us;
839 bool enable_driver_sequence_debug;
840 enum det_size crb_alloc_policy;
841 int crb_alloc_policy_min_disp_count;
843 bool enable_z9_disable_interface;
844 bool psr_skip_crtc_disable;
845 union dpia_debug_options dpia_debug;
846 bool disable_fixed_vs_aux_timeout_wa;
847 bool force_disable_subvp;
848 bool force_subvp_mclk_switch;
849 bool allow_sw_cursor_fallback;
850 unsigned int force_subvp_num_ways;
851 unsigned int force_mall_ss_num_ways;
852 bool alloc_extra_way_for_cursor;
853 uint32_t subvp_extra_lines;
854 bool force_usr_allow;
855 /* uses value at boot and disables switch */
856 bool disable_dtb_ref_clk_switch;
857 uint32_t fixed_vs_aux_delay_config_wa;
858 bool extended_blank_optimization;
859 union aux_wake_wa_options aux_wake_wa;
860 uint32_t mst_start_top_delay;
861 uint8_t psr_power_use_phy_fsm;
862 enum dml_hostvm_override_opts dml_hostvm_override;
863 bool dml_disallow_alternate_prefetch_modes;
864 bool use_legacy_soc_bb_mechanism;
865 bool exit_idle_opt_for_cursor_updates;
866 bool enable_single_display_2to1_odm_policy;
867 bool enable_double_buffered_dsc_pg_support;
868 bool enable_dp_dig_pixel_rate_div_policy;
869 enum lttpr_mode lttpr_mode_override;
870 unsigned int dsc_delay_factor_wa_x1000;
871 unsigned int min_prefetch_in_strobe_ns;
872 bool disable_unbounded_requesting;
873 bool dig_fifo_off_in_blank;
874 bool temp_mst_deallocation_sequence;
875 bool override_dispclk_programming;
876 bool disable_fpo_optimizations;
880 struct gpu_info_soc_bounding_box_v1_0;
882 struct dc_debug_options debug;
883 struct dc_versions versions;
885 struct dc_cap_funcs cap_funcs;
886 struct dc_config config;
887 struct dc_bounding_box_overrides bb_overrides;
888 struct dc_bug_wa work_arounds;
889 struct dc_context *ctx;
890 struct dc_phy_addr_space_config vm_pa_config;
893 struct dc_link *links[MAX_PIPES * 2];
894 struct link_service *link_srv;
896 struct dc_state *current_state;
897 struct resource_pool *res_pool;
899 struct clk_mgr *clk_mgr;
901 /* Display Engine Clock levels */
902 struct dm_pp_clock_levels sclk_lvls;
904 /* Inputs into BW and WM calculations. */
905 struct bw_calcs_dceip *bw_dceip;
906 struct bw_calcs_vbios *bw_vbios;
907 struct dcn_soc_bounding_box *dcn_soc;
908 struct dcn_ip_params *dcn_ip;
909 struct display_mode_lib dml;
912 struct hw_sequencer_funcs hwss;
913 struct dce_hwseq *hwseq;
915 /* Require to optimize clocks and bandwidth for added/removed planes */
916 bool optimized_required;
917 bool wm_optimized_required;
918 bool idle_optimizations_allowed;
919 bool enable_c20_dtm_b0;
921 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
924 struct compressor *fbc_compressor;
926 struct dc_debug_data debug_data;
927 struct dpcd_vendor_signature vendor_signature;
929 const char *build_id;
930 struct vm_helper *vm_helper;
932 uint32_t *dcn_reg_offsets;
933 uint32_t *nbio_reg_offsets;
939 * For matching clock_limits table in driver with table
942 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
943 } update_bw_bounding_box;
947 enum frame_buffer_mode {
948 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
949 FRAME_BUFFER_MODE_ZFB_ONLY,
950 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
953 struct dchub_init_data {
954 int64_t zfb_phys_addr_base;
955 int64_t zfb_mc_base_addr;
956 uint64_t zfb_size_in_byte;
957 enum frame_buffer_mode fb_mode;
958 bool dchub_initialzied;
959 bool dchub_info_valid;
962 struct dc_init_data {
963 struct hw_asic_id asic_id;
964 void *driver; /* ctx */
965 struct cgs_device *cgs_device;
966 struct dc_bounding_box_overrides bb_overrides;
968 int num_virtual_links;
970 * If 'vbios_override' not NULL, it will be called instead
971 * of the real VBIOS. Intended use is Diagnostics on FPGA.
973 struct dc_bios *vbios_override;
974 enum dce_environment dce_environment;
976 struct dmub_offload_funcs *dmub_if;
977 struct dc_reg_helper_state *dmub_offload;
979 struct dc_config flags;
982 struct dpcd_vendor_signature vendor_signature;
983 bool force_smu_not_present;
985 * IP offset for run time initializaion of register addresses
987 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
988 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
991 uint32_t *dcn_reg_offsets;
992 uint32_t *nbio_reg_offsets;
995 struct dc_callback_init {
996 struct cp_psp cp_psp;
999 struct dc *dc_create(const struct dc_init_data *init_params);
1000 void dc_hardware_init(struct dc *dc);
1002 int dc_get_vmid_use_vector(struct dc *dc);
1003 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1004 /* Returns the number of vmids supported */
1005 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1006 void dc_init_callbacks(struct dc *dc,
1007 const struct dc_callback_init *init_params);
1008 void dc_deinit_callbacks(struct dc *dc);
1009 void dc_destroy(struct dc **dc);
1011 /* Surface Interfaces */
1014 TRANSFER_FUNC_POINTS = 1025
1017 struct dc_hdr_static_metadata {
1018 /* display chromaticities and white point in units of 0.00001 */
1019 unsigned int chromaticity_green_x;
1020 unsigned int chromaticity_green_y;
1021 unsigned int chromaticity_blue_x;
1022 unsigned int chromaticity_blue_y;
1023 unsigned int chromaticity_red_x;
1024 unsigned int chromaticity_red_y;
1025 unsigned int chromaticity_white_point_x;
1026 unsigned int chromaticity_white_point_y;
1028 uint32_t min_luminance;
1029 uint32_t max_luminance;
1030 uint32_t maximum_content_light_level;
1031 uint32_t maximum_frame_average_light_level;
1034 enum dc_transfer_func_type {
1036 TF_TYPE_DISTRIBUTED_POINTS,
1041 struct dc_transfer_func_distributed_points {
1042 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1043 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1044 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1046 uint16_t end_exponent;
1047 uint16_t x_point_at_y1_red;
1048 uint16_t x_point_at_y1_green;
1049 uint16_t x_point_at_y1_blue;
1052 enum dc_transfer_func_predefined {
1053 TRANSFER_FUNCTION_SRGB,
1054 TRANSFER_FUNCTION_BT709,
1055 TRANSFER_FUNCTION_PQ,
1056 TRANSFER_FUNCTION_LINEAR,
1057 TRANSFER_FUNCTION_UNITY,
1058 TRANSFER_FUNCTION_HLG,
1059 TRANSFER_FUNCTION_HLG12,
1060 TRANSFER_FUNCTION_GAMMA22,
1061 TRANSFER_FUNCTION_GAMMA24,
1062 TRANSFER_FUNCTION_GAMMA26
1066 struct dc_transfer_func {
1067 struct kref refcount;
1068 enum dc_transfer_func_type type;
1069 enum dc_transfer_func_predefined tf;
1070 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1071 uint32_t sdr_ref_white_level;
1073 struct pwl_params pwl;
1074 struct dc_transfer_func_distributed_points tf_pts;
1079 union dc_3dlut_state {
1081 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
1082 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
1083 uint32_t rmu_mux_num:3; /*index of mux to use*/
1084 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1085 uint32_t mpc_rmu1_mux:4;
1086 uint32_t mpc_rmu2_mux:4;
1087 uint32_t reserved:15;
1094 struct kref refcount;
1095 struct tetrahedral_params lut_3d;
1096 struct fixed31_32 hdr_multiplier;
1097 union dc_3dlut_state state;
1100 * This structure is filled in by dc_surface_get_status and contains
1101 * the last requested address and the currently active address so the called
1102 * can determine if there are any outstanding flips
1104 struct dc_plane_status {
1105 struct dc_plane_address requested_address;
1106 struct dc_plane_address current_address;
1107 bool is_flip_pending;
1111 union surface_update_flags {
1114 uint32_t addr_update:1;
1115 /* Medium updates */
1116 uint32_t dcc_change:1;
1117 uint32_t color_space_change:1;
1118 uint32_t horizontal_mirror_change:1;
1119 uint32_t per_pixel_alpha_change:1;
1120 uint32_t global_alpha_change:1;
1121 uint32_t hdr_mult:1;
1122 uint32_t rotation_change:1;
1123 uint32_t swizzle_change:1;
1124 uint32_t scaling_change:1;
1125 uint32_t position_change:1;
1126 uint32_t in_transfer_func_change:1;
1127 uint32_t input_csc_change:1;
1128 uint32_t coeff_reduction_change:1;
1129 uint32_t output_tf_change:1;
1130 uint32_t pixel_format_change:1;
1131 uint32_t plane_size_change:1;
1132 uint32_t gamut_remap_change:1;
1135 uint32_t new_plane:1;
1136 uint32_t bpp_change:1;
1137 uint32_t gamma_change:1;
1138 uint32_t bandwidth_change:1;
1139 uint32_t clock_change:1;
1140 uint32_t stereo_format_change:1;
1142 uint32_t tmz_changed:1;
1143 uint32_t full_update:1;
1149 struct dc_plane_state {
1150 struct dc_plane_address address;
1151 struct dc_plane_flip_time time;
1152 bool triplebuffer_flips;
1153 struct scaling_taps scaling_quality;
1154 struct rect src_rect;
1155 struct rect dst_rect;
1156 struct rect clip_rect;
1158 struct plane_size plane_size;
1159 union dc_tiling_info tiling_info;
1161 struct dc_plane_dcc_param dcc;
1163 struct dc_gamma *gamma_correction;
1164 struct dc_transfer_func *in_transfer_func;
1165 struct dc_bias_and_scale *bias_and_scale;
1166 struct dc_csc_transform input_csc_color_matrix;
1167 struct fixed31_32 coeff_reduction_factor;
1168 struct fixed31_32 hdr_mult;
1169 struct colorspace_transform gamut_remap_matrix;
1171 // TODO: No longer used, remove
1172 struct dc_hdr_static_metadata hdr_static_ctx;
1174 enum dc_color_space color_space;
1176 struct dc_3dlut *lut3d_func;
1177 struct dc_transfer_func *in_shaper_func;
1178 struct dc_transfer_func *blend_tf;
1180 struct dc_transfer_func *gamcor_tf;
1181 enum surface_pixel_format format;
1182 enum dc_rotation_angle rotation;
1183 enum plane_stereo_format stereo_format;
1185 bool is_tiling_rotated;
1186 bool per_pixel_alpha;
1187 bool pre_multiplied_alpha;
1189 int global_alpha_value;
1191 bool flip_immediate;
1192 bool horizontal_mirror;
1195 union surface_update_flags update_flags;
1196 bool flip_int_enabled;
1197 bool skip_manual_trigger;
1199 /* private to DC core */
1200 struct dc_plane_status status;
1201 struct dc_context *ctx;
1203 /* HACK: Workaround for forcing full reprogramming under some conditions */
1204 bool force_full_update;
1206 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1208 /* private to dc_surface.c */
1209 enum dc_irq_source irq_source;
1210 struct kref refcount;
1211 struct tg_color visual_confirm_color;
1213 bool is_statically_allocated;
1216 struct dc_plane_info {
1217 struct plane_size plane_size;
1218 union dc_tiling_info tiling_info;
1219 struct dc_plane_dcc_param dcc;
1220 enum surface_pixel_format format;
1221 enum dc_rotation_angle rotation;
1222 enum plane_stereo_format stereo_format;
1223 enum dc_color_space color_space;
1224 bool horizontal_mirror;
1226 bool per_pixel_alpha;
1227 bool pre_multiplied_alpha;
1229 int global_alpha_value;
1230 bool input_csc_enabled;
1234 struct dc_scaling_info {
1235 struct rect src_rect;
1236 struct rect dst_rect;
1237 struct rect clip_rect;
1238 struct scaling_taps scaling_quality;
1241 struct dc_surface_update {
1242 struct dc_plane_state *surface;
1244 /* isr safe update parameters. null means no updates */
1245 const struct dc_flip_addrs *flip_addr;
1246 const struct dc_plane_info *plane_info;
1247 const struct dc_scaling_info *scaling_info;
1248 struct fixed31_32 hdr_mult;
1249 /* following updates require alloc/sleep/spin that is not isr safe,
1250 * null means no updates
1252 const struct dc_gamma *gamma;
1253 const struct dc_transfer_func *in_transfer_func;
1255 const struct dc_csc_transform *input_csc_color_matrix;
1256 const struct fixed31_32 *coeff_reduction_factor;
1257 const struct dc_transfer_func *func_shaper;
1258 const struct dc_3dlut *lut3d_func;
1259 const struct dc_transfer_func *blend_tf;
1260 const struct colorspace_transform *gamut_remap_matrix;
1264 * Create a new surface with default parameters;
1266 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1267 const struct dc_plane_status *dc_plane_get_status(
1268 const struct dc_plane_state *plane_state);
1270 void dc_plane_state_retain(struct dc_plane_state *plane_state);
1271 void dc_plane_state_release(struct dc_plane_state *plane_state);
1273 void dc_gamma_retain(struct dc_gamma *dc_gamma);
1274 void dc_gamma_release(struct dc_gamma **dc_gamma);
1275 struct dc_gamma *dc_create_gamma(void);
1277 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1278 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1279 struct dc_transfer_func *dc_create_transfer_func(void);
1281 struct dc_3dlut *dc_create_3dlut_func(void);
1282 void dc_3dlut_func_release(struct dc_3dlut *lut);
1283 void dc_3dlut_func_retain(struct dc_3dlut *lut);
1285 void dc_post_update_surfaces_to_stream(
1288 #include "dc_stream.h"
1291 * struct dc_validation_set - Struct to store surface/stream associations for validation
1293 struct dc_validation_set {
1295 * @stream: Stream state properties
1297 struct dc_stream_state *stream;
1300 * @plane_state: Surface state
1302 struct dc_plane_state *plane_states[MAX_SURFACES];
1305 * @plane_count: Total of active planes
1307 uint8_t plane_count;
1310 bool dc_validate_boot_timing(const struct dc *dc,
1311 const struct dc_sink *sink,
1312 struct dc_crtc_timing *crtc_timing);
1314 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1316 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1318 enum dc_status dc_validate_with_context(struct dc *dc,
1319 const struct dc_validation_set set[],
1321 struct dc_state *context,
1322 bool fast_validate);
1324 bool dc_set_generic_gpio_for_stereo(bool enable,
1325 struct gpio_service *gpio_service);
1328 * fast_validate: we return after determining if we can support the new state,
1329 * but before we populate the programming info
1331 enum dc_status dc_validate_global_state(
1333 struct dc_state *new_ctx,
1334 bool fast_validate);
1337 void dc_resource_state_construct(
1338 const struct dc *dc,
1339 struct dc_state *dst_ctx);
1341 bool dc_acquire_release_mpc_3dlut(
1342 struct dc *dc, bool acquire,
1343 struct dc_stream_state *stream,
1344 struct dc_3dlut **lut,
1345 struct dc_transfer_func **shaper);
1347 void dc_resource_state_copy_construct(
1348 const struct dc_state *src_ctx,
1349 struct dc_state *dst_ctx);
1351 void dc_resource_state_copy_construct_current(
1352 const struct dc *dc,
1353 struct dc_state *dst_ctx);
1355 void dc_resource_state_destruct(struct dc_state *context);
1357 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1359 enum dc_status dc_commit_streams(struct dc *dc,
1360 struct dc_stream_state *streams[],
1361 uint8_t stream_count);
1363 struct dc_state *dc_create_state(struct dc *dc);
1364 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1365 void dc_retain_state(struct dc_state *context);
1366 void dc_release_state(struct dc_state *context);
1368 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1369 struct dc_stream_state *stream,
1373 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1375 /* The function returns minimum bandwidth required to drive a given timing
1376 * return - minimum required timing bandwidth in kbps.
1378 uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing);
1380 /* Link Interfaces */
1382 * A link contains one or more sinks and their connected status.
1383 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1386 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1387 unsigned int sink_count;
1388 struct dc_sink *local_sink;
1389 unsigned int link_index;
1390 enum dc_connection_type type;
1391 enum signal_type connector_signal;
1392 enum dc_irq_source irq_source_hpd;
1393 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
1395 bool is_hpd_filter_disabled;
1399 * @link_state_valid:
1401 * If there is no link and local sink, this variable should be set to
1402 * false. Otherwise, it should be set to true; usually, the function
1403 * core_link_enable_stream sets this field to true.
1405 bool link_state_valid;
1406 bool aux_access_disabled;
1407 bool sync_lt_in_progress;
1408 bool skip_stream_reenable;
1409 bool is_internal_display;
1410 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1411 bool is_dig_mapping_flexible;
1412 bool hpd_status; /* HPD status of link without physical HPD pin. */
1413 bool is_hpd_pending; /* Indicates a new received hpd */
1414 bool is_automated; /* Indicates automated testing */
1416 bool edp_sink_present;
1418 struct dp_trace dp_trace;
1420 /* caps is the same as reported_link_cap. link_traing use
1421 * reported_link_cap. Will clean up. TODO
1423 struct dc_link_settings reported_link_cap;
1424 struct dc_link_settings verified_link_cap;
1425 struct dc_link_settings cur_link_settings;
1426 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1427 struct dc_link_settings preferred_link_setting;
1428 /* preferred_training_settings are override values that
1429 * come from DM. DM is responsible for the memory
1430 * management of the override pointers.
1432 struct dc_link_training_overrides preferred_training_settings;
1433 struct dp_audio_test_data audio_test_data;
1435 uint8_t ddc_hw_inst;
1439 uint8_t link_enc_hw_inst;
1440 /* DIG link encoder ID. Used as index in link encoder resource pool.
1441 * For links with fixed mapping to DIG, this is not changed after dc_link
1444 enum engine_id eng_id;
1446 bool test_pattern_enabled;
1447 union compliance_test_state compliance_test_state;
1451 struct ddc_service *ddc;
1455 /* Private to DC core */
1457 const struct dc *dc;
1459 struct dc_context *ctx;
1461 struct panel_cntl *panel_cntl;
1462 struct link_encoder *link_enc;
1463 struct graphics_object_id link_id;
1464 /* Endpoint type distinguishes display endpoints which do not have entries
1465 * in the BIOS connector table from those that do. Helps when tracking link
1466 * encoder to display endpoint assignments.
1468 enum display_endpoint_type ep_type;
1469 union ddi_channel_mapping ddi_channel_mapping;
1470 struct connector_device_tag_info device_tag;
1471 struct dpcd_caps dpcd_caps;
1472 uint32_t dongle_max_pix_clk;
1473 unsigned short chip_caps;
1474 unsigned int dpcd_sink_count;
1475 struct hdcp_caps hdcp_caps;
1476 enum edp_revision edp_revision;
1477 union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1479 struct psr_settings psr_settings;
1481 /* Drive settings read from integrated info table */
1482 struct dc_lane_settings bios_forced_drive_settings;
1484 /* Vendor specific LTTPR workaround variables */
1485 uint8_t vendor_specific_lttpr_link_rate_wa;
1486 bool apply_vendor_specific_lttpr_link_rate_wa;
1488 /* MST record stream using this link */
1490 bool dp_keep_receiver_powered;
1492 bool dp_skip_reset_segment;
1493 bool dp_skip_fs_144hz;
1494 bool dp_mot_reset_segment;
1495 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1496 bool dpia_mst_dsc_always_on;
1497 /* Forced DPIA into TBT3 compatibility mode. */
1498 bool dpia_forced_tbt3_mode;
1499 bool dongle_mode_timing_override;
1501 struct link_mst_stream_allocation_table mst_stream_alloc_table;
1503 struct dc_link_status link_status;
1504 struct dprx_states dprx_states;
1506 struct gpio *hpd_gpio;
1507 enum dc_link_fec_state fec_state;
1508 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
1510 struct dc_panel_config panel_config;
1511 struct phy_state phy_state;
1512 // BW ALLOCATON USB4 ONLY
1513 struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1516 /* Return an enumerated dc_link.
1517 * dc_link order is constant and determined at
1518 * boot time. They cannot be created or destroyed.
1519 * Use dc_get_caps() to get number of links.
1521 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1523 /* Return instance id of the edp link. Inst 0 is primary edp link. */
1524 bool dc_get_edp_link_panel_inst(const struct dc *dc,
1525 const struct dc_link *link,
1526 unsigned int *inst_out);
1528 /* Return an array of link pointers to edp links. */
1529 void dc_get_edp_links(const struct dc *dc,
1530 struct dc_link **edp_links,
1533 /* The function initiates detection handshake over the given link. It first
1534 * determines if there are display connections over the link. If so it initiates
1535 * detection protocols supported by the connected receiver device. The function
1536 * contains protocol specific handshake sequences which are sometimes mandatory
1537 * to establish a proper connection between TX and RX. So it is always
1538 * recommended to call this function as the first link operation upon HPD event
1539 * or power up event. Upon completion, the function will update link structure
1540 * in place based on latest RX capabilities. The function may also cause dpms
1541 * to be reset to off for all currently enabled streams to the link. It is DM's
1542 * responsibility to serialize detection and DPMS updates.
1544 * @reason - Indicate which event triggers this detection. dc may customize
1545 * detection flow depending on the triggering events.
1546 * return false - if detection is not fully completed. This could happen when
1547 * there is an unrecoverable error during detection or detection is partially
1548 * completed (detection has been delegated to dm mst manager ie.
1549 * link->connection_type == dc_connection_mst_branch when returning false).
1550 * return true - detection is completed, link has been fully updated with latest
1553 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1555 struct dc_sink_init_data;
1557 /* When link connection type is dc_connection_mst_branch, remote sink can be
1558 * added to the link. The interface creates a remote sink and associates it with
1559 * current link. The sink will be retained by link until remove remote sink is
1562 * @dc_link - link the remote sink will be added to.
1563 * @edid - byte array of EDID raw data.
1564 * @len - size of the edid in byte
1567 struct dc_sink *dc_link_add_remote_sink(
1568 struct dc_link *dc_link,
1569 const uint8_t *edid,
1571 struct dc_sink_init_data *init_data);
1573 /* Remove remote sink from a link with dc_connection_mst_branch connection type.
1574 * @link - link the sink should be removed from
1575 * @sink - sink to be removed.
1577 void dc_link_remove_remote_sink(
1578 struct dc_link *link,
1579 struct dc_sink *sink);
1581 /* Enable HPD interrupt handler for a given link */
1582 void dc_link_enable_hpd(const struct dc_link *link);
1584 /* Disable HPD interrupt handler for a given link */
1585 void dc_link_disable_hpd(const struct dc_link *link);
1587 /* determine if there is a sink connected to the link
1589 * @type - dc_connection_single if connected, dc_connection_none otherwise.
1590 * return - false if an unexpected error occurs, true otherwise.
1592 * NOTE: This function doesn't detect downstream sink connections i.e
1593 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1594 * return dc_connection_single if the branch device is connected despite of
1595 * downstream sink's connection status.
1597 bool dc_link_detect_connection_type(struct dc_link *link,
1598 enum dc_connection_type *type);
1600 /* query current hpd pin value
1601 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1604 bool dc_link_get_hpd_state(struct dc_link *link);
1606 /* Getter for cached link status from given link */
1607 const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1609 /* enable/disable hardware HPD filter.
1611 * @link - The link the HPD pin is associated with.
1612 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1613 * handler once after no HPD change has been detected within dc default HPD
1614 * filtering interval since last HPD event. i.e if display keeps toggling hpd
1615 * pulses within default HPD interval, no HPD event will be received until HPD
1616 * toggles have stopped. Then HPD event will be queued to irq handler once after
1617 * dc default HPD filtering interval since last HPD event.
1619 * @enable = false - disable hardware HPD filter. HPD event will be queued
1620 * immediately to irq handler after no HPD change has been detected within
1621 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
1623 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
1625 /* submit i2c read/write payloads through ddc channel
1626 * @link_index - index to a link with ddc in i2c mode
1627 * @cmd - i2c command structure
1628 * return - true if success, false otherwise.
1632 uint32_t link_index,
1633 struct i2c_command *cmd);
1635 /* submit i2c read/write payloads through oem channel
1636 * @link_index - index to a link with ddc in i2c mode
1637 * @cmd - i2c command structure
1638 * return - true if success, false otherwise.
1640 bool dc_submit_i2c_oem(
1642 struct i2c_command *cmd);
1644 enum aux_return_code_type;
1645 /* Attempt to transfer the given aux payload. This function does not perform
1646 * retries or handle error states. The reply is returned in the payload->reply
1647 * and the result through operation_result. Returns the number of bytes
1648 * transferred,or -1 on a failure.
1650 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
1651 struct aux_payload *payload,
1652 enum aux_return_code_type *operation_result);
1654 bool dc_is_oem_i2c_device_present(
1656 size_t slave_address
1659 /* return true if the connected receiver supports the hdcp version */
1660 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1661 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1663 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1665 * TODO - When defer_handling is true the function will have a different purpose.
1666 * It no longer does complete hpd rx irq handling. We should create a separate
1667 * interface specifically for this case.
1670 * true - Downstream port status changed. DM should call DC to do the
1672 * false - no change in Downstream port status. No further action required
1675 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
1676 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
1677 bool defer_handling, bool *has_left_work);
1678 /* handle DP specs define test automation sequence*/
1679 void dc_link_dp_handle_automated_test(struct dc_link *link);
1681 /* handle DP Link loss sequence and try to recover RX link loss with best
1684 void dc_link_dp_handle_link_loss(struct dc_link *link);
1686 /* Determine if hpd rx irq should be handled or ignored
1687 * return true - hpd rx irq should be handled.
1688 * return false - it is safe to ignore hpd rx irq event
1690 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
1692 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
1693 * @link - link the hpd irq data associated with
1694 * @hpd_irq_dpcd_data - input hpd irq data
1695 * return - true if hpd irq data indicates a link lost
1697 bool dc_link_check_link_loss_status(struct dc_link *link,
1698 union hpd_irq_data *hpd_irq_dpcd_data);
1700 /* Read hpd rx irq data from a given link
1701 * @link - link where the hpd irq data should be read from
1702 * @irq_data - output hpd irq data
1703 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1706 enum dc_status dc_link_dp_read_hpd_rx_irq_data(
1707 struct dc_link *link,
1708 union hpd_irq_data *irq_data);
1710 /* The function clears recorded DP RX states in the link. DM should call this
1711 * function when it is resuming from S3 power state to previously connected links.
1713 * TODO - in the future we should consider to expand link resume interface to
1714 * support clearing previous rx states. So we don't have to rely on dm to call
1715 * this interface explicitly.
1717 void dc_link_clear_dprx_states(struct dc_link *link);
1719 /* Destruct the mst topology of the link and reset the allocated payload table
1721 * NOTE: this should only be called if DM chooses not to call dc_link_detect but
1722 * still wants to reset MST topology on an unplug event */
1723 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
1725 /* The function calculates effective DP link bandwidth when a given link is
1726 * using the given link settings.
1728 * return - total effective link bandwidth in kbps.
1730 uint32_t dc_link_bandwidth_kbps(
1731 const struct dc_link *link,
1732 const struct dc_link_settings *link_setting);
1734 /* The function takes a snapshot of current link resource allocation state
1735 * @dc: pointer to dc of the dm calling this
1736 * @map: a dc link resource snapshot defined internally to dc.
1738 * DM needs to capture a snapshot of current link resource allocation mapping
1739 * and store it in its persistent storage.
1741 * Some of the link resource is using first come first serve policy.
1742 * The allocation mapping depends on original hotplug order. This information
1743 * is lost after driver is loaded next time. The snapshot is used in order to
1744 * restore link resource to its previous state so user will get consistent
1745 * link capability allocation across reboot.
1748 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
1750 /* This function restores link resource allocation state from a snapshot
1751 * @dc: pointer to dc of the dm calling this
1752 * @map: a dc link resource snapshot defined internally to dc.
1754 * DM needs to call this function after initial link detection on boot and
1755 * before first commit streams to restore link resource allocation state
1756 * from previous boot session.
1758 * Some of the link resource is using first come first serve policy.
1759 * The allocation mapping depends on original hotplug order. This information
1760 * is lost after driver is loaded next time. The snapshot is used in order to
1761 * restore link resource to its previous state so user will get consistent
1762 * link capability allocation across reboot.
1765 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
1767 /* TODO: this is not meant to be exposed to DM. Should switch to stream update
1768 * interface i.e stream_update->dsc_config
1770 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
1772 /* translate a raw link rate data to bandwidth in kbps */
1773 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
1775 /* determine the optimal bandwidth given link and required bw.
1776 * @link - current detected link
1777 * @req_bw - requested bandwidth in kbps
1778 * @link_settings - returned most optimal link settings that can fit the
1779 * requested bandwidth
1780 * return - false if link can't support requested bandwidth, true if link
1781 * settings is found.
1783 bool dc_link_decide_edp_link_settings(struct dc_link *link,
1784 struct dc_link_settings *link_settings,
1787 /* return the max dp link settings can be driven by the link without considering
1788 * connected RX device and its capability
1790 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
1791 struct dc_link_settings *max_link_enc_cap);
1793 /* determine when the link is driving MST mode, what DP link channel coding
1794 * format will be used. The decision will remain unchanged until next HPD event.
1796 * @link - a link with DP RX connection
1797 * return - if stream is committed to this link with MST signal type, type of
1798 * channel coding format dc will choose.
1800 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
1801 const struct dc_link *link);
1803 /* get max dp link settings the link can enable with all things considered. (i.e
1804 * TX/RX/Cable capabilities and dp override policies.
1806 * @link - a link with DP RX connection
1807 * return - max dp link settings the link can enable.
1810 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
1812 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
1813 * to a link with dp connector signal type.
1814 * @link - a link with dp connector signal type
1815 * return - true if connected, false otherwise
1817 bool dc_link_is_dp_sink_present(struct dc_link *link);
1819 /* Force DP lane settings update to main-link video signal and notify the change
1820 * to DP RX via DPCD. This is a debug interface used for video signal integrity
1821 * tuning purpose. The interface assumes link has already been enabled with DP
1824 * @lt_settings - a container structure with desired hw_lane_settings
1826 void dc_link_set_drive_settings(struct dc *dc,
1827 struct link_training_settings *lt_settings,
1828 struct dc_link *link);
1830 /* Enable a test pattern in Link or PHY layer in an active link for compliance
1831 * test or debugging purpose. The test pattern will remain until next un-plug.
1833 * @link - active link with DP signal output enabled.
1834 * @test_pattern - desired test pattern to output.
1835 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
1836 * @test_pattern_color_space - for video test pattern choose a desired color
1838 * @p_link_settings - For PHY pattern choose a desired link settings
1839 * @p_custom_pattern - some test pattern will require a custom input to
1840 * customize some pattern details. Otherwise keep it to NULL.
1841 * @cust_pattern_size - size of the custom pattern input.
1844 bool dc_link_dp_set_test_pattern(
1845 struct dc_link *link,
1846 enum dp_test_pattern test_pattern,
1847 enum dp_test_pattern_color_space test_pattern_color_space,
1848 const struct link_training_settings *p_link_settings,
1849 const unsigned char *p_custom_pattern,
1850 unsigned int cust_pattern_size);
1852 /* Force DP link settings to always use a specific value until reboot to a
1853 * specific link. If link has already been enabled, the interface will also
1854 * switch to desired link settings immediately. This is a debug interface to
1855 * generic dp issue trouble shooting.
1857 void dc_link_set_preferred_link_settings(struct dc *dc,
1858 struct dc_link_settings *link_setting,
1859 struct dc_link *link);
1861 /* Force DP link to customize a specific link training behavior by overriding to
1862 * standard DP specs defined protocol. This is a debug interface to trouble shoot
1863 * display specific link training issues or apply some display specific
1864 * workaround in link training.
1866 * @link_settings - if not NULL, force preferred link settings to the link.
1867 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
1868 * will apply this particular override in future link training. If NULL is
1869 * passed in, dc resets previous overrides.
1870 * NOTE: DM must keep the memory from override pointers until DM resets preferred
1871 * training settings.
1873 void dc_link_set_preferred_training_settings(struct dc *dc,
1874 struct dc_link_settings *link_setting,
1875 struct dc_link_training_overrides *lt_overrides,
1876 struct dc_link *link,
1877 bool skip_immediate_retrain);
1879 /* return - true if FEC is supported with connected DP RX, false otherwise */
1880 bool dc_link_is_fec_supported(const struct dc_link *link);
1882 /* query FEC enablement policy to determine if FEC will be enabled by dc during
1884 * return - true if FEC should be enabled, false otherwise.
1886 bool dc_link_should_enable_fec(const struct dc_link *link);
1888 /* determine lttpr mode the current link should be enabled with a specific link
1891 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
1892 struct dc_link_settings *link_setting);
1894 /* Force DP RX to update its power state.
1895 * NOTE: this interface doesn't update dp main-link. Calling this function will
1896 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
1897 * RX power state back upon finish DM specific execution requiring DP RX in a
1898 * specific power state.
1899 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
1902 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
1904 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
1905 * current value read from extended receiver cap from 02200h - 0220Fh.
1906 * Some DP RX has problems of providing accurate DP receiver caps from extended
1907 * field, this interface is a workaround to revert link back to use base caps.
1909 void dc_link_overwrite_extended_receiver_cap(
1910 struct dc_link *link);
1912 void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
1915 /* Set backlight level of an embedded panel (eDP, LVDS).
1916 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
1917 * and 16 bit fractional, where 1.0 is max backlight value.
1919 bool dc_link_set_backlight_level(const struct dc_link *dc_link,
1920 uint32_t backlight_pwm_u16_16,
1921 uint32_t frame_ramp);
1923 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
1924 bool dc_link_set_backlight_level_nits(struct dc_link *link,
1926 uint32_t backlight_millinits,
1927 uint32_t transition_time_in_ms);
1929 bool dc_link_get_backlight_level_nits(struct dc_link *link,
1930 uint32_t *backlight_millinits,
1931 uint32_t *backlight_millinits_peak);
1933 int dc_link_get_backlight_level(const struct dc_link *dc_link);
1935 int dc_link_get_target_backlight_pwm(const struct dc_link *link);
1937 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
1938 bool wait, bool force_static, const unsigned int *power_opts);
1940 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
1942 bool dc_link_setup_psr(struct dc_link *dc_link,
1943 const struct dc_stream_state *stream, struct psr_config *psr_config,
1944 struct psr_context *psr_context);
1946 /* On eDP links this function call will stall until T12 has elapsed.
1947 * If the panel is not in power off state, this function will return
1950 bool dc_link_wait_for_t12(struct dc_link *link);
1952 /* Determine if dp trace has been initialized to reflect upto date result *
1953 * return - true if trace is initialized and has valid data. False dp trace
1954 * doesn't have valid result.
1956 bool dc_dp_trace_is_initialized(struct dc_link *link);
1958 /* Query a dp trace flag to indicate if the current dp trace data has been
1961 bool dc_dp_trace_is_logged(struct dc_link *link,
1964 /* Set dp trace flag to indicate whether DM has already logged the current dp
1965 * trace data. DM can set is_logged to true upon logging and check
1966 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
1968 void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
1972 /* Obtain driver time stamp for last dp link training end. The time stamp is
1973 * formatted based on dm_get_timestamp DM function.
1974 * @in_detection - true to get link training end time stamp of last link
1975 * training in detection sequence. false to get link training end time stamp
1976 * of last link training in commit (dpms) sequence
1978 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
1981 /* Get how many link training attempts dc has done with latest sequence.
1982 * @in_detection - true to get link training count of last link
1983 * training in detection sequence. false to get link training count of last link
1984 * training in commit (dpms) sequence
1986 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
1989 /* Get how many link loss has happened since last link training attempts */
1990 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
1993 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
1996 * Send a request from DP-Tx requesting to allocate BW remotely after
1997 * allocating it locally. This will get processed by CM and a CB function
2000 * @link: pointer to the dc_link struct instance
2001 * @req_bw: The requested bw in Kbyte to allocated
2005 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2008 * Handle function for when the status of the Request above is complete.
2009 * We will find out the result of allocating on CM and update structs.
2011 * @link: pointer to the dc_link struct instance
2012 * @bw: Allocated or Estimated BW depending on the result
2013 * @result: Response type
2017 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,
2018 uint8_t bw, uint8_t result);
2021 * Handle the USB4 BW Allocation related functionality here:
2022 * Plug => Try to allocate max bw from timing parameters supported by the sink
2023 * Unplug => de-allocate bw
2025 * @link: pointer to the dc_link struct instance
2026 * @peak_bw: Peak bw used by the link/sink
2028 * return: allocated bw else return 0
2030 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2031 struct dc_link *link, int peak_bw);
2034 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2035 * available BW for each host router
2037 * @dc: pointer to dc struct
2038 * @stream: pointer to all possible streams
2039 * @num_streams: number of valid DPIA streams
2041 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2043 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams,
2044 const unsigned int count);
2046 /* Sink Interfaces - A sink corresponds to a display output device */
2048 struct dc_container_id {
2049 // 128bit GUID in binary form
2050 unsigned char guid[16];
2051 // 8 byte port ID -> ELD.PortID
2052 unsigned int portId[2];
2053 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2054 unsigned short manufacturerName;
2055 // 2 byte product code -> ELD.ProductCode
2056 unsigned short productCode;
2060 struct dc_sink_dsc_caps {
2061 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2062 // 'false' if they are sink's DSC caps
2063 bool is_virtual_dpcd_dsc;
2064 #if defined(CONFIG_DRM_AMD_DC_FP)
2065 // 'true' if MST topology supports DSC passthrough for sink
2066 // 'false' if MST topology does not support DSC passthrough
2067 bool is_dsc_passthrough_supported;
2069 struct dsc_dec_dpcd_caps dsc_dec_caps;
2072 struct dc_sink_fec_caps {
2073 bool is_rx_fec_supported;
2074 bool is_topology_fec_supported;
2078 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2079 union hdmi_scdc_device_id_data device_id;
2083 * The sink structure contains EDID and other display device properties
2086 enum signal_type sink_signal;
2087 struct dc_edid dc_edid; /* raw edid */
2088 struct dc_edid_caps edid_caps; /* parse display caps */
2089 struct dc_container_id *dc_container_id;
2090 uint32_t dongle_max_pix_clk;
2092 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2093 bool converter_disable_audio;
2095 struct scdc_caps scdc_caps;
2096 struct dc_sink_dsc_caps dsc_caps;
2097 struct dc_sink_fec_caps fec_caps;
2099 bool is_vsc_sdp_colorimetry_supported;
2101 /* private to DC core */
2102 struct dc_link *link;
2103 struct dc_context *ctx;
2107 /* private to dc_sink.c */
2108 // refcount must be the last member in dc_sink, since we want the
2109 // sink structure to be logically cloneable up to (but not including)
2111 struct kref refcount;
2114 void dc_sink_retain(struct dc_sink *sink);
2115 void dc_sink_release(struct dc_sink *sink);
2117 struct dc_sink_init_data {
2118 enum signal_type sink_signal;
2119 struct dc_link *link;
2120 uint32_t dongle_max_pix_clk;
2121 bool converter_disable_audio;
2124 bool dc_extended_blank_supported(struct dc *dc);
2126 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2128 /* Newer interfaces */
2130 struct dc_plane_address address;
2131 struct dc_cursor_attributes attributes;
2135 /* Interrupt interfaces */
2136 enum dc_irq_source dc_interrupt_to_irq_source(
2140 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2141 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2142 enum dc_irq_source dc_get_hpd_irq_source_at_index(
2143 struct dc *dc, uint32_t link_index);
2145 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2147 /* Power Interfaces */
2149 void dc_set_power_state(
2151 enum dc_acpi_cm_power_state power_state);
2152 void dc_resume(struct dc *dc);
2154 void dc_power_down_on_boot(struct dc *dc);
2159 enum hdcp_message_status dc_process_hdcp_msg(
2160 enum signal_type signal,
2161 struct dc_link *link,
2162 struct hdcp_protection_message *message_info);
2163 bool dc_is_dmcu_initialized(struct dc *dc);
2165 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2166 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2168 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
2169 struct dc_cursor_attributes *cursor_attr);
2171 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
2173 /* set min and max memory clock to lowest and highest DPM level, respectively */
2174 void dc_unlock_memory_clock_frequency(struct dc *dc);
2176 /* set min memory clock to the min required for current mode, max to maxDPM */
2177 void dc_lock_memory_clock_frequency(struct dc *dc);
2179 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
2180 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2182 /* cleanup on driver unload */
2183 void dc_hardware_release(struct dc *dc);
2185 /* disables fw based mclk switch */
2186 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2188 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2189 void dc_z10_restore(const struct dc *dc);
2190 void dc_z10_save_init(struct dc *dc);
2192 bool dc_is_dmub_outbox_supported(struct dc *dc);
2193 bool dc_enable_dmub_notifications(struct dc *dc);
2195 void dc_enable_dmub_outbox(struct dc *dc);
2197 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2198 uint32_t link_index,
2199 struct aux_payload *payload);
2201 /* Get dc link index from dpia port index */
2202 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2203 uint8_t dpia_port_index);
2205 bool dc_process_dmub_set_config_async(struct dc *dc,
2206 uint32_t link_index,
2207 struct set_config_cmd_payload *payload,
2208 struct dmub_notification *notify);
2210 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2211 uint32_t link_index,
2212 uint8_t mst_alloc_slots,
2213 uint8_t *mst_slots_in_use);
2215 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2216 uint32_t hpd_int_enable);
2218 /* DSC Interfaces */
2221 /* Disable acc mode Interfaces */
2222 void dc_disable_accelerated_mode(struct dc *dc);
2224 #endif /* DC_INTERFACE_H_ */