2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "hdcp_msg_types.h"
33 #include "gpio_types.h"
34 #include "link_service_types.h"
35 #include "grph_object_ctrl_defs.h"
36 #include <inc/hw/opp.h>
38 #include "inc/hw_sequencer.h"
39 #include "inc/compressor.h"
40 #include "inc/hw/dmcu.h"
41 #include "dml/display_mode_lib.h"
43 /* forward declaration */
45 struct set_config_cmd_payload;
46 struct dmub_notification;
48 #define DC_VER "3.2.234"
50 #define MAX_SURFACES 3
53 #define MIN_VIEWPORT_SIZE 12
56 /* Display Core Interfaces */
59 struct dmcu_version dmcu_version;
62 enum dp_protocol_version {
67 DC_PLANE_TYPE_INVALID,
68 DC_PLANE_TYPE_DCE_RGB,
69 DC_PLANE_TYPE_DCE_UNDERLAY,
70 DC_PLANE_TYPE_DCN_UNIVERSAL,
73 // Sizes defined as multiples of 64KB
84 enum dc_plane_type type;
85 uint32_t per_pixel_alpha : 1;
87 uint32_t argb8888 : 1;
92 } pixel_format_support;
93 // max upscaling factor x1000
94 // upscaling factors are always >= 1
95 // for example, 1080p -> 8K is 4.0, or 4000 raw value
100 } max_upscale_factor;
101 // max downscale factor x1000
102 // downscale factors are always <= 1
103 // for example, 8K -> 1080p is 0.25, or 250 raw value
108 } max_downscale_factor;
109 // minimal width/height
115 * DOC: color-management-caps
117 * **Color management caps (DPP and MPC)**
119 * Modules/color calculates various color operations which are translated to
120 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
121 * DCN1, every new generation comes with fairly major differences in color
122 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
123 * decide mapping to HW block based on logical capabilities.
127 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
128 * @srgb: RGB color space transfer func
129 * @bt2020: BT.2020 transfer func
130 * @gamma2_2: standard gamma
131 * @pq: perceptual quantizer transfer function
132 * @hlg: hybrid log–gamma transfer function
134 struct rom_curve_caps {
137 uint16_t gamma2_2 : 1;
143 * struct dpp_color_caps - color pipeline capabilities for display pipe and
146 * @dcn_arch: all DCE generations treated the same
147 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
148 * just plain 256-entry lookup
149 * @icsc: input color space conversion
150 * @dgam_ram: programmable degamma LUT
151 * @post_csc: post color space conversion, before gamut remap
152 * @gamma_corr: degamma correction
153 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
154 * with MPC by setting mpc:shared_3d_lut flag
155 * @ogam_ram: programmable out/blend gamma LUT
156 * @ocsc: output color space conversion
157 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
158 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
159 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
161 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
163 struct dpp_color_caps {
164 uint16_t dcn_arch : 1;
165 uint16_t input_lut_shared : 1;
167 uint16_t dgam_ram : 1;
168 uint16_t post_csc : 1;
169 uint16_t gamma_corr : 1;
170 uint16_t hw_3d_lut : 1;
171 uint16_t ogam_ram : 1;
173 uint16_t dgam_rom_for_yuv : 1;
174 struct rom_curve_caps dgam_rom_caps;
175 struct rom_curve_caps ogam_rom_caps;
179 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
180 * plane combined blocks
182 * @gamut_remap: color transformation matrix
183 * @ogam_ram: programmable out gamma LUT
184 * @ocsc: output color space conversion matrix
185 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
186 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
188 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
190 struct mpc_color_caps {
191 uint16_t gamut_remap : 1;
192 uint16_t ogam_ram : 1;
194 uint16_t num_3dluts : 3;
195 uint16_t shared_3d_lut:1;
196 struct rom_curve_caps ogam_rom_caps;
200 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
201 * @dpp: color pipes caps for DPP
202 * @mpc: color pipes caps for MPC
204 struct dc_color_caps {
205 struct dpp_color_caps dpp;
206 struct mpc_color_caps mpc;
209 struct dc_dmub_caps {
217 uint32_t max_streams;
220 uint32_t max_slave_planes;
221 uint32_t max_slave_yuv_planes;
222 uint32_t max_slave_rgb_planes;
224 uint32_t max_downscale_ratio;
225 uint32_t i2c_speed_in_khz;
226 uint32_t i2c_speed_in_khz_hdcp;
227 uint32_t dmdata_alloc_size;
228 unsigned int max_cursor_size;
229 unsigned int max_video_width;
230 unsigned int min_horizontal_blanking_period;
231 int linear_pitch_alignment;
232 bool dcc_const_color;
236 bool post_blend_color_processing;
237 bool force_dp_tps4_for_cp2520;
238 bool disable_dp_clk_share;
239 bool psp_setup_panel_mode;
240 bool extended_aux_timeout_support;
243 uint32_t num_of_internal_disp;
244 enum dp_protocol_version max_dp_protocol_version;
245 unsigned int mall_size_per_mem_channel;
246 unsigned int mall_size_total;
247 unsigned int cursor_cache_size;
248 struct dc_plane_cap planes[MAX_PLANES];
249 struct dc_color_caps color;
250 struct dc_dmub_caps dmub_caps;
252 bool dp_hdmi21_pcon_support;
253 bool edp_dsc_support;
254 bool vbios_lttpr_aware;
255 bool vbios_lttpr_enable;
256 uint32_t max_otg_num;
257 uint32_t max_cab_allocation_bytes;
258 uint32_t cache_line_size;
259 uint32_t cache_num_ways;
260 uint16_t subvp_fw_processing_delay_us;
261 uint8_t subvp_drr_max_vblank_margin_us;
262 uint16_t subvp_prefetch_end_to_mall_start_us;
263 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
264 uint16_t subvp_pstate_allow_width_us;
265 uint16_t subvp_vertical_int_margin_us;
267 uint8_t subvp_drr_vblank_start_margin_us;
271 bool no_connect_phy_config;
273 bool skip_clock_update;
274 bool lt_early_cr_pattern;
277 struct dc_dcc_surface_param {
278 struct dc_size surface_size;
279 enum surface_pixel_format format;
280 enum swizzle_mode_values swizzle_mode;
281 enum dc_scan_direction scan;
284 struct dc_dcc_setting {
285 unsigned int max_compressed_blk_size;
286 unsigned int max_uncompressed_blk_size;
287 bool independent_64b_blks;
288 //These bitfields to be used starting with DCN
290 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
291 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN
292 uint32_t dcc_256_128_128 : 1; //available starting with DCN
293 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
297 struct dc_surface_dcc_cap {
300 struct dc_dcc_setting rgb;
304 struct dc_dcc_setting luma;
305 struct dc_dcc_setting chroma;
310 bool const_color_support;
313 struct dc_static_screen_params {
320 unsigned int num_frames;
324 /* Surface update type is used by dc_update_surfaces_and_stream
325 * The update type is determined at the very beginning of the function based
326 * on parameters passed in and decides how much programming (or updating) is
327 * going to be done during the call.
329 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
330 * logical calculations or hardware register programming. This update MUST be
331 * ISR safe on windows. Currently fast update will only be used to flip surface
334 * UPDATE_TYPE_MED is used for slower updates which require significant hw
335 * re-programming however do not affect bandwidth consumption or clock
336 * requirements. At present, this is the level at which front end updates
337 * that do not require us to run bw_calcs happen. These are in/out transfer func
338 * updates, viewport offset changes, recout size changes and pixel depth changes.
339 * This update can be done at ISR, but we want to minimize how often this happens.
341 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
342 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
343 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
344 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
345 * a full update. This cannot be done at ISR level and should be a rare event.
346 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
347 * underscan we don't expect to see this call at all.
350 enum surface_update_type {
351 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
352 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
353 UPDATE_TYPE_FULL, /* may need to shuffle resources */
356 /* Forward declaration*/
358 struct dc_plane_state;
362 struct dc_cap_funcs {
363 bool (*get_dcc_compression_cap)(const struct dc *dc,
364 const struct dc_dcc_surface_param *input,
365 struct dc_surface_dcc_cap *output);
368 struct link_training_settings;
370 union allow_lttpr_non_transparent_mode {
378 /* Structure to hold configuration flags set by dm at dc creation. */
381 bool disable_disp_pll_sharing;
383 bool disable_fractional_pwm;
384 bool allow_seamless_boot_optimization;
385 bool seamless_boot_edp_requested;
386 bool edp_not_connected;
387 bool edp_no_power_sequencing;
390 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
391 bool multi_mon_pp_mclk_switch;
394 bool enable_windowed_mpo_odm;
395 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
396 uint32_t allow_edp_hotplug_detection;
397 bool clamp_min_dcfclk;
398 uint64_t vblank_alignment_dto_params;
399 uint8_t vblank_alignment_max_frame_time_diff;
400 bool is_asymmetric_memory;
401 bool is_single_rank_dimm;
402 bool is_vmin_only_asic;
403 bool use_pipe_ctx_sync_logic;
404 bool ignore_dpref_ss;
405 bool enable_mipi_converter_optimization;
406 bool use_default_clock_table;
407 bool force_bios_enable_lttpr;
408 uint8_t force_bios_fixed_vs;
409 int sdpif_request_limit_words_per_umc;
410 bool use_old_fixed_vs_sequence;
411 bool disable_subvp_drr;
414 enum visual_confirm {
415 VISUAL_CONFIRM_DISABLE = 0,
416 VISUAL_CONFIRM_SURFACE = 1,
417 VISUAL_CONFIRM_HDR = 2,
418 VISUAL_CONFIRM_MPCTREE = 4,
419 VISUAL_CONFIRM_PSR = 5,
420 VISUAL_CONFIRM_SWAPCHAIN = 6,
421 VISUAL_CONFIRM_FAMS = 7,
422 VISUAL_CONFIRM_SWIZZLE = 9,
423 VISUAL_CONFIRM_SUBVP = 14,
426 enum dc_psr_power_opts {
427 psr_power_opt_invalid = 0x0,
428 psr_power_opt_smu_opt_static_screen = 0x1,
429 psr_power_opt_z10_static_screen = 0x10,
430 psr_power_opt_ds_disable_allow = 0x100,
433 enum dml_hostvm_override_opts {
434 DML_HOSTVM_NO_OVERRIDE = 0x0,
435 DML_HOSTVM_OVERRIDE_FALSE = 0x1,
436 DML_HOSTVM_OVERRIDE_TRUE = 0x2,
442 DCC_HALF_REQ_DISALBE = 2,
446 * enum pipe_split_policy - Pipe split strategy supported by DCN
448 * This enum is used to define the pipe split policy supported by DCN. By
449 * default, DC favors MPC_SPLIT_DYNAMIC.
451 enum pipe_split_policy {
453 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
454 * pipe in order to bring the best trade-off between performance and
455 * power consumption. This is the recommended option.
457 MPC_SPLIT_DYNAMIC = 0,
460 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
461 * try any sort of split optimization.
466 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
467 * optimize the pipe utilization when using a single display; if the
468 * user connects to a second display, DC will avoid pipe split.
470 MPC_SPLIT_AVOID_MULT_DISP = 2,
473 enum wm_report_mode {
474 WM_REPORT_DEFAULT = 0,
475 WM_REPORT_OVERRIDE = 1,
478 dtm_level_p0 = 0,/*highest voltage*/
482 dtm_level_p4,/*when active_display_count = 0*/
486 DCN_PWR_STATE_UNKNOWN = -1,
487 DCN_PWR_STATE_MISSION_MODE = 0,
488 DCN_PWR_STATE_LOW_POWER = 3,
491 enum dcn_zstate_support_state {
492 DCN_ZSTATE_SUPPORT_UNKNOWN,
493 DCN_ZSTATE_SUPPORT_ALLOW,
494 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
495 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
496 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
497 DCN_ZSTATE_SUPPORT_DISALLOW,
501 * struct dc_clocks - DC pipe clocks
503 * For any clocks that may differ per pipe only the max is stored in this
508 int actual_dispclk_khz;
510 int actual_dppclk_khz;
511 int disp_dpp_voltage_level_khz;
514 int dcfclk_deep_sleep_khz;
518 bool p_state_change_support;
519 enum dcn_zstate_support_state zstate_support;
522 bool fclk_p_state_change_support;
523 enum dcn_pwr_state pwr_state;
525 * Elements below are not compared for the purposes of
526 * optimization required
528 bool prev_p_state_change_support;
529 bool fclk_prev_p_state_change_support;
533 * @fw_based_mclk_switching
535 * DC has a mechanism that leverage the variable refresh rate to switch
536 * memory clock in cases that we have a large latency to achieve the
537 * memory clock change and a short vblank window. DC has some
538 * requirements to enable this feature, and this field describes if the
539 * system support or not such a feature.
541 bool fw_based_mclk_switching;
542 bool fw_based_mclk_switching_shut_down;
544 enum dtm_pstate dtm_level;
545 int max_supported_dppclk_khz;
546 int max_supported_dispclk_khz;
547 int bw_dppclk_khz; /*a copy of dppclk_khz*/
551 struct dc_bw_validation_profile {
554 unsigned long long total_ticks;
555 unsigned long long voltage_level_ticks;
556 unsigned long long watermark_ticks;
557 unsigned long long rq_dlg_ticks;
559 unsigned long long total_count;
560 unsigned long long skip_fast_count;
561 unsigned long long skip_pass_count;
562 unsigned long long skip_fail_count;
565 #define BW_VAL_TRACE_SETUP() \
566 unsigned long long end_tick = 0; \
567 unsigned long long voltage_level_tick = 0; \
568 unsigned long long watermark_tick = 0; \
569 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
570 dm_get_timestamp(dc->ctx) : 0
572 #define BW_VAL_TRACE_COUNT() \
573 if (dc->debug.bw_val_profile.enable) \
574 dc->debug.bw_val_profile.total_count++
576 #define BW_VAL_TRACE_SKIP(status) \
577 if (dc->debug.bw_val_profile.enable) { \
578 if (!voltage_level_tick) \
579 voltage_level_tick = dm_get_timestamp(dc->ctx); \
580 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
583 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
584 if (dc->debug.bw_val_profile.enable) \
585 voltage_level_tick = dm_get_timestamp(dc->ctx)
587 #define BW_VAL_TRACE_END_WATERMARKS() \
588 if (dc->debug.bw_val_profile.enable) \
589 watermark_tick = dm_get_timestamp(dc->ctx)
591 #define BW_VAL_TRACE_FINISH() \
592 if (dc->debug.bw_val_profile.enable) { \
593 end_tick = dm_get_timestamp(dc->ctx); \
594 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
595 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
596 if (watermark_tick) { \
597 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
598 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
602 union mem_low_power_enable_options {
617 union root_clock_optimization_options {
629 uint32_t reserved: 22;
634 union dpia_debug_options {
636 uint32_t disable_dpia:1; /* bit 0 */
637 uint32_t force_non_lttpr:1; /* bit 1 */
638 uint32_t extend_aux_rd_interval:1; /* bit 2 */
639 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
640 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
641 uint32_t reserved:27;
646 /* AUX wake work around options
647 * 0: enable/disable work around
648 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
650 * 31-16: timeout in ms
652 union aux_wake_wa_options {
654 uint32_t enable_wa : 1;
655 uint32_t use_default_timeout : 1;
657 uint32_t timeout_ms : 16;
662 struct dc_debug_data {
663 uint32_t ltFailCount;
664 uint32_t i2cErrorCount;
665 uint32_t auxErrorCount;
668 struct dc_phy_addr_space_config {
681 uint64_t page_table_start_addr;
682 uint64_t page_table_end_addr;
683 uint64_t page_table_base_addr;
684 bool base_addr_is_mc_addr;
689 uint64_t page_table_default_page_addr;
692 struct dc_virtual_addr_space_config {
693 uint64_t page_table_base_addr;
694 uint64_t page_table_start_addr;
695 uint64_t page_table_end_addr;
696 uint32_t page_table_block_size_in_bytes;
697 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
700 struct dc_bounding_box_overrides {
702 int sr_enter_plus_exit_time_ns;
703 int sr_exit_z8_time_ns;
704 int sr_enter_plus_exit_z8_time_ns;
705 int urgent_latency_ns;
706 int percent_of_ideal_drambw;
707 int dram_clock_change_latency_ns;
708 int dummy_clock_change_latency_ns;
709 int fclk_clock_change_latency_ns;
710 /* This forces a hard min on the DCFCLK we use
711 * for DML. Unlike the debug option for forcing
712 * DCFCLK, this override affects watermark calculations
718 struct resource_pool;
723 * struct dc_debug_options - DC debug struct
725 * This struct provides a simple mechanism for developers to change some
726 * configurations, enable/disable features, and activate extra debug options.
727 * This can be very handy to narrow down whether some specific feature is
728 * causing an issue or not.
730 struct dc_debug_options {
731 bool native422_support;
733 enum visual_confirm visual_confirm;
734 int visual_confirm_rect_height;
741 bool validation_trace;
742 bool bandwidth_calcs_trace;
743 int max_downscale_src_width;
745 /* stutter efficiency related */
746 bool disable_stutter;
748 enum dcc_option disable_dcc;
751 * @pipe_split_policy: Define which pipe split policy is used by the
754 enum pipe_split_policy pipe_split_policy;
755 bool force_single_disp_pipe_split;
756 bool voltage_align_fclk;
757 bool disable_min_fclk;
759 bool disable_dfs_bypass;
760 bool disable_dpp_power_gate;
761 bool disable_hubp_power_gate;
762 bool disable_dsc_power_gate;
763 int dsc_min_slice_height_override;
764 int dsc_bpp_increment_div;
765 bool disable_pplib_wm_range;
766 enum wm_report_mode pplib_wm_report_mode;
767 unsigned int min_disp_clk_khz;
768 unsigned int min_dpp_clk_khz;
769 unsigned int min_dram_clk_khz;
770 int sr_exit_time_dpm0_ns;
771 int sr_enter_plus_exit_time_dpm0_ns;
773 int sr_enter_plus_exit_time_ns;
774 int sr_exit_z8_time_ns;
775 int sr_enter_plus_exit_z8_time_ns;
776 int urgent_latency_ns;
777 uint32_t underflow_assert_delay_us;
778 int percent_of_ideal_drambw;
779 int dram_clock_change_latency_ns;
780 bool optimized_watermark;
782 bool disable_pplib_clock_request;
783 bool disable_clock_gate;
784 bool disable_mem_low_power;
787 bool force_abm_enable;
788 bool disable_stereo_support;
790 bool performance_trace;
791 bool az_endpoint_mute_only;
792 bool always_use_regamma;
793 bool recovery_enabled;
794 bool avoid_vbios_exec_table;
795 bool scl_reset_length10;
797 bool skip_detection_link_training;
798 uint32_t edid_read_retry_times;
799 unsigned int force_odm_combine; //bit vector based on otg inst
800 unsigned int seamless_boot_odm_combine;
801 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
802 int minimum_z8_residency_time;
804 unsigned int force_fclk_khz;
806 bool dmub_offload_enabled;
807 bool dmcub_emulation;
808 bool disable_idle_power_optimizations;
809 unsigned int mall_size_override;
810 unsigned int mall_additional_timer_percent;
811 bool mall_error_as_fatal;
812 bool dmub_command_table; /* for testing only */
813 struct dc_bw_validation_profile bw_val_profile;
815 bool disable_48mhz_pwrdwn;
816 /* This forces a hard min on the DCFCLK requested to SMU/PP
817 * watermarks are not affected.
819 unsigned int force_min_dcfclk_mhz;
821 bool disable_timing_sync;
823 int force_clock_mode;/*every mode change.*/
825 bool disable_dram_clock_change_vactive_support;
826 bool validate_dml_output;
827 bool enable_dmcub_surface_flip;
828 bool usbc_combo_phy_reset_wa;
829 bool enable_dram_clock_change_one_display_vactive;
830 /* TODO - remove once tested */
832 bool set_mst_en_for_sst;
834 bool force_dp2_lt_fallback_method;
835 bool ignore_cable_id;
836 union mem_low_power_enable_options enable_mem_low_power;
837 union root_clock_optimization_options root_clock_optimization;
838 bool hpo_optimization;
839 bool force_vblank_alignment;
841 /* Enable dmub aux for legacy ddc */
842 bool enable_dmub_aux_for_legacy_ddc;
844 /* FEC/PSR1 sequence enable delay in 100us */
845 uint8_t fec_enable_delay_in100us;
846 bool enable_driver_sequence_debug;
847 enum det_size crb_alloc_policy;
848 int crb_alloc_policy_min_disp_count;
850 bool enable_z9_disable_interface;
851 bool psr_skip_crtc_disable;
852 union dpia_debug_options dpia_debug;
853 bool disable_fixed_vs_aux_timeout_wa;
854 bool force_disable_subvp;
855 bool force_subvp_mclk_switch;
856 bool allow_sw_cursor_fallback;
857 unsigned int force_subvp_num_ways;
858 unsigned int force_mall_ss_num_ways;
859 bool alloc_extra_way_for_cursor;
860 uint32_t subvp_extra_lines;
861 bool force_usr_allow;
862 /* uses value at boot and disables switch */
863 bool disable_dtb_ref_clk_switch;
864 bool extended_blank_optimization;
865 union aux_wake_wa_options aux_wake_wa;
866 uint32_t mst_start_top_delay;
867 uint8_t psr_power_use_phy_fsm;
868 enum dml_hostvm_override_opts dml_hostvm_override;
869 bool dml_disallow_alternate_prefetch_modes;
870 bool use_legacy_soc_bb_mechanism;
871 bool exit_idle_opt_for_cursor_updates;
872 bool enable_single_display_2to1_odm_policy;
873 bool enable_double_buffered_dsc_pg_support;
874 bool enable_dp_dig_pixel_rate_div_policy;
875 enum lttpr_mode lttpr_mode_override;
876 unsigned int dsc_delay_factor_wa_x1000;
877 unsigned int min_prefetch_in_strobe_ns;
878 bool disable_unbounded_requesting;
879 bool dig_fifo_off_in_blank;
880 bool temp_mst_deallocation_sequence;
881 bool override_dispclk_programming;
882 bool disable_fpo_optimizations;
884 uint32_t fpo_vactive_margin_us;
885 bool disable_fpo_vactive;
886 bool disable_boot_optimizations;
887 bool override_odm_optimization;
888 bool minimize_dispclk_using_odm;
889 bool disable_subvp_high_refresh;
890 bool disable_dp_plus_plus_wa;
893 struct gpu_info_soc_bounding_box_v1_0;
895 struct dc_debug_options debug;
896 struct dc_versions versions;
898 struct dc_cap_funcs cap_funcs;
899 struct dc_config config;
900 struct dc_bounding_box_overrides bb_overrides;
901 struct dc_bug_wa work_arounds;
902 struct dc_context *ctx;
903 struct dc_phy_addr_space_config vm_pa_config;
906 struct dc_link *links[MAX_PIPES * 2];
907 struct link_service *link_srv;
909 struct dc_state *current_state;
910 struct resource_pool *res_pool;
912 struct clk_mgr *clk_mgr;
914 /* Display Engine Clock levels */
915 struct dm_pp_clock_levels sclk_lvls;
917 /* Inputs into BW and WM calculations. */
918 struct bw_calcs_dceip *bw_dceip;
919 struct bw_calcs_vbios *bw_vbios;
920 struct dcn_soc_bounding_box *dcn_soc;
921 struct dcn_ip_params *dcn_ip;
922 struct display_mode_lib dml;
925 struct hw_sequencer_funcs hwss;
926 struct dce_hwseq *hwseq;
928 /* Require to optimize clocks and bandwidth for added/removed planes */
929 bool optimized_required;
930 bool wm_optimized_required;
931 bool idle_optimizations_allowed;
932 bool enable_c20_dtm_b0;
934 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
937 struct compressor *fbc_compressor;
939 struct dc_debug_data debug_data;
940 struct dpcd_vendor_signature vendor_signature;
942 const char *build_id;
943 struct vm_helper *vm_helper;
945 uint32_t *dcn_reg_offsets;
946 uint32_t *nbio_reg_offsets;
952 * For matching clock_limits table in driver with table
955 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
956 } update_bw_bounding_box;
960 enum frame_buffer_mode {
961 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
962 FRAME_BUFFER_MODE_ZFB_ONLY,
963 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
966 struct dchub_init_data {
967 int64_t zfb_phys_addr_base;
968 int64_t zfb_mc_base_addr;
969 uint64_t zfb_size_in_byte;
970 enum frame_buffer_mode fb_mode;
971 bool dchub_initialzied;
972 bool dchub_info_valid;
975 struct dc_init_data {
976 struct hw_asic_id asic_id;
977 void *driver; /* ctx */
978 struct cgs_device *cgs_device;
979 struct dc_bounding_box_overrides bb_overrides;
981 int num_virtual_links;
983 * If 'vbios_override' not NULL, it will be called instead
984 * of the real VBIOS. Intended use is Diagnostics on FPGA.
986 struct dc_bios *vbios_override;
987 enum dce_environment dce_environment;
989 struct dmub_offload_funcs *dmub_if;
990 struct dc_reg_helper_state *dmub_offload;
992 struct dc_config flags;
995 struct dpcd_vendor_signature vendor_signature;
996 bool force_smu_not_present;
998 * IP offset for run time initializaion of register addresses
1000 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
1001 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
1004 uint32_t *dcn_reg_offsets;
1005 uint32_t *nbio_reg_offsets;
1008 struct dc_callback_init {
1009 struct cp_psp cp_psp;
1012 struct dc *dc_create(const struct dc_init_data *init_params);
1013 void dc_hardware_init(struct dc *dc);
1015 int dc_get_vmid_use_vector(struct dc *dc);
1016 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1017 /* Returns the number of vmids supported */
1018 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1019 void dc_init_callbacks(struct dc *dc,
1020 const struct dc_callback_init *init_params);
1021 void dc_deinit_callbacks(struct dc *dc);
1022 void dc_destroy(struct dc **dc);
1024 /* Surface Interfaces */
1027 TRANSFER_FUNC_POINTS = 1025
1030 struct dc_hdr_static_metadata {
1031 /* display chromaticities and white point in units of 0.00001 */
1032 unsigned int chromaticity_green_x;
1033 unsigned int chromaticity_green_y;
1034 unsigned int chromaticity_blue_x;
1035 unsigned int chromaticity_blue_y;
1036 unsigned int chromaticity_red_x;
1037 unsigned int chromaticity_red_y;
1038 unsigned int chromaticity_white_point_x;
1039 unsigned int chromaticity_white_point_y;
1041 uint32_t min_luminance;
1042 uint32_t max_luminance;
1043 uint32_t maximum_content_light_level;
1044 uint32_t maximum_frame_average_light_level;
1047 enum dc_transfer_func_type {
1049 TF_TYPE_DISTRIBUTED_POINTS,
1054 struct dc_transfer_func_distributed_points {
1055 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1056 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1057 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1059 uint16_t end_exponent;
1060 uint16_t x_point_at_y1_red;
1061 uint16_t x_point_at_y1_green;
1062 uint16_t x_point_at_y1_blue;
1065 enum dc_transfer_func_predefined {
1066 TRANSFER_FUNCTION_SRGB,
1067 TRANSFER_FUNCTION_BT709,
1068 TRANSFER_FUNCTION_PQ,
1069 TRANSFER_FUNCTION_LINEAR,
1070 TRANSFER_FUNCTION_UNITY,
1071 TRANSFER_FUNCTION_HLG,
1072 TRANSFER_FUNCTION_HLG12,
1073 TRANSFER_FUNCTION_GAMMA22,
1074 TRANSFER_FUNCTION_GAMMA24,
1075 TRANSFER_FUNCTION_GAMMA26
1079 struct dc_transfer_func {
1080 struct kref refcount;
1081 enum dc_transfer_func_type type;
1082 enum dc_transfer_func_predefined tf;
1083 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1084 uint32_t sdr_ref_white_level;
1086 struct pwl_params pwl;
1087 struct dc_transfer_func_distributed_points tf_pts;
1092 union dc_3dlut_state {
1094 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
1095 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
1096 uint32_t rmu_mux_num:3; /*index of mux to use*/
1097 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1098 uint32_t mpc_rmu1_mux:4;
1099 uint32_t mpc_rmu2_mux:4;
1100 uint32_t reserved:15;
1107 struct kref refcount;
1108 struct tetrahedral_params lut_3d;
1109 struct fixed31_32 hdr_multiplier;
1110 union dc_3dlut_state state;
1113 * This structure is filled in by dc_surface_get_status and contains
1114 * the last requested address and the currently active address so the called
1115 * can determine if there are any outstanding flips
1117 struct dc_plane_status {
1118 struct dc_plane_address requested_address;
1119 struct dc_plane_address current_address;
1120 bool is_flip_pending;
1124 union surface_update_flags {
1127 uint32_t addr_update:1;
1128 /* Medium updates */
1129 uint32_t dcc_change:1;
1130 uint32_t color_space_change:1;
1131 uint32_t horizontal_mirror_change:1;
1132 uint32_t per_pixel_alpha_change:1;
1133 uint32_t global_alpha_change:1;
1134 uint32_t hdr_mult:1;
1135 uint32_t rotation_change:1;
1136 uint32_t swizzle_change:1;
1137 uint32_t scaling_change:1;
1138 uint32_t position_change:1;
1139 uint32_t in_transfer_func_change:1;
1140 uint32_t input_csc_change:1;
1141 uint32_t coeff_reduction_change:1;
1142 uint32_t output_tf_change:1;
1143 uint32_t pixel_format_change:1;
1144 uint32_t plane_size_change:1;
1145 uint32_t gamut_remap_change:1;
1148 uint32_t new_plane:1;
1149 uint32_t bpp_change:1;
1150 uint32_t gamma_change:1;
1151 uint32_t bandwidth_change:1;
1152 uint32_t clock_change:1;
1153 uint32_t stereo_format_change:1;
1155 uint32_t tmz_changed:1;
1156 uint32_t full_update:1;
1162 struct dc_plane_state {
1163 struct dc_plane_address address;
1164 struct dc_plane_flip_time time;
1165 bool triplebuffer_flips;
1166 struct scaling_taps scaling_quality;
1167 struct rect src_rect;
1168 struct rect dst_rect;
1169 struct rect clip_rect;
1171 struct plane_size plane_size;
1172 union dc_tiling_info tiling_info;
1174 struct dc_plane_dcc_param dcc;
1176 struct dc_gamma *gamma_correction;
1177 struct dc_transfer_func *in_transfer_func;
1178 struct dc_bias_and_scale *bias_and_scale;
1179 struct dc_csc_transform input_csc_color_matrix;
1180 struct fixed31_32 coeff_reduction_factor;
1181 struct fixed31_32 hdr_mult;
1182 struct colorspace_transform gamut_remap_matrix;
1184 // TODO: No longer used, remove
1185 struct dc_hdr_static_metadata hdr_static_ctx;
1187 enum dc_color_space color_space;
1189 struct dc_3dlut *lut3d_func;
1190 struct dc_transfer_func *in_shaper_func;
1191 struct dc_transfer_func *blend_tf;
1193 struct dc_transfer_func *gamcor_tf;
1194 enum surface_pixel_format format;
1195 enum dc_rotation_angle rotation;
1196 enum plane_stereo_format stereo_format;
1198 bool is_tiling_rotated;
1199 bool per_pixel_alpha;
1200 bool pre_multiplied_alpha;
1202 int global_alpha_value;
1204 bool flip_immediate;
1205 bool horizontal_mirror;
1208 union surface_update_flags update_flags;
1209 bool flip_int_enabled;
1210 bool skip_manual_trigger;
1212 /* private to DC core */
1213 struct dc_plane_status status;
1214 struct dc_context *ctx;
1216 /* HACK: Workaround for forcing full reprogramming under some conditions */
1217 bool force_full_update;
1219 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1221 /* private to dc_surface.c */
1222 enum dc_irq_source irq_source;
1223 struct kref refcount;
1224 struct tg_color visual_confirm_color;
1226 bool is_statically_allocated;
1229 struct dc_plane_info {
1230 struct plane_size plane_size;
1231 union dc_tiling_info tiling_info;
1232 struct dc_plane_dcc_param dcc;
1233 enum surface_pixel_format format;
1234 enum dc_rotation_angle rotation;
1235 enum plane_stereo_format stereo_format;
1236 enum dc_color_space color_space;
1237 bool horizontal_mirror;
1239 bool per_pixel_alpha;
1240 bool pre_multiplied_alpha;
1242 int global_alpha_value;
1243 bool input_csc_enabled;
1247 struct dc_scaling_info {
1248 struct rect src_rect;
1249 struct rect dst_rect;
1250 struct rect clip_rect;
1251 struct scaling_taps scaling_quality;
1254 struct dc_surface_update {
1255 struct dc_plane_state *surface;
1257 /* isr safe update parameters. null means no updates */
1258 const struct dc_flip_addrs *flip_addr;
1259 const struct dc_plane_info *plane_info;
1260 const struct dc_scaling_info *scaling_info;
1261 struct fixed31_32 hdr_mult;
1262 /* following updates require alloc/sleep/spin that is not isr safe,
1263 * null means no updates
1265 const struct dc_gamma *gamma;
1266 const struct dc_transfer_func *in_transfer_func;
1268 const struct dc_csc_transform *input_csc_color_matrix;
1269 const struct fixed31_32 *coeff_reduction_factor;
1270 const struct dc_transfer_func *func_shaper;
1271 const struct dc_3dlut *lut3d_func;
1272 const struct dc_transfer_func *blend_tf;
1273 const struct colorspace_transform *gamut_remap_matrix;
1277 * Create a new surface with default parameters;
1279 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1280 const struct dc_plane_status *dc_plane_get_status(
1281 const struct dc_plane_state *plane_state);
1283 void dc_plane_state_retain(struct dc_plane_state *plane_state);
1284 void dc_plane_state_release(struct dc_plane_state *plane_state);
1286 void dc_gamma_retain(struct dc_gamma *dc_gamma);
1287 void dc_gamma_release(struct dc_gamma **dc_gamma);
1288 struct dc_gamma *dc_create_gamma(void);
1290 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1291 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1292 struct dc_transfer_func *dc_create_transfer_func(void);
1294 struct dc_3dlut *dc_create_3dlut_func(void);
1295 void dc_3dlut_func_release(struct dc_3dlut *lut);
1296 void dc_3dlut_func_retain(struct dc_3dlut *lut);
1298 void dc_post_update_surfaces_to_stream(
1301 #include "dc_stream.h"
1304 * struct dc_validation_set - Struct to store surface/stream associations for validation
1306 struct dc_validation_set {
1308 * @stream: Stream state properties
1310 struct dc_stream_state *stream;
1313 * @plane_state: Surface state
1315 struct dc_plane_state *plane_states[MAX_SURFACES];
1318 * @plane_count: Total of active planes
1320 uint8_t plane_count;
1323 bool dc_validate_boot_timing(const struct dc *dc,
1324 const struct dc_sink *sink,
1325 struct dc_crtc_timing *crtc_timing);
1327 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1329 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1331 enum dc_status dc_validate_with_context(struct dc *dc,
1332 const struct dc_validation_set set[],
1334 struct dc_state *context,
1335 bool fast_validate);
1337 bool dc_set_generic_gpio_for_stereo(bool enable,
1338 struct gpio_service *gpio_service);
1341 * fast_validate: we return after determining if we can support the new state,
1342 * but before we populate the programming info
1344 enum dc_status dc_validate_global_state(
1346 struct dc_state *new_ctx,
1347 bool fast_validate);
1350 void dc_resource_state_construct(
1351 const struct dc *dc,
1352 struct dc_state *dst_ctx);
1354 bool dc_acquire_release_mpc_3dlut(
1355 struct dc *dc, bool acquire,
1356 struct dc_stream_state *stream,
1357 struct dc_3dlut **lut,
1358 struct dc_transfer_func **shaper);
1360 void dc_resource_state_copy_construct(
1361 const struct dc_state *src_ctx,
1362 struct dc_state *dst_ctx);
1364 void dc_resource_state_copy_construct_current(
1365 const struct dc *dc,
1366 struct dc_state *dst_ctx);
1368 void dc_resource_state_destruct(struct dc_state *context);
1370 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1372 enum dc_status dc_commit_streams(struct dc *dc,
1373 struct dc_stream_state *streams[],
1374 uint8_t stream_count);
1376 struct dc_state *dc_create_state(struct dc *dc);
1377 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1378 void dc_retain_state(struct dc_state *context);
1379 void dc_release_state(struct dc_state *context);
1381 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1382 struct dc_stream_state *stream,
1386 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1388 /* The function returns minimum bandwidth required to drive a given timing
1389 * return - minimum required timing bandwidth in kbps.
1391 uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing);
1393 /* Link Interfaces */
1395 * A link contains one or more sinks and their connected status.
1396 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1399 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1400 unsigned int sink_count;
1401 struct dc_sink *local_sink;
1402 unsigned int link_index;
1403 enum dc_connection_type type;
1404 enum signal_type connector_signal;
1405 enum dc_irq_source irq_source_hpd;
1406 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
1408 bool is_hpd_filter_disabled;
1412 * @link_state_valid:
1414 * If there is no link and local sink, this variable should be set to
1415 * false. Otherwise, it should be set to true; usually, the function
1416 * core_link_enable_stream sets this field to true.
1418 bool link_state_valid;
1419 bool aux_access_disabled;
1420 bool sync_lt_in_progress;
1421 bool skip_stream_reenable;
1422 bool is_internal_display;
1423 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1424 bool is_dig_mapping_flexible;
1425 bool hpd_status; /* HPD status of link without physical HPD pin. */
1426 bool is_hpd_pending; /* Indicates a new received hpd */
1427 bool is_automated; /* Indicates automated testing */
1429 bool edp_sink_present;
1431 struct dp_trace dp_trace;
1433 /* caps is the same as reported_link_cap. link_traing use
1434 * reported_link_cap. Will clean up. TODO
1436 struct dc_link_settings reported_link_cap;
1437 struct dc_link_settings verified_link_cap;
1438 struct dc_link_settings cur_link_settings;
1439 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1440 struct dc_link_settings preferred_link_setting;
1441 /* preferred_training_settings are override values that
1442 * come from DM. DM is responsible for the memory
1443 * management of the override pointers.
1445 struct dc_link_training_overrides preferred_training_settings;
1446 struct dp_audio_test_data audio_test_data;
1448 uint8_t ddc_hw_inst;
1452 uint8_t link_enc_hw_inst;
1453 /* DIG link encoder ID. Used as index in link encoder resource pool.
1454 * For links with fixed mapping to DIG, this is not changed after dc_link
1457 enum engine_id eng_id;
1459 bool test_pattern_enabled;
1460 union compliance_test_state compliance_test_state;
1464 struct ddc_service *ddc;
1466 enum dp_panel_mode panel_mode;
1469 /* Private to DC core */
1471 const struct dc *dc;
1473 struct dc_context *ctx;
1475 struct panel_cntl *panel_cntl;
1476 struct link_encoder *link_enc;
1477 struct graphics_object_id link_id;
1478 /* Endpoint type distinguishes display endpoints which do not have entries
1479 * in the BIOS connector table from those that do. Helps when tracking link
1480 * encoder to display endpoint assignments.
1482 enum display_endpoint_type ep_type;
1483 union ddi_channel_mapping ddi_channel_mapping;
1484 struct connector_device_tag_info device_tag;
1485 struct dpcd_caps dpcd_caps;
1486 uint32_t dongle_max_pix_clk;
1487 unsigned short chip_caps;
1488 unsigned int dpcd_sink_count;
1489 struct hdcp_caps hdcp_caps;
1490 enum edp_revision edp_revision;
1491 union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1493 struct psr_settings psr_settings;
1495 /* Drive settings read from integrated info table */
1496 struct dc_lane_settings bios_forced_drive_settings;
1498 /* Vendor specific LTTPR workaround variables */
1499 uint8_t vendor_specific_lttpr_link_rate_wa;
1500 bool apply_vendor_specific_lttpr_link_rate_wa;
1502 /* MST record stream using this link */
1504 bool dp_keep_receiver_powered;
1506 bool dp_skip_reset_segment;
1507 bool dp_skip_fs_144hz;
1508 bool dp_mot_reset_segment;
1509 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1510 bool dpia_mst_dsc_always_on;
1511 /* Forced DPIA into TBT3 compatibility mode. */
1512 bool dpia_forced_tbt3_mode;
1513 bool dongle_mode_timing_override;
1514 bool blank_stream_on_ocs_change;
1516 struct link_mst_stream_allocation_table mst_stream_alloc_table;
1518 struct dc_link_status link_status;
1519 struct dprx_states dprx_states;
1521 struct gpio *hpd_gpio;
1522 enum dc_link_fec_state fec_state;
1523 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
1525 struct dc_panel_config panel_config;
1526 struct phy_state phy_state;
1527 // BW ALLOCATON USB4 ONLY
1528 struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1531 /* Return an enumerated dc_link.
1532 * dc_link order is constant and determined at
1533 * boot time. They cannot be created or destroyed.
1534 * Use dc_get_caps() to get number of links.
1536 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1538 /* Return instance id of the edp link. Inst 0 is primary edp link. */
1539 bool dc_get_edp_link_panel_inst(const struct dc *dc,
1540 const struct dc_link *link,
1541 unsigned int *inst_out);
1543 /* Return an array of link pointers to edp links. */
1544 void dc_get_edp_links(const struct dc *dc,
1545 struct dc_link **edp_links,
1548 /* The function initiates detection handshake over the given link. It first
1549 * determines if there are display connections over the link. If so it initiates
1550 * detection protocols supported by the connected receiver device. The function
1551 * contains protocol specific handshake sequences which are sometimes mandatory
1552 * to establish a proper connection between TX and RX. So it is always
1553 * recommended to call this function as the first link operation upon HPD event
1554 * or power up event. Upon completion, the function will update link structure
1555 * in place based on latest RX capabilities. The function may also cause dpms
1556 * to be reset to off for all currently enabled streams to the link. It is DM's
1557 * responsibility to serialize detection and DPMS updates.
1559 * @reason - Indicate which event triggers this detection. dc may customize
1560 * detection flow depending on the triggering events.
1561 * return false - if detection is not fully completed. This could happen when
1562 * there is an unrecoverable error during detection or detection is partially
1563 * completed (detection has been delegated to dm mst manager ie.
1564 * link->connection_type == dc_connection_mst_branch when returning false).
1565 * return true - detection is completed, link has been fully updated with latest
1568 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1570 struct dc_sink_init_data;
1572 /* When link connection type is dc_connection_mst_branch, remote sink can be
1573 * added to the link. The interface creates a remote sink and associates it with
1574 * current link. The sink will be retained by link until remove remote sink is
1577 * @dc_link - link the remote sink will be added to.
1578 * @edid - byte array of EDID raw data.
1579 * @len - size of the edid in byte
1582 struct dc_sink *dc_link_add_remote_sink(
1583 struct dc_link *dc_link,
1584 const uint8_t *edid,
1586 struct dc_sink_init_data *init_data);
1588 /* Remove remote sink from a link with dc_connection_mst_branch connection type.
1589 * @link - link the sink should be removed from
1590 * @sink - sink to be removed.
1592 void dc_link_remove_remote_sink(
1593 struct dc_link *link,
1594 struct dc_sink *sink);
1596 /* Enable HPD interrupt handler for a given link */
1597 void dc_link_enable_hpd(const struct dc_link *link);
1599 /* Disable HPD interrupt handler for a given link */
1600 void dc_link_disable_hpd(const struct dc_link *link);
1602 /* determine if there is a sink connected to the link
1604 * @type - dc_connection_single if connected, dc_connection_none otherwise.
1605 * return - false if an unexpected error occurs, true otherwise.
1607 * NOTE: This function doesn't detect downstream sink connections i.e
1608 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1609 * return dc_connection_single if the branch device is connected despite of
1610 * downstream sink's connection status.
1612 bool dc_link_detect_connection_type(struct dc_link *link,
1613 enum dc_connection_type *type);
1615 /* query current hpd pin value
1616 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1619 bool dc_link_get_hpd_state(struct dc_link *link);
1621 /* Getter for cached link status from given link */
1622 const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1624 /* enable/disable hardware HPD filter.
1626 * @link - The link the HPD pin is associated with.
1627 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1628 * handler once after no HPD change has been detected within dc default HPD
1629 * filtering interval since last HPD event. i.e if display keeps toggling hpd
1630 * pulses within default HPD interval, no HPD event will be received until HPD
1631 * toggles have stopped. Then HPD event will be queued to irq handler once after
1632 * dc default HPD filtering interval since last HPD event.
1634 * @enable = false - disable hardware HPD filter. HPD event will be queued
1635 * immediately to irq handler after no HPD change has been detected within
1636 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
1638 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
1640 /* submit i2c read/write payloads through ddc channel
1641 * @link_index - index to a link with ddc in i2c mode
1642 * @cmd - i2c command structure
1643 * return - true if success, false otherwise.
1647 uint32_t link_index,
1648 struct i2c_command *cmd);
1650 /* submit i2c read/write payloads through oem channel
1651 * @link_index - index to a link with ddc in i2c mode
1652 * @cmd - i2c command structure
1653 * return - true if success, false otherwise.
1655 bool dc_submit_i2c_oem(
1657 struct i2c_command *cmd);
1659 enum aux_return_code_type;
1660 /* Attempt to transfer the given aux payload. This function does not perform
1661 * retries or handle error states. The reply is returned in the payload->reply
1662 * and the result through operation_result. Returns the number of bytes
1663 * transferred,or -1 on a failure.
1665 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
1666 struct aux_payload *payload,
1667 enum aux_return_code_type *operation_result);
1669 bool dc_is_oem_i2c_device_present(
1671 size_t slave_address
1674 /* return true if the connected receiver supports the hdcp version */
1675 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1676 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1678 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1680 * TODO - When defer_handling is true the function will have a different purpose.
1681 * It no longer does complete hpd rx irq handling. We should create a separate
1682 * interface specifically for this case.
1685 * true - Downstream port status changed. DM should call DC to do the
1687 * false - no change in Downstream port status. No further action required
1690 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
1691 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
1692 bool defer_handling, bool *has_left_work);
1693 /* handle DP specs define test automation sequence*/
1694 void dc_link_dp_handle_automated_test(struct dc_link *link);
1696 /* handle DP Link loss sequence and try to recover RX link loss with best
1699 void dc_link_dp_handle_link_loss(struct dc_link *link);
1701 /* Determine if hpd rx irq should be handled or ignored
1702 * return true - hpd rx irq should be handled.
1703 * return false - it is safe to ignore hpd rx irq event
1705 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
1707 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
1708 * @link - link the hpd irq data associated with
1709 * @hpd_irq_dpcd_data - input hpd irq data
1710 * return - true if hpd irq data indicates a link lost
1712 bool dc_link_check_link_loss_status(struct dc_link *link,
1713 union hpd_irq_data *hpd_irq_dpcd_data);
1715 /* Read hpd rx irq data from a given link
1716 * @link - link where the hpd irq data should be read from
1717 * @irq_data - output hpd irq data
1718 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1721 enum dc_status dc_link_dp_read_hpd_rx_irq_data(
1722 struct dc_link *link,
1723 union hpd_irq_data *irq_data);
1725 /* The function clears recorded DP RX states in the link. DM should call this
1726 * function when it is resuming from S3 power state to previously connected links.
1728 * TODO - in the future we should consider to expand link resume interface to
1729 * support clearing previous rx states. So we don't have to rely on dm to call
1730 * this interface explicitly.
1732 void dc_link_clear_dprx_states(struct dc_link *link);
1734 /* Destruct the mst topology of the link and reset the allocated payload table
1736 * NOTE: this should only be called if DM chooses not to call dc_link_detect but
1737 * still wants to reset MST topology on an unplug event */
1738 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
1740 /* The function calculates effective DP link bandwidth when a given link is
1741 * using the given link settings.
1743 * return - total effective link bandwidth in kbps.
1745 uint32_t dc_link_bandwidth_kbps(
1746 const struct dc_link *link,
1747 const struct dc_link_settings *link_setting);
1749 /* The function takes a snapshot of current link resource allocation state
1750 * @dc: pointer to dc of the dm calling this
1751 * @map: a dc link resource snapshot defined internally to dc.
1753 * DM needs to capture a snapshot of current link resource allocation mapping
1754 * and store it in its persistent storage.
1756 * Some of the link resource is using first come first serve policy.
1757 * The allocation mapping depends on original hotplug order. This information
1758 * is lost after driver is loaded next time. The snapshot is used in order to
1759 * restore link resource to its previous state so user will get consistent
1760 * link capability allocation across reboot.
1763 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
1765 /* This function restores link resource allocation state from a snapshot
1766 * @dc: pointer to dc of the dm calling this
1767 * @map: a dc link resource snapshot defined internally to dc.
1769 * DM needs to call this function after initial link detection on boot and
1770 * before first commit streams to restore link resource allocation state
1771 * from previous boot session.
1773 * Some of the link resource is using first come first serve policy.
1774 * The allocation mapping depends on original hotplug order. This information
1775 * is lost after driver is loaded next time. The snapshot is used in order to
1776 * restore link resource to its previous state so user will get consistent
1777 * link capability allocation across reboot.
1780 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
1782 /* TODO: this is not meant to be exposed to DM. Should switch to stream update
1783 * interface i.e stream_update->dsc_config
1785 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
1787 /* translate a raw link rate data to bandwidth in kbps */
1788 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
1790 /* determine the optimal bandwidth given link and required bw.
1791 * @link - current detected link
1792 * @req_bw - requested bandwidth in kbps
1793 * @link_settings - returned most optimal link settings that can fit the
1794 * requested bandwidth
1795 * return - false if link can't support requested bandwidth, true if link
1796 * settings is found.
1798 bool dc_link_decide_edp_link_settings(struct dc_link *link,
1799 struct dc_link_settings *link_settings,
1802 /* return the max dp link settings can be driven by the link without considering
1803 * connected RX device and its capability
1805 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
1806 struct dc_link_settings *max_link_enc_cap);
1808 /* determine when the link is driving MST mode, what DP link channel coding
1809 * format will be used. The decision will remain unchanged until next HPD event.
1811 * @link - a link with DP RX connection
1812 * return - if stream is committed to this link with MST signal type, type of
1813 * channel coding format dc will choose.
1815 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
1816 const struct dc_link *link);
1818 /* get max dp link settings the link can enable with all things considered. (i.e
1819 * TX/RX/Cable capabilities and dp override policies.
1821 * @link - a link with DP RX connection
1822 * return - max dp link settings the link can enable.
1825 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
1827 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
1828 * to a link with dp connector signal type.
1829 * @link - a link with dp connector signal type
1830 * return - true if connected, false otherwise
1832 bool dc_link_is_dp_sink_present(struct dc_link *link);
1834 /* Force DP lane settings update to main-link video signal and notify the change
1835 * to DP RX via DPCD. This is a debug interface used for video signal integrity
1836 * tuning purpose. The interface assumes link has already been enabled with DP
1839 * @lt_settings - a container structure with desired hw_lane_settings
1841 void dc_link_set_drive_settings(struct dc *dc,
1842 struct link_training_settings *lt_settings,
1843 struct dc_link *link);
1845 /* Enable a test pattern in Link or PHY layer in an active link for compliance
1846 * test or debugging purpose. The test pattern will remain until next un-plug.
1848 * @link - active link with DP signal output enabled.
1849 * @test_pattern - desired test pattern to output.
1850 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
1851 * @test_pattern_color_space - for video test pattern choose a desired color
1853 * @p_link_settings - For PHY pattern choose a desired link settings
1854 * @p_custom_pattern - some test pattern will require a custom input to
1855 * customize some pattern details. Otherwise keep it to NULL.
1856 * @cust_pattern_size - size of the custom pattern input.
1859 bool dc_link_dp_set_test_pattern(
1860 struct dc_link *link,
1861 enum dp_test_pattern test_pattern,
1862 enum dp_test_pattern_color_space test_pattern_color_space,
1863 const struct link_training_settings *p_link_settings,
1864 const unsigned char *p_custom_pattern,
1865 unsigned int cust_pattern_size);
1867 /* Force DP link settings to always use a specific value until reboot to a
1868 * specific link. If link has already been enabled, the interface will also
1869 * switch to desired link settings immediately. This is a debug interface to
1870 * generic dp issue trouble shooting.
1872 void dc_link_set_preferred_link_settings(struct dc *dc,
1873 struct dc_link_settings *link_setting,
1874 struct dc_link *link);
1876 /* Force DP link to customize a specific link training behavior by overriding to
1877 * standard DP specs defined protocol. This is a debug interface to trouble shoot
1878 * display specific link training issues or apply some display specific
1879 * workaround in link training.
1881 * @link_settings - if not NULL, force preferred link settings to the link.
1882 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
1883 * will apply this particular override in future link training. If NULL is
1884 * passed in, dc resets previous overrides.
1885 * NOTE: DM must keep the memory from override pointers until DM resets preferred
1886 * training settings.
1888 void dc_link_set_preferred_training_settings(struct dc *dc,
1889 struct dc_link_settings *link_setting,
1890 struct dc_link_training_overrides *lt_overrides,
1891 struct dc_link *link,
1892 bool skip_immediate_retrain);
1894 /* return - true if FEC is supported with connected DP RX, false otherwise */
1895 bool dc_link_is_fec_supported(const struct dc_link *link);
1897 /* query FEC enablement policy to determine if FEC will be enabled by dc during
1899 * return - true if FEC should be enabled, false otherwise.
1901 bool dc_link_should_enable_fec(const struct dc_link *link);
1903 /* determine lttpr mode the current link should be enabled with a specific link
1906 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
1907 struct dc_link_settings *link_setting);
1909 /* Force DP RX to update its power state.
1910 * NOTE: this interface doesn't update dp main-link. Calling this function will
1911 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
1912 * RX power state back upon finish DM specific execution requiring DP RX in a
1913 * specific power state.
1914 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
1917 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
1919 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
1920 * current value read from extended receiver cap from 02200h - 0220Fh.
1921 * Some DP RX has problems of providing accurate DP receiver caps from extended
1922 * field, this interface is a workaround to revert link back to use base caps.
1924 void dc_link_overwrite_extended_receiver_cap(
1925 struct dc_link *link);
1927 void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
1930 /* Set backlight level of an embedded panel (eDP, LVDS).
1931 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
1932 * and 16 bit fractional, where 1.0 is max backlight value.
1934 bool dc_link_set_backlight_level(const struct dc_link *dc_link,
1935 uint32_t backlight_pwm_u16_16,
1936 uint32_t frame_ramp);
1938 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
1939 bool dc_link_set_backlight_level_nits(struct dc_link *link,
1941 uint32_t backlight_millinits,
1942 uint32_t transition_time_in_ms);
1944 bool dc_link_get_backlight_level_nits(struct dc_link *link,
1945 uint32_t *backlight_millinits,
1946 uint32_t *backlight_millinits_peak);
1948 int dc_link_get_backlight_level(const struct dc_link *dc_link);
1950 int dc_link_get_target_backlight_pwm(const struct dc_link *link);
1952 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
1953 bool wait, bool force_static, const unsigned int *power_opts);
1955 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
1957 bool dc_link_setup_psr(struct dc_link *dc_link,
1958 const struct dc_stream_state *stream, struct psr_config *psr_config,
1959 struct psr_context *psr_context);
1961 /* On eDP links this function call will stall until T12 has elapsed.
1962 * If the panel is not in power off state, this function will return
1965 bool dc_link_wait_for_t12(struct dc_link *link);
1967 /* Determine if dp trace has been initialized to reflect upto date result *
1968 * return - true if trace is initialized and has valid data. False dp trace
1969 * doesn't have valid result.
1971 bool dc_dp_trace_is_initialized(struct dc_link *link);
1973 /* Query a dp trace flag to indicate if the current dp trace data has been
1976 bool dc_dp_trace_is_logged(struct dc_link *link,
1979 /* Set dp trace flag to indicate whether DM has already logged the current dp
1980 * trace data. DM can set is_logged to true upon logging and check
1981 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
1983 void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
1987 /* Obtain driver time stamp for last dp link training end. The time stamp is
1988 * formatted based on dm_get_timestamp DM function.
1989 * @in_detection - true to get link training end time stamp of last link
1990 * training in detection sequence. false to get link training end time stamp
1991 * of last link training in commit (dpms) sequence
1993 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
1996 /* Get how many link training attempts dc has done with latest sequence.
1997 * @in_detection - true to get link training count of last link
1998 * training in detection sequence. false to get link training count of last link
1999 * training in commit (dpms) sequence
2001 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
2004 /* Get how many link loss has happened since last link training attempts */
2005 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
2008 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
2011 * Send a request from DP-Tx requesting to allocate BW remotely after
2012 * allocating it locally. This will get processed by CM and a CB function
2015 * @link: pointer to the dc_link struct instance
2016 * @req_bw: The requested bw in Kbyte to allocated
2020 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2023 * Handle function for when the status of the Request above is complete.
2024 * We will find out the result of allocating on CM and update structs.
2026 * @link: pointer to the dc_link struct instance
2027 * @bw: Allocated or Estimated BW depending on the result
2028 * @result: Response type
2032 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,
2033 uint8_t bw, uint8_t result);
2036 * Handle the USB4 BW Allocation related functionality here:
2037 * Plug => Try to allocate max bw from timing parameters supported by the sink
2038 * Unplug => de-allocate bw
2040 * @link: pointer to the dc_link struct instance
2041 * @peak_bw: Peak bw used by the link/sink
2043 * return: allocated bw else return 0
2045 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2046 struct dc_link *link, int peak_bw);
2049 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2050 * available BW for each host router
2052 * @dc: pointer to dc struct
2053 * @stream: pointer to all possible streams
2054 * @num_streams: number of valid DPIA streams
2056 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2058 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams,
2059 const unsigned int count);
2061 /* Sink Interfaces - A sink corresponds to a display output device */
2063 struct dc_container_id {
2064 // 128bit GUID in binary form
2065 unsigned char guid[16];
2066 // 8 byte port ID -> ELD.PortID
2067 unsigned int portId[2];
2068 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2069 unsigned short manufacturerName;
2070 // 2 byte product code -> ELD.ProductCode
2071 unsigned short productCode;
2075 struct dc_sink_dsc_caps {
2076 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2077 // 'false' if they are sink's DSC caps
2078 bool is_virtual_dpcd_dsc;
2079 #if defined(CONFIG_DRM_AMD_DC_FP)
2080 // 'true' if MST topology supports DSC passthrough for sink
2081 // 'false' if MST topology does not support DSC passthrough
2082 bool is_dsc_passthrough_supported;
2084 struct dsc_dec_dpcd_caps dsc_dec_caps;
2087 struct dc_sink_fec_caps {
2088 bool is_rx_fec_supported;
2089 bool is_topology_fec_supported;
2093 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2094 union hdmi_scdc_device_id_data device_id;
2098 * The sink structure contains EDID and other display device properties
2101 enum signal_type sink_signal;
2102 struct dc_edid dc_edid; /* raw edid */
2103 struct dc_edid_caps edid_caps; /* parse display caps */
2104 struct dc_container_id *dc_container_id;
2105 uint32_t dongle_max_pix_clk;
2107 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2108 bool converter_disable_audio;
2110 struct scdc_caps scdc_caps;
2111 struct dc_sink_dsc_caps dsc_caps;
2112 struct dc_sink_fec_caps fec_caps;
2114 bool is_vsc_sdp_colorimetry_supported;
2116 /* private to DC core */
2117 struct dc_link *link;
2118 struct dc_context *ctx;
2122 /* private to dc_sink.c */
2123 // refcount must be the last member in dc_sink, since we want the
2124 // sink structure to be logically cloneable up to (but not including)
2126 struct kref refcount;
2129 void dc_sink_retain(struct dc_sink *sink);
2130 void dc_sink_release(struct dc_sink *sink);
2132 struct dc_sink_init_data {
2133 enum signal_type sink_signal;
2134 struct dc_link *link;
2135 uint32_t dongle_max_pix_clk;
2136 bool converter_disable_audio;
2139 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2141 /* Newer interfaces */
2143 struct dc_plane_address address;
2144 struct dc_cursor_attributes attributes;
2148 /* Interrupt interfaces */
2149 enum dc_irq_source dc_interrupt_to_irq_source(
2153 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2154 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2155 enum dc_irq_source dc_get_hpd_irq_source_at_index(
2156 struct dc *dc, uint32_t link_index);
2158 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2160 /* Power Interfaces */
2162 void dc_set_power_state(
2164 enum dc_acpi_cm_power_state power_state);
2165 void dc_resume(struct dc *dc);
2167 void dc_power_down_on_boot(struct dc *dc);
2172 enum hdcp_message_status dc_process_hdcp_msg(
2173 enum signal_type signal,
2174 struct dc_link *link,
2175 struct hdcp_protection_message *message_info);
2176 bool dc_is_dmcu_initialized(struct dc *dc);
2178 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2179 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2181 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
2182 struct dc_cursor_attributes *cursor_attr);
2184 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
2186 /* set min and max memory clock to lowest and highest DPM level, respectively */
2187 void dc_unlock_memory_clock_frequency(struct dc *dc);
2189 /* set min memory clock to the min required for current mode, max to maxDPM */
2190 void dc_lock_memory_clock_frequency(struct dc *dc);
2192 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
2193 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2195 /* cleanup on driver unload */
2196 void dc_hardware_release(struct dc *dc);
2198 /* disables fw based mclk switch */
2199 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2201 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2202 void dc_z10_restore(const struct dc *dc);
2203 void dc_z10_save_init(struct dc *dc);
2205 bool dc_is_dmub_outbox_supported(struct dc *dc);
2206 bool dc_enable_dmub_notifications(struct dc *dc);
2208 void dc_enable_dmub_outbox(struct dc *dc);
2210 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2211 uint32_t link_index,
2212 struct aux_payload *payload);
2214 /* Get dc link index from dpia port index */
2215 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2216 uint8_t dpia_port_index);
2218 bool dc_process_dmub_set_config_async(struct dc *dc,
2219 uint32_t link_index,
2220 struct set_config_cmd_payload *payload,
2221 struct dmub_notification *notify);
2223 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2224 uint32_t link_index,
2225 uint8_t mst_alloc_slots,
2226 uint8_t *mst_slots_in_use);
2228 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2229 uint32_t hpd_int_enable);
2231 /* DSC Interfaces */
2234 /* Disable acc mode Interfaces */
2235 void dc_disable_accelerated_mode(struct dc *dc);
2237 bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2238 struct dc_stream_state *new_stream);
2240 #endif /* DC_INTERFACE_H_ */