2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #if defined(CONFIG_DRM_AMD_DC_HDCP)
33 #include "hdcp_types.h"
35 #include "gpio_types.h"
36 #include "link_service_types.h"
37 #include "grph_object_ctrl_defs.h"
38 #include <inc/hw/opp.h>
40 #include "inc/hw_sequencer.h"
41 #include "inc/compressor.h"
42 #include "inc/hw/dmcu.h"
43 #include "dml/display_mode_lib.h"
45 /* forward declaration */
47 struct set_config_cmd_payload;
48 struct dmub_notification;
50 #define DC_VER "3.2.205"
52 #define MAX_SURFACES 3
55 #define MAX_SINKS_PER_LINK 4
56 #define MIN_VIEWPORT_SIZE 12
59 /*******************************************************************************
60 * Display Core Interfaces
61 ******************************************************************************/
64 struct dmcu_version dmcu_version;
67 enum dp_protocol_version {
72 DC_PLANE_TYPE_INVALID,
73 DC_PLANE_TYPE_DCE_RGB,
74 DC_PLANE_TYPE_DCE_UNDERLAY,
75 DC_PLANE_TYPE_DCN_UNIVERSAL,
78 // Sizes defined as multiples of 64KB
89 enum dc_plane_type type;
90 uint32_t blends_with_above : 1;
91 uint32_t blends_with_below : 1;
92 uint32_t per_pixel_alpha : 1;
94 uint32_t argb8888 : 1;
99 } pixel_format_support;
100 // max upscaling factor x1000
101 // upscaling factors are always >= 1
102 // for example, 1080p -> 8K is 4.0, or 4000 raw value
107 } max_upscale_factor;
108 // max downscale factor x1000
109 // downscale factors are always <= 1
110 // for example, 8K -> 1080p is 0.25, or 250 raw value
115 } max_downscale_factor;
116 // minimal width/height
122 * DOC: color-management-caps
124 * **Color management caps (DPP and MPC)**
126 * Modules/color calculates various color operations which are translated to
127 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
128 * DCN1, every new generation comes with fairly major differences in color
129 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
130 * decide mapping to HW block based on logical capabilities.
134 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
135 * @srgb: RGB color space transfer func
136 * @bt2020: BT.2020 transfer func
137 * @gamma2_2: standard gamma
138 * @pq: perceptual quantizer transfer function
139 * @hlg: hybrid log–gamma transfer function
141 struct rom_curve_caps {
144 uint16_t gamma2_2 : 1;
150 * struct dpp_color_caps - color pipeline capabilities for display pipe and
153 * @dcn_arch: all DCE generations treated the same
154 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
155 * just plain 256-entry lookup
156 * @icsc: input color space conversion
157 * @dgam_ram: programmable degamma LUT
158 * @post_csc: post color space conversion, before gamut remap
159 * @gamma_corr: degamma correction
160 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
161 * with MPC by setting mpc:shared_3d_lut flag
162 * @ogam_ram: programmable out/blend gamma LUT
163 * @ocsc: output color space conversion
164 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
165 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
166 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
168 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
170 struct dpp_color_caps {
171 uint16_t dcn_arch : 1;
172 uint16_t input_lut_shared : 1;
174 uint16_t dgam_ram : 1;
175 uint16_t post_csc : 1;
176 uint16_t gamma_corr : 1;
177 uint16_t hw_3d_lut : 1;
178 uint16_t ogam_ram : 1;
180 uint16_t dgam_rom_for_yuv : 1;
181 struct rom_curve_caps dgam_rom_caps;
182 struct rom_curve_caps ogam_rom_caps;
186 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
187 * plane combined blocks
189 * @gamut_remap: color transformation matrix
190 * @ogam_ram: programmable out gamma LUT
191 * @ocsc: output color space conversion matrix
192 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
193 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
195 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
197 struct mpc_color_caps {
198 uint16_t gamut_remap : 1;
199 uint16_t ogam_ram : 1;
201 uint16_t num_3dluts : 3;
202 uint16_t shared_3d_lut:1;
203 struct rom_curve_caps ogam_rom_caps;
207 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
208 * @dpp: color pipes caps for DPP
209 * @mpc: color pipes caps for MPC
211 struct dc_color_caps {
212 struct dpp_color_caps dpp;
213 struct mpc_color_caps mpc;
216 struct dc_dmub_caps {
222 uint32_t max_streams;
225 uint32_t max_slave_planes;
226 uint32_t max_slave_yuv_planes;
227 uint32_t max_slave_rgb_planes;
229 uint32_t max_downscale_ratio;
230 uint32_t i2c_speed_in_khz;
231 uint32_t i2c_speed_in_khz_hdcp;
232 uint32_t dmdata_alloc_size;
233 unsigned int max_cursor_size;
234 unsigned int max_video_width;
235 unsigned int min_horizontal_blanking_period;
236 int linear_pitch_alignment;
237 bool dcc_const_color;
241 bool post_blend_color_processing;
242 bool force_dp_tps4_for_cp2520;
243 bool disable_dp_clk_share;
244 bool psp_setup_panel_mode;
245 bool extended_aux_timeout_support;
248 uint32_t num_of_internal_disp;
249 enum dp_protocol_version max_dp_protocol_version;
250 unsigned int mall_size_per_mem_channel;
251 unsigned int mall_size_total;
252 unsigned int cursor_cache_size;
253 struct dc_plane_cap planes[MAX_PLANES];
254 struct dc_color_caps color;
255 struct dc_dmub_caps dmub_caps;
257 bool dp_hdmi21_pcon_support;
258 bool edp_dsc_support;
259 bool vbios_lttpr_aware;
260 bool vbios_lttpr_enable;
261 uint32_t max_otg_num;
262 uint32_t max_cab_allocation_bytes;
263 uint32_t cache_line_size;
264 uint32_t cache_num_ways;
265 uint16_t subvp_fw_processing_delay_us;
266 uint16_t subvp_prefetch_end_to_mall_start_us;
267 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
268 uint16_t subvp_pstate_allow_width_us;
269 uint16_t subvp_vertical_int_margin_us;
274 bool no_connect_phy_config;
276 bool skip_clock_update;
277 bool lt_early_cr_pattern;
280 struct dc_dcc_surface_param {
281 struct dc_size surface_size;
282 enum surface_pixel_format format;
283 enum swizzle_mode_values swizzle_mode;
284 enum dc_scan_direction scan;
287 struct dc_dcc_setting {
288 unsigned int max_compressed_blk_size;
289 unsigned int max_uncompressed_blk_size;
290 bool independent_64b_blks;
291 //These bitfields to be used starting with DCN
293 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
294 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN
295 uint32_t dcc_256_128_128 : 1; //available starting with DCN
296 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
300 struct dc_surface_dcc_cap {
303 struct dc_dcc_setting rgb;
307 struct dc_dcc_setting luma;
308 struct dc_dcc_setting chroma;
313 bool const_color_support;
316 struct dc_static_screen_params {
323 unsigned int num_frames;
327 /* Surface update type is used by dc_update_surfaces_and_stream
328 * The update type is determined at the very beginning of the function based
329 * on parameters passed in and decides how much programming (or updating) is
330 * going to be done during the call.
332 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
333 * logical calculations or hardware register programming. This update MUST be
334 * ISR safe on windows. Currently fast update will only be used to flip surface
337 * UPDATE_TYPE_MED is used for slower updates which require significant hw
338 * re-programming however do not affect bandwidth consumption or clock
339 * requirements. At present, this is the level at which front end updates
340 * that do not require us to run bw_calcs happen. These are in/out transfer func
341 * updates, viewport offset changes, recout size changes and pixel depth changes.
342 * This update can be done at ISR, but we want to minimize how often this happens.
344 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
345 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
346 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
347 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
348 * a full update. This cannot be done at ISR level and should be a rare event.
349 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
350 * underscan we don't expect to see this call at all.
353 enum surface_update_type {
354 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
355 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
356 UPDATE_TYPE_FULL, /* may need to shuffle resources */
359 /* Forward declaration*/
361 struct dc_plane_state;
365 struct dc_cap_funcs {
366 bool (*get_dcc_compression_cap)(const struct dc *dc,
367 const struct dc_dcc_surface_param *input,
368 struct dc_surface_dcc_cap *output);
371 struct link_training_settings;
373 union allow_lttpr_non_transparent_mode {
381 /* Structure to hold configuration flags set by dm at dc creation. */
384 bool disable_disp_pll_sharing;
386 bool disable_fractional_pwm;
387 bool allow_seamless_boot_optimization;
388 bool seamless_boot_edp_requested;
389 bool edp_not_connected;
390 bool edp_no_power_sequencing;
393 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
394 bool multi_mon_pp_mclk_switch;
397 bool enable_windowed_mpo_odm;
398 uint32_t allow_edp_hotplug_detection;
399 bool clamp_min_dcfclk;
400 uint64_t vblank_alignment_dto_params;
401 uint8_t vblank_alignment_max_frame_time_diff;
402 bool is_asymmetric_memory;
403 bool is_single_rank_dimm;
404 bool is_vmin_only_asic;
405 bool use_pipe_ctx_sync_logic;
406 bool ignore_dpref_ss;
407 bool enable_mipi_converter_optimization;
408 bool use_default_clock_table;
409 bool force_bios_enable_lttpr;
410 uint8_t force_bios_fixed_vs;
414 enum visual_confirm {
415 VISUAL_CONFIRM_DISABLE = 0,
416 VISUAL_CONFIRM_SURFACE = 1,
417 VISUAL_CONFIRM_HDR = 2,
418 VISUAL_CONFIRM_MPCTREE = 4,
419 VISUAL_CONFIRM_PSR = 5,
420 VISUAL_CONFIRM_SWAPCHAIN = 6,
421 VISUAL_CONFIRM_FAMS = 7,
422 VISUAL_CONFIRM_SWIZZLE = 9,
423 VISUAL_CONFIRM_SUBVP = 14,
426 enum dc_psr_power_opts {
427 psr_power_opt_invalid = 0x0,
428 psr_power_opt_smu_opt_static_screen = 0x1,
429 psr_power_opt_z10_static_screen = 0x10,
430 psr_power_opt_ds_disable_allow = 0x100,
433 enum dml_hostvm_override_opts {
434 DML_HOSTVM_NO_OVERRIDE = 0x0,
435 DML_HOSTVM_OVERRIDE_FALSE = 0x1,
436 DML_HOSTVM_OVERRIDE_TRUE = 0x2,
442 DCC_HALF_REQ_DISALBE = 2,
446 * enum pipe_split_policy - Pipe split strategy supported by DCN
448 * This enum is used to define the pipe split policy supported by DCN. By
449 * default, DC favors MPC_SPLIT_DYNAMIC.
451 enum pipe_split_policy {
453 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
454 * pipe in order to bring the best trade-off between performance and
455 * power consumption. This is the recommended option.
457 MPC_SPLIT_DYNAMIC = 0,
460 * @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not
461 * try any sort of split optimization.
466 * @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize
467 * the pipe utilization when using a single display; if the user
468 * connects to a second display, DC will avoid pipe split.
470 MPC_SPLIT_AVOID_MULT_DISP = 2,
473 enum wm_report_mode {
474 WM_REPORT_DEFAULT = 0,
475 WM_REPORT_OVERRIDE = 1,
478 dtm_level_p0 = 0,/*highest voltage*/
482 dtm_level_p4,/*when active_display_count = 0*/
486 DCN_PWR_STATE_UNKNOWN = -1,
487 DCN_PWR_STATE_MISSION_MODE = 0,
488 DCN_PWR_STATE_LOW_POWER = 3,
491 enum dcn_zstate_support_state {
492 DCN_ZSTATE_SUPPORT_UNKNOWN,
493 DCN_ZSTATE_SUPPORT_ALLOW,
494 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
495 DCN_ZSTATE_SUPPORT_DISALLOW,
498 * For any clocks that may differ per pipe
499 * only the max is stored in this structure
503 int actual_dispclk_khz;
505 int actual_dppclk_khz;
506 int disp_dpp_voltage_level_khz;
509 int dcfclk_deep_sleep_khz;
513 bool p_state_change_support;
514 enum dcn_zstate_support_state zstate_support;
517 bool fclk_p_state_change_support;
518 enum dcn_pwr_state pwr_state;
520 * Elements below are not compared for the purposes of
521 * optimization required
523 bool prev_p_state_change_support;
524 bool fclk_prev_p_state_change_support;
526 bool fw_based_mclk_switching;
527 bool fw_based_mclk_switching_shut_down;
529 enum dtm_pstate dtm_level;
530 int max_supported_dppclk_khz;
531 int max_supported_dispclk_khz;
532 int bw_dppclk_khz; /*a copy of dppclk_khz*/
536 struct dc_bw_validation_profile {
539 unsigned long long total_ticks;
540 unsigned long long voltage_level_ticks;
541 unsigned long long watermark_ticks;
542 unsigned long long rq_dlg_ticks;
544 unsigned long long total_count;
545 unsigned long long skip_fast_count;
546 unsigned long long skip_pass_count;
547 unsigned long long skip_fail_count;
550 #define BW_VAL_TRACE_SETUP() \
551 unsigned long long end_tick = 0; \
552 unsigned long long voltage_level_tick = 0; \
553 unsigned long long watermark_tick = 0; \
554 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
555 dm_get_timestamp(dc->ctx) : 0
557 #define BW_VAL_TRACE_COUNT() \
558 if (dc->debug.bw_val_profile.enable) \
559 dc->debug.bw_val_profile.total_count++
561 #define BW_VAL_TRACE_SKIP(status) \
562 if (dc->debug.bw_val_profile.enable) { \
563 if (!voltage_level_tick) \
564 voltage_level_tick = dm_get_timestamp(dc->ctx); \
565 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
568 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
569 if (dc->debug.bw_val_profile.enable) \
570 voltage_level_tick = dm_get_timestamp(dc->ctx)
572 #define BW_VAL_TRACE_END_WATERMARKS() \
573 if (dc->debug.bw_val_profile.enable) \
574 watermark_tick = dm_get_timestamp(dc->ctx)
576 #define BW_VAL_TRACE_FINISH() \
577 if (dc->debug.bw_val_profile.enable) { \
578 end_tick = dm_get_timestamp(dc->ctx); \
579 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
580 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
581 if (watermark_tick) { \
582 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
583 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
587 union mem_low_power_enable_options {
602 union root_clock_optimization_options {
614 uint32_t reserved: 22;
619 union dpia_debug_options {
621 uint32_t disable_dpia:1; /* bit 0 */
622 uint32_t force_non_lttpr:1; /* bit 1 */
623 uint32_t extend_aux_rd_interval:1; /* bit 2 */
624 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
625 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
626 uint32_t reserved:27;
631 /* AUX wake work around options
632 * 0: enable/disable work around
633 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
635 * 31-16: timeout in ms
637 union aux_wake_wa_options {
639 uint32_t enable_wa : 1;
640 uint32_t use_default_timeout : 1;
642 uint32_t timeout_ms : 16;
647 struct dc_debug_data {
648 uint32_t ltFailCount;
649 uint32_t i2cErrorCount;
650 uint32_t auxErrorCount;
653 struct dc_phy_addr_space_config {
666 uint64_t page_table_start_addr;
667 uint64_t page_table_end_addr;
668 uint64_t page_table_base_addr;
669 bool base_addr_is_mc_addr;
674 uint64_t page_table_default_page_addr;
677 struct dc_virtual_addr_space_config {
678 uint64_t page_table_base_addr;
679 uint64_t page_table_start_addr;
680 uint64_t page_table_end_addr;
681 uint32_t page_table_block_size_in_bytes;
682 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
685 struct dc_bounding_box_overrides {
687 int sr_enter_plus_exit_time_ns;
688 int urgent_latency_ns;
689 int percent_of_ideal_drambw;
690 int dram_clock_change_latency_ns;
691 int dummy_clock_change_latency_ns;
692 int fclk_clock_change_latency_ns;
693 /* This forces a hard min on the DCFCLK we use
694 * for DML. Unlike the debug option for forcing
695 * DCFCLK, this override affects watermark calculations
701 struct resource_pool;
705 * struct dc_debug_options - DC debug struct
707 * This struct provides a simple mechanism for developers to change some
708 * configurations, enable/disable features, and activate extra debug options.
709 * This can be very handy to narrow down whether some specific feature is
710 * causing an issue or not.
712 struct dc_debug_options {
713 bool native422_support;
715 enum visual_confirm visual_confirm;
716 int visual_confirm_rect_height;
723 bool validation_trace;
724 bool bandwidth_calcs_trace;
725 int max_downscale_src_width;
727 /* stutter efficiency related */
728 bool disable_stutter;
730 enum dcc_option disable_dcc;
733 * @pipe_split_policy: Define which pipe split policy is used by the
736 enum pipe_split_policy pipe_split_policy;
737 bool force_single_disp_pipe_split;
738 bool voltage_align_fclk;
739 bool disable_min_fclk;
741 bool disable_dfs_bypass;
742 bool disable_dpp_power_gate;
743 bool disable_hubp_power_gate;
744 bool disable_dsc_power_gate;
745 int dsc_min_slice_height_override;
746 int dsc_bpp_increment_div;
747 bool disable_pplib_wm_range;
748 enum wm_report_mode pplib_wm_report_mode;
749 unsigned int min_disp_clk_khz;
750 unsigned int min_dpp_clk_khz;
751 unsigned int min_dram_clk_khz;
752 int sr_exit_time_dpm0_ns;
753 int sr_enter_plus_exit_time_dpm0_ns;
755 int sr_enter_plus_exit_time_ns;
756 int urgent_latency_ns;
757 uint32_t underflow_assert_delay_us;
758 int percent_of_ideal_drambw;
759 int dram_clock_change_latency_ns;
760 bool optimized_watermark;
762 bool disable_pplib_clock_request;
763 bool disable_clock_gate;
764 bool disable_mem_low_power;
768 bool force_abm_enable;
769 bool disable_stereo_support;
771 bool performance_trace;
772 bool az_endpoint_mute_only;
773 bool always_use_regamma;
774 bool recovery_enabled;
775 bool avoid_vbios_exec_table;
776 bool scl_reset_length10;
778 bool skip_detection_link_training;
779 uint32_t edid_read_retry_times;
780 unsigned int force_odm_combine; //bit vector based on otg inst
781 unsigned int seamless_boot_odm_combine;
782 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
784 unsigned int force_fclk_khz;
786 bool dmub_offload_enabled;
787 bool dmcub_emulation;
788 bool disable_idle_power_optimizations;
789 unsigned int mall_size_override;
790 unsigned int mall_additional_timer_percent;
791 bool mall_error_as_fatal;
792 bool dmub_command_table; /* for testing only */
793 struct dc_bw_validation_profile bw_val_profile;
795 bool disable_48mhz_pwrdwn;
796 /* This forces a hard min on the DCFCLK requested to SMU/PP
797 * watermarks are not affected.
799 unsigned int force_min_dcfclk_mhz;
801 bool disable_timing_sync;
803 int force_clock_mode;/*every mode change.*/
805 bool disable_dram_clock_change_vactive_support;
806 bool validate_dml_output;
807 bool enable_dmcub_surface_flip;
808 bool usbc_combo_phy_reset_wa;
809 bool enable_dram_clock_change_one_display_vactive;
810 /* TODO - remove once tested */
812 bool set_mst_en_for_sst;
814 bool force_dp2_lt_fallback_method;
815 bool ignore_cable_id;
816 union mem_low_power_enable_options enable_mem_low_power;
817 union root_clock_optimization_options root_clock_optimization;
818 bool hpo_optimization;
819 bool force_vblank_alignment;
821 /* Enable dmub aux for legacy ddc */
822 bool enable_dmub_aux_for_legacy_ddc;
824 bool optimize_edp_link_rate; /* eDP ILR */
825 /* FEC/PSR1 sequence enable delay in 100us */
826 uint8_t fec_enable_delay_in100us;
827 bool enable_driver_sequence_debug;
828 enum det_size crb_alloc_policy;
829 int crb_alloc_policy_min_disp_count;
831 bool enable_z9_disable_interface;
832 union dpia_debug_options dpia_debug;
833 bool disable_fixed_vs_aux_timeout_wa;
834 bool force_disable_subvp;
835 bool force_subvp_mclk_switch;
836 bool allow_sw_cursor_fallback;
837 unsigned int force_subvp_num_ways;
838 unsigned int force_mall_ss_num_ways;
839 bool alloc_extra_way_for_cursor;
840 bool force_usr_allow;
841 /* uses value at boot and disables switch */
842 bool disable_dtb_ref_clk_switch;
843 uint32_t fixed_vs_aux_delay_config_wa;
844 bool extended_blank_optimization;
845 union aux_wake_wa_options aux_wake_wa;
846 uint32_t mst_start_top_delay;
847 uint8_t psr_power_use_phy_fsm;
848 enum dml_hostvm_override_opts dml_hostvm_override;
849 bool dml_disallow_alternate_prefetch_modes;
850 bool use_legacy_soc_bb_mechanism;
851 bool exit_idle_opt_for_cursor_updates;
852 bool enable_single_display_2to1_odm_policy;
853 bool enable_double_buffered_dsc_pg_support;
854 bool enable_dp_dig_pixel_rate_div_policy;
855 enum lttpr_mode lttpr_mode_override;
858 struct gpu_info_soc_bounding_box_v1_0;
860 struct dc_debug_options debug;
861 struct dc_versions versions;
863 struct dc_cap_funcs cap_funcs;
864 struct dc_config config;
865 struct dc_bounding_box_overrides bb_overrides;
866 struct dc_bug_wa work_arounds;
867 struct dc_context *ctx;
868 struct dc_phy_addr_space_config vm_pa_config;
871 struct dc_link *links[MAX_PIPES * 2];
873 struct dc_state *current_state;
874 struct resource_pool *res_pool;
876 struct clk_mgr *clk_mgr;
878 /* Display Engine Clock levels */
879 struct dm_pp_clock_levels sclk_lvls;
881 /* Inputs into BW and WM calculations. */
882 struct bw_calcs_dceip *bw_dceip;
883 struct bw_calcs_vbios *bw_vbios;
884 struct dcn_soc_bounding_box *dcn_soc;
885 struct dcn_ip_params *dcn_ip;
886 struct display_mode_lib dml;
889 struct hw_sequencer_funcs hwss;
890 struct dce_hwseq *hwseq;
892 /* Require to optimize clocks and bandwidth for added/removed planes */
893 bool optimized_required;
894 bool wm_optimized_required;
895 bool idle_optimizations_allowed;
896 bool enable_c20_dtm_b0;
898 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
901 struct compressor *fbc_compressor;
903 struct dc_debug_data debug_data;
904 struct dpcd_vendor_signature vendor_signature;
906 const char *build_id;
907 struct vm_helper *vm_helper;
909 uint32_t *dcn_reg_offsets;
910 uint32_t *nbio_reg_offsets;
916 * For matching clock_limits table in driver with table
919 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
920 } update_bw_bounding_box;
924 enum frame_buffer_mode {
925 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
926 FRAME_BUFFER_MODE_ZFB_ONLY,
927 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
930 struct dchub_init_data {
931 int64_t zfb_phys_addr_base;
932 int64_t zfb_mc_base_addr;
933 uint64_t zfb_size_in_byte;
934 enum frame_buffer_mode fb_mode;
935 bool dchub_initialzied;
936 bool dchub_info_valid;
939 struct dc_init_data {
940 struct hw_asic_id asic_id;
941 void *driver; /* ctx */
942 struct cgs_device *cgs_device;
943 struct dc_bounding_box_overrides bb_overrides;
945 int num_virtual_links;
947 * If 'vbios_override' not NULL, it will be called instead
948 * of the real VBIOS. Intended use is Diagnostics on FPGA.
950 struct dc_bios *vbios_override;
951 enum dce_environment dce_environment;
953 struct dmub_offload_funcs *dmub_if;
954 struct dc_reg_helper_state *dmub_offload;
956 struct dc_config flags;
959 struct dpcd_vendor_signature vendor_signature;
960 bool force_smu_not_present;
962 * IP offset for run time initializaion of register addresses
964 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
965 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
968 uint32_t *dcn_reg_offsets;
969 uint32_t *nbio_reg_offsets;
972 struct dc_callback_init {
973 #ifdef CONFIG_DRM_AMD_DC_HDCP
974 struct cp_psp cp_psp;
980 struct dc *dc_create(const struct dc_init_data *init_params);
981 void dc_hardware_init(struct dc *dc);
983 int dc_get_vmid_use_vector(struct dc *dc);
984 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
985 /* Returns the number of vmids supported */
986 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
987 void dc_init_callbacks(struct dc *dc,
988 const struct dc_callback_init *init_params);
989 void dc_deinit_callbacks(struct dc *dc);
990 void dc_destroy(struct dc **dc);
992 /*******************************************************************************
994 ******************************************************************************/
997 TRANSFER_FUNC_POINTS = 1025
1000 struct dc_hdr_static_metadata {
1001 /* display chromaticities and white point in units of 0.00001 */
1002 unsigned int chromaticity_green_x;
1003 unsigned int chromaticity_green_y;
1004 unsigned int chromaticity_blue_x;
1005 unsigned int chromaticity_blue_y;
1006 unsigned int chromaticity_red_x;
1007 unsigned int chromaticity_red_y;
1008 unsigned int chromaticity_white_point_x;
1009 unsigned int chromaticity_white_point_y;
1011 uint32_t min_luminance;
1012 uint32_t max_luminance;
1013 uint32_t maximum_content_light_level;
1014 uint32_t maximum_frame_average_light_level;
1017 enum dc_transfer_func_type {
1019 TF_TYPE_DISTRIBUTED_POINTS,
1024 struct dc_transfer_func_distributed_points {
1025 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1026 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1027 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1029 uint16_t end_exponent;
1030 uint16_t x_point_at_y1_red;
1031 uint16_t x_point_at_y1_green;
1032 uint16_t x_point_at_y1_blue;
1035 enum dc_transfer_func_predefined {
1036 TRANSFER_FUNCTION_SRGB,
1037 TRANSFER_FUNCTION_BT709,
1038 TRANSFER_FUNCTION_PQ,
1039 TRANSFER_FUNCTION_LINEAR,
1040 TRANSFER_FUNCTION_UNITY,
1041 TRANSFER_FUNCTION_HLG,
1042 TRANSFER_FUNCTION_HLG12,
1043 TRANSFER_FUNCTION_GAMMA22,
1044 TRANSFER_FUNCTION_GAMMA24,
1045 TRANSFER_FUNCTION_GAMMA26
1049 struct dc_transfer_func {
1050 struct kref refcount;
1051 enum dc_transfer_func_type type;
1052 enum dc_transfer_func_predefined tf;
1053 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1054 uint32_t sdr_ref_white_level;
1056 struct pwl_params pwl;
1057 struct dc_transfer_func_distributed_points tf_pts;
1062 union dc_3dlut_state {
1064 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
1065 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
1066 uint32_t rmu_mux_num:3; /*index of mux to use*/
1067 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1068 uint32_t mpc_rmu1_mux:4;
1069 uint32_t mpc_rmu2_mux:4;
1070 uint32_t reserved:15;
1077 struct kref refcount;
1078 struct tetrahedral_params lut_3d;
1079 struct fixed31_32 hdr_multiplier;
1080 union dc_3dlut_state state;
1083 * This structure is filled in by dc_surface_get_status and contains
1084 * the last requested address and the currently active address so the called
1085 * can determine if there are any outstanding flips
1087 struct dc_plane_status {
1088 struct dc_plane_address requested_address;
1089 struct dc_plane_address current_address;
1090 bool is_flip_pending;
1094 union surface_update_flags {
1097 uint32_t addr_update:1;
1098 /* Medium updates */
1099 uint32_t dcc_change:1;
1100 uint32_t color_space_change:1;
1101 uint32_t horizontal_mirror_change:1;
1102 uint32_t per_pixel_alpha_change:1;
1103 uint32_t global_alpha_change:1;
1104 uint32_t hdr_mult:1;
1105 uint32_t rotation_change:1;
1106 uint32_t swizzle_change:1;
1107 uint32_t scaling_change:1;
1108 uint32_t position_change:1;
1109 uint32_t in_transfer_func_change:1;
1110 uint32_t input_csc_change:1;
1111 uint32_t coeff_reduction_change:1;
1112 uint32_t output_tf_change:1;
1113 uint32_t pixel_format_change:1;
1114 uint32_t plane_size_change:1;
1115 uint32_t gamut_remap_change:1;
1118 uint32_t new_plane:1;
1119 uint32_t bpp_change:1;
1120 uint32_t gamma_change:1;
1121 uint32_t bandwidth_change:1;
1122 uint32_t clock_change:1;
1123 uint32_t stereo_format_change:1;
1125 uint32_t tmz_changed:1;
1126 uint32_t full_update:1;
1132 struct dc_plane_state {
1133 struct dc_plane_address address;
1134 struct dc_plane_flip_time time;
1135 bool triplebuffer_flips;
1136 struct scaling_taps scaling_quality;
1137 struct rect src_rect;
1138 struct rect dst_rect;
1139 struct rect clip_rect;
1141 struct plane_size plane_size;
1142 union dc_tiling_info tiling_info;
1144 struct dc_plane_dcc_param dcc;
1146 struct dc_gamma *gamma_correction;
1147 struct dc_transfer_func *in_transfer_func;
1148 struct dc_bias_and_scale *bias_and_scale;
1149 struct dc_csc_transform input_csc_color_matrix;
1150 struct fixed31_32 coeff_reduction_factor;
1151 struct fixed31_32 hdr_mult;
1152 struct colorspace_transform gamut_remap_matrix;
1154 // TODO: No longer used, remove
1155 struct dc_hdr_static_metadata hdr_static_ctx;
1157 enum dc_color_space color_space;
1159 struct dc_3dlut *lut3d_func;
1160 struct dc_transfer_func *in_shaper_func;
1161 struct dc_transfer_func *blend_tf;
1163 struct dc_transfer_func *gamcor_tf;
1164 enum surface_pixel_format format;
1165 enum dc_rotation_angle rotation;
1166 enum plane_stereo_format stereo_format;
1168 bool is_tiling_rotated;
1169 bool per_pixel_alpha;
1170 bool pre_multiplied_alpha;
1172 int global_alpha_value;
1174 bool flip_immediate;
1175 bool horizontal_mirror;
1178 union surface_update_flags update_flags;
1179 bool flip_int_enabled;
1180 bool skip_manual_trigger;
1182 /* private to DC core */
1183 struct dc_plane_status status;
1184 struct dc_context *ctx;
1186 /* HACK: Workaround for forcing full reprogramming under some conditions */
1187 bool force_full_update;
1189 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1191 /* private to dc_surface.c */
1192 enum dc_irq_source irq_source;
1193 struct kref refcount;
1194 struct tg_color visual_confirm_color;
1197 struct dc_plane_info {
1198 struct plane_size plane_size;
1199 union dc_tiling_info tiling_info;
1200 struct dc_plane_dcc_param dcc;
1201 enum surface_pixel_format format;
1202 enum dc_rotation_angle rotation;
1203 enum plane_stereo_format stereo_format;
1204 enum dc_color_space color_space;
1205 bool horizontal_mirror;
1207 bool per_pixel_alpha;
1208 bool pre_multiplied_alpha;
1210 int global_alpha_value;
1211 bool input_csc_enabled;
1215 struct dc_scaling_info {
1216 struct rect src_rect;
1217 struct rect dst_rect;
1218 struct rect clip_rect;
1219 struct scaling_taps scaling_quality;
1222 struct dc_surface_update {
1223 struct dc_plane_state *surface;
1225 /* isr safe update parameters. null means no updates */
1226 const struct dc_flip_addrs *flip_addr;
1227 const struct dc_plane_info *plane_info;
1228 const struct dc_scaling_info *scaling_info;
1229 struct fixed31_32 hdr_mult;
1230 /* following updates require alloc/sleep/spin that is not isr safe,
1231 * null means no updates
1233 const struct dc_gamma *gamma;
1234 const struct dc_transfer_func *in_transfer_func;
1236 const struct dc_csc_transform *input_csc_color_matrix;
1237 const struct fixed31_32 *coeff_reduction_factor;
1238 const struct dc_transfer_func *func_shaper;
1239 const struct dc_3dlut *lut3d_func;
1240 const struct dc_transfer_func *blend_tf;
1241 const struct colorspace_transform *gamut_remap_matrix;
1245 * Create a new surface with default parameters;
1247 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1248 const struct dc_plane_status *dc_plane_get_status(
1249 const struct dc_plane_state *plane_state);
1251 void dc_plane_state_retain(struct dc_plane_state *plane_state);
1252 void dc_plane_state_release(struct dc_plane_state *plane_state);
1254 void dc_gamma_retain(struct dc_gamma *dc_gamma);
1255 void dc_gamma_release(struct dc_gamma **dc_gamma);
1256 struct dc_gamma *dc_create_gamma(void);
1258 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1259 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1260 struct dc_transfer_func *dc_create_transfer_func(void);
1262 struct dc_3dlut *dc_create_3dlut_func(void);
1263 void dc_3dlut_func_release(struct dc_3dlut *lut);
1264 void dc_3dlut_func_retain(struct dc_3dlut *lut);
1266 void dc_post_update_surfaces_to_stream(
1269 #include "dc_stream.h"
1272 * Structure to store surface/stream associations for validation
1274 struct dc_validation_set {
1275 struct dc_stream_state *stream;
1276 struct dc_plane_state *plane_states[MAX_SURFACES];
1277 uint8_t plane_count;
1280 bool dc_validate_boot_timing(const struct dc *dc,
1281 const struct dc_sink *sink,
1282 struct dc_crtc_timing *crtc_timing);
1284 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1286 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1288 bool dc_set_generic_gpio_for_stereo(bool enable,
1289 struct gpio_service *gpio_service);
1292 * fast_validate: we return after determining if we can support the new state,
1293 * but before we populate the programming info
1295 enum dc_status dc_validate_global_state(
1297 struct dc_state *new_ctx,
1298 bool fast_validate);
1301 void dc_resource_state_construct(
1302 const struct dc *dc,
1303 struct dc_state *dst_ctx);
1305 bool dc_acquire_release_mpc_3dlut(
1306 struct dc *dc, bool acquire,
1307 struct dc_stream_state *stream,
1308 struct dc_3dlut **lut,
1309 struct dc_transfer_func **shaper);
1311 void dc_resource_state_copy_construct(
1312 const struct dc_state *src_ctx,
1313 struct dc_state *dst_ctx);
1315 void dc_resource_state_copy_construct_current(
1316 const struct dc *dc,
1317 struct dc_state *dst_ctx);
1319 void dc_resource_state_destruct(struct dc_state *context);
1321 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1324 * TODO update to make it about validation sets
1325 * Set up streams and links associated to drive sinks
1326 * The streams parameter is an absolute set of all active streams.
1329 * Phy, Encoder, Timing Generator are programmed and enabled.
1330 * New streams are enabled with blank stream; no memory read.
1332 bool dc_commit_state(struct dc *dc, struct dc_state *context);
1334 struct dc_state *dc_create_state(struct dc *dc);
1335 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1336 void dc_retain_state(struct dc_state *context);
1337 void dc_release_state(struct dc_state *context);
1339 /*******************************************************************************
1341 ******************************************************************************/
1344 union dpcd_rev dpcd_rev;
1345 union max_lane_count max_ln_count;
1346 union max_down_spread max_down_spread;
1347 union dprx_feature dprx_feature;
1349 /* valid only for eDP v1.4 or higher*/
1350 uint8_t edp_supported_link_rates_count;
1351 enum dc_link_rate edp_supported_link_rates[8];
1353 /* dongle type (DP converter, CV smart dongle) */
1354 enum display_dongle_type dongle_type;
1355 bool is_dongle_type_one;
1356 /* branch device or sink device */
1358 /* Dongle's downstream count. */
1359 union sink_count sink_count;
1360 bool is_mst_capable;
1361 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1362 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1363 struct dc_dongle_caps dongle_caps;
1365 uint32_t sink_dev_id;
1366 int8_t sink_dev_id_str[6];
1367 int8_t sink_hw_revision;
1368 int8_t sink_fw_revision[2];
1370 uint32_t branch_dev_id;
1371 int8_t branch_dev_name[6];
1372 int8_t branch_hw_revision;
1373 int8_t branch_fw_revision[2];
1375 bool allow_invalid_MSA_timing_param;
1376 bool panel_mode_edp;
1377 bool dpcd_display_control_capable;
1378 bool ext_receiver_cap_field_present;
1379 bool set_power_state_capable_edp;
1380 bool dynamic_backlight_capable_edp;
1381 union dpcd_fec_capability fec_cap;
1382 struct dpcd_dsc_capabilities dsc_caps;
1383 struct dc_lttpr_caps lttpr_caps;
1384 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1386 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
1387 union dp_main_line_channel_coding_cap channel_coding_cap;
1388 union dp_sink_video_fallback_formats fallback_formats;
1389 union dp_fec_capability1 fec_cap1;
1390 union dp_cable_id cable_id;
1392 union edp_alpm_caps alpm_caps;
1393 struct edp_psr_info psr_info;
1396 union dpcd_sink_ext_caps {
1398 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1399 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1401 uint8_t sdr_aux_backlight_control : 1;
1402 uint8_t hdr_aux_backlight_control : 1;
1403 uint8_t reserved_1 : 2;
1405 uint8_t reserved : 3;
1410 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1411 union hdcp_rx_caps {
1416 uint8_t repeater : 1;
1417 uint8_t hdcp_capable : 1;
1418 uint8_t reserved : 6;
1426 uint8_t HDCP_CAPABLE:1;
1434 union hdcp_rx_caps rx_caps;
1435 union hdcp_bcaps bcaps;
1439 #include "dc_link.h"
1441 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1443 /*******************************************************************************
1444 * Sink Interfaces - A sink corresponds to a display output device
1445 ******************************************************************************/
1447 struct dc_container_id {
1448 // 128bit GUID in binary form
1449 unsigned char guid[16];
1450 // 8 byte port ID -> ELD.PortID
1451 unsigned int portId[2];
1452 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1453 unsigned short manufacturerName;
1454 // 2 byte product code -> ELD.ProductCode
1455 unsigned short productCode;
1459 struct dc_sink_dsc_caps {
1460 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1461 // 'false' if they are sink's DSC caps
1462 bool is_virtual_dpcd_dsc;
1463 #if defined(CONFIG_DRM_AMD_DC_DCN)
1464 // 'true' if MST topology supports DSC passthrough for sink
1465 // 'false' if MST topology does not support DSC passthrough
1466 bool is_dsc_passthrough_supported;
1468 struct dsc_dec_dpcd_caps dsc_dec_caps;
1471 struct dc_sink_fec_caps {
1472 bool is_rx_fec_supported;
1473 bool is_topology_fec_supported;
1477 * The sink structure contains EDID and other display device properties
1480 enum signal_type sink_signal;
1481 struct dc_edid dc_edid; /* raw edid */
1482 struct dc_edid_caps edid_caps; /* parse display caps */
1483 struct dc_container_id *dc_container_id;
1484 uint32_t dongle_max_pix_clk;
1486 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1487 bool converter_disable_audio;
1489 struct dc_sink_dsc_caps dsc_caps;
1490 struct dc_sink_fec_caps fec_caps;
1492 bool is_vsc_sdp_colorimetry_supported;
1494 /* private to DC core */
1495 struct dc_link *link;
1496 struct dc_context *ctx;
1500 /* private to dc_sink.c */
1501 // refcount must be the last member in dc_sink, since we want the
1502 // sink structure to be logically cloneable up to (but not including)
1504 struct kref refcount;
1507 void dc_sink_retain(struct dc_sink *sink);
1508 void dc_sink_release(struct dc_sink *sink);
1510 struct dc_sink_init_data {
1511 enum signal_type sink_signal;
1512 struct dc_link *link;
1513 uint32_t dongle_max_pix_clk;
1514 bool converter_disable_audio;
1517 bool dc_extended_blank_supported(struct dc *dc);
1519 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1521 /* Newer interfaces */
1523 struct dc_plane_address address;
1524 struct dc_cursor_attributes attributes;
1528 /*******************************************************************************
1529 * Interrupt interfaces
1530 ******************************************************************************/
1531 enum dc_irq_source dc_interrupt_to_irq_source(
1535 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1536 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1537 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1538 struct dc *dc, uint32_t link_index);
1540 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
1542 /*******************************************************************************
1544 ******************************************************************************/
1546 void dc_set_power_state(
1548 enum dc_acpi_cm_power_state power_state);
1549 void dc_resume(struct dc *dc);
1551 void dc_power_down_on_boot(struct dc *dc);
1553 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1557 enum hdcp_message_status dc_process_hdcp_msg(
1558 enum signal_type signal,
1559 struct dc_link *link,
1560 struct hdcp_protection_message *message_info);
1562 bool dc_is_dmcu_initialized(struct dc *dc);
1564 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1565 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1567 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1568 struct dc_cursor_attributes *cursor_attr);
1570 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1572 /* set min and max memory clock to lowest and highest DPM level, respectively */
1573 void dc_unlock_memory_clock_frequency(struct dc *dc);
1575 /* set min memory clock to the min required for current mode, max to maxDPM */
1576 void dc_lock_memory_clock_frequency(struct dc *dc);
1578 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
1579 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
1581 /* cleanup on driver unload */
1582 void dc_hardware_release(struct dc *dc);
1584 /* disables fw based mclk switch */
1585 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
1587 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1588 void dc_z10_restore(const struct dc *dc);
1589 void dc_z10_save_init(struct dc *dc);
1591 bool dc_is_dmub_outbox_supported(struct dc *dc);
1592 bool dc_enable_dmub_notifications(struct dc *dc);
1594 void dc_enable_dmub_outbox(struct dc *dc);
1596 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1597 uint32_t link_index,
1598 struct aux_payload *payload);
1600 /* Get dc link index from dpia port index */
1601 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
1602 uint8_t dpia_port_index);
1604 bool dc_process_dmub_set_config_async(struct dc *dc,
1605 uint32_t link_index,
1606 struct set_config_cmd_payload *payload,
1607 struct dmub_notification *notify);
1609 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
1610 uint32_t link_index,
1611 uint8_t mst_alloc_slots,
1612 uint8_t *mst_slots_in_use);
1614 /*******************************************************************************
1616 ******************************************************************************/
1619 /*******************************************************************************
1620 * Disable acc mode Interfaces
1621 ******************************************************************************/
1622 void dc_disable_accelerated_mode(struct dc *dc);
1624 #endif /* DC_INTERFACE_H_ */