2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
31 #include "include/irq_service_interface.h"
32 #include "link_encoder.h"
33 #include "stream_encoder.h"
35 #include "timing_generator.h"
36 #include "transform.h"
40 #include "core_types.h"
41 #include "set_mode_types.h"
42 #include "virtual/virtual_stream_encoder.h"
43 #include "dpcd_defs.h"
45 #include "dce80/dce80_resource.h"
46 #include "dce100/dce100_resource.h"
47 #include "dce110/dce110_resource.h"
48 #include "dce112/dce112_resource.h"
49 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
50 #include "dcn10/dcn10_resource.h"
52 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
53 #include "dcn20/dcn20_resource.h"
55 #include "dce120/dce120_resource.h"
57 #define DC_LOGGER_INIT(logger)
59 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
61 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
62 switch (asic_id.chip_family) {
65 dc_version = DCE_VERSION_8_0;
68 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
70 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
71 dc_version = DCE_VERSION_8_3;
73 dc_version = DCE_VERSION_8_1;
76 dc_version = DCE_VERSION_11_0;
80 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
81 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
82 dc_version = DCE_VERSION_10_0;
85 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
88 dc_version = DCE_VERSION_11_2;
90 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
91 dc_version = DCE_VERSION_11_22;
94 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
95 dc_version = DCE_VERSION_12_1;
97 dc_version = DCE_VERSION_12_0;
99 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
101 dc_version = DCN_VERSION_1_0;
102 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
103 dc_version = DCN_VERSION_1_01;
107 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
109 dc_version = DCN_VERSION_2_0;
113 dc_version = DCE_VERSION_UNKNOWN;
119 struct resource_pool *dc_create_resource_pool(struct dc *dc,
120 const struct dc_init_data *init_data,
121 enum dce_version dc_version)
123 struct resource_pool *res_pool = NULL;
125 switch (dc_version) {
126 case DCE_VERSION_8_0:
127 res_pool = dce80_create_resource_pool(
128 init_data->num_virtual_links, dc);
130 case DCE_VERSION_8_1:
131 res_pool = dce81_create_resource_pool(
132 init_data->num_virtual_links, dc);
134 case DCE_VERSION_8_3:
135 res_pool = dce83_create_resource_pool(
136 init_data->num_virtual_links, dc);
138 case DCE_VERSION_10_0:
139 res_pool = dce100_create_resource_pool(
140 init_data->num_virtual_links, dc);
142 case DCE_VERSION_11_0:
143 res_pool = dce110_create_resource_pool(
144 init_data->num_virtual_links, dc,
147 case DCE_VERSION_11_2:
148 case DCE_VERSION_11_22:
149 res_pool = dce112_create_resource_pool(
150 init_data->num_virtual_links, dc);
152 case DCE_VERSION_12_0:
153 case DCE_VERSION_12_1:
154 res_pool = dce120_create_resource_pool(
155 init_data->num_virtual_links, dc);
158 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
159 case DCN_VERSION_1_0:
160 case DCN_VERSION_1_01:
161 res_pool = dcn10_create_resource_pool(init_data, dc);
166 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
167 case DCN_VERSION_2_0:
168 res_pool = dcn20_create_resource_pool(init_data, dc);
175 if (res_pool != NULL) {
176 struct dc_firmware_info fw_info = { { 0 } };
178 if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
179 &fw_info) == BP_RESULT_OK) {
180 res_pool->ref_clocks.xtalin_clock_inKhz =
181 fw_info.pll_info.crystal_frequency;
182 /* initialize with firmware data first, no all
183 * ASIC have DCCG SW component. FPGA or
184 * simulation need initialization of
185 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
186 * with xtalin_clock_inKhz
188 res_pool->ref_clocks.dccg_ref_clock_inKhz =
189 res_pool->ref_clocks.xtalin_clock_inKhz;
190 res_pool->ref_clocks.dchub_ref_clock_inKhz =
191 res_pool->ref_clocks.xtalin_clock_inKhz;
193 ASSERT_CRITICAL(false);
199 void dc_destroy_resource_pool(struct dc *dc)
203 dc->res_pool->funcs->destroy(&dc->res_pool);
209 static void update_num_audio(
210 const struct resource_straps *straps,
211 unsigned int *num_audio,
212 struct audio_support *aud_support)
214 aud_support->dp_audio = true;
215 aud_support->hdmi_audio_native = false;
216 aud_support->hdmi_audio_on_dongle = false;
218 if (straps->hdmi_disable == 0) {
219 if (straps->dc_pinstraps_audio & 0x2) {
220 aud_support->hdmi_audio_on_dongle = true;
221 aud_support->hdmi_audio_native = true;
225 switch (straps->audio_stream_number) {
226 case 0: /* multi streams supported */
228 case 1: /* multi streams not supported */
232 DC_ERR("DC: unexpected audio fuse!\n");
236 bool resource_construct(
237 unsigned int num_virtual_links,
239 struct resource_pool *pool,
240 const struct resource_create_funcs *create_funcs)
242 struct dc_context *ctx = dc->ctx;
243 const struct resource_caps *caps = pool->res_cap;
245 unsigned int num_audio = caps->num_audio;
246 struct resource_straps straps = {0};
248 if (create_funcs->read_dce_straps)
249 create_funcs->read_dce_straps(dc->ctx, &straps);
251 pool->audio_count = 0;
252 if (create_funcs->create_audio) {
253 /* find the total number of streams available via the
254 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
255 * registers (one for each pin) starting from pin 1
256 * up to the max number of audio pins.
257 * We stop on the first pin where
258 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
260 update_num_audio(&straps, &num_audio, &pool->audio_support);
261 for (i = 0; i < caps->num_audio; i++) {
262 struct audio *aud = create_funcs->create_audio(ctx, i);
265 DC_ERR("DC: failed to create audio!\n");
269 if (!aud->funcs->endpoint_valid(aud)) {
270 aud->funcs->destroy(&aud);
274 pool->audios[i] = aud;
279 pool->stream_enc_count = 0;
280 if (create_funcs->create_stream_encoder) {
281 for (i = 0; i < caps->num_stream_encoder; i++) {
282 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
283 if (pool->stream_enc[i] == NULL)
284 DC_ERR("DC: failed to create stream_encoder!\n");
285 pool->stream_enc_count++;
289 dc->caps.dynamic_audio = false;
290 if (pool->audio_count < pool->stream_enc_count) {
291 dc->caps.dynamic_audio = true;
293 for (i = 0; i < num_virtual_links; i++) {
294 pool->stream_enc[pool->stream_enc_count] =
295 virtual_stream_encoder_create(
297 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
298 DC_ERR("DC: failed to create stream_encoder!\n");
301 pool->stream_enc_count++;
304 dc->hwseq = create_funcs->create_hwseq(ctx);
308 static int find_matching_clock_source(
309 const struct resource_pool *pool,
310 struct clock_source *clock_source)
315 for (i = 0; i < pool->clk_src_count; i++) {
316 if (pool->clock_sources[i] == clock_source)
322 void resource_unreference_clock_source(
323 struct resource_context *res_ctx,
324 const struct resource_pool *pool,
325 struct clock_source *clock_source)
327 int i = find_matching_clock_source(pool, clock_source);
330 res_ctx->clock_source_ref_count[i]--;
332 if (pool->dp_clock_source == clock_source)
333 res_ctx->dp_clock_source_ref_count--;
336 void resource_reference_clock_source(
337 struct resource_context *res_ctx,
338 const struct resource_pool *pool,
339 struct clock_source *clock_source)
341 int i = find_matching_clock_source(pool, clock_source);
344 res_ctx->clock_source_ref_count[i]++;
346 if (pool->dp_clock_source == clock_source)
347 res_ctx->dp_clock_source_ref_count++;
350 int resource_get_clock_source_reference(
351 struct resource_context *res_ctx,
352 const struct resource_pool *pool,
353 struct clock_source *clock_source)
355 int i = find_matching_clock_source(pool, clock_source);
358 return res_ctx->clock_source_ref_count[i];
360 if (pool->dp_clock_source == clock_source)
361 return res_ctx->dp_clock_source_ref_count;
366 bool resource_are_streams_timing_synchronizable(
367 struct dc_stream_state *stream1,
368 struct dc_stream_state *stream2)
370 if (stream1->timing.h_total != stream2->timing.h_total)
373 if (stream1->timing.v_total != stream2->timing.v_total)
376 if (stream1->timing.h_addressable
377 != stream2->timing.h_addressable)
380 if (stream1->timing.v_addressable
381 != stream2->timing.v_addressable)
384 if (stream1->timing.pix_clk_100hz
385 != stream2->timing.pix_clk_100hz)
388 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
391 if (stream1->phy_pix_clk != stream2->phy_pix_clk
392 && (!dc_is_dp_signal(stream1->signal)
393 || !dc_is_dp_signal(stream2->signal)))
396 if (stream1->view_format != stream2->view_format)
401 static bool is_dp_and_hdmi_sharable(
402 struct dc_stream_state *stream1,
403 struct dc_stream_state *stream2)
405 if (stream1->ctx->dc->caps.disable_dp_clk_share)
408 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
409 stream2->clamping.c_depth != COLOR_DEPTH_888)
416 static bool is_sharable_clk_src(
417 const struct pipe_ctx *pipe_with_clk_src,
418 const struct pipe_ctx *pipe)
420 if (pipe_with_clk_src->clock_source == NULL)
423 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
426 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
427 (dc_is_dp_signal(pipe->stream->signal) &&
428 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
432 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
433 && dc_is_dual_link_signal(pipe->stream->signal))
436 if (dc_is_hdmi_signal(pipe->stream->signal)
437 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
440 if (!resource_are_streams_timing_synchronizable(
441 pipe_with_clk_src->stream, pipe->stream))
447 struct clock_source *resource_find_used_clk_src_for_sharing(
448 struct resource_context *res_ctx,
449 struct pipe_ctx *pipe_ctx)
453 for (i = 0; i < MAX_PIPES; i++) {
454 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
455 return res_ctx->pipe_ctx[i].clock_source;
461 static enum pixel_format convert_pixel_format_to_dalsurface(
462 enum surface_pixel_format surface_pixel_format)
464 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
466 switch (surface_pixel_format) {
467 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
468 dal_pixel_format = PIXEL_FORMAT_INDEX8;
470 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
471 dal_pixel_format = PIXEL_FORMAT_RGB565;
473 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
474 dal_pixel_format = PIXEL_FORMAT_RGB565;
476 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
477 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
479 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
480 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
482 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
483 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
485 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
486 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
488 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
489 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
491 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
492 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
493 dal_pixel_format = PIXEL_FORMAT_FP16;
495 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
496 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
497 dal_pixel_format = PIXEL_FORMAT_420BPP8;
499 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
500 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
501 dal_pixel_format = PIXEL_FORMAT_420BPP10;
503 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
505 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
508 return dal_pixel_format;
511 static inline void get_vp_scan_direction(
512 enum dc_rotation_angle rotation,
513 bool horizontal_mirror,
514 bool *orthogonal_rotation,
515 bool *flip_vert_scan_dir,
516 bool *flip_horz_scan_dir)
518 *orthogonal_rotation = false;
519 *flip_vert_scan_dir = false;
520 *flip_horz_scan_dir = false;
521 if (rotation == ROTATION_ANGLE_180) {
522 *flip_vert_scan_dir = true;
523 *flip_horz_scan_dir = true;
524 } else if (rotation == ROTATION_ANGLE_90) {
525 *orthogonal_rotation = true;
526 *flip_horz_scan_dir = true;
527 } else if (rotation == ROTATION_ANGLE_270) {
528 *orthogonal_rotation = true;
529 *flip_vert_scan_dir = true;
532 if (horizontal_mirror)
533 *flip_horz_scan_dir = !*flip_horz_scan_dir;
536 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
538 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
539 const struct dc_stream_state *stream = pipe_ctx->stream;
540 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
541 struct rect surf_src = plane_state->src_rect;
542 struct rect clip, dest;
543 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
544 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
545 bool pri_split = pipe_ctx->bottom_pipe &&
546 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
547 bool sec_split = pipe_ctx->top_pipe &&
548 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
549 bool orthogonal_rotation, flip_y_start, flip_x_start;
551 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
552 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
557 /* The actual clip is an intersection between stream
558 * source and surface clip
560 dest = plane_state->dst_rect;
561 clip.x = stream->src.x > plane_state->clip_rect.x ?
562 stream->src.x : plane_state->clip_rect.x;
564 clip.width = stream->src.x + stream->src.width <
565 plane_state->clip_rect.x + plane_state->clip_rect.width ?
566 stream->src.x + stream->src.width - clip.x :
567 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
569 clip.y = stream->src.y > plane_state->clip_rect.y ?
570 stream->src.y : plane_state->clip_rect.y;
572 clip.height = stream->src.y + stream->src.height <
573 plane_state->clip_rect.y + plane_state->clip_rect.height ?
574 stream->src.y + stream->src.height - clip.y :
575 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
578 * Need to calculate how scan origin is shifted in vp space
579 * to correctly rotate clip and dst
581 get_vp_scan_direction(
582 plane_state->rotation,
583 plane_state->horizontal_mirror,
584 &orthogonal_rotation,
588 if (orthogonal_rotation) {
589 swap(clip.x, clip.y);
590 swap(clip.width, clip.height);
591 swap(dest.x, dest.y);
592 swap(dest.width, dest.height);
595 clip.x = dest.x + dest.width - clip.x - clip.width;
599 clip.y = dest.y + dest.height - clip.y - clip.height;
603 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
604 * num_pixels = clip.num_pix * scl_ratio
606 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
607 data->viewport.width = clip.width * surf_src.width / dest.width;
609 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
610 data->viewport.height = clip.height * surf_src.height / dest.height;
613 if (pri_split || sec_split) {
614 if (orthogonal_rotation) {
615 if (flip_y_start != pri_split)
616 data->viewport.height /= 2;
618 data->viewport.y += data->viewport.height / 2;
619 /* Ceil offset pipe */
620 data->viewport.height = (data->viewport.height + 1) / 2;
623 if (flip_x_start != pri_split)
624 data->viewport.width /= 2;
626 data->viewport.x += data->viewport.width / 2;
627 /* Ceil offset pipe */
628 data->viewport.width = (data->viewport.width + 1) / 2;
633 /* Round down, compensate in init */
634 data->viewport_c.x = data->viewport.x / vpc_div;
635 data->viewport_c.y = data->viewport.y / vpc_div;
636 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
637 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
639 /* Round up, assume original video size always even dimensions */
640 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
641 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
644 static void calculate_recout(struct pipe_ctx *pipe_ctx)
646 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
647 const struct dc_stream_state *stream = pipe_ctx->stream;
648 struct rect surf_clip = plane_state->clip_rect;
649 bool pri_split = pipe_ctx->bottom_pipe &&
650 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
651 bool sec_split = pipe_ctx->top_pipe &&
652 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
653 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
655 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
656 if (stream->src.x < surf_clip.x)
657 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
658 - stream->src.x) * stream->dst.width
661 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
662 stream->dst.width / stream->src.width;
663 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
664 stream->dst.x + stream->dst.width)
665 pipe_ctx->plane_res.scl_data.recout.width =
666 stream->dst.x + stream->dst.width
667 - pipe_ctx->plane_res.scl_data.recout.x;
669 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
670 if (stream->src.y < surf_clip.y)
671 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
672 - stream->src.y) * stream->dst.height
673 / stream->src.height;
675 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
676 stream->dst.height / stream->src.height;
677 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
678 stream->dst.y + stream->dst.height)
679 pipe_ctx->plane_res.scl_data.recout.height =
680 stream->dst.y + stream->dst.height
681 - pipe_ctx->plane_res.scl_data.recout.y;
683 /* Handle h & v split, handle rotation using viewport */
684 if (sec_split && top_bottom_split) {
685 pipe_ctx->plane_res.scl_data.recout.y +=
686 pipe_ctx->plane_res.scl_data.recout.height / 2;
687 /* Floor primary pipe, ceil 2ndary pipe */
688 pipe_ctx->plane_res.scl_data.recout.height =
689 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
690 } else if (pri_split && top_bottom_split)
691 pipe_ctx->plane_res.scl_data.recout.height /= 2;
692 else if (sec_split) {
693 pipe_ctx->plane_res.scl_data.recout.x +=
694 pipe_ctx->plane_res.scl_data.recout.width / 2;
695 /* Ceil offset pipe */
696 pipe_ctx->plane_res.scl_data.recout.width =
697 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
698 } else if (pri_split)
699 pipe_ctx->plane_res.scl_data.recout.width /= 2;
702 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
704 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
705 const struct dc_stream_state *stream = pipe_ctx->stream;
706 struct rect surf_src = plane_state->src_rect;
707 const int in_w = stream->src.width;
708 const int in_h = stream->src.height;
709 const int out_w = stream->dst.width;
710 const int out_h = stream->dst.height;
712 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
713 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
714 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
715 swap(surf_src.height, surf_src.width);
717 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
719 plane_state->dst_rect.width);
720 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
722 plane_state->dst_rect.height);
724 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
725 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
726 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
727 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
729 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
730 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
731 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
732 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
734 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
735 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
737 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
738 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
739 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
740 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
742 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
743 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
744 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
745 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
746 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
747 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
748 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
749 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
752 static inline void adjust_vp_and_init_for_seamless_clip(
757 struct fixed31_32 ratio,
758 struct fixed31_32 *init,
762 if (!flip_scan_dir) {
763 /* Adjust for viewport end clip-off */
764 if ((*vp_offset + *vp_size) < src_size) {
765 int vp_clip = src_size - *vp_size - *vp_offset;
766 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
768 int_part = int_part > 0 ? int_part : 0;
769 *vp_size += int_part < vp_clip ? int_part : vp_clip;
772 /* Adjust for non-0 viewport offset */
776 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
777 int_part = dc_fixpt_floor(*init) - *vp_offset;
778 if (int_part < taps) {
779 int int_adj = *vp_offset >= (taps - int_part) ?
780 (taps - int_part) : *vp_offset;
781 *vp_offset -= int_adj;
784 } else if (int_part > taps) {
785 *vp_offset += int_part - taps;
786 *vp_size -= int_part - taps;
789 init->value &= 0xffffffff;
790 *init = dc_fixpt_add_int(*init, int_part);
793 /* Adjust for non-0 viewport offset */
795 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
797 int_part = int_part > 0 ? int_part : 0;
798 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
799 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
802 /* Adjust for viewport end clip-off */
803 if ((*vp_offset + *vp_size) < src_size) {
805 int end_offset = src_size - *vp_offset - *vp_size;
808 * this is init if vp had no offset, keep in mind this is from the
809 * right side of vp due to scan direction
811 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
813 * this is the difference between first pixel of viewport available to read
814 * and init position, takning into account scan direction
816 int_part = dc_fixpt_floor(*init) - end_offset;
817 if (int_part < taps) {
818 int int_adj = end_offset >= (taps - int_part) ?
819 (taps - int_part) : end_offset;
822 } else if (int_part > taps) {
823 *vp_size += int_part - taps;
826 init->value &= 0xffffffff;
827 *init = dc_fixpt_add_int(*init, int_part);
832 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
834 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
835 const struct dc_stream_state *stream = pipe_ctx->stream;
836 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
837 struct rect src = pipe_ctx->plane_state->src_rect;
838 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
839 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
840 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
841 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
844 * Need to calculate the scan direction for viewport to make adjustments
846 get_vp_scan_direction(
847 plane_state->rotation,
848 plane_state->horizontal_mirror,
849 &orthogonal_rotation,
851 &flip_horz_scan_dir);
853 /* Calculate src rect rotation adjusted to recout space */
854 surf_size_h = src.x + src.width;
855 surf_size_v = src.y + src.height;
856 if (flip_horz_scan_dir)
858 if (flip_vert_scan_dir)
860 if (orthogonal_rotation) {
862 swap(src.width, src.height);
865 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
866 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
867 * - (surf surf_src offset * 1/ full scl ratio))
869 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
870 * stream->dst.width / stream->src.width -
871 src.x * plane_state->dst_rect.width / src.width
872 * stream->dst.width / stream->src.width);
873 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
874 * stream->dst.height / stream->src.height -
875 src.y * plane_state->dst_rect.height / src.height
876 * stream->dst.height / stream->src.height);
877 if (orthogonal_rotation)
878 swap(recout_skip_h, recout_skip_v);
880 * Init calculated according to formula:
881 * init = (scaling_ratio + number_of_taps + 1) / 2
882 * init_bot = init + scaling_ratio
883 * init_c = init + truncated_vp_c_offset(from calculate viewport)
885 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
886 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
888 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
889 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
891 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
892 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
894 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
895 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
898 * Taps, inits and scaling ratios are in recout space need to rotate
899 * to viewport rotation before adjustment
901 adjust_vp_and_init_for_seamless_clip(
905 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
906 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
907 orthogonal_rotation ? &data->inits.v : &data->inits.h,
909 &data->viewport.width);
910 adjust_vp_and_init_for_seamless_clip(
913 surf_size_h / vpc_div,
914 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
915 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
916 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
918 &data->viewport_c.width);
919 adjust_vp_and_init_for_seamless_clip(
923 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
924 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
925 orthogonal_rotation ? &data->inits.h : &data->inits.v,
927 &data->viewport.height);
928 adjust_vp_and_init_for_seamless_clip(
931 surf_size_v / vpc_div,
932 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
933 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
934 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
936 &data->viewport_c.height);
938 /* Interlaced inits based on final vert inits */
939 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
940 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
944 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
946 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
947 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
949 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
950 /* Important: scaling ratio calculation requires pixel format,
951 * lb depth calculation requires recout and taps require scaling ratios.
952 * Inits require viewport, taps, ratios and recout of split pipe
954 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
955 pipe_ctx->plane_state->format);
957 calculate_scaling_ratios(pipe_ctx);
959 calculate_viewport(pipe_ctx);
961 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
964 calculate_recout(pipe_ctx);
967 * Setting line buffer pixel depth to 24bpp yields banding
968 * on certain displays, such as the Sharp 4k
970 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
972 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
973 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
975 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
976 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
978 /* Taps calculations */
979 if (pipe_ctx->plane_res.xfm != NULL)
980 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
981 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
983 if (pipe_ctx->plane_res.dpp != NULL)
984 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
985 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
987 /* Try 24 bpp linebuffer */
988 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
990 if (pipe_ctx->plane_res.xfm != NULL)
991 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
992 pipe_ctx->plane_res.xfm,
993 &pipe_ctx->plane_res.scl_data,
994 &plane_state->scaling_quality);
996 if (pipe_ctx->plane_res.dpp != NULL)
997 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
998 pipe_ctx->plane_res.dpp,
999 &pipe_ctx->plane_res.scl_data,
1000 &plane_state->scaling_quality);
1004 /* May need to re-check lb size after this in some obscure scenario */
1005 calculate_inits_and_adj_vp(pipe_ctx);
1008 "%s: Viewport:\nheight:%d width:%d x:%d "
1009 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1012 pipe_ctx->plane_res.scl_data.viewport.height,
1013 pipe_ctx->plane_res.scl_data.viewport.width,
1014 pipe_ctx->plane_res.scl_data.viewport.x,
1015 pipe_ctx->plane_res.scl_data.viewport.y,
1016 plane_state->dst_rect.height,
1017 plane_state->dst_rect.width,
1018 plane_state->dst_rect.x,
1019 plane_state->dst_rect.y);
1025 enum dc_status resource_build_scaling_params_for_context(
1026 const struct dc *dc,
1027 struct dc_state *context)
1031 for (i = 0; i < MAX_PIPES; i++) {
1032 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1033 context->res_ctx.pipe_ctx[i].stream != NULL)
1034 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1035 return DC_FAIL_SCALING;
1041 struct pipe_ctx *find_idle_secondary_pipe(
1042 struct resource_context *res_ctx,
1043 const struct resource_pool *pool,
1044 const struct pipe_ctx *primary_pipe)
1047 struct pipe_ctx *secondary_pipe = NULL;
1050 * We add a preferred pipe mapping to avoid the chance that
1051 * MPCCs already in use will need to be reassigned to other trees.
1052 * For example, if we went with the strict, assign backwards logic:
1055 * Display A on, no surface, top pipe = 0
1056 * Display B on, no surface, top pipe = 1
1059 * Display A on, no surface, top pipe = 0
1060 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1063 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1064 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1066 * The state 2->3 transition requires remapping MPCC 5 from display B
1069 * However, with the preferred pipe logic, state 2 would look like:
1072 * Display A on, no surface, top pipe = 0
1073 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1075 * This would then cause 2->3 to not require remapping any MPCCs.
1078 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1079 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1080 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1081 secondary_pipe->pipe_idx = preferred_pipe_idx;
1086 * search backwards for the second pipe to keep pipe
1087 * assignment more consistent
1089 if (!secondary_pipe)
1090 for (i = pool->pipe_count - 1; i >= 0; i--) {
1091 if (res_ctx->pipe_ctx[i].stream == NULL) {
1092 secondary_pipe = &res_ctx->pipe_ctx[i];
1093 secondary_pipe->pipe_idx = i;
1098 return secondary_pipe;
1101 struct pipe_ctx *resource_get_head_pipe_for_stream(
1102 struct resource_context *res_ctx,
1103 struct dc_stream_state *stream)
1106 for (i = 0; i < MAX_PIPES; i++) {
1107 if (res_ctx->pipe_ctx[i].stream == stream &&
1108 !res_ctx->pipe_ctx[i].top_pipe) {
1109 return &res_ctx->pipe_ctx[i];
1116 static struct pipe_ctx *resource_get_tail_pipe_for_stream(
1117 struct resource_context *res_ctx,
1118 struct dc_stream_state *stream)
1120 struct pipe_ctx *head_pipe, *tail_pipe;
1121 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1126 tail_pipe = head_pipe->bottom_pipe;
1129 head_pipe = tail_pipe;
1130 tail_pipe = tail_pipe->bottom_pipe;
1137 * A free_pipe for a stream is defined here as a pipe
1138 * that has no surface attached yet
1140 static struct pipe_ctx *acquire_free_pipe_for_stream(
1141 struct dc_state *context,
1142 const struct resource_pool *pool,
1143 struct dc_stream_state *stream)
1146 struct resource_context *res_ctx = &context->res_ctx;
1148 struct pipe_ctx *head_pipe = NULL;
1150 /* Find head pipe, which has the back end set up*/
1152 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1159 if (!head_pipe->plane_state)
1162 /* Re-use pipe already acquired for this stream if available*/
1163 for (i = pool->pipe_count - 1; i >= 0; i--) {
1164 if (res_ctx->pipe_ctx[i].stream == stream &&
1165 !res_ctx->pipe_ctx[i].plane_state) {
1166 return &res_ctx->pipe_ctx[i];
1171 * At this point we have no re-useable pipe for this stream and we need
1172 * to acquire an idle one to satisfy the request
1175 if (!pool->funcs->acquire_idle_pipe_for_layer)
1178 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
1182 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1183 static int acquire_first_split_pipe(
1184 struct resource_context *res_ctx,
1185 const struct resource_pool *pool,
1186 struct dc_stream_state *stream)
1190 for (i = 0; i < pool->pipe_count; i++) {
1191 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1193 if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) &&
1194 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1195 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1196 if (split_pipe->bottom_pipe)
1197 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1199 if (split_pipe->top_pipe->plane_state)
1200 resource_build_scaling_params(split_pipe->top_pipe);
1202 memset(split_pipe, 0, sizeof(*split_pipe));
1203 split_pipe->stream_res.tg = pool->timing_generators[i];
1204 split_pipe->plane_res.hubp = pool->hubps[i];
1205 split_pipe->plane_res.ipp = pool->ipps[i];
1206 split_pipe->plane_res.dpp = pool->dpps[i];
1207 split_pipe->stream_res.opp = pool->opps[i];
1208 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1209 split_pipe->pipe_idx = i;
1211 split_pipe->stream = stream;
1219 bool dc_add_plane_to_context(
1220 const struct dc *dc,
1221 struct dc_stream_state *stream,
1222 struct dc_plane_state *plane_state,
1223 struct dc_state *context)
1226 struct resource_pool *pool = dc->res_pool;
1227 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
1228 struct dc_stream_status *stream_status = NULL;
1230 for (i = 0; i < context->stream_count; i++)
1231 if (context->streams[i] == stream) {
1232 stream_status = &context->stream_status[i];
1235 if (stream_status == NULL) {
1236 dm_error("Existing stream not found; failed to attach surface!\n");
1241 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1242 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1243 plane_state, MAX_SURFACE_NUM);
1247 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1250 dm_error("Head pipe not found for stream_state %p !\n", stream);
1254 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1257 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1259 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1261 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1263 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1269 /* retain new surfaces */
1270 dc_plane_state_retain(plane_state);
1271 free_pipe->plane_state = plane_state;
1273 if (head_pipe != free_pipe) {
1274 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1275 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1276 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1277 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1278 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1279 free_pipe->clock_source = tail_pipe->clock_source;
1280 free_pipe->top_pipe = tail_pipe;
1281 tail_pipe->bottom_pipe = free_pipe;
1282 } else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
1283 ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
1284 free_pipe->bottom_pipe->plane_state = plane_state;
1287 /* assign new surfaces*/
1288 stream_status->plane_states[stream_status->plane_count] = plane_state;
1290 stream_status->plane_count++;
1295 struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
1297 struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe;
1299 /* ODM should only be updated once per otg */
1300 if (pipe_ctx->top_pipe)
1303 while (bottom_pipe) {
1304 if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp)
1306 bottom_pipe = bottom_pipe->bottom_pipe;
1312 bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
1314 struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
1318 if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp)
1324 bool dc_remove_plane_from_context(
1325 const struct dc *dc,
1326 struct dc_stream_state *stream,
1327 struct dc_plane_state *plane_state,
1328 struct dc_state *context)
1331 struct dc_stream_status *stream_status = NULL;
1332 struct resource_pool *pool = dc->res_pool;
1334 for (i = 0; i < context->stream_count; i++)
1335 if (context->streams[i] == stream) {
1336 stream_status = &context->stream_status[i];
1340 if (stream_status == NULL) {
1341 dm_error("Existing stream not found; failed to remove plane.\n");
1345 /* release pipe for plane*/
1346 for (i = pool->pipe_count - 1; i >= 0; i--) {
1347 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1349 if (pipe_ctx->plane_state == plane_state) {
1350 if (dc_res_is_odm_head_pipe(pipe_ctx)) {
1351 pipe_ctx->plane_state = NULL;
1352 pipe_ctx->bottom_pipe = NULL;
1356 if (pipe_ctx->top_pipe)
1357 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1359 /* Second condition is to avoid setting NULL to top pipe
1360 * of tail pipe making it look like head pipe in subsequent
1363 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1364 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1367 * For head pipe detach surfaces from pipe for tail
1368 * pipe just zero it out
1370 if (!pipe_ctx->top_pipe) {
1371 pipe_ctx->plane_state = NULL;
1372 if (!dc_res_get_odm_bottom_pipe(pipe_ctx))
1373 pipe_ctx->bottom_pipe = NULL;
1375 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1381 for (i = 0; i < stream_status->plane_count; i++) {
1382 if (stream_status->plane_states[i] == plane_state) {
1384 dc_plane_state_release(stream_status->plane_states[i]);
1389 if (i == stream_status->plane_count) {
1390 dm_error("Existing plane_state not found; failed to detach it!\n");
1394 stream_status->plane_count--;
1396 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1397 for (; i < stream_status->plane_count; i++)
1398 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1400 stream_status->plane_states[stream_status->plane_count] = NULL;
1405 bool dc_rem_all_planes_for_stream(
1406 const struct dc *dc,
1407 struct dc_stream_state *stream,
1408 struct dc_state *context)
1410 int i, old_plane_count;
1411 struct dc_stream_status *stream_status = NULL;
1412 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1414 for (i = 0; i < context->stream_count; i++)
1415 if (context->streams[i] == stream) {
1416 stream_status = &context->stream_status[i];
1420 if (stream_status == NULL) {
1421 dm_error("Existing stream %p not found!\n", stream);
1425 old_plane_count = stream_status->plane_count;
1427 for (i = 0; i < old_plane_count; i++)
1428 del_planes[i] = stream_status->plane_states[i];
1430 for (i = 0; i < old_plane_count; i++)
1431 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1437 static bool add_all_planes_for_stream(
1438 const struct dc *dc,
1439 struct dc_stream_state *stream,
1440 const struct dc_validation_set set[],
1442 struct dc_state *context)
1446 for (i = 0; i < set_count; i++)
1447 if (set[i].stream == stream)
1450 if (i == set_count) {
1451 dm_error("Stream %p not found in set!\n", stream);
1455 for (j = 0; j < set[i].plane_count; j++)
1456 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1462 bool dc_add_all_planes_for_stream(
1463 const struct dc *dc,
1464 struct dc_stream_state *stream,
1465 struct dc_plane_state * const *plane_states,
1467 struct dc_state *context)
1469 struct dc_validation_set set;
1472 set.stream = stream;
1473 set.plane_count = plane_count;
1475 for (i = 0; i < plane_count; i++)
1476 set.plane_states[i] = plane_states[i];
1478 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1482 static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1483 struct dc_stream_state *new_stream)
1485 if (cur_stream == NULL)
1488 if (memcmp(&cur_stream->hdr_static_metadata,
1489 &new_stream->hdr_static_metadata,
1490 sizeof(struct dc_info_packet)) != 0)
1496 static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1497 struct dc_stream_state *new_stream)
1499 if (cur_stream == NULL)
1502 if (memcmp(&cur_stream->vsc_infopacket,
1503 &new_stream->vsc_infopacket,
1504 sizeof(struct dc_info_packet)) != 0)
1510 static bool is_timing_changed(struct dc_stream_state *cur_stream,
1511 struct dc_stream_state *new_stream)
1513 if (cur_stream == NULL)
1516 /* If sink pointer changed, it means this is a hotplug, we should do
1519 if (cur_stream->sink != new_stream->sink)
1522 /* If output color space is changed, need to reprogram info frames */
1523 if (cur_stream->output_color_space != new_stream->output_color_space)
1527 &cur_stream->timing,
1528 &new_stream->timing,
1529 sizeof(struct dc_crtc_timing)) != 0;
1532 static bool are_stream_backends_same(
1533 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
1535 if (stream_a == stream_b)
1538 if (stream_a == NULL || stream_b == NULL)
1541 if (is_timing_changed(stream_a, stream_b))
1544 if (is_hdr_static_meta_changed(stream_a, stream_b))
1547 if (stream_a->dpms_off != stream_b->dpms_off)
1550 if (is_vsc_info_packet_changed(stream_a, stream_b))
1557 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1559 * Checks if there a difference between the two states
1560 * that would require a mode change.
1562 * Does not compare cursor position or attributes.
1564 bool dc_is_stream_unchanged(
1565 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1568 if (!are_stream_backends_same(old_stream, stream))
1575 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1577 bool dc_is_stream_scaling_unchanged(
1578 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1580 if (old_stream == stream)
1583 if (old_stream == NULL || stream == NULL)
1586 if (memcmp(&old_stream->src,
1588 sizeof(struct rect)) != 0)
1591 if (memcmp(&old_stream->dst,
1593 sizeof(struct rect)) != 0)
1599 static void update_stream_engine_usage(
1600 struct resource_context *res_ctx,
1601 const struct resource_pool *pool,
1602 struct stream_encoder *stream_enc,
1607 for (i = 0; i < pool->stream_enc_count; i++) {
1608 if (pool->stream_enc[i] == stream_enc)
1609 res_ctx->is_stream_enc_acquired[i] = acquired;
1613 /* TODO: release audio object */
1614 void update_audio_usage(
1615 struct resource_context *res_ctx,
1616 const struct resource_pool *pool,
1617 struct audio *audio,
1621 for (i = 0; i < pool->audio_count; i++) {
1622 if (pool->audios[i] == audio)
1623 res_ctx->is_audio_acquired[i] = acquired;
1627 static int acquire_first_free_pipe(
1628 struct resource_context *res_ctx,
1629 const struct resource_pool *pool,
1630 struct dc_stream_state *stream)
1634 for (i = 0; i < pool->pipe_count; i++) {
1635 if (!res_ctx->pipe_ctx[i].stream) {
1636 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1638 pipe_ctx->stream_res.tg = pool->timing_generators[i];
1639 pipe_ctx->plane_res.mi = pool->mis[i];
1640 pipe_ctx->plane_res.hubp = pool->hubps[i];
1641 pipe_ctx->plane_res.ipp = pool->ipps[i];
1642 pipe_ctx->plane_res.xfm = pool->transforms[i];
1643 pipe_ctx->plane_res.dpp = pool->dpps[i];
1644 pipe_ctx->stream_res.opp = pool->opps[i];
1646 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
1647 pipe_ctx->pipe_idx = i;
1650 pipe_ctx->stream = stream;
1657 static struct audio *find_first_free_audio(
1658 struct resource_context *res_ctx,
1659 const struct resource_pool *pool,
1663 for (i = 0; i < pool->audio_count; i++) {
1664 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1665 /*we have enough audio endpoint, find the matching inst*/
1669 return pool->audios[i];
1673 /* use engine id to find free audio */
1674 if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1675 return pool->audios[id];
1678 /*not found the matching one, first come first serve*/
1679 for (i = 0; i < pool->audio_count; i++) {
1680 if (res_ctx->is_audio_acquired[i] == false) {
1681 return pool->audios[i];
1687 bool resource_is_stream_unchanged(
1688 struct dc_state *old_context, struct dc_stream_state *stream)
1692 for (i = 0; i < old_context->stream_count; i++) {
1693 struct dc_stream_state *old_stream = old_context->streams[i];
1695 if (are_stream_backends_same(old_stream, stream))
1703 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1705 enum dc_status dc_add_stream_to_ctx(
1707 struct dc_state *new_ctx,
1708 struct dc_stream_state *stream)
1711 DC_LOGGER_INIT(dc->ctx->logger);
1713 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
1714 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1715 return DC_ERROR_UNEXPECTED;
1718 new_ctx->streams[new_ctx->stream_count] = stream;
1719 dc_stream_retain(stream);
1720 new_ctx->stream_count++;
1722 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1724 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1730 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1732 enum dc_status dc_remove_stream_from_ctx(
1734 struct dc_state *new_ctx,
1735 struct dc_stream_state *stream)
1738 struct dc_context *dc_ctx = dc->ctx;
1739 struct pipe_ctx *del_pipe = NULL;
1741 /* Release primary pipe */
1742 for (i = 0; i < MAX_PIPES; i++) {
1743 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1744 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1745 struct pipe_ctx *odm_pipe =
1746 dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]);
1748 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1750 ASSERT(del_pipe->stream_res.stream_enc);
1751 update_stream_engine_usage(
1754 del_pipe->stream_res.stream_enc,
1757 if (del_pipe->stream_res.audio)
1761 del_pipe->stream_res.audio,
1764 resource_unreference_clock_source(&new_ctx->res_ctx,
1766 del_pipe->clock_source);
1768 if (dc->res_pool->funcs->remove_stream_from_ctx)
1769 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1771 memset(del_pipe, 0, sizeof(*del_pipe));
1773 memset(odm_pipe, 0, sizeof(*odm_pipe));
1780 DC_ERROR("Pipe not found for stream %p !\n", stream);
1781 return DC_ERROR_UNEXPECTED;
1784 for (i = 0; i < new_ctx->stream_count; i++)
1785 if (new_ctx->streams[i] == stream)
1788 if (new_ctx->streams[i] != stream) {
1789 DC_ERROR("Context doesn't have stream %p !\n", stream);
1790 return DC_ERROR_UNEXPECTED;
1793 dc_stream_release(new_ctx->streams[i]);
1794 new_ctx->stream_count--;
1796 /* Trim back arrays */
1797 for (; i < new_ctx->stream_count; i++) {
1798 new_ctx->streams[i] = new_ctx->streams[i + 1];
1799 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1802 new_ctx->streams[new_ctx->stream_count] = NULL;
1804 &new_ctx->stream_status[new_ctx->stream_count],
1806 sizeof(new_ctx->stream_status[0]));
1811 static struct dc_stream_state *find_pll_sharable_stream(
1812 struct dc_stream_state *stream_needs_pll,
1813 struct dc_state *context)
1817 for (i = 0; i < context->stream_count; i++) {
1818 struct dc_stream_state *stream_has_pll = context->streams[i];
1820 /* We are looking for non dp, non virtual stream */
1821 if (resource_are_streams_timing_synchronizable(
1822 stream_needs_pll, stream_has_pll)
1823 && !dc_is_dp_signal(stream_has_pll->signal)
1824 && stream_has_pll->link->connector_signal
1825 != SIGNAL_TYPE_VIRTUAL)
1826 return stream_has_pll;
1833 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1835 uint32_t pix_clk = timing->pix_clk_100hz;
1836 uint32_t normalized_pix_clk = pix_clk;
1838 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1840 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1841 switch (timing->display_color_depth) {
1842 case COLOR_DEPTH_666:
1843 case COLOR_DEPTH_888:
1844 normalized_pix_clk = pix_clk;
1846 case COLOR_DEPTH_101010:
1847 normalized_pix_clk = (pix_clk * 30) / 24;
1849 case COLOR_DEPTH_121212:
1850 normalized_pix_clk = (pix_clk * 36) / 24;
1852 case COLOR_DEPTH_161616:
1853 normalized_pix_clk = (pix_clk * 48) / 24;
1860 return normalized_pix_clk;
1863 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
1865 /* update actual pixel clock on all streams */
1866 if (dc_is_hdmi_signal(stream->signal))
1867 stream->phy_pix_clk = get_norm_pix_clk(
1868 &stream->timing) / 10;
1870 stream->phy_pix_clk =
1871 stream->timing.pix_clk_100hz / 10;
1873 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1874 stream->phy_pix_clk *= 2;
1877 static int acquire_resource_from_hw_enabled_state(
1878 struct resource_context *res_ctx,
1879 const struct resource_pool *pool,
1880 struct dc_stream_state *stream)
1882 struct dc_link *link = stream->link;
1885 /* Check for enabled DIG to identify enabled display */
1886 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1889 /* Check for which front end is used by this encoder.
1890 * Note the inst is 1 indexed, where 0 is undefined.
1891 * Note that DIG_FE can source from different OTG but our
1892 * current implementation always map 1-to-1, so this code makes
1893 * the same assumption and doesn't check OTG source.
1895 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
1897 /* Instance should be within the range of the pool */
1898 if (inst >= pool->pipe_count)
1901 if (!res_ctx->pipe_ctx[inst].stream) {
1902 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
1904 pipe_ctx->stream_res.tg = pool->timing_generators[inst];
1905 pipe_ctx->plane_res.mi = pool->mis[inst];
1906 pipe_ctx->plane_res.hubp = pool->hubps[inst];
1907 pipe_ctx->plane_res.ipp = pool->ipps[inst];
1908 pipe_ctx->plane_res.xfm = pool->transforms[inst];
1909 pipe_ctx->plane_res.dpp = pool->dpps[inst];
1910 pipe_ctx->stream_res.opp = pool->opps[inst];
1911 if (pool->dpps[inst])
1912 pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
1913 pipe_ctx->pipe_idx = inst;
1915 pipe_ctx->stream = stream;
1922 enum dc_status resource_map_pool_resources(
1923 const struct dc *dc,
1924 struct dc_state *context,
1925 struct dc_stream_state *stream)
1927 const struct resource_pool *pool = dc->res_pool;
1929 struct dc_context *dc_ctx = dc->ctx;
1930 struct pipe_ctx *pipe_ctx = NULL;
1932 struct dc_bios *dcb = dc->ctx->dc_bios;
1934 /* TODO Check if this is needed */
1935 /*if (!resource_is_stream_unchanged(old_context, stream)) {
1936 if (stream != NULL && old_context->streams[i] != NULL) {
1937 stream->bit_depth_params =
1938 old_context->streams[i]->bit_depth_params;
1939 stream->clamping = old_context->streams[i]->clamping;
1945 calculate_phy_pix_clks(stream);
1947 /* TODO: Check Linux */
1948 if (dc->config.allow_seamless_boot_optimization &&
1949 !dcb->funcs->is_accelerated_mode(dcb)) {
1950 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1951 stream->apply_seamless_boot_optimization = true;
1954 if (stream->apply_seamless_boot_optimization)
1955 pipe_idx = acquire_resource_from_hw_enabled_state(
1961 /* acquire new resources */
1962 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
1964 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
1966 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1969 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1970 return DC_NO_CONTROLLER_RESOURCE;
1972 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1974 pipe_ctx->stream_res.stream_enc =
1975 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1976 &context->res_ctx, pool, stream);
1978 if (!pipe_ctx->stream_res.stream_enc)
1979 return DC_NO_STREAM_ENC_RESOURCE;
1981 update_stream_engine_usage(
1982 &context->res_ctx, pool,
1983 pipe_ctx->stream_res.stream_enc,
1986 /* TODO: Add check if ASIC support and EDID audio */
1987 if (!stream->converter_disable_audio &&
1988 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1989 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1990 pipe_ctx->stream_res.audio = find_first_free_audio(
1991 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1994 * Audio assigned in order first come first get.
1995 * There are asics which has number of audio
1996 * resources less then number of pipes
1998 if (pipe_ctx->stream_res.audio)
1999 update_audio_usage(&context->res_ctx, pool,
2000 pipe_ctx->stream_res.audio, true);
2003 /* Add ABM to the resource if on EDP */
2004 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
2005 pipe_ctx->stream_res.abm = pool->abm;
2007 for (i = 0; i < context->stream_count; i++)
2008 if (context->streams[i] == stream) {
2009 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2010 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
2011 context->stream_status[i].audio_inst =
2012 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2017 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2018 return DC_ERROR_UNEXPECTED;
2022 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2023 * Is a shallow copy. Increments refcounts on existing streams and planes.
2024 * @dc: copy out of dc->current_state
2025 * @dst_ctx: copy into this
2027 void dc_resource_state_copy_construct_current(
2028 const struct dc *dc,
2029 struct dc_state *dst_ctx)
2031 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2035 void dc_resource_state_construct(
2036 const struct dc *dc,
2037 struct dc_state *dst_ctx)
2039 dst_ctx->clk_mgr = dc->clk_mgr;
2043 * dc_validate_global_state() - Determine if HW can support a given state
2044 * Checks HW resource availability and bandwidth requirement.
2045 * @dc: dc struct for this driver
2046 * @new_ctx: state to be validated
2047 * @fast_validate: set to true if only yes/no to support matters
2049 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2051 enum dc_status dc_validate_global_state(
2053 struct dc_state *new_ctx,
2056 enum dc_status result = DC_ERROR_UNEXPECTED;
2060 return DC_ERROR_UNEXPECTED;
2062 if (dc->res_pool->funcs->validate_global) {
2063 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2064 if (result != DC_OK)
2068 for (i = 0; i < new_ctx->stream_count; i++) {
2069 struct dc_stream_state *stream = new_ctx->streams[i];
2071 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2072 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2074 if (pipe_ctx->stream != stream)
2077 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2078 pipe_ctx->plane_state &&
2079 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2080 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2081 if (result != DC_OK)
2085 /* Switch to dp clock source only if there is
2086 * no non dp stream that shares the same timing
2087 * with the dp stream.
2089 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2090 !find_pll_sharable_stream(stream, new_ctx)) {
2092 resource_unreference_clock_source(
2095 pipe_ctx->clock_source);
2097 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2098 resource_reference_clock_source(
2101 pipe_ctx->clock_source);
2106 result = resource_build_scaling_params_for_context(dc, new_ctx);
2108 if (result == DC_OK)
2109 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
2110 result = DC_FAIL_BANDWIDTH_VALIDATE;
2115 static void patch_gamut_packet_checksum(
2116 struct dc_info_packet *gamut_packet)
2118 /* For gamut we recalc checksum */
2119 if (gamut_packet->valid) {
2120 uint8_t chk_sum = 0;
2124 /*start of the Gamut data. */
2125 ptr = &gamut_packet->sb[3];
2127 for (i = 0; i <= gamut_packet->sb[1]; i++)
2130 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
2134 static void set_avi_info_frame(
2135 struct dc_info_packet *info_packet,
2136 struct pipe_ctx *pipe_ctx)
2138 struct dc_stream_state *stream = pipe_ctx->stream;
2139 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
2140 uint32_t pixel_encoding = 0;
2141 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2142 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2144 uint8_t itc_value = 0;
2145 uint8_t cn0_cn1 = 0;
2146 unsigned int cn0_cn1_value = 0;
2147 uint8_t *check_sum = NULL;
2148 uint8_t byte_index = 0;
2149 union hdmi_info_packet hdmi_info;
2150 union display_content_support support = {0};
2151 unsigned int vic = pipe_ctx->stream->timing.vic;
2152 enum dc_timing_3d_format format;
2154 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2156 color_space = pipe_ctx->stream->output_color_space;
2157 if (color_space == COLOR_SPACE_UNKNOWN)
2158 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
2159 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
2161 /* Initialize header */
2162 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
2163 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2164 * not be used in HDMI 2.0 (Section 10.1) */
2165 hdmi_info.bits.header.version = 2;
2166 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
2169 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2170 * according to HDMI 2.0 spec (Section 10.1)
2173 switch (stream->timing.pixel_encoding) {
2174 case PIXEL_ENCODING_YCBCR422:
2178 case PIXEL_ENCODING_YCBCR444:
2181 case PIXEL_ENCODING_YCBCR420:
2185 case PIXEL_ENCODING_RGB:
2190 /* Y0_Y1_Y2 : The pixel encoding */
2191 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
2192 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
2194 /* A0 = 1 Active Format Information valid */
2195 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
2197 /* B0, B1 = 3; Bar info data is valid */
2198 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
2200 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
2202 /* S0, S1 : Underscan / Overscan */
2203 /* TODO: un-hardcode scan type */
2204 scan_type = SCANNING_TYPE_UNDERSCAN;
2205 hdmi_info.bits.S0_S1 = scan_type;
2207 /* C0, C1 : Colorimetry */
2208 if (color_space == COLOR_SPACE_YCBCR709 ||
2209 color_space == COLOR_SPACE_YCBCR709_LIMITED)
2210 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
2211 else if (color_space == COLOR_SPACE_YCBCR601 ||
2212 color_space == COLOR_SPACE_YCBCR601_LIMITED)
2213 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
2215 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
2217 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
2218 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2219 color_space == COLOR_SPACE_2020_YCBCR) {
2220 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2221 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2222 } else if (color_space == COLOR_SPACE_ADOBERGB) {
2223 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2224 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2227 /* TODO: un-hardcode aspect ratio */
2228 aspect = stream->timing.aspect_ratio;
2231 case ASPECT_RATIO_4_3:
2232 case ASPECT_RATIO_16_9:
2233 hdmi_info.bits.M0_M1 = aspect;
2236 case ASPECT_RATIO_NO_DATA:
2237 case ASPECT_RATIO_64_27:
2238 case ASPECT_RATIO_256_135:
2240 hdmi_info.bits.M0_M1 = 0;
2243 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
2244 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
2246 /* TODO: un-hardcode cn0_cn1 and itc */
2254 support = stream->content_support;
2257 if (!support.bits.valid_content_type) {
2260 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2261 if (support.bits.graphics_content == 1) {
2264 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2265 if (support.bits.photo_content == 1) {
2271 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2272 if (support.bits.cinema_content == 1) {
2278 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2279 if (support.bits.game_content == 1) {
2287 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2288 hdmi_info.bits.ITC = itc_value;
2291 /* TODO : We should handle YCC quantization */
2292 /* but we do not have matrix calculation */
2293 if (stream->qs_bit == 1 &&
2294 stream->qy_bit == 1) {
2295 if (color_space == COLOR_SPACE_SRGB ||
2296 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
2297 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2298 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
2299 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2300 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2301 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2302 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2304 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2305 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2308 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2309 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2313 format = stream->timing.timing_3d_format;
2314 /*todo, add 3DStereo support*/
2315 if (format != TIMING_3D_FORMAT_NONE) {
2316 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
2317 switch (pipe_ctx->stream->timing.hdmi_vic) {
2334 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
2335 hdmi_info.bits.VIC0_VIC7 = vic;
2337 hdmi_info.bits.header.version = 3;
2338 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2339 * the Source shall use 20 AVI InfoFrame Version 4
2341 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2342 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2343 hdmi_info.bits.header.version = 4;
2344 hdmi_info.bits.header.length = 14;
2348 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2349 * repetition start from 1 */
2350 hdmi_info.bits.PR0_PR3 = 0;
2353 * barTop: Line Number of End of Top Bar.
2354 * barBottom: Line Number of Start of Bottom Bar.
2355 * barLeft: Pixel Number of End of Left Bar.
2356 * barRight: Pixel Number of Start of Right Bar. */
2357 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2358 hdmi_info.bits.bar_bottom = (stream->timing.v_total
2359 - stream->timing.v_border_bottom + 1);
2360 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2361 hdmi_info.bits.bar_right = (stream->timing.h_total
2362 - stream->timing.h_border_right + 1);
2364 /* Additional Colorimetry Extension
2365 * Used in conduction with C0-C1 and EC0-EC2
2366 * 0 = DCI-P3 RGB (D65)
2367 * 1 = DCI-P3 RGB (theater)
2369 hdmi_info.bits.ACE0_ACE3 = 0;
2371 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2372 check_sum = &hdmi_info.packet_raw_data.sb[0];
2374 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
2376 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
2377 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2379 /* one byte complement */
2380 *check_sum = (uint8_t) (0x100 - *check_sum);
2382 /* Store in hw_path_mode */
2383 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2384 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2385 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2387 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2388 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2390 info_packet->valid = true;
2393 static void set_vendor_info_packet(
2394 struct dc_info_packet *info_packet,
2395 struct dc_stream_state *stream)
2397 /* SPD info packet for FreeSync */
2399 /* Check if Freesync is supported. Return if false. If true,
2400 * set the corresponding bit in the info packet
2402 if (!stream->vsp_infopacket.valid)
2405 *info_packet = stream->vsp_infopacket;
2408 static void set_spd_info_packet(
2409 struct dc_info_packet *info_packet,
2410 struct dc_stream_state *stream)
2412 /* SPD info packet for FreeSync */
2414 /* Check if Freesync is supported. Return if false. If true,
2415 * set the corresponding bit in the info packet
2417 if (!stream->vrr_infopacket.valid)
2420 *info_packet = stream->vrr_infopacket;
2423 static void set_hdr_static_info_packet(
2424 struct dc_info_packet *info_packet,
2425 struct dc_stream_state *stream)
2427 /* HDR Static Metadata info packet for HDR10 */
2429 if (!stream->hdr_static_metadata.valid ||
2430 stream->use_dynamic_meta)
2433 *info_packet = stream->hdr_static_metadata;
2436 static void set_vsc_info_packet(
2437 struct dc_info_packet *info_packet,
2438 struct dc_stream_state *stream)
2440 if (!stream->vsc_infopacket.valid)
2443 *info_packet = stream->vsc_infopacket;
2446 void dc_resource_state_destruct(struct dc_state *context)
2450 for (i = 0; i < context->stream_count; i++) {
2451 for (j = 0; j < context->stream_status[i].plane_count; j++)
2452 dc_plane_state_release(
2453 context->stream_status[i].plane_states[j]);
2455 context->stream_status[i].plane_count = 0;
2456 dc_stream_release(context->streams[i]);
2457 context->streams[i] = NULL;
2461 void dc_resource_state_copy_construct(
2462 const struct dc_state *src_ctx,
2463 struct dc_state *dst_ctx)
2466 struct kref refcount = dst_ctx->refcount;
2468 *dst_ctx = *src_ctx;
2470 for (i = 0; i < MAX_PIPES; i++) {
2471 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2473 if (cur_pipe->top_pipe)
2474 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2476 if (cur_pipe->bottom_pipe)
2477 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2480 for (i = 0; i < dst_ctx->stream_count; i++) {
2481 dc_stream_retain(dst_ctx->streams[i]);
2482 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2483 dc_plane_state_retain(
2484 dst_ctx->stream_status[i].plane_states[j]);
2487 /* context refcount should not be overridden */
2488 dst_ctx->refcount = refcount;
2492 struct clock_source *dc_resource_find_first_free_pll(
2493 struct resource_context *res_ctx,
2494 const struct resource_pool *pool)
2498 for (i = 0; i < pool->clk_src_count; ++i) {
2499 if (res_ctx->clock_source_ref_count[i] == 0)
2500 return pool->clock_sources[i];
2506 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2508 enum signal_type signal = SIGNAL_TYPE_NONE;
2509 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
2511 /* default all packets to invalid */
2512 info->avi.valid = false;
2513 info->gamut.valid = false;
2514 info->vendor.valid = false;
2515 info->spd.valid = false;
2516 info->hdrsmd.valid = false;
2517 info->vsc.valid = false;
2519 signal = pipe_ctx->stream->signal;
2521 /* HDMi and DP have different info packets*/
2522 if (dc_is_hdmi_signal(signal)) {
2523 set_avi_info_frame(&info->avi, pipe_ctx);
2525 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2527 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2529 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2531 } else if (dc_is_dp_signal(signal)) {
2532 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2534 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2536 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2539 patch_gamut_packet_checksum(&info->gamut);
2542 enum dc_status resource_map_clock_resources(
2543 const struct dc *dc,
2544 struct dc_state *context,
2545 struct dc_stream_state *stream)
2547 /* acquire new resources */
2548 const struct resource_pool *pool = dc->res_pool;
2549 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2550 &context->res_ctx, stream);
2553 return DC_ERROR_UNEXPECTED;
2555 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2556 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2557 pipe_ctx->clock_source = pool->dp_clock_source;
2559 pipe_ctx->clock_source = NULL;
2561 if (!dc->config.disable_disp_pll_sharing)
2562 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
2566 if (pipe_ctx->clock_source == NULL)
2567 pipe_ctx->clock_source =
2568 dc_resource_find_first_free_pll(
2573 if (pipe_ctx->clock_source == NULL)
2574 return DC_NO_CLOCK_SOURCE_RESOURCE;
2576 resource_reference_clock_source(
2577 &context->res_ctx, pool,
2578 pipe_ctx->clock_source);
2584 * Note: We need to disable output if clock sources change,
2585 * since bios does optimization and doesn't apply if changing
2586 * PHY when not already disabled.
2588 bool pipe_need_reprogram(
2589 struct pipe_ctx *pipe_ctx_old,
2590 struct pipe_ctx *pipe_ctx)
2592 if (!pipe_ctx_old->stream)
2595 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2598 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2601 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
2604 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2605 && pipe_ctx_old->stream != pipe_ctx->stream)
2608 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
2611 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2614 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2617 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2620 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2623 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2624 false == pipe_ctx_old->stream->dpms_off)
2630 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
2631 struct bit_depth_reduction_params *fmt_bit_depth)
2633 enum dc_dither_option option = stream->dither_option;
2634 enum dc_pixel_encoding pixel_encoding =
2635 stream->timing.pixel_encoding;
2637 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2639 if (option == DITHER_OPTION_DEFAULT) {
2640 switch (stream->timing.display_color_depth) {
2641 case COLOR_DEPTH_666:
2642 option = DITHER_OPTION_SPATIAL6;
2644 case COLOR_DEPTH_888:
2645 option = DITHER_OPTION_SPATIAL8;
2647 case COLOR_DEPTH_101010:
2648 option = DITHER_OPTION_SPATIAL10;
2651 option = DITHER_OPTION_DISABLE;
2655 if (option == DITHER_OPTION_DISABLE)
2658 if (option == DITHER_OPTION_TRUN6) {
2659 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2660 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2661 } else if (option == DITHER_OPTION_TRUN8 ||
2662 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2663 option == DITHER_OPTION_TRUN8_FM6) {
2664 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2665 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2666 } else if (option == DITHER_OPTION_TRUN10 ||
2667 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2668 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2669 option == DITHER_OPTION_TRUN10_FM8 ||
2670 option == DITHER_OPTION_TRUN10_FM6 ||
2671 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2672 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2673 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2676 /* special case - Formatter can only reduce by 4 bits at most.
2677 * When reducing from 12 to 6 bits,
2678 * HW recommends we use trunc with round mode
2679 * (if we did nothing, trunc to 10 bits would be used)
2680 * note that any 12->10 bit reduction is ignored prior to DCE8,
2681 * as the input was 10 bits.
2683 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2684 option == DITHER_OPTION_SPATIAL6 ||
2685 option == DITHER_OPTION_FM6) {
2686 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2687 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2688 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2692 * note that spatial modes 1-3 are never used
2694 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2695 option == DITHER_OPTION_SPATIAL6 ||
2696 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2697 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2698 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2699 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2700 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2701 fmt_bit_depth->flags.RGB_RANDOM =
2702 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2703 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2704 option == DITHER_OPTION_SPATIAL8 ||
2705 option == DITHER_OPTION_SPATIAL8_FM6 ||
2706 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2707 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2708 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2709 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2710 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2711 fmt_bit_depth->flags.RGB_RANDOM =
2712 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2713 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2714 option == DITHER_OPTION_SPATIAL10 ||
2715 option == DITHER_OPTION_SPATIAL10_FM8 ||
2716 option == DITHER_OPTION_SPATIAL10_FM6) {
2717 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2718 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2719 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2720 fmt_bit_depth->flags.RGB_RANDOM =
2721 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2724 if (option == DITHER_OPTION_SPATIAL6 ||
2725 option == DITHER_OPTION_SPATIAL8 ||
2726 option == DITHER_OPTION_SPATIAL10) {
2727 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2729 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2732 //////////////////////
2733 //// temporal dither
2734 //////////////////////
2735 if (option == DITHER_OPTION_FM6 ||
2736 option == DITHER_OPTION_SPATIAL8_FM6 ||
2737 option == DITHER_OPTION_SPATIAL10_FM6 ||
2738 option == DITHER_OPTION_TRUN10_FM6 ||
2739 option == DITHER_OPTION_TRUN8_FM6 ||
2740 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2741 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2742 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2743 } else if (option == DITHER_OPTION_FM8 ||
2744 option == DITHER_OPTION_SPATIAL10_FM8 ||
2745 option == DITHER_OPTION_TRUN10_FM8) {
2746 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2747 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2748 } else if (option == DITHER_OPTION_FM10) {
2749 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2750 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2753 fmt_bit_depth->pixel_encoding = pixel_encoding;
2756 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
2758 struct dc *core_dc = dc;
2759 struct dc_link *link = stream->link;
2760 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2761 enum dc_status res = DC_OK;
2763 calculate_phy_pix_clks(stream);
2765 if (!tg->funcs->validate_timing(tg, &stream->timing))
2766 res = DC_FAIL_CONTROLLER_VALIDATE;
2769 if (!link->link_enc->funcs->validate_output_with_stream(
2770 link->link_enc, stream))
2771 res = DC_FAIL_ENC_VALIDATE;
2774 /* TODO: validate audio ASIC caps, encoder */
2777 res = dc_link_validate_mode_timing(stream,
2784 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
2786 enum dc_status res = DC_OK;
2788 /* TODO For now validates pixel format only */
2789 if (dc->res_pool->funcs->validate_plane)
2790 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
2795 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2798 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2800 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2801 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2803 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2804 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2805 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2806 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2808 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2809 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2810 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2811 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2812 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2814 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2815 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2816 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2819 ASSERT_CRITICAL(false);