drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17 #include "inc/link_enc_cfg.h"
  18
  19 /*Travis*/
  20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  21 /*Nutmeg*/
  22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  23
  24 #define DC_LOGGER \
  25         link->ctx->logger
  26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  27
  28         /* maximum pre emphasis level allowed for each voltage swing level*/
  29         static const enum dc_pre_emphasis
  30         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  31                                             PRE_EMPHASIS_LEVEL2,
  32                                             PRE_EMPHASIS_LEVEL1,
  33                                             PRE_EMPHASIS_DISABLED };
  34
  35 enum {
  36         POST_LT_ADJ_REQ_LIMIT = 6,
  37         POST_LT_ADJ_REQ_TIMEOUT = 200
  38 };
  39
  40 static bool decide_fallback_link_setting(
  41                 struct dc_link_settings initial_link_settings,
  42                 struct dc_link_settings *current_link_setting,
  43                 enum link_training_result training_result);
  44 static struct dc_link_settings get_common_supported_link_settings(
  45                 struct dc_link_settings link_setting_a,
  46                 struct dc_link_settings link_setting_b);
  47
  48 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  49                 const struct dc_link_settings *link_settings)
  50 {
  51         union training_aux_rd_interval training_rd_interval;
  52         uint32_t wait_in_micro_secs = 100;
  53
  54         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  55         core_link_read_dpcd(
  56                         link,
  57                         DP_TRAINING_AUX_RD_INTERVAL,
  58                         (uint8_t *)&training_rd_interval,
  59                         sizeof(training_rd_interval));
  60         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  61                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  62         return wait_in_micro_secs;
  63 }
  64
  65 static uint32_t get_eq_training_aux_rd_interval(
  66         struct dc_link *link,
  67         const struct dc_link_settings *link_settings)
  68 {
  69         union training_aux_rd_interval training_rd_interval;
  70         uint32_t wait_in_micro_secs = 400;
  71
  72         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  73         /* overwrite the delay if rev > 1.1*/
  74         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  75                 /* DP 1.2 or later - retrieve delay through
  76                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  77                 core_link_read_dpcd(
  78                         link,
  79                         DP_TRAINING_AUX_RD_INTERVAL,
  80                         (uint8_t *)&training_rd_interval,
  81                         sizeof(training_rd_interval));
  82
  83                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  84                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  85         }
  86
  87         return wait_in_micro_secs;
  88 }
  89
  90 void dp_wait_for_training_aux_rd_interval(
  91         struct dc_link *link,
  92         uint32_t wait_in_micro_secs)
  93 {
  94         udelay(wait_in_micro_secs);
  95
  96         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  97                 __func__,
  98                 wait_in_micro_secs);
  99 }
 100
 101 enum dpcd_training_patterns
 102         dc_dp_training_pattern_to_dpcd_training_pattern(
 103         struct dc_link *link,
 104         enum dc_dp_training_pattern pattern)
 105 {
 106         enum dpcd_training_patterns dpcd_tr_pattern =
 107         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 108
 109         switch (pattern) {
 110         case DP_TRAINING_PATTERN_SEQUENCE_1:
 111                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 112                 break;
 113         case DP_TRAINING_PATTERN_SEQUENCE_2:
 114                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 115                 break;
 116         case DP_TRAINING_PATTERN_SEQUENCE_3:
 117                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 118                 break;
 119         case DP_TRAINING_PATTERN_SEQUENCE_4:
 120                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 121                 break;
 122         case DP_TRAINING_PATTERN_VIDEOIDLE:
 123                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 124                 break;
 125         default:
 126                 ASSERT(0);
 127                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 128                         __func__, pattern);
 129                 break;
 130         }
 131
 132         return dpcd_tr_pattern;
 133 }
 134
 135 static void dpcd_set_training_pattern(
 136         struct dc_link *link,
 137         enum dc_dp_training_pattern training_pattern)
 138 {
 139         union dpcd_training_pattern dpcd_pattern = { {0} };
 140
 141         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 142                         dc_dp_training_pattern_to_dpcd_training_pattern(
 143                                         link, training_pattern);
 144
 145         core_link_write_dpcd(
 146                 link,
 147                 DP_TRAINING_PATTERN_SET,
 148                 &dpcd_pattern.raw,
 149                 1);
 150
 151         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 152                 __func__,
 153                 DP_TRAINING_PATTERN_SET,
 154                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 155 }
 156
 157 static enum dc_dp_training_pattern decide_cr_training_pattern(
 158                 const struct dc_link_settings *link_settings)
 159 {
 160         return DP_TRAINING_PATTERN_SEQUENCE_1;
 161 }
 162
 163 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 164                 const struct dc_link_settings *link_settings)
 165 {
 166         struct link_encoder *link_enc;
 167         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 168         struct encoder_feature_support *features;
 169         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 170
 171         /* Access link encoder capability based on whether it is statically
 172          * or dynamically assigned to a link.
 173          */
 174         if (link->is_dig_mapping_flexible &&
 175                         link->dc->res_pool->funcs->link_encs_assign)
 176                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 177         else
 178                 link_enc = link->link_enc;
 179         ASSERT(link_enc);
 180         features = &link_enc->features;
 181
 182         if (features->flags.bits.IS_TPS3_CAPABLE)
 183                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 184
 185         if (features->flags.bits.IS_TPS4_CAPABLE)
 186                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 187
 188         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 189                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 190                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 191
 192         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 193                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 194                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 195
 196         return DP_TRAINING_PATTERN_SEQUENCE_2;
 197 }
 198
 199 enum dc_status dpcd_set_link_settings(
 200         struct dc_link *link,
 201         const struct link_training_settings *lt_settings)
 202 {
 203         uint8_t rate;
 204         enum dc_status status;
 205
 206         union down_spread_ctrl downspread = { {0} };
 207         union lane_count_set lane_count_set = { {0} };
 208
 209         downspread.raw = (uint8_t)
 210         (lt_settings->link_settings.link_spread);
 211
 212         lane_count_set.bits.LANE_COUNT_SET =
 213         lt_settings->link_settings.lane_count;
 214
 215         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 216         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 217
 218
 219         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 220                         lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 221                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 222                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 223         }
 224
 225         status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 226                 &downspread.raw, sizeof(downspread));
 227
 228         status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 229                 &lane_count_set.raw, 1);
 230
 231         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 232                         lt_settings->link_settings.use_link_rate_set == true) {
 233                 rate = 0;
 234                 /* WA for some MUX chips that will power down with eDP and lose supported
 235                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 236                  * MUX chip gets link rate set back before link training.
 237                  */
 238                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 239                         uint8_t supported_link_rates[16];
 240
 241                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 242                                         supported_link_rates, sizeof(supported_link_rates));
 243                 }
 244                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 245                 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
 246                                 &lt_settings->link_settings.link_rate_set, 1);
 247         } else {
 248                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 249                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 250         }
 251
 252         if (rate) {
 253                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 254                         __func__,
 255                         DP_LINK_BW_SET,
 256                         lt_settings->link_settings.link_rate,
 257                         DP_LANE_COUNT_SET,
 258                         lt_settings->link_settings.lane_count,
 259                         lt_settings->enhanced_framing,
 260                         DP_DOWNSPREAD_CTRL,
 261                         lt_settings->link_settings.link_spread);
 262         } else {
 263                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 264                         __func__,
 265                         DP_LINK_RATE_SET,
 266                         lt_settings->link_settings.link_rate_set,
 267                         DP_LANE_COUNT_SET,
 268                         lt_settings->link_settings.lane_count,
 269                         lt_settings->enhanced_framing,
 270                         DP_DOWNSPREAD_CTRL,
 271                         lt_settings->link_settings.link_spread);
 272         }
 273
 274         return status;
 275 }
 276
 277 uint8_t dc_dp_initialize_scrambling_data_symbols(
 278         struct dc_link *link,
 279         enum dc_dp_training_pattern pattern)
 280 {
 281         uint8_t disable_scrabled_data_symbols = 0;
 282
 283         switch (pattern) {
 284         case DP_TRAINING_PATTERN_SEQUENCE_1:
 285         case DP_TRAINING_PATTERN_SEQUENCE_2:
 286         case DP_TRAINING_PATTERN_SEQUENCE_3:
 287                 disable_scrabled_data_symbols = 1;
 288                 break;
 289         case DP_TRAINING_PATTERN_SEQUENCE_4:
 290                 disable_scrabled_data_symbols = 0;
 291                 break;
 292         default:
 293                 ASSERT(0);
 294                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 295                         __func__, pattern);
 296                 break;
 297         }
 298         return disable_scrabled_data_symbols;
 299 }
 300
 301 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 302 {
 303         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 304 }
 305
 306 static void dpcd_set_lt_pattern_and_lane_settings(
 307         struct dc_link *link,
 308         const struct link_training_settings *lt_settings,
 309         enum dc_dp_training_pattern pattern,
 310         uint32_t offset)
 311 {
 312         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 313
 314         uint32_t dpcd_base_lt_offset;
 315
 316         uint8_t dpcd_lt_buffer[5] = {0};
 317         union dpcd_training_pattern dpcd_pattern = { {0} };
 318         uint32_t lane;
 319         uint32_t size_in_bytes;
 320         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 321         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 322
 323         if (is_repeater(link, offset))
 324                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 325                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 326
 327         /*****************************************************************
 328         * DpcdAddress_TrainingPatternSet
 329         *****************************************************************/
 330         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 331                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 332
 333         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 334                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 335
 336         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 337                 = dpcd_pattern.raw;
 338
 339         if (is_repeater(link, offset)) {
 340                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 341                         __func__,
 342                         offset,
 343                         dpcd_base_lt_offset,
 344                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 345         } else {
 346                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 347                         __func__,
 348                         dpcd_base_lt_offset,
 349                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 350         }
 351         /*****************************************************************
 352         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 353         *****************************************************************/
 354         for (lane = 0; lane <
 355                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 356
 357                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 358                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 359                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 360                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 361
 362                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 363                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 364                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 365                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 366                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 367                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 368         }
 369
 370         /* concatenate everything into one buffer*/
 371
 372         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 373
 374          // 0x00103 - 0x00102
 375         memmove(
 376                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 377                 dpcd_lane,
 378                 size_in_bytes);
 379
 380         if (is_repeater(link, offset)) {
 381                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 382                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 383                         __func__,
 384                         offset,
 385                         dpcd_base_lt_offset,
 386                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 387                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 388                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 389                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 390         } else {
 391                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 392                         __func__,
 393                         dpcd_base_lt_offset,
 394                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 395                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 396                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 397                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 398         }
 399         if (edp_workaround) {
 400                 /* for eDP write in 2 parts because the 5-byte burst is
 401                 * causing issues on some eDP panels (EPR#366724)
 402                 */
 403                 core_link_write_dpcd(
 404                         link,
 405                         DP_TRAINING_PATTERN_SET,
 406                         &dpcd_pattern.raw,
 407                         sizeof(dpcd_pattern.raw));
 408
 409                 core_link_write_dpcd(
 410                         link,
 411                         DP_TRAINING_LANE0_SET,
 412                         (uint8_t *)(dpcd_lane),
 413                         size_in_bytes);
 414
 415                 } else
 416                 /* write it all in (1 + number-of-lanes)-byte burst*/
 417                         core_link_write_dpcd(
 418                                 link,
 419                                 dpcd_base_lt_offset,
 420                                 dpcd_lt_buffer,
 421                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 422
 423         link->cur_lane_setting = lt_settings->lane_settings[0];
 424 }
 425
 426 bool dp_is_cr_done(enum dc_lane_count ln_count,
 427         union lane_status *dpcd_lane_status)
 428 {
 429         uint32_t lane;
 430         /*LANEx_CR_DONE bits All 1's?*/
 431         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 432                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 433                         return false;
 434         }
 435         return true;
 436 }
 437
 438 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
 439                 union lane_status *dpcd_lane_status)
 440 {
 441         bool done = true;
 442         uint32_t lane;
 443         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 444                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 445                         done = false;
 446         return done;
 447 }
 448
 449 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
 450                 union lane_status *dpcd_lane_status)
 451 {
 452         bool locked = true;
 453         uint32_t lane;
 454         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 455                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 456                         locked = false;
 457         return locked;
 458 }
 459
 460 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 461 {
 462         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 463 }
 464
 465 void dp_update_drive_settings(
 466                 struct link_training_settings *dest,
 467                 struct link_training_settings src)
 468 {
 469         uint32_t lane;
 470         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 471                 if (dest->voltage_swing == NULL)
 472                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 473                 else
 474                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 475
 476                 if (dest->pre_emphasis == NULL)
 477                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 478                 else
 479                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 480
 481                 if (dest->post_cursor2 == NULL)
 482                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 483                 else
 484                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 485         }
 486 }
 487
 488 static uint8_t get_nibble_at_index(const uint8_t *buf,
 489         uint32_t index)
 490 {
 491         uint8_t nibble;
 492         nibble = buf[index / 2];
 493
 494         if (index % 2)
 495                 nibble >>= 4;
 496         else
 497                 nibble &= 0x0F;
 498
 499         return nibble;
 500 }
 501
 502 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 503         enum dc_voltage_swing voltage)
 504 {
 505         enum dc_pre_emphasis pre_emphasis;
 506         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 507
 508         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 509                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 510
 511         return pre_emphasis;
 512
 513 }
 514
 515 static void find_max_drive_settings(
 516         const struct link_training_settings *link_training_setting,
 517         struct link_training_settings *max_lt_setting)
 518 {
 519         uint32_t lane;
 520         struct dc_lane_settings max_requested;
 521
 522         max_requested.VOLTAGE_SWING =
 523                 link_training_setting->
 524                 lane_settings[0].VOLTAGE_SWING;
 525         max_requested.PRE_EMPHASIS =
 526                 link_training_setting->
 527                 lane_settings[0].PRE_EMPHASIS;
 528         /*max_requested.postCursor2 =
 529          * link_training_setting->laneSettings[0].postCursor2;*/
 530
 531         /* Determine what the maximum of the requested settings are*/
 532         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 533                         lane++) {
 534                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 535                         max_requested.VOLTAGE_SWING)
 536
 537                         max_requested.VOLTAGE_SWING =
 538                         link_training_setting->
 539                         lane_settings[lane].VOLTAGE_SWING;
 540
 541                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 542                                 max_requested.PRE_EMPHASIS)
 543                         max_requested.PRE_EMPHASIS =
 544                         link_training_setting->
 545                         lane_settings[lane].PRE_EMPHASIS;
 546
 547                 /*
 548                 if (link_training_setting->laneSettings[lane].postCursor2 >
 549                  max_requested.postCursor2)
 550                 {
 551                 max_requested.postCursor2 =
 552                 link_training_setting->laneSettings[lane].postCursor2;
 553                 }
 554                 */
 555         }
 556
 557         /* make sure the requested settings are
 558          * not higher than maximum settings*/
 559         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 560                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 561
 562         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 563                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 564         /*
 565         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 566         max_requested.postCursor2 = PostCursor2_MaxLevel;
 567         */
 568
 569         /* make sure the pre-emphasis matches the voltage swing*/
 570         if (max_requested.PRE_EMPHASIS >
 571                 get_max_pre_emphasis_for_voltage_swing(
 572                         max_requested.VOLTAGE_SWING))
 573                 max_requested.PRE_EMPHASIS =
 574                 get_max_pre_emphasis_for_voltage_swing(
 575                         max_requested.VOLTAGE_SWING);
 576
 577         /*
 578          * Post Cursor2 levels are completely independent from
 579          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 580          * can only be applied to each allowable combination of voltage
 581          * swing and pre-emphasis levels */
 582          /* if ( max_requested.postCursor2 >
 583           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 584           *  max_requested.postCursor2 =
 585           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 586           */
 587
 588         max_lt_setting->link_settings.link_rate =
 589                 link_training_setting->link_settings.link_rate;
 590         max_lt_setting->link_settings.lane_count =
 591         link_training_setting->link_settings.lane_count;
 592         max_lt_setting->link_settings.link_spread =
 593                 link_training_setting->link_settings.link_spread;
 594
 595         for (lane = 0; lane <
 596                 link_training_setting->link_settings.lane_count;
 597                 lane++) {
 598                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 599                         max_requested.VOLTAGE_SWING;
 600                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 601                         max_requested.PRE_EMPHASIS;
 602                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 603                  * max_requested.postCursor2;
 604                  */
 605         }
 606
 607 }
 608
 609 enum dc_status dp_get_lane_status_and_drive_settings(
 610         struct dc_link *link,
 611         const struct link_training_settings *link_training_setting,
 612         union lane_status *ln_status,
 613         union lane_align_status_updated *ln_status_updated,
 614         struct link_training_settings *req_settings,
 615         uint32_t offset)
 616 {
 617         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 618         uint8_t lane_adjust_offset = 4;
 619         unsigned int lane01_adjust_address;
 620         uint8_t dpcd_buf[6] = {0};
 621         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 622         struct link_training_settings request_settings = { {0} };
 623         uint32_t lane;
 624         enum dc_status status;
 625
 626         memset(req_settings, '\0', sizeof(struct link_training_settings));
 627
 628         if (is_repeater(link, offset)) {
 629                 lane01_status_address =
 630                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 631                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 632                 lane_adjust_offset = 3;
 633         }
 634
 635         status = core_link_read_dpcd(
 636                 link,
 637                 lane01_status_address,
 638                 (uint8_t *)(dpcd_buf),
 639                 sizeof(dpcd_buf));
 640
 641         for (lane = 0; lane <
 642                 (uint32_t)(link_training_setting->link_settings.lane_count);
 643                 lane++) {
 644
 645                 ln_status[lane].raw =
 646                         get_nibble_at_index(&dpcd_buf[0], lane);
 647                 dpcd_lane_adjust[lane].raw =
 648                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 649         }
 650
 651         ln_status_updated->raw = dpcd_buf[2];
 652
 653         if (is_repeater(link, offset)) {
 654                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 655                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 656                         __func__,
 657                         offset,
 658                         lane01_status_address, dpcd_buf[0],
 659                         lane01_status_address + 1, dpcd_buf[1]);
 660         } else {
 661                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 662                         __func__,
 663                         lane01_status_address, dpcd_buf[0],
 664                         lane01_status_address + 1, dpcd_buf[1]);
 665         }
 666         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 667
 668         if (is_repeater(link, offset))
 669                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 670                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 671
 672         if (is_repeater(link, offset)) {
 673                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 674                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 675                                         __func__,
 676                                         offset,
 677                                         lane01_adjust_address,
 678                                         dpcd_buf[lane_adjust_offset],
 679                                         lane01_adjust_address + 1,
 680                                         dpcd_buf[lane_adjust_offset + 1]);
 681         } else {
 682                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 683                         __func__,
 684                         lane01_adjust_address,
 685                         dpcd_buf[lane_adjust_offset],
 686                         lane01_adjust_address + 1,
 687                         dpcd_buf[lane_adjust_offset + 1]);
 688         }
 689
 690         /*copy to req_settings*/
 691         request_settings.link_settings.lane_count =
 692                 link_training_setting->link_settings.lane_count;
 693         request_settings.link_settings.link_rate =
 694                 link_training_setting->link_settings.link_rate;
 695         request_settings.link_settings.link_spread =
 696                 link_training_setting->link_settings.link_spread;
 697
 698         for (lane = 0; lane <
 699                 (uint32_t)(link_training_setting->link_settings.lane_count);
 700                 lane++) {
 701
 702                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 703                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 704                                 VOLTAGE_SWING_LANE);
 705                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 706                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 707                                 PRE_EMPHASIS_LANE);
 708         }
 709
 710         /*Note: for postcursor2, read adjusted
 711          * postcursor2 settings from*/
 712         /*DpcdAddress_AdjustRequestPostCursor2 =
 713          *0x020C (not implemented yet)*/
 714
 715         /* we find the maximum of the requested settings across all lanes*/
 716         /* and set this maximum for all lanes*/
 717         find_max_drive_settings(&request_settings, req_settings);
 718
 719         /* if post cursor 2 is needed in the future,
 720          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 721          */
 722
 723         return status;
 724 }
 725
 726 enum dc_status dpcd_set_lane_settings(
 727         struct dc_link *link,
 728         const struct link_training_settings *link_training_setting,
 729         uint32_t offset)
 730 {
 731         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 732         uint32_t lane;
 733         unsigned int lane0_set_address;
 734         enum dc_status status;
 735
 736         lane0_set_address = DP_TRAINING_LANE0_SET;
 737
 738         if (is_repeater(link, offset))
 739                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 740                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 741
 742         for (lane = 0; lane <
 743                 (uint32_t)(link_training_setting->
 744                 link_settings.lane_count);
 745                 lane++) {
 746                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 747                         (uint8_t)(link_training_setting->
 748                         lane_settings[lane].VOLTAGE_SWING);
 749                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 750                         (uint8_t)(link_training_setting->
 751                         lane_settings[lane].PRE_EMPHASIS);
 752                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 753                         (link_training_setting->
 754                         lane_settings[lane].VOLTAGE_SWING ==
 755                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 756                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 757                         (link_training_setting->
 758                         lane_settings[lane].PRE_EMPHASIS ==
 759                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 760         }
 761
 762         status = core_link_write_dpcd(link,
 763                 lane0_set_address,
 764                 (uint8_t *)(dpcd_lane),
 765                 link_training_setting->link_settings.lane_count);
 766
 767         /*
 768         if (LTSettings.link.rate == LinkRate_High2)
 769         {
 770                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 771                 for ( uint32_t lane = 0;
 772                 lane < lane_count_DPMax; lane++)
 773                 {
 774                         dpcd_lane2[lane].bits.post_cursor2_set =
 775                         static_cast<unsigned char>(
 776                         LTSettings.laneSettings[lane].postCursor2);
 777                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 778                 }
 779                 m_pDpcdAccessSrv->WriteDpcdData(
 780                 DpcdAddress_Lane0Set2,
 781                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 782                 LTSettings.link.lanes);
 783         }
 784         */
 785
 786         if (is_repeater(link, offset)) {
 787                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 788                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 789                         __func__,
 790                         offset,
 791                         lane0_set_address,
 792                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 793                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 794                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 795                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 796
 797         } else {
 798                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 799                         __func__,
 800                         lane0_set_address,
 801                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 802                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 803                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 804                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 805         }
 806         link->cur_lane_setting = link_training_setting->lane_settings[0];
 807
 808         return status;
 809 }
 810
 811 bool dp_is_max_vs_reached(
 812         const struct link_training_settings *lt_settings)
 813 {
 814         uint32_t lane;
 815         for (lane = 0; lane <
 816                 (uint32_t)(lt_settings->link_settings.lane_count);
 817                 lane++) {
 818                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 819                         == VOLTAGE_SWING_MAX_LEVEL)
 820                         return true;
 821         }
 822         return false;
 823
 824 }
 825
 826 static bool perform_post_lt_adj_req_sequence(
 827         struct dc_link *link,
 828         struct link_training_settings *lt_settings)
 829 {
 830         enum dc_lane_count lane_count =
 831         lt_settings->link_settings.lane_count;
 832
 833         uint32_t adj_req_count;
 834         uint32_t adj_req_timer;
 835         bool req_drv_setting_changed;
 836         uint32_t lane;
 837
 838         req_drv_setting_changed = false;
 839         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 840         adj_req_count++) {
 841
 842                 req_drv_setting_changed = false;
 843
 844                 for (adj_req_timer = 0;
 845                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 846                         adj_req_timer++) {
 847
 848                         struct link_training_settings req_settings;
 849                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 850                         union lane_align_status_updated
 851                                 dpcd_lane_status_updated;
 852
 853                         dp_get_lane_status_and_drive_settings(
 854                                 link,
 855                                 lt_settings,
 856                                 dpcd_lane_status,
 857                                 &dpcd_lane_status_updated,
 858                                 &req_settings,
 859                                 DPRX);
 860
 861                         if (dpcd_lane_status_updated.bits.
 862                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 863                                 return true;
 864
 865                         if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 866                                 return false;
 867
 868                         if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
 869                                         !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
 870                                         !dp_is_interlane_aligned(dpcd_lane_status_updated))
 871                                 return false;
 872
 873                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 874
 875                                 if (lt_settings->
 876                                 lane_settings[lane].VOLTAGE_SWING !=
 877                                 req_settings.lane_settings[lane].
 878                                 VOLTAGE_SWING ||
 879                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 880                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 881
 882                                         req_drv_setting_changed = true;
 883                                         break;
 884                                 }
 885                         }
 886
 887                         if (req_drv_setting_changed) {
 888                                 dp_update_drive_settings(
 889                                         lt_settings, req_settings);
 890
 891                                 dc_link_dp_set_drive_settings(link,
 892                                                 lt_settings);
 893                                 break;
 894                         }
 895
 896                         msleep(1);
 897                 }
 898
 899                 if (!req_drv_setting_changed) {
 900                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 901                                 __func__);
 902
 903                         ASSERT(0);
 904                         return true;
 905                 }
 906         }
 907         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 908                 __func__);
 909
 910         ASSERT(0);
 911         return true;
 912
 913 }
 914
 915 /* Only used for channel equalization */
 916 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 917 {
 918         unsigned int aux_rd_interval_us = 400;
 919
 920         switch (dpcd_aux_read_interval) {
 921         case 0x01:
 922                 aux_rd_interval_us = 4000;
 923                 break;
 924         case 0x02:
 925                 aux_rd_interval_us = 8000;
 926                 break;
 927         case 0x03:
 928                 aux_rd_interval_us = 12000;
 929                 break;
 930         case 0x04:
 931                 aux_rd_interval_us = 16000;
 932                 break;
 933         default:
 934                 break;
 935         }
 936
 937         return aux_rd_interval_us;
 938 }
 939
 940 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
 941                                         union lane_status *dpcd_lane_status)
 942 {
 943         enum link_training_result result = LINK_TRAINING_SUCCESS;
 944
 945         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 946                 result = LINK_TRAINING_CR_FAIL_LANE0;
 947         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 948                 result = LINK_TRAINING_CR_FAIL_LANE1;
 949         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 950                 result = LINK_TRAINING_CR_FAIL_LANE23;
 951         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 952                 result = LINK_TRAINING_CR_FAIL_LANE23;
 953         return result;
 954 }
 955
 956 static enum link_training_result perform_channel_equalization_sequence(
 957         struct dc_link *link,
 958         struct link_training_settings *lt_settings,
 959         uint32_t offset)
 960 {
 961         struct link_training_settings req_settings;
 962         enum dc_dp_training_pattern tr_pattern;
 963         uint32_t retries_ch_eq;
 964         uint32_t wait_time_microsec;
 965         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 966         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 967         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 968
 969         /* Note: also check that TPS4 is a supported feature*/
 970
 971         tr_pattern = lt_settings->pattern_for_eq;
 972
 973         if (is_repeater(link, offset))
 974                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 975
 976         dp_set_hw_training_pattern(link, tr_pattern, offset);
 977
 978         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 979                 retries_ch_eq++) {
 980
 981                 dp_set_hw_lane_settings(link, lt_settings, offset);
 982
 983                 /* 2. update DPCD*/
 984                 if (!retries_ch_eq)
 985                         /* EPR #361076 - write as a 5-byte burst,
 986                          * but only for the 1-st iteration
 987                          */
 988
 989                         dpcd_set_lt_pattern_and_lane_settings(
 990                                 link,
 991                                 lt_settings,
 992                                 tr_pattern, offset);
 993                 else
 994                         dpcd_set_lane_settings(link, lt_settings, offset);
 995
 996                 /* 3. wait for receiver to lock-on*/
 997                 wait_time_microsec = lt_settings->eq_pattern_time;
 998
 999                 if (is_repeater(link, offset))
1000                         wait_time_microsec =
1001                                         dp_translate_training_aux_read_interval(
1002                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1003
1004                 dp_wait_for_training_aux_rd_interval(
1005                                 link,
1006                                 wait_time_microsec);
1007
1008                 /* 4. Read lane status and requested
1009                  * drive settings as set by the sink*/
1010
1011                 dp_get_lane_status_and_drive_settings(
1012                         link,
1013                         lt_settings,
1014                         dpcd_lane_status,
1015                         &dpcd_lane_status_updated,
1016                         &req_settings,
1017                         offset);
1018
1019                 /* 5. check CR done*/
1020                 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1021                         return LINK_TRAINING_EQ_FAIL_CR;
1022
1023                 /* 6. check CHEQ done*/
1024                 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1025                                 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1026                                 dp_is_interlane_aligned(dpcd_lane_status_updated))
1027                         return LINK_TRAINING_SUCCESS;
1028
1029                 /* 7. update VS/PE/PC2 in lt_settings*/
1030                 dp_update_drive_settings(lt_settings, req_settings);
1031         }
1032
1033         return LINK_TRAINING_EQ_FAIL_EQ;
1034
1035 }
1036
1037 static void start_clock_recovery_pattern_early(struct dc_link *link,
1038                 struct link_training_settings *lt_settings,
1039                 uint32_t offset)
1040 {
1041         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1042                         __func__);
1043         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1044         dp_set_hw_lane_settings(link, lt_settings, offset);
1045         udelay(400);
1046 }
1047
1048 static enum link_training_result perform_clock_recovery_sequence(
1049         struct dc_link *link,
1050         struct link_training_settings *lt_settings,
1051         uint32_t offset)
1052 {
1053         uint32_t retries_cr;
1054         uint32_t retry_count;
1055         uint32_t wait_time_microsec;
1056         struct link_training_settings req_settings;
1057         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1058         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1059         union lane_align_status_updated dpcd_lane_status_updated;
1060
1061         retries_cr = 0;
1062         retry_count = 0;
1063
1064         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1065                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1066
1067         /* najeeb - The synaptics MST hub can put the LT in
1068         * infinite loop by switching the VS
1069         */
1070         /* between level 0 and level 1 continuously, here
1071         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1072         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1073                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1074
1075                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1076                 memset(&dpcd_lane_status_updated, '\0',
1077                 sizeof(dpcd_lane_status_updated));
1078
1079                 /* 1. call HWSS to set lane settings*/
1080                 dp_set_hw_lane_settings(
1081                                 link,
1082                                 lt_settings,
1083                                 offset);
1084
1085                 /* 2. update DPCD of the receiver*/
1086                 if (!retry_count)
1087                         /* EPR #361076 - write as a 5-byte burst,
1088                          * but only for the 1-st iteration.*/
1089                         dpcd_set_lt_pattern_and_lane_settings(
1090                                         link,
1091                                         lt_settings,
1092                                         lt_settings->pattern_for_cr,
1093                                         offset);
1094                 else
1095                         dpcd_set_lane_settings(
1096                                         link,
1097                                         lt_settings,
1098                                         offset);
1099
1100                 /* 3. wait receiver to lock-on*/
1101                 wait_time_microsec = lt_settings->cr_pattern_time;
1102
1103                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1104                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1105
1106                 dp_wait_for_training_aux_rd_interval(
1107                                 link,
1108                                 wait_time_microsec);
1109
1110                 /* 4. Read lane status and requested drive
1111                 * settings as set by the sink
1112                 */
1113                 dp_get_lane_status_and_drive_settings(
1114                                 link,
1115                                 lt_settings,
1116                                 dpcd_lane_status,
1117                                 &dpcd_lane_status_updated,
1118                                 &req_settings,
1119                                 offset);
1120
1121                 /* 5. check CR done*/
1122                 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1123                         return LINK_TRAINING_SUCCESS;
1124
1125                 /* 6. max VS reached*/
1126                 if (dp_is_max_vs_reached(lt_settings))
1127                         break;
1128
1129                 /* 7. same lane settings*/
1130                 /* Note: settings are the same for all lanes,
1131                  * so comparing first lane is sufficient*/
1132                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1133                         req_settings.lane_settings[0].VOLTAGE_SWING)
1134                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1135                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1136                         retries_cr++;
1137                 else
1138                         retries_cr = 0;
1139
1140                 /* 8. update VS/PE/PC2 in lt_settings*/
1141                 dp_update_drive_settings(lt_settings, req_settings);
1142
1143                 retry_count++;
1144         }
1145
1146         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1147                 ASSERT(0);
1148                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1149                         __func__,
1150                         LINK_TRAINING_MAX_CR_RETRY);
1151
1152         }
1153
1154         return dp_get_cr_failure(lane_count, dpcd_lane_status);
1155 }
1156
1157 static inline enum link_training_result dp_transition_to_video_idle(
1158         struct dc_link *link,
1159         struct link_training_settings *lt_settings,
1160         enum link_training_result status)
1161 {
1162         union lane_count_set lane_count_set = { {0} };
1163
1164         /* 4. mainlink output idle pattern*/
1165         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1166
1167         /*
1168          * 5. post training adjust if required
1169          * If the upstream DPTX and downstream DPRX both support TPS4,
1170          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1171          */
1172         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1173                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1174                 /* delay 5ms after Main Link output idle pattern and then check
1175                  * DPCD 0202h.
1176                  */
1177                 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1178                         msleep(5);
1179                         status = dp_check_link_loss_status(link, lt_settings);
1180                 }
1181                 return status;
1182         }
1183
1184         if (status == LINK_TRAINING_SUCCESS &&
1185                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1186                 status = LINK_TRAINING_LQA_FAIL;
1187
1188         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1189         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1190         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1191
1192         core_link_write_dpcd(
1193                 link,
1194                 DP_LANE_COUNT_SET,
1195                 &lane_count_set.raw,
1196                 sizeof(lane_count_set));
1197
1198         return status;
1199 }
1200
1201 enum link_training_result dp_check_link_loss_status(
1202         struct dc_link *link,
1203         const struct link_training_settings *link_training_setting)
1204 {
1205         enum link_training_result status = LINK_TRAINING_SUCCESS;
1206         union lane_status lane_status;
1207         uint8_t dpcd_buf[6] = {0};
1208         uint32_t lane;
1209
1210         core_link_read_dpcd(
1211                         link,
1212                         DP_SINK_COUNT,
1213                         (uint8_t *)(dpcd_buf),
1214                         sizeof(dpcd_buf));
1215
1216         /*parse lane status*/
1217         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1218                 /*
1219                  * check lanes status
1220                  */
1221                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1222
1223                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1224                         !lane_status.bits.CR_DONE_0 ||
1225                         !lane_status.bits.SYMBOL_LOCKED_0) {
1226                         /* if one of the channel equalization, clock
1227                          * recovery or symbol lock is dropped
1228                          * consider it as (link has been
1229                          * dropped) dp sink status has changed
1230                          */
1231                         status = LINK_TRAINING_LINK_LOSS;
1232                         break;
1233                 }
1234         }
1235
1236         return status;
1237 }
1238
1239 static inline void decide_8b_10b_training_settings(
1240          struct dc_link *link,
1241         const struct dc_link_settings *link_setting,
1242         const struct dc_link_training_overrides *overrides,
1243         struct link_training_settings *lt_settings)
1244 {
1245         uint32_t lane;
1246
1247         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1248
1249         /* Initialize link settings */
1250         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1251         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1252
1253         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1254                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1255         else
1256                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1257
1258         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1259                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1260         else
1261                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1262
1263         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1264
1265         /* TODO hard coded to SS for now
1266          * lt_settings.link_settings.link_spread =
1267          * dal_display_path_is_ss_supported(
1268          * path_mode->display_path) ?
1269          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1270          * LINK_SPREAD_DISABLED;
1271          */
1272         /* Initialize link spread */
1273         if (link->dp_ss_off)
1274                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1275         else if (overrides->downspread != NULL)
1276                 lt_settings->link_settings.link_spread
1277                         = *overrides->downspread
1278                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1279                         : LINK_SPREAD_DISABLED;
1280         else
1281                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1282
1283         lt_settings->lttpr_mode = link->lttpr_mode;
1284
1285         /* Initialize lane settings overrides */
1286         if (overrides->voltage_swing != NULL)
1287                 lt_settings->voltage_swing = overrides->voltage_swing;
1288
1289         if (overrides->pre_emphasis != NULL)
1290                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1291
1292         if (overrides->post_cursor2 != NULL)
1293                 lt_settings->post_cursor2 = overrides->post_cursor2;
1294
1295         /* Initialize lane settings (VS/PE/PC2) */
1296         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1297                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1298                         lt_settings->voltage_swing != NULL ?
1299                         *lt_settings->voltage_swing :
1300                         VOLTAGE_SWING_LEVEL0;
1301                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1302                         lt_settings->pre_emphasis != NULL ?
1303                         *lt_settings->pre_emphasis
1304                         : PRE_EMPHASIS_DISABLED;
1305                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1306                         lt_settings->post_cursor2 != NULL ?
1307                         *lt_settings->post_cursor2
1308                         : POST_CURSOR2_DISABLED;
1309         }
1310
1311         /* Initialize training timings */
1312         if (overrides->cr_pattern_time != NULL)
1313                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1314         else
1315                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1316
1317         if (overrides->eq_pattern_time != NULL)
1318                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1319         else
1320                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1321
1322         if (overrides->pattern_for_cr != NULL)
1323                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1324         else
1325                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1326         if (overrides->pattern_for_eq != NULL)
1327                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1328         else
1329                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1330
1331         if (overrides->enhanced_framing != NULL)
1332                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1333         else
1334                 lt_settings->enhanced_framing = 1;
1335
1336         if (link->preferred_training_settings.fec_enable != NULL)
1337                 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1338         else
1339                 lt_settings->should_set_fec_ready = true;
1340 }
1341
1342 void dp_decide_training_settings(
1343                 struct dc_link *link,
1344                 const struct dc_link_settings *link_settings,
1345                 const struct dc_link_training_overrides *overrides,
1346                 struct link_training_settings *lt_settings)
1347 {
1348         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1349                 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1350 }
1351
1352
1353 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1354 {
1355         switch (lttpr_repeater_count) {
1356         case 0x80: // 1 lttpr repeater
1357                 return 1;
1358         case 0x40: // 2 lttpr repeaters
1359                 return 2;
1360         case 0x20: // 3 lttpr repeaters
1361                 return 3;
1362         case 0x10: // 4 lttpr repeaters
1363                 return 4;
1364         case 0x08: // 5 lttpr repeaters
1365                 return 5;
1366         case 0x04: // 6 lttpr repeaters
1367                 return 6;
1368         case 0x02: // 7 lttpr repeaters
1369                 return 7;
1370         case 0x01: // 8 lttpr repeaters
1371                 return 8;
1372         default:
1373                 break;
1374         }
1375         return 0; // invalid value
1376 }
1377
1378 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1379 {
1380         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1381
1382         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1383         return core_link_write_dpcd(link,
1384                         DP_PHY_REPEATER_MODE,
1385                         (uint8_t *)&repeater_mode,
1386                         sizeof(repeater_mode));
1387 }
1388
1389 enum dc_status configure_lttpr_mode_non_transparent(
1390                 struct dc_link *link,
1391                 const struct link_training_settings *lt_settings)
1392 {
1393         /* aux timeout is already set to extended */
1394         /* RESET/SET lttpr mode to enable non transparent mode */
1395         uint8_t repeater_cnt;
1396         uint32_t aux_interval_address;
1397         uint8_t repeater_id;
1398         enum dc_status result = DC_ERROR_UNEXPECTED;
1399         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1400
1401         enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1402
1403         if (encoding == DP_8b_10b_ENCODING) {
1404                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1405                 result = core_link_write_dpcd(link,
1406                                 DP_PHY_REPEATER_MODE,
1407                                 (uint8_t *)&repeater_mode,
1408                                 sizeof(repeater_mode));
1409
1410         }
1411
1412         if (result == DC_OK) {
1413                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1414         }
1415
1416         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1417
1418                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1419
1420                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1421                 result = core_link_write_dpcd(link,
1422                                 DP_PHY_REPEATER_MODE,
1423                                 (uint8_t *)&repeater_mode,
1424                                 sizeof(repeater_mode));
1425
1426                 if (result == DC_OK) {
1427                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1428                 }
1429
1430                 if (encoding == DP_8b_10b_ENCODING) {
1431                         repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1432                         for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1433                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1434                                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1435                                 core_link_read_dpcd(
1436                                         link,
1437                                         aux_interval_address,
1438                                         (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1439                                         sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1440                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1441                         }
1442                 }
1443         }
1444
1445         return result;
1446 }
1447
1448 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1449 {
1450         union dpcd_training_pattern dpcd_pattern = { {0} };
1451
1452         const uint32_t dpcd_base_lt_offset =
1453                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1454                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1455         /* Set training not in progress*/
1456         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1457
1458         core_link_write_dpcd(
1459                 link,
1460                 dpcd_base_lt_offset,
1461                 &dpcd_pattern.raw,
1462                 1);
1463
1464         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1465                 __func__,
1466                 offset,
1467                 dpcd_base_lt_offset,
1468                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1469 }
1470
1471 static void print_status_message(
1472         struct dc_link *link,
1473         const struct link_training_settings *lt_settings,
1474         enum link_training_result status)
1475 {
1476         char *link_rate = "Unknown";
1477         char *lt_result = "Unknown";
1478         char *lt_spread = "Disabled";
1479
1480         switch (lt_settings->link_settings.link_rate) {
1481         case LINK_RATE_LOW:
1482                 link_rate = "RBR";
1483                 break;
1484         case LINK_RATE_RATE_2:
1485                 link_rate = "R2";
1486                 break;
1487         case LINK_RATE_RATE_3:
1488                 link_rate = "R3";
1489                 break;
1490         case LINK_RATE_HIGH:
1491                 link_rate = "HBR";
1492                 break;
1493         case LINK_RATE_RBR2:
1494                 link_rate = "RBR2";
1495                 break;
1496         case LINK_RATE_RATE_6:
1497                 link_rate = "R6";
1498                 break;
1499         case LINK_RATE_HIGH2:
1500                 link_rate = "HBR2";
1501                 break;
1502         case LINK_RATE_HIGH3:
1503                 link_rate = "HBR3";
1504                 break;
1505         default:
1506                 break;
1507         }
1508
1509         switch (status) {
1510         case LINK_TRAINING_SUCCESS:
1511                 lt_result = "pass";
1512                 break;
1513         case LINK_TRAINING_CR_FAIL_LANE0:
1514                 lt_result = "CR failed lane0";
1515                 break;
1516         case LINK_TRAINING_CR_FAIL_LANE1:
1517                 lt_result = "CR failed lane1";
1518                 break;
1519         case LINK_TRAINING_CR_FAIL_LANE23:
1520                 lt_result = "CR failed lane23";
1521                 break;
1522         case LINK_TRAINING_EQ_FAIL_CR:
1523                 lt_result = "CR failed in EQ";
1524                 break;
1525         case LINK_TRAINING_EQ_FAIL_EQ:
1526                 lt_result = "EQ failed";
1527                 break;
1528         case LINK_TRAINING_LQA_FAIL:
1529                 lt_result = "LQA failed";
1530                 break;
1531         case LINK_TRAINING_LINK_LOSS:
1532                 lt_result = "Link loss";
1533                 break;
1534         default:
1535                 break;
1536         }
1537
1538         switch (lt_settings->link_settings.link_spread) {
1539         case LINK_SPREAD_DISABLED:
1540                 lt_spread = "Disabled";
1541                 break;
1542         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1543                 lt_spread = "0.5% 30KHz";
1544                 break;
1545         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1546                 lt_spread = "0.5% 33KHz";
1547                 break;
1548         default:
1549                 break;
1550         }
1551
1552         /* Connectivity log: link training */
1553         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1554                                 link_rate,
1555                                 lt_settings->link_settings.lane_count,
1556                                 lt_result,
1557                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1558                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1559                                 lt_spread);
1560 }
1561
1562 void dc_link_dp_set_drive_settings(
1563         struct dc_link *link,
1564         struct link_training_settings *lt_settings)
1565 {
1566         /* program ASIC PHY settings*/
1567         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1568
1569         /* Notify DP sink the PHY settings from source */
1570         dpcd_set_lane_settings(link, lt_settings, DPRX);
1571 }
1572
1573 bool dc_link_dp_perform_link_training_skip_aux(
1574         struct dc_link *link,
1575         const struct dc_link_settings *link_setting)
1576 {
1577         struct link_training_settings lt_settings;
1578
1579         dp_decide_training_settings(
1580                         link,
1581                         link_setting,
1582                         &link->preferred_training_settings,
1583                         &lt_settings);
1584
1585         /* 1. Perform_clock_recovery_sequence. */
1586
1587         /* transmit training pattern for clock recovery */
1588         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1589
1590         /* call HWSS to set lane settings*/
1591         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1592
1593         /* wait receiver to lock-on*/
1594         dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1595
1596         /* 2. Perform_channel_equalization_sequence. */
1597
1598         /* transmit training pattern for channel equalization. */
1599         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1600
1601         /* call HWSS to set lane settings*/
1602         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1603
1604         /* wait receiver to lock-on. */
1605         dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1606
1607         /* 3. Perform_link_training_int. */
1608
1609         /* Mainlink output idle pattern. */
1610         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1611
1612         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1613
1614         return true;
1615 }
1616
1617 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1618 {
1619         enum dc_status status = DC_OK;
1620
1621         if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1622                 status = configure_lttpr_mode_transparent(link);
1623
1624         else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1625                 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1626
1627         return status;
1628 }
1629
1630 static void dpcd_exit_training_mode(struct dc_link *link)
1631 {
1632
1633         /* clear training pattern set */
1634         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1635 }
1636
1637 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1638                 struct link_training_settings *lt_settings)
1639 {
1640         enum dp_link_encoding encoding =
1641                         dp_get_link_encoding_format(
1642                                         &lt_settings->link_settings);
1643         enum dc_status status;
1644
1645         status = core_link_write_dpcd(
1646                         link,
1647                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1648                         (uint8_t *) &encoding,
1649                         1);
1650         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1651                                         __func__,
1652                                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1653                                         encoding);
1654
1655         return status;
1656 }
1657
1658 static enum link_training_result dp_perform_8b_10b_link_training(
1659                 struct dc_link *link,
1660                 struct link_training_settings *lt_settings)
1661 {
1662         enum link_training_result status = LINK_TRAINING_SUCCESS;
1663
1664         uint8_t repeater_cnt;
1665         uint8_t repeater_id;
1666
1667         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1668                 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
1669
1670         /* 1. set link rate, lane count and spread. */
1671         dpcd_set_link_settings(link, lt_settings);
1672
1673         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1674
1675                 /* 2. perform link training (set link training done
1676                  *  to false is done as well)
1677                  */
1678                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1679
1680                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1681                                 repeater_id--) {
1682                         status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
1683
1684                         if (status != LINK_TRAINING_SUCCESS)
1685                                 break;
1686
1687                         status = perform_channel_equalization_sequence(link,
1688                                         lt_settings,
1689                                         repeater_id);
1690
1691                         if (status != LINK_TRAINING_SUCCESS)
1692                                 break;
1693
1694                         repeater_training_done(link, repeater_id);
1695                 }
1696         }
1697
1698         if (status == LINK_TRAINING_SUCCESS) {
1699                 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
1700         if (status == LINK_TRAINING_SUCCESS) {
1701                 status = perform_channel_equalization_sequence(link,
1702                                         lt_settings,
1703                                         DPRX);
1704                 }
1705         }
1706
1707         return status;
1708 }
1709
1710 enum link_training_result dc_link_dp_perform_link_training(
1711         struct dc_link *link,
1712         const struct dc_link_settings *link_settings,
1713         bool skip_video_pattern)
1714 {
1715         enum link_training_result status = LINK_TRAINING_SUCCESS;
1716         struct link_training_settings lt_settings;
1717         enum dp_link_encoding encoding =
1718                         dp_get_link_encoding_format(link_settings);
1719
1720         /* decide training settings */
1721         dp_decide_training_settings(
1722                         link,
1723                         link_settings,
1724                         &link->preferred_training_settings,
1725                         &lt_settings);
1726
1727         /* reset previous training states */
1728         dpcd_exit_training_mode(link);
1729
1730         /* configure link prior to entering training mode */
1731         dpcd_configure_lttpr_mode(link, &lt_settings);
1732         dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1733         dpcd_configure_channel_coding(link, &lt_settings);
1734
1735         /* enter training mode:
1736          * Per DP specs starting from here, DPTX device shall not issue
1737          * Non-LT AUX transactions inside training mode.
1738          */
1739         if (encoding == DP_8b_10b_ENCODING)
1740                 status = dp_perform_8b_10b_link_training(link, &lt_settings);
1741         else
1742                 ASSERT(0);
1743
1744         /* exit training mode and switch to video idle */
1745         dpcd_exit_training_mode(link);
1746         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1747                 status = dp_transition_to_video_idle(link,
1748                                 &lt_settings,
1749                                 status);
1750
1751         /* dump debug data */
1752         print_status_message(link, &lt_settings, status);
1753         if (status != LINK_TRAINING_SUCCESS)
1754                 link->ctx->dc->debug_data.ltFailCount++;
1755         return status;
1756 }
1757
1758 static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1759 {
1760         struct dc_link *link = stream->link;
1761         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1762 #ifdef CONFIG_DRM_AMD_DC_HDCP
1763         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1764 #endif
1765
1766         /* ASSR must be supported on the panel */
1767         if (panel_mode == DP_PANEL_MODE_DEFAULT)
1768                 return panel_mode;
1769
1770         /* eDP or internal DP only */
1771         if (link->connector_signal != SIGNAL_TYPE_EDP &&
1772                 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1773                  link->is_internal_display))
1774                 return DP_PANEL_MODE_DEFAULT;
1775
1776 #ifdef CONFIG_DRM_AMD_DC_HDCP
1777         if (cp_psp && cp_psp->funcs.enable_assr) {
1778                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1779                         /* since eDP implies ASSR on, change panel
1780                          * mode to disable ASSR
1781                          */
1782                         panel_mode = DP_PANEL_MODE_DEFAULT;
1783                 }
1784         } else
1785                 panel_mode = DP_PANEL_MODE_DEFAULT;
1786
1787 #else
1788         /* turn off ASSR if the implementation is not compiled in */
1789         panel_mode = DP_PANEL_MODE_DEFAULT;
1790 #endif
1791         return panel_mode;
1792 }
1793
1794 bool perform_link_training_with_retries(
1795         const struct dc_link_settings *link_setting,
1796         bool skip_video_pattern,
1797         int attempts,
1798         struct pipe_ctx *pipe_ctx,
1799         enum signal_type signal,
1800         bool do_fallback)
1801 {
1802         uint8_t j;
1803         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1804         struct dc_stream_state *stream = pipe_ctx->stream;
1805         struct dc_link *link = stream->link;
1806         enum dp_panel_mode panel_mode;
1807         struct link_encoder *link_enc;
1808         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1809         struct dc_link_settings currnet_setting = *link_setting;
1810
1811         /* Dynamically assigned link encoders associated with stream rather than
1812          * link.
1813          */
1814         if (link->dc->res_pool->funcs->link_encs_assign)
1815                 link_enc = stream->link_enc;
1816         else
1817                 link_enc = link->link_enc;
1818         ASSERT(link_enc);
1819
1820         /* We need to do this before the link training to ensure the idle pattern in SST
1821          * mode will be sent right after the link training
1822          */
1823         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1824                                                         pipe_ctx->stream_res.stream_enc->id, true);
1825
1826         for (j = 0; j < attempts; ++j) {
1827
1828                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1829                         __func__, (unsigned int)j + 1, attempts);
1830
1831                 dp_enable_link_phy(
1832                         link,
1833                         signal,
1834                         pipe_ctx->clock_source->id,
1835                         &currnet_setting);
1836
1837                 if (stream->sink_patches.dppowerup_delay > 0) {
1838                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1839
1840                         msleep(delay_dp_power_up_in_ms);
1841                 }
1842
1843                 panel_mode = try_enable_assr(stream);
1844                 dp_set_panel_mode(link, panel_mode);
1845                 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1846                          link->link_index,
1847                          panel_mode != DP_PANEL_MODE_DEFAULT);
1848
1849                 if (link->aux_access_disabled) {
1850                         dc_link_dp_perform_link_training_skip_aux(link, &currnet_setting);
1851                         return true;
1852                 } else {
1853                                 status = dc_link_dp_perform_link_training(
1854                                                                                 link,
1855                                                                                 &currnet_setting,
1856                                                                                 skip_video_pattern);
1857                         if (status == LINK_TRAINING_SUCCESS)
1858                                 return true;
1859                 }
1860
1861                 /* latest link training still fail, skip delay and keep PHY on
1862                  */
1863                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1864                         break;
1865
1866                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1867                         __func__, (unsigned int)j + 1, attempts);
1868
1869                 dp_disable_link_phy(link, signal);
1870
1871                 /* Abort link training if failure due to sink being unplugged. */
1872                 if (status == LINK_TRAINING_ABORT)
1873                         break;
1874                 else if (do_fallback) {
1875                         decide_fallback_link_setting(*link_setting, &currnet_setting, status);
1876                         /* Fail link training if reduced link bandwidth no longer meets
1877                          * stream requirements.
1878                          */
1879                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1880                                         dc_link_bandwidth_kbps(link, &currnet_setting))
1881                                 break;
1882                 }
1883
1884                 msleep(delay_between_attempts);
1885
1886                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1887         }
1888
1889         return false;
1890 }
1891
1892 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1893 {
1894         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1895         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1896
1897         if (dp_cs != NULL) {
1898                 dp_cs_id = dp_cs->id;
1899         } else {
1900                 /*
1901                  * dp clock source is not initialized for some reason.
1902                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1903                  */
1904                 ASSERT(dp_cs);
1905         }
1906
1907         return dp_cs_id;
1908 }
1909
1910 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1911 {
1912         if (mst_enable == false &&
1913                 link->type == dc_connection_mst_branch) {
1914                 /* Disable MST on link. Use only local sink. */
1915                 dp_disable_link_phy_mst(link, link->connector_signal);
1916
1917                 link->type = dc_connection_single;
1918                 link->local_sink = link->remote_sinks[0];
1919                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1920                 dc_sink_retain(link->local_sink);
1921                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1922         } else if (mst_enable == true &&
1923                         link->type == dc_connection_single &&
1924                         link->remote_sinks[0] != NULL) {
1925                 /* Re-enable MST on link. */
1926                 dp_disable_link_phy(link, link->connector_signal);
1927                 dp_enable_mst_on_sink(link, true);
1928
1929                 link->type = dc_connection_mst_branch;
1930                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1931         }
1932 }
1933
1934 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1935 {
1936         /* Begin Sync LT. During this time,
1937          * DPCD:600h must not be powered down.
1938          */
1939         link->sync_lt_in_progress = true;
1940
1941         /*Clear any existing preferred settings.*/
1942         memset(&link->preferred_training_settings, 0,
1943                 sizeof(struct dc_link_training_overrides));
1944         memset(&link->preferred_link_setting, 0,
1945                 sizeof(struct dc_link_settings));
1946
1947         return true;
1948 }
1949
1950 enum link_training_result dc_link_dp_sync_lt_attempt(
1951     struct dc_link *link,
1952     struct dc_link_settings *link_settings,
1953     struct dc_link_training_overrides *lt_overrides)
1954 {
1955         struct link_training_settings lt_settings;
1956         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1957         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1958         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1959         bool fec_enable = false;
1960
1961         dp_decide_training_settings(
1962                 link,
1963                 link_settings,
1964                 lt_overrides,
1965                 &lt_settings);
1966
1967         /* Setup MST Mode */
1968         if (lt_overrides->mst_enable)
1969                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1970
1971         /* Disable link */
1972         dp_disable_link_phy(link, link->connector_signal);
1973
1974         /* Enable link */
1975         dp_cs_id = get_clock_source_id(link);
1976         dp_enable_link_phy(link, link->connector_signal,
1977                 dp_cs_id, link_settings);
1978
1979         /* Set FEC enable */
1980         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1981         dp_set_fec_ready(link, fec_enable);
1982
1983         if (lt_overrides->alternate_scrambler_reset) {
1984                 if (*lt_overrides->alternate_scrambler_reset)
1985                         panel_mode = DP_PANEL_MODE_EDP;
1986                 else
1987                         panel_mode = DP_PANEL_MODE_DEFAULT;
1988         } else
1989                 panel_mode = dp_get_panel_mode(link);
1990
1991         dp_set_panel_mode(link, panel_mode);
1992
1993         /* Attempt to train with given link training settings */
1994         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1995                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1996
1997         /* Set link rate, lane count and spread. */
1998         dpcd_set_link_settings(link, &lt_settings);
1999
2000         /* 2. perform link training (set link training done
2001          *  to false is done as well)
2002          */
2003         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
2004         if (lt_status == LINK_TRAINING_SUCCESS) {
2005                 lt_status = perform_channel_equalization_sequence(link,
2006                                                 &lt_settings,
2007                                                 DPRX);
2008         }
2009
2010         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
2011         /* 4. print status message*/
2012         print_status_message(link, &lt_settings, lt_status);
2013
2014         return lt_status;
2015 }
2016
2017 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
2018 {
2019         /* If input parameter is set, shut down phy.
2020          * Still shouldn't turn off dp_receiver (DPCD:600h)
2021          */
2022         if (link_down == true) {
2023                 dp_disable_link_phy(link, link->connector_signal);
2024                 dp_set_fec_ready(link, false);
2025         }
2026
2027         link->sync_lt_in_progress = false;
2028         return true;
2029 }
2030
2031 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2032 {
2033         if (!max_link_enc_cap) {
2034                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2035                 return false;
2036         }
2037
2038         if (link->link_enc->funcs->get_max_link_cap) {
2039                 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2040                 return true;
2041         }
2042
2043         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2044         max_link_enc_cap->lane_count = 1;
2045         max_link_enc_cap->link_rate = 6;
2046         return false;
2047 }
2048
2049 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2050 {
2051         struct dc_link_settings max_link_cap = {0};
2052
2053         /* get max link encoder capability */
2054         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
2055
2056         /* Lower link settings based on sink's link cap */
2057         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2058                 max_link_cap.lane_count =
2059                                 link->reported_link_cap.lane_count;
2060         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2061                 max_link_cap.link_rate =
2062                                 link->reported_link_cap.link_rate;
2063         if (link->reported_link_cap.link_spread <
2064                         max_link_cap.link_spread)
2065                 max_link_cap.link_spread =
2066                                 link->reported_link_cap.link_spread;
2067         /*
2068          * account for lttpr repeaters cap
2069          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2070          */
2071         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2072                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2073                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2074
2075                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2076                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2077
2078                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2079                                                 __func__,
2080                                                 max_link_cap.lane_count,
2081                                                 max_link_cap.link_rate);
2082         }
2083         return max_link_cap;
2084 }
2085
2086 enum dc_status read_hpd_rx_irq_data(
2087         struct dc_link *link,
2088         union hpd_irq_data *irq_data)
2089 {
2090         static enum dc_status retval;
2091
2092         /* The HW reads 16 bytes from 200h on HPD,
2093          * but if we get an AUX_DEFER, the HW cannot retry
2094          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2095          * fail, so we now explicitly read 6 bytes which is
2096          * the req from the above mentioned test cases.
2097          *
2098          * For DP 1.4 we need to read those from 2002h range.
2099          */
2100         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2101                 retval = core_link_read_dpcd(
2102                         link,
2103                         DP_SINK_COUNT,
2104                         irq_data->raw,
2105                         sizeof(union hpd_irq_data));
2106         else {
2107                 /* Read 14 bytes in a single read and then copy only the required fields.
2108                  * This is more efficient than doing it in two separate AUX reads. */
2109
2110                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2111
2112                 retval = core_link_read_dpcd(
2113                         link,
2114                         DP_SINK_COUNT_ESI,
2115                         tmp,
2116                         sizeof(tmp));
2117
2118                 if (retval != DC_OK)
2119                         return retval;
2120
2121                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2122                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2123                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2124                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2125                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2126                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2127         }
2128
2129         return retval;
2130 }
2131
2132 bool hpd_rx_irq_check_link_loss_status(
2133         struct dc_link *link,
2134         union hpd_irq_data *hpd_irq_dpcd_data)
2135 {
2136         uint8_t irq_reg_rx_power_state = 0;
2137         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2138         union lane_status lane_status;
2139         uint32_t lane;
2140         bool sink_status_changed;
2141         bool return_code;
2142
2143         sink_status_changed = false;
2144         return_code = false;
2145
2146         if (link->cur_link_settings.lane_count == 0)
2147                 return return_code;
2148
2149         /*1. Check that Link Status changed, before re-training.*/
2150
2151         /*parse lane status*/
2152         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2153                 /* check status of lanes 0,1
2154                  * changed DpcdAddress_Lane01Status (0x202)
2155                  */
2156                 lane_status.raw = get_nibble_at_index(
2157                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2158                         lane);
2159
2160                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2161                         !lane_status.bits.CR_DONE_0 ||
2162                         !lane_status.bits.SYMBOL_LOCKED_0) {
2163                         /* if one of the channel equalization, clock
2164                          * recovery or symbol lock is dropped
2165                          * consider it as (link has been
2166                          * dropped) dp sink status has changed
2167                          */
2168                         sink_status_changed = true;
2169                         break;
2170                 }
2171         }
2172
2173         /* Check interlane align.*/
2174         if (sink_status_changed ||
2175                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2176
2177                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2178
2179                 return_code = true;
2180
2181                 /*2. Check that we can handle interrupt: Not in FS DOS,
2182                  *  Not in "Display Timeout" state, Link is trained.
2183                  */
2184                 dpcd_result = core_link_read_dpcd(link,
2185                         DP_SET_POWER,
2186                         &irq_reg_rx_power_state,
2187                         sizeof(irq_reg_rx_power_state));
2188
2189                 if (dpcd_result != DC_OK) {
2190                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2191                                 __func__);
2192                 } else {
2193                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2194                                 return_code = false;
2195                 }
2196         }
2197
2198         return return_code;
2199 }
2200
2201 bool dp_verify_link_cap(
2202         struct dc_link *link,
2203         struct dc_link_settings *known_limit_link_setting,
2204         int *fail_count)
2205 {
2206         struct dc_link_settings max_link_cap = {0};
2207         struct dc_link_settings cur_link_setting = {0};
2208         struct dc_link_settings *cur = &cur_link_setting;
2209         struct dc_link_settings initial_link_settings = {0};
2210         bool success;
2211         bool skip_link_training;
2212         bool skip_video_pattern;
2213         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2214         enum link_training_result status;
2215         union hpd_irq_data irq_data;
2216
2217         if (link->dc->debug.skip_detection_link_training) {
2218                 link->verified_link_cap = *known_limit_link_setting;
2219                 return true;
2220         }
2221
2222         memset(&irq_data, 0, sizeof(irq_data));
2223         success = false;
2224         skip_link_training = false;
2225
2226         max_link_cap = get_max_link_cap(link);
2227
2228         /* Grant extended timeout request */
2229         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2230                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2231
2232                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2233         }
2234
2235         /* TODO implement override and monitor patch later */
2236
2237         /* try to train the link from high to low to
2238          * find the physical link capability
2239          */
2240         /* disable PHY done possible by BIOS, will be done by driver itself */
2241         dp_disable_link_phy(link, link->connector_signal);
2242
2243         dp_cs_id = get_clock_source_id(link);
2244
2245         /* link training starts with the maximum common settings
2246          * supported by both sink and ASIC.
2247          */
2248         initial_link_settings = get_common_supported_link_settings(
2249                         *known_limit_link_setting,
2250                         max_link_cap);
2251         cur_link_setting = initial_link_settings;
2252
2253         /* Temporary Renoir-specific workaround for SWDEV-215184;
2254          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2255          * so add extra cycle of enabling and disabling the PHY before first link training.
2256          */
2257         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2258                         link->dc->debug.usbc_combo_phy_reset_wa) {
2259                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2260                 dp_disable_link_phy(link, link->connector_signal);
2261         }
2262
2263         do {
2264                 skip_video_pattern = true;
2265
2266                 if (cur->link_rate == LINK_RATE_LOW)
2267                         skip_video_pattern = false;
2268
2269                 dp_enable_link_phy(
2270                                 link,
2271                                 link->connector_signal,
2272                                 dp_cs_id,
2273                                 cur);
2274
2275
2276                 if (skip_link_training)
2277                         success = true;
2278                 else {
2279                         status = dc_link_dp_perform_link_training(
2280                                                         link,
2281                                                         cur,
2282                                                         skip_video_pattern);
2283                         if (status == LINK_TRAINING_SUCCESS)
2284                                 success = true;
2285                         else
2286                                 (*fail_count)++;
2287                 }
2288
2289                 if (success) {
2290                         link->verified_link_cap = *cur;
2291                         udelay(1000);
2292                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2293                                 if (hpd_rx_irq_check_link_loss_status(
2294                                                 link,
2295                                                 &irq_data))
2296                                         (*fail_count)++;
2297                 }
2298                 /* always disable the link before trying another
2299                  * setting or before returning we'll enable it later
2300                  * based on the actual mode we're driving
2301                  */
2302                 dp_disable_link_phy(link, link->connector_signal);
2303         } while (!success && decide_fallback_link_setting(
2304                         initial_link_settings, cur, status));
2305
2306         /* Link Training failed for all Link Settings
2307          *  (Lane Count is still unknown)
2308          */
2309         if (!success) {
2310                 /* If all LT fails for all settings,
2311                  * set verified = failed safe (1 lane low)
2312                  */
2313                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2314                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2315
2316                 link->verified_link_cap.link_spread =
2317                 LINK_SPREAD_DISABLED;
2318         }
2319
2320
2321         return success;
2322 }
2323
2324 bool dp_verify_link_cap_with_retries(
2325         struct dc_link *link,
2326         struct dc_link_settings *known_limit_link_setting,
2327         int attempts)
2328 {
2329         uint8_t i = 0;
2330         bool success = false;
2331
2332         for (i = 0; i < attempts; i++) {
2333                 int fail_count = 0;
2334                 enum dc_connection_type type = dc_connection_none;
2335
2336                 memset(&link->verified_link_cap, 0,
2337                                 sizeof(struct dc_link_settings));
2338                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2339                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2340                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2341                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2342                         break;
2343                 } else if (dp_verify_link_cap(link,
2344                                 &link->reported_link_cap,
2345                                 &fail_count) && fail_count == 0) {
2346                         success = true;
2347                         break;
2348                 }
2349                 msleep(10);
2350         }
2351         return success;
2352 }
2353
2354 bool dp_verify_mst_link_cap(
2355         struct dc_link *link)
2356 {
2357         struct dc_link_settings max_link_cap = {0};
2358
2359         max_link_cap = get_max_link_cap(link);
2360         link->verified_link_cap = get_common_supported_link_settings(
2361                 link->reported_link_cap,
2362                 max_link_cap);
2363
2364         return true;
2365 }
2366
2367 static struct dc_link_settings get_common_supported_link_settings(
2368                 struct dc_link_settings link_setting_a,
2369                 struct dc_link_settings link_setting_b)
2370 {
2371         struct dc_link_settings link_settings = {0};
2372
2373         link_settings.lane_count =
2374                 (link_setting_a.lane_count <=
2375                         link_setting_b.lane_count) ?
2376                         link_setting_a.lane_count :
2377                         link_setting_b.lane_count;
2378         link_settings.link_rate =
2379                 (link_setting_a.link_rate <=
2380                         link_setting_b.link_rate) ?
2381                         link_setting_a.link_rate :
2382                         link_setting_b.link_rate;
2383         link_settings.link_spread = LINK_SPREAD_DISABLED;
2384
2385         /* in DP compliance test, DPR-120 may have
2386          * a random value in its MAX_LINK_BW dpcd field.
2387          * We map it to the maximum supported link rate that
2388          * is smaller than MAX_LINK_BW in this case.
2389          */
2390         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2391                 link_settings.link_rate = LINK_RATE_HIGH3;
2392         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2393                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2394                 link_settings.link_rate = LINK_RATE_HIGH2;
2395         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2396                         && link_settings.link_rate > LINK_RATE_HIGH) {
2397                 link_settings.link_rate = LINK_RATE_HIGH;
2398         } else if (link_settings.link_rate < LINK_RATE_HIGH
2399                         && link_settings.link_rate > LINK_RATE_LOW) {
2400                 link_settings.link_rate = LINK_RATE_LOW;
2401         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2402                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2403         }
2404
2405         return link_settings;
2406 }
2407
2408 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2409 {
2410         return lane_count <= LANE_COUNT_ONE;
2411 }
2412
2413 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2414 {
2415         return link_rate <= LINK_RATE_LOW;
2416 }
2417
2418 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2419 {
2420         switch (lane_count) {
2421         case LANE_COUNT_FOUR:
2422                 return LANE_COUNT_TWO;
2423         case LANE_COUNT_TWO:
2424                 return LANE_COUNT_ONE;
2425         case LANE_COUNT_ONE:
2426                 return LANE_COUNT_UNKNOWN;
2427         default:
2428                 return LANE_COUNT_UNKNOWN;
2429         }
2430 }
2431
2432 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2433 {
2434         switch (link_rate) {
2435         case LINK_RATE_HIGH3:
2436                 return LINK_RATE_HIGH2;
2437         case LINK_RATE_HIGH2:
2438                 return LINK_RATE_HIGH;
2439         case LINK_RATE_HIGH:
2440                 return LINK_RATE_LOW;
2441         case LINK_RATE_LOW:
2442                 return LINK_RATE_UNKNOWN;
2443         default:
2444                 return LINK_RATE_UNKNOWN;
2445         }
2446 }
2447
2448 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2449 {
2450         switch (lane_count) {
2451         case LANE_COUNT_ONE:
2452                 return LANE_COUNT_TWO;
2453         case LANE_COUNT_TWO:
2454                 return LANE_COUNT_FOUR;
2455         default:
2456                 return LANE_COUNT_UNKNOWN;
2457         }
2458 }
2459
2460 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2461 {
2462         switch (link_rate) {
2463         case LINK_RATE_LOW:
2464                 return LINK_RATE_HIGH;
2465         case LINK_RATE_HIGH:
2466                 return LINK_RATE_HIGH2;
2467         case LINK_RATE_HIGH2:
2468                 return LINK_RATE_HIGH3;
2469         default:
2470                 return LINK_RATE_UNKNOWN;
2471         }
2472 }
2473
2474 /*
2475  * function: set link rate and lane count fallback based
2476  * on current link setting and last link training result
2477  * return value:
2478  *                      true - link setting could be set
2479  *                      false - has reached minimum setting
2480  *                                      and no further fallback could be done
2481  */
2482 static bool decide_fallback_link_setting(
2483                 struct dc_link_settings initial_link_settings,
2484                 struct dc_link_settings *current_link_setting,
2485                 enum link_training_result training_result)
2486 {
2487         if (!current_link_setting)
2488                 return false;
2489
2490         switch (training_result) {
2491         case LINK_TRAINING_CR_FAIL_LANE0:
2492         case LINK_TRAINING_CR_FAIL_LANE1:
2493         case LINK_TRAINING_CR_FAIL_LANE23:
2494         case LINK_TRAINING_LQA_FAIL:
2495         {
2496                 if (!reached_minimum_link_rate
2497                                 (current_link_setting->link_rate)) {
2498                         current_link_setting->link_rate =
2499                                 reduce_link_rate(
2500                                         current_link_setting->link_rate);
2501                 } else if (!reached_minimum_lane_count
2502                                 (current_link_setting->lane_count)) {
2503                         current_link_setting->link_rate =
2504                                 initial_link_settings.link_rate;
2505                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2506                                 return false;
2507                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2508                                 current_link_setting->lane_count =
2509                                                 LANE_COUNT_ONE;
2510                         else if (training_result ==
2511                                         LINK_TRAINING_CR_FAIL_LANE23)
2512                                 current_link_setting->lane_count =
2513                                                 LANE_COUNT_TWO;
2514                         else
2515                                 current_link_setting->lane_count =
2516                                         reduce_lane_count(
2517                                         current_link_setting->lane_count);
2518                 } else {
2519                         return false;
2520                 }
2521                 break;
2522         }
2523         case LINK_TRAINING_EQ_FAIL_EQ:
2524         {
2525                 if (!reached_minimum_lane_count
2526                                 (current_link_setting->lane_count)) {
2527                         current_link_setting->lane_count =
2528                                 reduce_lane_count(
2529                                         current_link_setting->lane_count);
2530                 } else if (!reached_minimum_link_rate
2531                                 (current_link_setting->link_rate)) {
2532                         current_link_setting->link_rate =
2533                                 reduce_link_rate(
2534                                         current_link_setting->link_rate);
2535                 } else {
2536                         return false;
2537                 }
2538                 break;
2539         }
2540         case LINK_TRAINING_EQ_FAIL_CR:
2541         {
2542                 if (!reached_minimum_link_rate
2543                                 (current_link_setting->link_rate)) {
2544                         current_link_setting->link_rate =
2545                                 reduce_link_rate(
2546                                         current_link_setting->link_rate);
2547                 } else {
2548                         return false;
2549                 }
2550                 break;
2551         }
2552         default:
2553                 return false;
2554         }
2555         return true;
2556 }
2557
2558 bool dp_validate_mode_timing(
2559         struct dc_link *link,
2560         const struct dc_crtc_timing *timing)
2561 {
2562         uint32_t req_bw;
2563         uint32_t max_bw;
2564
2565         const struct dc_link_settings *link_setting;
2566
2567         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2568         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2569                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2570                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2571                 return false;
2572
2573         /*always DP fail safe mode*/
2574         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2575                 timing->h_addressable == (uint32_t) 640 &&
2576                 timing->v_addressable == (uint32_t) 480)
2577                 return true;
2578
2579         link_setting = dc_link_get_link_cap(link);
2580
2581         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2582         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2583                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2584                 link_setting = &link->verified_link_cap;
2585         */
2586
2587         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2588         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2589
2590         if (req_bw <= max_bw) {
2591                 /* remember the biggest mode here, during
2592                  * initial link training (to get
2593                  * verified_link_cap), LS sends event about
2594                  * cannot train at reported cap to upper
2595                  * layer and upper layer will re-enumerate modes.
2596                  * this is not necessary if the lower
2597                  * verified_link_cap is enough to drive
2598                  * all the modes */
2599
2600                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2601                 /* if (flags.DYNAMIC_VALIDATION == 1)
2602                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2603                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2604                 return true;
2605         } else
2606                 return false;
2607 }
2608
2609 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2610 {
2611         struct dc_link_settings initial_link_setting = {
2612                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2613         struct dc_link_settings current_link_setting =
2614                         initial_link_setting;
2615         uint32_t link_bw;
2616
2617         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2618                 return false;
2619
2620         /* search for the minimum link setting that:
2621          * 1. is supported according to the link training result
2622          * 2. could support the b/w requested by the timing
2623          */
2624         while (current_link_setting.link_rate <=
2625                         link->verified_link_cap.link_rate) {
2626                 link_bw = dc_link_bandwidth_kbps(
2627                                 link,
2628                                 &current_link_setting);
2629                 if (req_bw <= link_bw) {
2630                         *link_setting = current_link_setting;
2631                         return true;
2632                 }
2633
2634                 if (current_link_setting.lane_count <
2635                                 link->verified_link_cap.lane_count) {
2636                         current_link_setting.lane_count =
2637                                         increase_lane_count(
2638                                                         current_link_setting.lane_count);
2639                 } else {
2640                         current_link_setting.link_rate =
2641                                         increase_link_rate(
2642                                                         current_link_setting.link_rate);
2643                         current_link_setting.lane_count =
2644                                         initial_link_setting.lane_count;
2645                 }
2646         }
2647
2648         return false;
2649 }
2650
2651 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2652 {
2653         struct dc_link_settings initial_link_setting;
2654         struct dc_link_settings current_link_setting;
2655         uint32_t link_bw;
2656
2657         /*
2658          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2659          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2660          */
2661         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2662                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2663                 *link_setting = link->verified_link_cap;
2664                 return true;
2665         }
2666
2667         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2668         initial_link_setting.lane_count = LANE_COUNT_ONE;
2669         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2670         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2671         initial_link_setting.use_link_rate_set = true;
2672         initial_link_setting.link_rate_set = 0;
2673         current_link_setting = initial_link_setting;
2674
2675         /* search for the minimum link setting that:
2676          * 1. is supported according to the link training result
2677          * 2. could support the b/w requested by the timing
2678          */
2679         while (current_link_setting.link_rate <=
2680                         link->verified_link_cap.link_rate) {
2681                 link_bw = dc_link_bandwidth_kbps(
2682                                 link,
2683                                 &current_link_setting);
2684                 if (req_bw <= link_bw) {
2685                         *link_setting = current_link_setting;
2686                         return true;
2687                 }
2688
2689                 if (current_link_setting.lane_count <
2690                                 link->verified_link_cap.lane_count) {
2691                         current_link_setting.lane_count =
2692                                         increase_lane_count(
2693                                                         current_link_setting.lane_count);
2694                 } else {
2695                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2696                                 current_link_setting.link_rate_set++;
2697                                 current_link_setting.link_rate =
2698                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2699                                 current_link_setting.lane_count =
2700                                                                         initial_link_setting.lane_count;
2701                         } else
2702                                 break;
2703                 }
2704         }
2705         return false;
2706 }
2707
2708 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2709 {
2710         *link_setting = link->verified_link_cap;
2711         return true;
2712 }
2713
2714 void decide_link_settings(struct dc_stream_state *stream,
2715         struct dc_link_settings *link_setting)
2716 {
2717         struct dc_link *link;
2718         uint32_t req_bw;
2719
2720         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2721
2722         link = stream->link;
2723
2724         /* if preferred is specified through AMDDP, use it, if it's enough
2725          * to drive the mode
2726          */
2727         if (link->preferred_link_setting.lane_count !=
2728                         LANE_COUNT_UNKNOWN &&
2729                         link->preferred_link_setting.link_rate !=
2730                                         LINK_RATE_UNKNOWN) {
2731                 *link_setting =  link->preferred_link_setting;
2732                 return;
2733         }
2734
2735         /* MST doesn't perform link training for now
2736          * TODO: add MST specific link training routine
2737          */
2738         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2739                 if (decide_mst_link_settings(link, link_setting))
2740                         return;
2741         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2742                 if (decide_edp_link_settings(link, link_setting, req_bw))
2743                         return;
2744         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2745                 return;
2746
2747         BREAK_TO_DEBUGGER();
2748         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2749
2750         *link_setting = link->verified_link_cap;
2751 }
2752
2753 /*************************Short Pulse IRQ***************************/
2754 static bool allow_hpd_rx_irq(const struct dc_link *link)
2755 {
2756         /*
2757          * Don't handle RX IRQ unless one of following is met:
2758          * 1) The link is established (cur_link_settings != unknown)
2759          * 2) We know we're dealing with a branch device, SST or MST
2760          */
2761
2762         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2763                 is_dp_branch_device(link))
2764                 return true;
2765
2766         return false;
2767 }
2768
2769 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2770 {
2771         union dpcd_psr_configuration psr_configuration;
2772
2773         if (!link->psr_settings.psr_feature_enabled)
2774                 return false;
2775
2776         dm_helpers_dp_read_dpcd(
2777                 link->ctx,
2778                 link,
2779                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2780                 &psr_configuration.raw,
2781                 sizeof(psr_configuration.raw));
2782
2783
2784         if (psr_configuration.bits.ENABLE) {
2785                 unsigned char dpcdbuf[3] = {0};
2786                 union psr_error_status psr_error_status;
2787                 union psr_sink_psr_status psr_sink_psr_status;
2788
2789                 dm_helpers_dp_read_dpcd(
2790                         link->ctx,
2791                         link,
2792                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2793                         (unsigned char *) dpcdbuf,
2794                         sizeof(dpcdbuf));
2795
2796                 /*DPCD 2006h   ERROR STATUS*/
2797                 psr_error_status.raw = dpcdbuf[0];
2798                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2799                 psr_sink_psr_status.raw = dpcdbuf[2];
2800
2801                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2802                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2803                                 psr_error_status.bits.VSC_SDP_ERROR) {
2804                         /* Acknowledge and clear error bits */
2805                         dm_helpers_dp_write_dpcd(
2806                                 link->ctx,
2807                                 link,
2808                                 8198,/*DpcdAddress_PSR_Error_Status*/
2809                                 &psr_error_status.raw,
2810                                 sizeof(psr_error_status.raw));
2811
2812                         /* PSR error, disable and re-enable PSR */
2813                         dc_link_set_psr_allow_active(link, false, true, false);
2814                         dc_link_set_psr_allow_active(link, true, true, false);
2815
2816                         return true;
2817                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2818                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2819                         /* No error is detect, PSR is active.
2820                          * We should return with IRQ_HPD handled without
2821                          * checking for loss of sync since PSR would have
2822                          * powered down main link.
2823                          */
2824                         return true;
2825                 }
2826         }
2827         return false;
2828 }
2829
2830 static void dp_test_send_link_training(struct dc_link *link)
2831 {
2832         struct dc_link_settings link_settings = {0};
2833
2834         core_link_read_dpcd(
2835                         link,
2836                         DP_TEST_LANE_COUNT,
2837                         (unsigned char *)(&link_settings.lane_count),
2838                         1);
2839         core_link_read_dpcd(
2840                         link,
2841                         DP_TEST_LINK_RATE,
2842                         (unsigned char *)(&link_settings.link_rate),
2843                         1);
2844
2845         /* Set preferred link settings */
2846         link->verified_link_cap.lane_count = link_settings.lane_count;
2847         link->verified_link_cap.link_rate = link_settings.link_rate;
2848
2849         dp_retrain_link_dp_test(link, &link_settings, false);
2850 }
2851
2852 /* TODO Raven hbr2 compliance eye output is unstable
2853  * (toggling on and off) with debugger break
2854  * This caueses intermittent PHY automation failure
2855  * Need to look into the root cause */
2856 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2857 {
2858         union phy_test_pattern dpcd_test_pattern;
2859         union lane_adjust dpcd_lane_adjustment[2];
2860         unsigned char dpcd_post_cursor_2_adjustment = 0;
2861         unsigned char test_pattern_buffer[
2862                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2863                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2864         unsigned int test_pattern_size = 0;
2865         enum dp_test_pattern test_pattern;
2866         struct dc_link_training_settings link_settings;
2867         union lane_adjust dpcd_lane_adjust;
2868         unsigned int lane;
2869         struct link_training_settings link_training_settings;
2870         int i = 0;
2871
2872         dpcd_test_pattern.raw = 0;
2873         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2874         memset(&link_settings, 0, sizeof(link_settings));
2875
2876         /* get phy test pattern and pattern parameters from DP receiver */
2877         core_link_read_dpcd(
2878                         link,
2879                         DP_PHY_TEST_PATTERN,
2880                         &dpcd_test_pattern.raw,
2881                         sizeof(dpcd_test_pattern));
2882         core_link_read_dpcd(
2883                         link,
2884                         DP_ADJUST_REQUEST_LANE0_1,
2885                         &dpcd_lane_adjustment[0].raw,
2886                         sizeof(dpcd_lane_adjustment));
2887
2888         /*get post cursor 2 parameters
2889          * For DP 1.1a or eariler, this DPCD register's value is 0
2890          * For DP 1.2 or later:
2891          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2892          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2893          */
2894         core_link_read_dpcd(
2895                         link,
2896                         DP_ADJUST_REQUEST_POST_CURSOR2,
2897                         &dpcd_post_cursor_2_adjustment,
2898                         sizeof(dpcd_post_cursor_2_adjustment));
2899
2900         /* translate request */
2901         switch (dpcd_test_pattern.bits.PATTERN) {
2902         case PHY_TEST_PATTERN_D10_2:
2903                 test_pattern = DP_TEST_PATTERN_D102;
2904                 break;
2905         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2906                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2907                 break;
2908         case PHY_TEST_PATTERN_PRBS7:
2909                 test_pattern = DP_TEST_PATTERN_PRBS7;
2910                 break;
2911         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2912                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2913                 break;
2914         case PHY_TEST_PATTERN_CP2520_1:
2915                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2916                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2917                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2918                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2919                 break;
2920         case PHY_TEST_PATTERN_CP2520_2:
2921                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2922                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2923                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2924                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2925                 break;
2926         case PHY_TEST_PATTERN_CP2520_3:
2927                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2928                 break;
2929         default:
2930                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2931         break;
2932         }
2933
2934         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2935                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2936                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2937                 core_link_read_dpcd(
2938                                 link,
2939                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2940                                 test_pattern_buffer,
2941                                 test_pattern_size);
2942         }
2943
2944         /* prepare link training settings */
2945         link_settings.link = link->cur_link_settings;
2946
2947         for (lane = 0; lane <
2948                 (unsigned int)(link->cur_link_settings.lane_count);
2949                 lane++) {
2950                 dpcd_lane_adjust.raw =
2951                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2952                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2953                         (enum dc_voltage_swing)
2954                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2955                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2956                         (enum dc_pre_emphasis)
2957                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2958                 link_settings.lane_settings[lane].POST_CURSOR2 =
2959                         (enum dc_post_cursor2)
2960                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2961         }
2962
2963         for (i = 0; i < 4; i++)
2964                 link_training_settings.lane_settings[i] =
2965                                 link_settings.lane_settings[i];
2966         link_training_settings.link_settings = link_settings.link;
2967         link_training_settings.allow_invalid_msa_timing_param = false;
2968         /*Usage: Measure DP physical lane signal
2969          * by DP SI test equipment automatically.
2970          * PHY test pattern request is generated by equipment via HPD interrupt.
2971          * HPD needs to be active all the time. HPD should be active
2972          * all the time. Do not touch it.
2973          * forward request to DS
2974          */
2975         dc_link_dp_set_test_pattern(
2976                 link,
2977                 test_pattern,
2978                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2979                 &link_training_settings,
2980                 test_pattern_buffer,
2981                 test_pattern_size);
2982 }
2983
2984 static void dp_test_send_link_test_pattern(struct dc_link *link)
2985 {
2986         union link_test_pattern dpcd_test_pattern;
2987         union test_misc dpcd_test_params;
2988         enum dp_test_pattern test_pattern;
2989         enum dp_test_pattern_color_space test_pattern_color_space =
2990                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2991         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2992         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2993         struct pipe_ctx *pipe_ctx = NULL;
2994         int i;
2995
2996         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2997         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2998
2999         for (i = 0; i < MAX_PIPES; i++) {
3000                 if (pipes[i].stream == NULL)
3001                         continue;
3002
3003                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3004                         pipe_ctx = &pipes[i];
3005                         break;
3006                 }
3007         }
3008
3009         if (pipe_ctx == NULL)
3010                 return;
3011
3012         /* get link test pattern and pattern parameters */
3013         core_link_read_dpcd(
3014                         link,
3015                         DP_TEST_PATTERN,
3016                         &dpcd_test_pattern.raw,
3017                         sizeof(dpcd_test_pattern));
3018         core_link_read_dpcd(
3019                         link,
3020                         DP_TEST_MISC0,
3021                         &dpcd_test_params.raw,
3022                         sizeof(dpcd_test_params));
3023
3024         switch (dpcd_test_pattern.bits.PATTERN) {
3025         case LINK_TEST_PATTERN_COLOR_RAMP:
3026                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3027         break;
3028         case LINK_TEST_PATTERN_VERTICAL_BARS:
3029                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3030         break; /* black and white */
3031         case LINK_TEST_PATTERN_COLOR_SQUARES:
3032                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3033                                 TEST_DYN_RANGE_VESA ?
3034                                 DP_TEST_PATTERN_COLOR_SQUARES :
3035                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3036         break;
3037         default:
3038                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3039         break;
3040         }
3041
3042         if (dpcd_test_params.bits.CLR_FORMAT == 0)
3043                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3044         else
3045                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3046                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3047                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
3048
3049         switch (dpcd_test_params.bits.BPC) {
3050         case 0: // 6 bits
3051                 requestColorDepth = COLOR_DEPTH_666;
3052                 break;
3053         case 1: // 8 bits
3054                 requestColorDepth = COLOR_DEPTH_888;
3055                 break;
3056         case 2: // 10 bits
3057                 requestColorDepth = COLOR_DEPTH_101010;
3058                 break;
3059         case 3: // 12 bits
3060                 requestColorDepth = COLOR_DEPTH_121212;
3061                 break;
3062         default:
3063                 break;
3064         }
3065
3066         switch (dpcd_test_params.bits.CLR_FORMAT) {
3067         case 0:
3068                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3069                 break;
3070         case 1:
3071                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3072                 break;
3073         case 2:
3074                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3075                 break;
3076         default:
3077                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3078                 break;
3079         }
3080
3081
3082         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3083                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3084                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3085                                 __func__,
3086                                 pipe_ctx->stream->timing.display_color_depth,
3087                                 requestColorDepth);
3088                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3089         }
3090
3091         dp_update_dsc_config(pipe_ctx);
3092
3093         dc_link_dp_set_test_pattern(
3094                         link,
3095                         test_pattern,
3096                         test_pattern_color_space,
3097                         NULL,
3098                         NULL,
3099                         0);
3100 }
3101
3102 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3103 {
3104         union audio_test_mode            dpcd_test_mode = {0};
3105         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3106         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3107         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3108
3109         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3110         struct pipe_ctx *pipe_ctx = &pipes[0];
3111         unsigned int channel_count;
3112         unsigned int channel = 0;
3113         unsigned int modes = 0;
3114         unsigned int sampling_rate_in_hz = 0;
3115
3116         // get audio test mode and test pattern parameters
3117         core_link_read_dpcd(
3118                 link,
3119                 DP_TEST_AUDIO_MODE,
3120                 &dpcd_test_mode.raw,
3121                 sizeof(dpcd_test_mode));
3122
3123         core_link_read_dpcd(
3124                 link,
3125                 DP_TEST_AUDIO_PATTERN_TYPE,
3126                 &dpcd_pattern_type.value,
3127                 sizeof(dpcd_pattern_type));
3128
3129         channel_count = dpcd_test_mode.bits.channel_count + 1;
3130
3131         // read pattern periods for requested channels when sawTooth pattern is requested
3132         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3133                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3134
3135                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3136                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3137                 // read period for each channel
3138                 for (channel = 0; channel < channel_count; channel++) {
3139                         core_link_read_dpcd(
3140                                                         link,
3141                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3142                                                         &dpcd_pattern_period[channel].raw,
3143                                                         sizeof(dpcd_pattern_period[channel]));
3144                 }
3145         }
3146
3147         // translate sampling rate
3148         switch (dpcd_test_mode.bits.sampling_rate) {
3149         case AUDIO_SAMPLING_RATE_32KHZ:
3150                 sampling_rate_in_hz = 32000;
3151                 break;
3152         case AUDIO_SAMPLING_RATE_44_1KHZ:
3153                 sampling_rate_in_hz = 44100;
3154                 break;
3155         case AUDIO_SAMPLING_RATE_48KHZ:
3156                 sampling_rate_in_hz = 48000;
3157                 break;
3158         case AUDIO_SAMPLING_RATE_88_2KHZ:
3159                 sampling_rate_in_hz = 88200;
3160                 break;
3161         case AUDIO_SAMPLING_RATE_96KHZ:
3162                 sampling_rate_in_hz = 96000;
3163                 break;
3164         case AUDIO_SAMPLING_RATE_176_4KHZ:
3165                 sampling_rate_in_hz = 176400;
3166                 break;
3167         case AUDIO_SAMPLING_RATE_192KHZ:
3168                 sampling_rate_in_hz = 192000;
3169                 break;
3170         default:
3171                 sampling_rate_in_hz = 0;
3172                 break;
3173         }
3174
3175         link->audio_test_data.flags.test_requested = 1;
3176         link->audio_test_data.flags.disable_video = disable_video;
3177         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3178         link->audio_test_data.channel_count = channel_count;
3179         link->audio_test_data.pattern_type = test_pattern;
3180
3181         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3182                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3183                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3184                 }
3185         }
3186 }
3187
3188 static void handle_automated_test(struct dc_link *link)
3189 {
3190         union test_request test_request;
3191         union test_response test_response;
3192
3193         memset(&test_request, 0, sizeof(test_request));
3194         memset(&test_response, 0, sizeof(test_response));
3195
3196         core_link_read_dpcd(
3197                 link,
3198                 DP_TEST_REQUEST,
3199                 &test_request.raw,
3200                 sizeof(union test_request));
3201         if (test_request.bits.LINK_TRAINING) {
3202                 /* ACK first to let DP RX test box monitor LT sequence */
3203                 test_response.bits.ACK = 1;
3204                 core_link_write_dpcd(
3205                         link,
3206                         DP_TEST_RESPONSE,
3207                         &test_response.raw,
3208                         sizeof(test_response));
3209                 dp_test_send_link_training(link);
3210                 /* no acknowledge request is needed again */
3211                 test_response.bits.ACK = 0;
3212         }
3213         if (test_request.bits.LINK_TEST_PATTRN) {
3214                 dp_test_send_link_test_pattern(link);
3215                 test_response.bits.ACK = 1;
3216         }
3217
3218         if (test_request.bits.AUDIO_TEST_PATTERN) {
3219                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3220                 test_response.bits.ACK = 1;
3221         }
3222
3223         if (test_request.bits.PHY_TEST_PATTERN) {
3224                 dp_test_send_phy_test_pattern(link);
3225                 test_response.bits.ACK = 1;
3226         }
3227
3228         /* send request acknowledgment */
3229         if (test_response.bits.ACK)
3230                 core_link_write_dpcd(
3231                         link,
3232                         DP_TEST_RESPONSE,
3233                         &test_response.raw,
3234                         sizeof(test_response));
3235 }
3236
3237 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3238 {
3239         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3240         union device_service_irq device_service_clear = { { 0 } };
3241         enum dc_status result;
3242         bool status = false;
3243         struct pipe_ctx *pipe_ctx;
3244         int i;
3245
3246         if (out_link_loss)
3247                 *out_link_loss = false;
3248         /* For use cases related to down stream connection status change,
3249          * PSR and device auto test, refer to function handle_sst_hpd_irq
3250          * in DAL2.1*/
3251
3252         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3253                 __func__, link->link_index);
3254
3255
3256          /* All the "handle_hpd_irq_xxx()" methods
3257                  * should be called only after
3258                  * dal_dpsst_ls_read_hpd_irq_data
3259                  * Order of calls is important too
3260                  */
3261         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3262         if (out_hpd_irq_dpcd_data)
3263                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3264
3265         if (result != DC_OK) {
3266                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3267                         __func__);
3268                 return false;
3269         }
3270
3271         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3272                 device_service_clear.bits.AUTOMATED_TEST = 1;
3273                 core_link_write_dpcd(
3274                         link,
3275                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3276                         &device_service_clear.raw,
3277                         sizeof(device_service_clear.raw));
3278                 device_service_clear.raw = 0;
3279                 handle_automated_test(link);
3280                 return false;
3281         }
3282
3283         if (!allow_hpd_rx_irq(link)) {
3284                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3285                         __func__, link->link_index);
3286                 return false;
3287         }
3288
3289         if (handle_hpd_irq_psr_sink(link))
3290                 /* PSR-related error was detected and handled */
3291                 return true;
3292
3293         /* If PSR-related error handled, Main link may be off,
3294          * so do not handle as a normal sink status change interrupt.
3295          */
3296
3297         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3298                 return true;
3299
3300         /* check if we have MST msg and return since we poll for it */
3301         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3302                 return false;
3303
3304         /* For now we only handle 'Downstream port status' case.
3305          * If we got sink count changed it means
3306          * Downstream port status changed,
3307          * then DM should call DC to do the detection.
3308          * NOTE: Do not handle link loss on eDP since it is internal link*/
3309         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3310                 hpd_rx_irq_check_link_loss_status(
3311                         link,
3312                         &hpd_irq_dpcd_data)) {
3313                 /* Connectivity log: link loss */
3314                 CONN_DATA_LINK_LOSS(link,
3315                                         hpd_irq_dpcd_data.raw,
3316                                         sizeof(hpd_irq_dpcd_data),
3317                                         "Status: ");
3318
3319                 for (i = 0; i < MAX_PIPES; i++) {
3320                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3321                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3322                                 break;
3323                 }
3324
3325                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3326                         return false;
3327
3328
3329                 for (i = 0; i < MAX_PIPES; i++) {
3330                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3331                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3332                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3333                                 core_link_disable_stream(pipe_ctx);
3334                 }
3335
3336                 for (i = 0; i < MAX_PIPES; i++) {
3337                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3338                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3339                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3340                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3341                 }
3342
3343                 status = false;
3344                 if (out_link_loss)
3345                         *out_link_loss = true;
3346         }
3347
3348         if (link->type == dc_connection_sst_branch &&
3349                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3350                         != link->dpcd_sink_count)
3351                 status = true;
3352
3353         /* reasons for HPD RX:
3354          * 1. Link Loss - ie Re-train the Link
3355          * 2. MST sideband message
3356          * 3. Automated Test - ie. Internal Commit
3357          * 4. CP (copy protection) - (not interesting for DM???)
3358          * 5. DRR
3359          * 6. Downstream Port status changed
3360          * -ie. Detect - this the only one
3361          * which is interesting for DM because
3362          * it must call dc_link_detect.
3363          */
3364         return status;
3365 }
3366
3367 /*query dpcd for version and mst cap addresses*/
3368 bool is_mst_supported(struct dc_link *link)
3369 {
3370         bool mst          = false;
3371         enum dc_status st = DC_OK;
3372         union dpcd_rev rev;
3373         union mstm_cap cap;
3374
3375         if (link->preferred_training_settings.mst_enable &&
3376                 *link->preferred_training_settings.mst_enable == false) {
3377                 return false;
3378         }
3379
3380         rev.raw  = 0;
3381         cap.raw  = 0;
3382
3383         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3384                         sizeof(rev));
3385
3386         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3387
3388                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3389                                 &cap.raw, sizeof(cap));
3390                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3391                         mst = true;
3392         }
3393         return mst;
3394
3395 }
3396
3397 bool is_dp_active_dongle(const struct dc_link *link)
3398 {
3399         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3400                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3401 }
3402
3403 bool is_dp_branch_device(const struct dc_link *link)
3404 {
3405         return link->dpcd_caps.is_branch_dev;
3406 }
3407
3408 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3409 {
3410         switch (bpc) {
3411         case DOWN_STREAM_MAX_8BPC:
3412                 return 8;
3413         case DOWN_STREAM_MAX_10BPC:
3414                 return 10;
3415         case DOWN_STREAM_MAX_12BPC:
3416                 return 12;
3417         case DOWN_STREAM_MAX_16BPC:
3418                 return 16;
3419         default:
3420                 break;
3421         }
3422
3423         return -1;
3424 }
3425
3426 static void read_dp_device_vendor_id(struct dc_link *link)
3427 {
3428         struct dp_device_vendor_id dp_id;
3429
3430         /* read IEEE branch device id */
3431         core_link_read_dpcd(
3432                 link,
3433                 DP_BRANCH_OUI,
3434                 (uint8_t *)&dp_id,
3435                 sizeof(dp_id));
3436
3437         link->dpcd_caps.branch_dev_id =
3438                 (dp_id.ieee_oui[0] << 16) +
3439                 (dp_id.ieee_oui[1] << 8) +
3440                 dp_id.ieee_oui[2];
3441
3442         memmove(
3443                 link->dpcd_caps.branch_dev_name,
3444                 dp_id.ieee_device_id,
3445                 sizeof(dp_id.ieee_device_id));
3446 }
3447
3448
3449
3450 static void get_active_converter_info(
3451         uint8_t data, struct dc_link *link)
3452 {
3453         union dp_downstream_port_present ds_port = { .byte = data };
3454         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3455
3456         /* decode converter info*/
3457         if (!ds_port.fields.PORT_PRESENT) {
3458                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3459                 ddc_service_set_dongle_type(link->ddc,
3460                                 link->dpcd_caps.dongle_type);
3461                 link->dpcd_caps.is_branch_dev = false;
3462                 return;
3463         }
3464
3465         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3466         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3467
3468         switch (ds_port.fields.PORT_TYPE) {
3469         case DOWNSTREAM_VGA:
3470                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3471                 break;
3472         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3473                 /* At this point we don't know is it DVI or HDMI or DP++,
3474                  * assume DVI.*/
3475                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3476                 break;
3477         default:
3478                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3479                 break;
3480         }
3481
3482         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3483                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3484                 union dwnstream_port_caps_byte0 *port_caps =
3485                         (union dwnstream_port_caps_byte0 *)det_caps;
3486                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3487                                 det_caps, sizeof(det_caps)) == DC_OK) {
3488
3489                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3490                         /*Handle DP case as DONGLE_NONE*/
3491                         case DOWN_STREAM_DETAILED_DP:
3492                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3493                                 break;
3494                         case DOWN_STREAM_DETAILED_VGA:
3495                                 link->dpcd_caps.dongle_type =
3496                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3497                                 break;
3498                         case DOWN_STREAM_DETAILED_DVI:
3499                                 link->dpcd_caps.dongle_type =
3500                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3501                                 break;
3502                         case DOWN_STREAM_DETAILED_HDMI:
3503                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3504                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3505                                 link->dpcd_caps.dongle_type =
3506                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3507
3508                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3509                                 if (ds_port.fields.DETAILED_CAPS) {
3510
3511                                         union dwnstream_port_caps_byte3_hdmi
3512                                                 hdmi_caps = {.raw = det_caps[3] };
3513                                         union dwnstream_port_caps_byte2
3514                                                 hdmi_color_caps = {.raw = det_caps[2] };
3515                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3516                                                 det_caps[1] * 2500;
3517
3518                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3519                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3520                                         /*YCBCR capability only for HDMI case*/
3521                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3522                                                         == DOWN_STREAM_DETAILED_HDMI) {
3523                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3524                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3525                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3526                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3527                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3528                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3529                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3530                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3531                                         }
3532
3533                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3534                                                 translate_dpcd_max_bpc(
3535                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3536
3537                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3538                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3539                                 }
3540
3541                                 break;
3542                         }
3543                 }
3544         }
3545
3546         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3547
3548         {
3549                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3550
3551                 core_link_read_dpcd(
3552                         link,
3553                         DP_BRANCH_REVISION_START,
3554                         (uint8_t *)&dp_hw_fw_revision,
3555                         sizeof(dp_hw_fw_revision));
3556
3557                 link->dpcd_caps.branch_hw_revision =
3558                         dp_hw_fw_revision.ieee_hw_rev;
3559
3560                 memmove(
3561                         link->dpcd_caps.branch_fw_revision,
3562                         dp_hw_fw_revision.ieee_fw_rev,
3563                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3564         }
3565 }
3566
3567 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3568                 int length)
3569 {
3570         int retry = 0;
3571
3572         if (!link->dpcd_caps.dpcd_rev.raw) {
3573                 do {
3574                         dp_receiver_power_ctrl(link, true);
3575                         core_link_read_dpcd(link, DP_DPCD_REV,
3576                                                         dpcd_data, length);
3577                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3578                                 DP_DPCD_REV -
3579                                 DP_DPCD_REV];
3580                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3581         }
3582
3583         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3584                 switch (link->dpcd_caps.branch_dev_id) {
3585                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3586                  * all internal circuits including AUX communication preventing
3587                  * reading DPCD table and EDID (spec violation).
3588                  * Encoder will skip DP RX power down on disable_output to
3589                  * keep receiver powered all the time.*/
3590                 case DP_BRANCH_DEVICE_ID_0010FA:
3591                 case DP_BRANCH_DEVICE_ID_0080E1:
3592                 case DP_BRANCH_DEVICE_ID_00E04C:
3593                         link->wa_flags.dp_keep_receiver_powered = true;
3594                         break;
3595
3596                 /* TODO: May need work around for other dongles. */
3597                 default:
3598                         link->wa_flags.dp_keep_receiver_powered = false;
3599                         break;
3600                 }
3601         } else
3602                 link->wa_flags.dp_keep_receiver_powered = false;
3603 }
3604
3605 /* Read additional sink caps defined in source specific DPCD area
3606  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3607  */
3608 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3609 {
3610         uint8_t dpcd_data;
3611
3612         if (!link)
3613                 return false;
3614
3615         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3616                 return false;
3617
3618         link->dpcd_sink_ext_caps.raw = dpcd_data;
3619         return true;
3620 }
3621
3622 static bool retrieve_link_cap(struct dc_link *link)
3623 {
3624         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3625          * which means size 16 will be good for both of those DPCD register block reads
3626          */
3627         uint8_t dpcd_data[16];
3628         uint8_t lttpr_dpcd_data[6];
3629
3630         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3631          */
3632         uint8_t dpcd_dprx_data = '\0';
3633         uint8_t dpcd_power_state = '\0';
3634
3635         struct dp_device_vendor_id sink_id;
3636         union down_stream_port_count down_strm_port_count;
3637         union edp_configuration_cap edp_config_cap;
3638         union dp_downstream_port_present ds_port = { 0 };
3639         enum dc_status status = DC_ERROR_UNEXPECTED;
3640         uint32_t read_dpcd_retry_cnt = 3;
3641         int i;
3642         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3643         bool is_lttpr_present = false;
3644         const uint32_t post_oui_delay = 30; // 30ms
3645         bool vbios_lttpr_enable = false;
3646         bool vbios_lttpr_interop = false;
3647         struct dc_bios *bios = link->dc->ctx->dc_bios;
3648
3649         memset(dpcd_data, '\0', sizeof(dpcd_data));
3650         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3651         memset(&down_strm_port_count,
3652                 '\0', sizeof(union down_stream_port_count));
3653         memset(&edp_config_cap, '\0',
3654                 sizeof(union edp_configuration_cap));
3655
3656         /* if extended timeout is supported in hardware,
3657          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3658          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3659          */
3660         dc_link_aux_try_to_configure_timeout(link->ddc,
3661                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3662
3663         status = core_link_read_dpcd(link, DP_SET_POWER,
3664                                 &dpcd_power_state, sizeof(dpcd_power_state));
3665
3666         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3667          * section 2.3.1.2, if AUX CH may be powered down due to
3668          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3669          * signal and may need up to 1 ms before being able to reply.
3670          */
3671         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3672                 udelay(1000);
3673
3674         dpcd_set_source_specific_data(link);
3675         /* Sink may need to configure internals based on vendor, so allow some
3676          * time before proceeding with possibly vendor specific transactions
3677          */
3678         msleep(post_oui_delay);
3679
3680         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3681                 status = core_link_read_dpcd(
3682                                 link,
3683                                 DP_DPCD_REV,
3684                                 dpcd_data,
3685                                 sizeof(dpcd_data));
3686                 if (status == DC_OK)
3687                         break;
3688         }
3689
3690         if (status != DC_OK) {
3691                 dm_error("%s: Read dpcd data failed.\n", __func__);
3692                 return false;
3693         }
3694
3695         /* Query BIOS to determine if LTTPR functionality is forced on by system */
3696         if (bios->funcs->get_lttpr_caps) {
3697                 enum bp_result bp_query_result;
3698                 uint8_t is_vbios_lttpr_enable = 0;
3699
3700                 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3701                 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3702         }
3703
3704         if (bios->funcs->get_lttpr_interop) {
3705                 enum bp_result bp_query_result;
3706                 uint8_t is_vbios_interop_enabled = 0;
3707
3708                 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3709                 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3710         }
3711
3712         /*
3713          * Logic to determine LTTPR mode
3714          */
3715         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3716         if (vbios_lttpr_enable && vbios_lttpr_interop)
3717                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3718         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3719                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3720                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3721                 else
3722                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3723         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3724                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3725                         || !link->dc->caps.extended_aux_timeout_support)
3726                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3727                 else
3728                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3729         }
3730
3731         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3732                 /* By reading LTTPR capability, RX assumes that we will enable
3733                  * LTTPR extended aux timeout if LTTPR is present.
3734                  */
3735                 status = core_link_read_dpcd(
3736                                 link,
3737                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3738                                 lttpr_dpcd_data,
3739                                 sizeof(lttpr_dpcd_data));
3740
3741                 link->dpcd_caps.lttpr_caps.revision.raw =
3742                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3743                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3744
3745                 link->dpcd_caps.lttpr_caps.max_link_rate =
3746                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3747                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3748
3749                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3750                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3751                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3752
3753                 link->dpcd_caps.lttpr_caps.max_lane_count =
3754                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3755                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3756
3757                 link->dpcd_caps.lttpr_caps.mode =
3758                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3759                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3760
3761                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3762                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3763                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3764
3765                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3766                 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3767                                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
3768                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3769                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3770                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3771                 if (is_lttpr_present)
3772                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3773                 else
3774                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3775         }
3776
3777         if (!is_lttpr_present)
3778                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3779
3780
3781         {
3782                 union training_aux_rd_interval aux_rd_interval;
3783
3784                 aux_rd_interval.raw =
3785                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3786
3787                 link->dpcd_caps.ext_receiver_cap_field_present =
3788                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3789
3790                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3791                         uint8_t ext_cap_data[16];
3792
3793                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3794                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3795                                 status = core_link_read_dpcd(
3796                                 link,
3797                                 DP_DP13_DPCD_REV,
3798                                 ext_cap_data,
3799                                 sizeof(ext_cap_data));
3800                                 if (status == DC_OK) {
3801                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3802                                         break;
3803                                 }
3804                         }
3805                         if (status != DC_OK)
3806                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3807                 }
3808         }
3809
3810         link->dpcd_caps.dpcd_rev.raw =
3811                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3812
3813         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3814                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3815                         status = core_link_read_dpcd(
3816                                         link,
3817                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3818                                         &dpcd_dprx_data,
3819                                         sizeof(dpcd_dprx_data));
3820                         if (status == DC_OK)
3821                                 break;
3822                 }
3823
3824                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3825
3826                 if (status != DC_OK)
3827                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3828         }
3829
3830         else {
3831                 link->dpcd_caps.dprx_feature.raw = 0;
3832         }
3833
3834
3835         /* Error condition checking...
3836          * It is impossible for Sink to report Max Lane Count = 0.
3837          * It is possible for Sink to report Max Link Rate = 0, if it is
3838          * an eDP device that is reporting specialized link rates in the
3839          * SUPPORTED_LINK_RATE table.
3840          */
3841         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3842                 return false;
3843
3844         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3845                                  DP_DPCD_REV];
3846
3847         read_dp_device_vendor_id(link);
3848
3849         get_active_converter_info(ds_port.byte, link);
3850
3851         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3852
3853         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3854                                  DP_DPCD_REV];
3855
3856         link->dpcd_caps.allow_invalid_MSA_timing_param =
3857                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3858
3859         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3860                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3861
3862         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3863                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3864
3865         link->reported_link_cap.lane_count =
3866                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3867         link->reported_link_cap.link_rate = dpcd_data[
3868                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3869         link->reported_link_cap.link_spread =
3870                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3871                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3872
3873         edp_config_cap.raw = dpcd_data[
3874                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3875         link->dpcd_caps.panel_mode_edp =
3876                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3877         link->dpcd_caps.dpcd_display_control_capable =
3878                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3879
3880         link->test_pattern_enabled = false;
3881         link->compliance_test_state.raw = 0;
3882
3883         /* read sink count */
3884         core_link_read_dpcd(link,
3885                         DP_SINK_COUNT,
3886                         &link->dpcd_caps.sink_count.raw,
3887                         sizeof(link->dpcd_caps.sink_count.raw));
3888
3889         /* read sink ieee oui */
3890         core_link_read_dpcd(link,
3891                         DP_SINK_OUI,
3892                         (uint8_t *)(&sink_id),
3893                         sizeof(sink_id));
3894
3895         link->dpcd_caps.sink_dev_id =
3896                         (sink_id.ieee_oui[0] << 16) +
3897                         (sink_id.ieee_oui[1] << 8) +
3898                         (sink_id.ieee_oui[2]);
3899
3900         memmove(
3901                 link->dpcd_caps.sink_dev_id_str,
3902                 sink_id.ieee_device_id,
3903                 sizeof(sink_id.ieee_device_id));
3904
3905         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3906         {
3907                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3908
3909                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3910                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3911                             sizeof(str_mbp_2017))) {
3912                         link->reported_link_cap.link_rate = 0x0c;
3913                 }
3914         }
3915
3916         core_link_read_dpcd(
3917                 link,
3918                 DP_SINK_HW_REVISION_START,
3919                 (uint8_t *)&dp_hw_fw_revision,
3920                 sizeof(dp_hw_fw_revision));
3921
3922         link->dpcd_caps.sink_hw_revision =
3923                 dp_hw_fw_revision.ieee_hw_rev;
3924
3925         memmove(
3926                 link->dpcd_caps.sink_fw_revision,
3927                 dp_hw_fw_revision.ieee_fw_rev,
3928                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3929
3930         memset(&link->dpcd_caps.dsc_caps, '\0',
3931                         sizeof(link->dpcd_caps.dsc_caps));
3932         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3933         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3934         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3935                 status = core_link_read_dpcd(
3936                                 link,
3937                                 DP_FEC_CAPABILITY,
3938                                 &link->dpcd_caps.fec_cap.raw,
3939                                 sizeof(link->dpcd_caps.fec_cap.raw));
3940                 status = core_link_read_dpcd(
3941                                 link,
3942                                 DP_DSC_SUPPORT,
3943                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3944                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3945                 status = core_link_read_dpcd(
3946                                 link,
3947                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3948                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3949                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3950         }
3951
3952         if (!dpcd_read_sink_ext_caps(link))
3953                 link->dpcd_sink_ext_caps.raw = 0;
3954
3955         /* Connectivity log: detection */
3956         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3957
3958         return true;
3959 }
3960
3961 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3962 {
3963         uint8_t dpcd_data[16];
3964         uint32_t read_dpcd_retry_cnt = 3;
3965         enum dc_status status = DC_ERROR_UNEXPECTED;
3966         union dp_downstream_port_present ds_port = { 0 };
3967         union down_stream_port_count down_strm_port_count;
3968         union edp_configuration_cap edp_config_cap;
3969
3970         int i;
3971
3972         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3973                 status = core_link_read_dpcd(
3974                                 link,
3975                                 DP_DPCD_REV,
3976                                 dpcd_data,
3977                                 sizeof(dpcd_data));
3978                 if (status == DC_OK)
3979                         break;
3980         }
3981
3982         link->dpcd_caps.dpcd_rev.raw =
3983                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3984
3985         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3986                 return false;
3987
3988         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3989                         DP_DPCD_REV];
3990
3991         get_active_converter_info(ds_port.byte, link);
3992
3993         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3994                         DP_DPCD_REV];
3995
3996         link->dpcd_caps.allow_invalid_MSA_timing_param =
3997                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3998
3999         link->dpcd_caps.max_ln_count.raw = dpcd_data[
4000                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4001
4002         link->dpcd_caps.max_down_spread.raw = dpcd_data[
4003                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4004
4005         link->reported_link_cap.lane_count =
4006                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
4007         link->reported_link_cap.link_rate = dpcd_data[
4008                 DP_MAX_LINK_RATE - DP_DPCD_REV];
4009         link->reported_link_cap.link_spread =
4010                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
4011                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
4012
4013         edp_config_cap.raw = dpcd_data[
4014                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4015         link->dpcd_caps.panel_mode_edp =
4016                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
4017         link->dpcd_caps.dpcd_display_control_capable =
4018                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4019
4020         return true;
4021 }
4022
4023 bool detect_dp_sink_caps(struct dc_link *link)
4024 {
4025         return retrieve_link_cap(link);
4026
4027         /* dc init_hw has power encoder using default
4028          * signal for connector. For native DP, no
4029          * need to power up encoder again. If not native
4030          * DP, hw_init may need check signal or power up
4031          * encoder here.
4032          */
4033         /* TODO save sink caps in link->sink */
4034 }
4035
4036 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
4037 {
4038         enum dc_link_rate link_rate;
4039         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4040         switch (link_rate_in_khz) {
4041         case 1620000:
4042                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
4043                 break;
4044         case 2160000:
4045                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
4046                 break;
4047         case 2430000:
4048                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
4049                 break;
4050         case 2700000:
4051                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
4052                 break;
4053         case 3240000:
4054                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
4055                 break;
4056         case 4320000:
4057                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
4058                 break;
4059         case 5400000:
4060                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
4061                 break;
4062         case 8100000:
4063                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
4064                 break;
4065         default:
4066                 link_rate = LINK_RATE_UNKNOWN;
4067                 break;
4068         }
4069         return link_rate;
4070 }
4071
4072 void detect_edp_sink_caps(struct dc_link *link)
4073 {
4074         uint8_t supported_link_rates[16];
4075         uint32_t entry;
4076         uint32_t link_rate_in_khz;
4077         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4078         uint8_t backlight_adj_cap;
4079
4080         retrieve_link_cap(link);
4081         link->dpcd_caps.edp_supported_link_rates_count = 0;
4082         memset(supported_link_rates, 0, sizeof(supported_link_rates));
4083
4084         /*
4085          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4086          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4087          */
4088         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4089                         (link->dc->debug.optimize_edp_link_rate ||
4090                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4091                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4092                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4093                                                         supported_link_rates, sizeof(supported_link_rates));
4094
4095                 for (entry = 0; entry < 16; entry += 2) {
4096                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4097                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4098                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4099                                                                                 supported_link_rates[entry]) * 200;
4100
4101                         if (link_rate_in_khz != 0) {
4102                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4103                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4104                                 link->dpcd_caps.edp_supported_link_rates_count++;
4105
4106                                 if (link->reported_link_cap.link_rate < link_rate)
4107                                         link->reported_link_cap.link_rate = link_rate;
4108                         }
4109                 }
4110         }
4111         link->verified_link_cap = link->reported_link_cap;
4112
4113         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4114                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4115
4116         link->dpcd_caps.dynamic_backlight_capable_edp =
4117                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4118
4119         dc_link_set_default_brightness_aux(link);
4120 }
4121
4122 void dc_link_dp_enable_hpd(const struct dc_link *link)
4123 {
4124         struct link_encoder *encoder = link->link_enc;
4125
4126         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4127                 encoder->funcs->enable_hpd(encoder);
4128 }
4129
4130 void dc_link_dp_disable_hpd(const struct dc_link *link)
4131 {
4132         struct link_encoder *encoder = link->link_enc;
4133
4134         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4135                 encoder->funcs->disable_hpd(encoder);
4136 }
4137
4138 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4139 {
4140         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4141                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4142                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4143                 return true;
4144         else
4145                 return false;
4146 }
4147
4148 static void set_crtc_test_pattern(struct dc_link *link,
4149                                 struct pipe_ctx *pipe_ctx,
4150                                 enum dp_test_pattern test_pattern,
4151                                 enum dp_test_pattern_color_space test_pattern_color_space)
4152 {
4153         enum controller_dp_test_pattern controller_test_pattern;
4154         enum dc_color_depth color_depth = pipe_ctx->
4155                 stream->timing.display_color_depth;
4156         struct bit_depth_reduction_params params;
4157         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4158         int width = pipe_ctx->stream->timing.h_addressable +
4159                 pipe_ctx->stream->timing.h_border_left +
4160                 pipe_ctx->stream->timing.h_border_right;
4161         int height = pipe_ctx->stream->timing.v_addressable +
4162                 pipe_ctx->stream->timing.v_border_bottom +
4163                 pipe_ctx->stream->timing.v_border_top;
4164
4165         memset(&params, 0, sizeof(params));
4166
4167         switch (test_pattern) {
4168         case DP_TEST_PATTERN_COLOR_SQUARES:
4169                 controller_test_pattern =
4170                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4171         break;
4172         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4173                 controller_test_pattern =
4174                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4175         break;
4176         case DP_TEST_PATTERN_VERTICAL_BARS:
4177                 controller_test_pattern =
4178                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4179         break;
4180         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4181                 controller_test_pattern =
4182                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4183         break;
4184         case DP_TEST_PATTERN_COLOR_RAMP:
4185                 controller_test_pattern =
4186                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4187         break;
4188         default:
4189                 controller_test_pattern =
4190                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4191         break;
4192         }
4193
4194         switch (test_pattern) {
4195         case DP_TEST_PATTERN_COLOR_SQUARES:
4196         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4197         case DP_TEST_PATTERN_VERTICAL_BARS:
4198         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4199         case DP_TEST_PATTERN_COLOR_RAMP:
4200         {
4201                 /* disable bit depth reduction */
4202                 pipe_ctx->stream->bit_depth_params = params;
4203                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4204                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4205                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4206                                 controller_test_pattern, color_depth);
4207                 else if (link->dc->hwss.set_disp_pattern_generator) {
4208                         struct pipe_ctx *odm_pipe;
4209                         enum controller_dp_color_space controller_color_space;
4210                         int opp_cnt = 1;
4211                         int offset = 0;
4212                         int dpg_width = width;
4213
4214                         switch (test_pattern_color_space) {
4215                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4216                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4217                                 break;
4218                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4219                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4220                                 break;
4221                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4222                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4223                                 break;
4224                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4225                         default:
4226                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4227                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4228                                 ASSERT(0);
4229                                 break;
4230                         }
4231
4232                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4233                                 opp_cnt++;
4234                         dpg_width = width / opp_cnt;
4235                         offset = dpg_width;
4236
4237                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4238                                         pipe_ctx,
4239                                         controller_test_pattern,
4240                                         controller_color_space,
4241                                         color_depth,
4242                                         NULL,
4243                                         dpg_width,
4244                                         height,
4245                                         0);
4246
4247                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4248                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4249
4250                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4251                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4252                                                 odm_pipe,
4253                                                 controller_test_pattern,
4254                                                 controller_color_space,
4255                                                 color_depth,
4256                                                 NULL,
4257                                                 dpg_width,
4258                                                 height,
4259                                                 offset);
4260                                 offset += offset;
4261                         }
4262                 }
4263         }
4264         break;
4265         case DP_TEST_PATTERN_VIDEO_MODE:
4266         {
4267                 /* restore bitdepth reduction */
4268                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4269                 pipe_ctx->stream->bit_depth_params = params;
4270                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4271                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4272                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4273                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4274                                 color_depth);
4275                 else if (link->dc->hwss.set_disp_pattern_generator) {
4276                         struct pipe_ctx *odm_pipe;
4277                         int opp_cnt = 1;
4278                         int dpg_width = width;
4279
4280                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4281                                 opp_cnt++;
4282
4283                         dpg_width = width / opp_cnt;
4284                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4285                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4286
4287                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4288                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4289                                                 odm_pipe,
4290                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4291                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4292                                                 color_depth,
4293                                                 NULL,
4294                                                 dpg_width,
4295                                                 height,
4296                                                 0);
4297                         }
4298                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4299                                         pipe_ctx,
4300                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4301                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4302                                         color_depth,
4303                                         NULL,
4304                                         dpg_width,
4305                                         height,
4306                                         0);
4307                 }
4308         }
4309         break;
4310
4311         default:
4312         break;
4313         }
4314 }
4315
4316 bool dc_link_dp_set_test_pattern(
4317         struct dc_link *link,
4318         enum dp_test_pattern test_pattern,
4319         enum dp_test_pattern_color_space test_pattern_color_space,
4320         const struct link_training_settings *p_link_settings,
4321         const unsigned char *p_custom_pattern,
4322         unsigned int cust_pattern_size)
4323 {
4324         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4325         struct pipe_ctx *pipe_ctx = NULL;
4326         unsigned int lane;
4327         unsigned int i;
4328         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4329         union dpcd_training_pattern training_pattern;
4330         enum dpcd_phy_test_patterns pattern;
4331
4332         memset(&training_pattern, 0, sizeof(training_pattern));
4333
4334         for (i = 0; i < MAX_PIPES; i++) {
4335                 if (pipes[i].stream == NULL)
4336                         continue;
4337
4338                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4339                         pipe_ctx = &pipes[i];
4340                         break;
4341                 }
4342         }
4343
4344         if (pipe_ctx == NULL)
4345                 return false;
4346
4347         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4348         if (link->test_pattern_enabled && test_pattern ==
4349                         DP_TEST_PATTERN_VIDEO_MODE) {
4350                 /* Set CRTC Test Pattern */
4351                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4352                 dp_set_hw_test_pattern(link, test_pattern,
4353                                 (uint8_t *)p_custom_pattern,
4354                                 (uint32_t)cust_pattern_size);
4355
4356                 /* Unblank Stream */
4357                 link->dc->hwss.unblank_stream(
4358                         pipe_ctx,
4359                         &link->verified_link_cap);
4360                 /* TODO:m_pHwss->MuteAudioEndpoint
4361                  * (pPathMode->pDisplayPath, false);
4362                  */
4363
4364                 /* Reset Test Pattern state */
4365                 link->test_pattern_enabled = false;
4366
4367                 return true;
4368         }
4369
4370         /* Check for PHY Test Patterns */
4371         if (is_dp_phy_pattern(test_pattern)) {
4372                 /* Set DPCD Lane Settings before running test pattern */
4373                 if (p_link_settings != NULL) {
4374                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4375                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4376                 }
4377
4378                 /* Blank stream if running test pattern */
4379                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4380                         /*TODO:
4381                          * m_pHwss->
4382                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4383                          */
4384                         /* Blank stream */
4385                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4386                 }
4387
4388                 dp_set_hw_test_pattern(link, test_pattern,
4389                                 (uint8_t *)p_custom_pattern,
4390                                 (uint32_t)cust_pattern_size);
4391
4392                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4393                         /* Set Test Pattern state */
4394                         link->test_pattern_enabled = true;
4395                         if (p_link_settings != NULL)
4396                                 dpcd_set_link_settings(link,
4397                                                 p_link_settings);
4398                 }
4399
4400                 switch (test_pattern) {
4401                 case DP_TEST_PATTERN_VIDEO_MODE:
4402                         pattern = PHY_TEST_PATTERN_NONE;
4403                         break;
4404                 case DP_TEST_PATTERN_D102:
4405                         pattern = PHY_TEST_PATTERN_D10_2;
4406                         break;
4407                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4408                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4409                         break;
4410                 case DP_TEST_PATTERN_PRBS7:
4411                         pattern = PHY_TEST_PATTERN_PRBS7;
4412                         break;
4413                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4414                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4415                         break;
4416                 case DP_TEST_PATTERN_CP2520_1:
4417                         pattern = PHY_TEST_PATTERN_CP2520_1;
4418                         break;
4419                 case DP_TEST_PATTERN_CP2520_2:
4420                         pattern = PHY_TEST_PATTERN_CP2520_2;
4421                         break;
4422                 case DP_TEST_PATTERN_CP2520_3:
4423                         pattern = PHY_TEST_PATTERN_CP2520_3;
4424                         break;
4425                 default:
4426                         return false;
4427                 }
4428
4429                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4430                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4431                         return false;
4432
4433                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4434                         /* tell receiver that we are sending qualification
4435                          * pattern DP 1.2 or later - DP receiver's link quality
4436                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4437                          * register (0x10B~0x10E)\
4438                          */
4439                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4440                                 link_qual_pattern[lane] =
4441                                                 (unsigned char)(pattern);
4442
4443                         core_link_write_dpcd(link,
4444                                         DP_LINK_QUAL_LANE0_SET,
4445                                         link_qual_pattern,
4446                                         sizeof(link_qual_pattern));
4447                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4448                            link->dpcd_caps.dpcd_rev.raw == 0) {
4449                         /* tell receiver that we are sending qualification
4450                          * pattern DP 1.1a or earlier - DP receiver's link
4451                          * quality pattern is set using
4452                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4453                          * register (0x102). We will use v_1.3 when we are
4454                          * setting test pattern for DP 1.1.
4455                          */
4456                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4457                                             &training_pattern.raw,
4458                                             sizeof(training_pattern));
4459                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4460                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4461                                              &training_pattern.raw,
4462                                              sizeof(training_pattern));
4463                 }
4464         } else {
4465                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4466
4467                 switch (test_pattern_color_space) {
4468                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4469                         color_space = COLOR_SPACE_SRGB;
4470                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4471                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4472                         break;
4473
4474                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4475                         color_space = COLOR_SPACE_YCBCR601;
4476                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4477                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4478                         break;
4479                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4480                         color_space = COLOR_SPACE_YCBCR709;
4481                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4482                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4483                         break;
4484                 default:
4485                         break;
4486                 }
4487
4488                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4489                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4490                                 union dmub_hw_lock_flags hw_locks = { 0 };
4491                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4492
4493                                 hw_locks.bits.lock_dig = 1;
4494                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4495
4496                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4497                                                         true,
4498                                                         &hw_locks,
4499                                                         &inst_flags);
4500                         } else
4501                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4502                                                 pipe_ctx->stream_res.tg);
4503                 }
4504
4505                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4506                 /* update MSA to requested color space */
4507                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4508                                 &pipe_ctx->stream->timing,
4509                                 color_space,
4510                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4511                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4512
4513                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4514                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4515                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4516                         else
4517                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4518                         resource_build_info_frame(pipe_ctx);
4519                         link->dc->hwss.update_info_frame(pipe_ctx);
4520                 }
4521
4522                 /* CRTC Patterns */
4523                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4524                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4525                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4526                                 CRTC_STATE_VACTIVE);
4527                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4528                                 CRTC_STATE_VBLANK);
4529                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4530                                 CRTC_STATE_VACTIVE);
4531
4532                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4533                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4534                                 union dmub_hw_lock_flags hw_locks = { 0 };
4535                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4536
4537                                 hw_locks.bits.lock_dig = 1;
4538                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4539
4540                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4541                                                         false,
4542                                                         &hw_locks,
4543                                                         &inst_flags);
4544                         } else
4545                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4546                                                 pipe_ctx->stream_res.tg);
4547                 }
4548
4549                 /* Set Test Pattern state */
4550                 link->test_pattern_enabled = true;
4551         }
4552
4553         return true;
4554 }
4555
4556 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4557 {
4558         unsigned char mstmCntl;
4559
4560         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4561         if (enable)
4562                 mstmCntl |= DP_MST_EN;
4563         else
4564                 mstmCntl &= (~DP_MST_EN);
4565
4566         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4567 }
4568
4569 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4570 {
4571         union dpcd_edp_config edp_config_set;
4572         bool panel_mode_edp = false;
4573
4574         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4575
4576         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4577
4578                 switch (panel_mode) {
4579                 case DP_PANEL_MODE_EDP:
4580                 case DP_PANEL_MODE_SPECIAL:
4581                         panel_mode_edp = true;
4582                         break;
4583
4584                 default:
4585                                 break;
4586                 }
4587
4588                 /*set edp panel mode in receiver*/
4589                 core_link_read_dpcd(
4590                         link,
4591                         DP_EDP_CONFIGURATION_SET,
4592                         &edp_config_set.raw,
4593                         sizeof(edp_config_set.raw));
4594
4595                 if (edp_config_set.bits.PANEL_MODE_EDP
4596                         != panel_mode_edp) {
4597                         enum dc_status result;
4598
4599                         edp_config_set.bits.PANEL_MODE_EDP =
4600                         panel_mode_edp;
4601                         result = core_link_write_dpcd(
4602                                 link,
4603                                 DP_EDP_CONFIGURATION_SET,
4604                                 &edp_config_set.raw,
4605                                 sizeof(edp_config_set.raw));
4606
4607                         ASSERT(result == DC_OK);
4608                 }
4609         }
4610         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4611                  "eDP panel mode enabled: %d \n",
4612                  link->link_index,
4613                  link->dpcd_caps.panel_mode_edp,
4614                  panel_mode_edp);
4615 }
4616
4617 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4618 {
4619         /* We need to explicitly check that connector
4620          * is not DP. Some Travis_VGA get reported
4621          * by video bios as DP.
4622          */
4623         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4624
4625                 switch (link->dpcd_caps.branch_dev_id) {
4626                 case DP_BRANCH_DEVICE_ID_0022B9:
4627                         /* alternate scrambler reset is required for Travis
4628                          * for the case when external chip does not
4629                          * provide sink device id, alternate scrambler
4630                          * scheme will  be overriden later by querying
4631                          * Encoder features
4632                          */
4633                         if (strncmp(
4634                                 link->dpcd_caps.branch_dev_name,
4635                                 DP_VGA_LVDS_CONVERTER_ID_2,
4636                                 sizeof(
4637                                 link->dpcd_caps.
4638                                 branch_dev_name)) == 0) {
4639                                         return DP_PANEL_MODE_SPECIAL;
4640                         }
4641                         break;
4642                 case DP_BRANCH_DEVICE_ID_00001A:
4643                         /* alternate scrambler reset is required for Travis
4644                          * for the case when external chip does not provide
4645                          * sink device id, alternate scrambler scheme will
4646                          * be overriden later by querying Encoder feature
4647                          */
4648                         if (strncmp(link->dpcd_caps.branch_dev_name,
4649                                 DP_VGA_LVDS_CONVERTER_ID_3,
4650                                 sizeof(
4651                                 link->dpcd_caps.
4652                                 branch_dev_name)) == 0) {
4653                                         return DP_PANEL_MODE_SPECIAL;
4654                         }
4655                         break;
4656                 default:
4657                         break;
4658                 }
4659         }
4660
4661         if (link->dpcd_caps.panel_mode_edp) {
4662                 return DP_PANEL_MODE_EDP;
4663         }
4664
4665         return DP_PANEL_MODE_DEFAULT;
4666 }
4667
4668 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
4669 {
4670         /* FEC has to be "set ready" before the link training.
4671          * The policy is to always train with FEC
4672          * if the sink supports it and leave it enabled on link.
4673          * If FEC is not supported, disable it.
4674          */
4675         struct link_encoder *link_enc = NULL;
4676         enum dc_status status = DC_OK;
4677         uint8_t fec_config = 0;
4678
4679         /* Access link encoder based on whether it is statically
4680          * or dynamically assigned to a link.
4681          */
4682         if (link->is_dig_mapping_flexible &&
4683                         link->dc->res_pool->funcs->link_encs_assign)
4684                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4685         else
4686                 link_enc = link->link_enc;
4687         ASSERT(link_enc);
4688
4689         if (!dc_link_should_enable_fec(link))
4690                 return status;
4691
4692         if (link_enc->funcs->fec_set_ready &&
4693                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4694                 if (ready) {
4695                         fec_config = 1;
4696                         status = core_link_write_dpcd(link,
4697                                         DP_FEC_CONFIGURATION,
4698                                         &fec_config,
4699                                         sizeof(fec_config));
4700                         if (status == DC_OK) {
4701                                 link_enc->funcs->fec_set_ready(link_enc, true);
4702                                 link->fec_state = dc_link_fec_ready;
4703                         } else {
4704                                 link_enc->funcs->fec_set_ready(link->link_enc, false);
4705                                 link->fec_state = dc_link_fec_not_ready;
4706                                 dm_error("dpcd write failed to set fec_ready");
4707                         }
4708                 } else if (link->fec_state == dc_link_fec_ready) {
4709                         fec_config = 0;
4710                         status = core_link_write_dpcd(link,
4711                                         DP_FEC_CONFIGURATION,
4712                                         &fec_config,
4713                                         sizeof(fec_config));
4714                         link_enc->funcs->fec_set_ready(link_enc, false);
4715                         link->fec_state = dc_link_fec_not_ready;
4716                 }
4717         }
4718
4719         return status;
4720 }
4721
4722 void dp_set_fec_enable(struct dc_link *link, bool enable)
4723 {
4724         struct link_encoder *link_enc = NULL;
4725
4726         /* Access link encoder based on whether it is statically
4727          * or dynamically assigned to a link.
4728          */
4729         if (link->is_dig_mapping_flexible &&
4730                         link->dc->res_pool->funcs->link_encs_assign)
4731                 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4732                                 link->dc->current_state, link);
4733         else
4734                 link_enc = link->link_enc;
4735         ASSERT(link_enc);
4736
4737         if (!dc_link_should_enable_fec(link))
4738                 return;
4739
4740         if (link_enc->funcs->fec_set_enable &&
4741                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4742                 if (link->fec_state == dc_link_fec_ready && enable) {
4743                         /* Accord to DP spec, FEC enable sequence can first
4744                          * be transmitted anytime after 1000 LL codes have
4745                          * been transmitted on the link after link training
4746                          * completion. Using 1 lane RBR should have the maximum
4747                          * time for transmitting 1000 LL codes which is 6.173 us.
4748                          * So use 7 microseconds delay instead.
4749                          */
4750                         udelay(7);
4751                         link_enc->funcs->fec_set_enable(link_enc, true);
4752                         link->fec_state = dc_link_fec_enabled;
4753                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4754                         link_enc->funcs->fec_set_enable(link_enc, false);
4755                         link->fec_state = dc_link_fec_ready;
4756                 }
4757         }
4758 }
4759
4760 void dpcd_set_source_specific_data(struct dc_link *link)
4761 {
4762         if (!link->dc->vendor_signature.is_valid) {
4763                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4764                 struct dpcd_amd_signature amd_signature = {0};
4765                 struct dpcd_amd_device_id amd_device_id = {0};
4766
4767                 amd_device_id.device_id_byte1 =
4768                                 (uint8_t)(link->ctx->asic_id.chip_id);
4769                 amd_device_id.device_id_byte2 =
4770                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4771                 amd_device_id.dce_version =
4772                                 (uint8_t)(link->ctx->dce_version);
4773                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4774                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4775
4776                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4777                                 (uint8_t *)(&amd_signature),
4778                                 sizeof(amd_signature));
4779
4780                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4781                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4782                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4783
4784                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4785                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4786                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4787
4788                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4789                                 (uint8_t *)(&amd_signature),
4790                                 sizeof(amd_signature));
4791                 }
4792
4793                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4794                                 (uint8_t *)(&amd_device_id),
4795                                 sizeof(amd_device_id));
4796
4797                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4798                         link->dc->caps.min_horizontal_blanking_period != 0) {
4799
4800                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4801
4802                         result_write_min_hblank = core_link_write_dpcd(link,
4803                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4804                                 sizeof(hblank_size));
4805                 }
4806                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4807                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4808                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4809                                                         result_write_min_hblank,
4810                                                         link->link_index,
4811                                                         link->ctx->dce_version,
4812                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4813                                                         link->dc->caps.min_horizontal_blanking_period,
4814                                                         link->dpcd_caps.branch_dev_id,
4815                                                         link->dpcd_caps.branch_dev_name[0],
4816                                                         link->dpcd_caps.branch_dev_name[1],
4817                                                         link->dpcd_caps.branch_dev_name[2],
4818                                                         link->dpcd_caps.branch_dev_name[3],
4819                                                         link->dpcd_caps.branch_dev_name[4],
4820                                                         link->dpcd_caps.branch_dev_name[5]);
4821         } else {
4822                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4823                                 link->dc->vendor_signature.data.raw,
4824                                 sizeof(link->dc->vendor_signature.data.raw));
4825         }
4826 }
4827
4828 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4829                 bool isHDR,
4830                 uint32_t backlight_millinits,
4831                 uint32_t transition_time_in_ms)
4832 {
4833         struct dpcd_source_backlight_set dpcd_backlight_set;
4834         uint8_t backlight_control = isHDR ? 1 : 0;
4835
4836         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4837                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4838                 return false;
4839
4840         // OLEDs have no PWM, they can only use AUX
4841         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4842                 backlight_control = 1;
4843
4844         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4845         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4846
4847
4848         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4849                         (uint8_t *)(&dpcd_backlight_set),
4850                         sizeof(dpcd_backlight_set)) != DC_OK)
4851                 return false;
4852
4853         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4854                         &backlight_control, 1) != DC_OK)
4855                 return false;
4856
4857         return true;
4858 }
4859
4860 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4861                 uint32_t *backlight_millinits_avg,
4862                 uint32_t *backlight_millinits_peak)
4863 {
4864         union dpcd_source_backlight_get dpcd_backlight_get;
4865
4866         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4867
4868         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4869                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4870                 return false;
4871
4872         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4873                         dpcd_backlight_get.raw,
4874                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4875                 return false;
4876
4877         *backlight_millinits_avg =
4878                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4879         *backlight_millinits_peak =
4880                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4881
4882         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4883         if (*backlight_millinits_avg == 0 ||
4884                         *backlight_millinits_avg > *backlight_millinits_peak)
4885                 return false;
4886
4887         return true;
4888 }
4889
4890 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4891 {
4892         uint8_t backlight_enable = enable ? 1 : 0;
4893
4894         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4895                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4896                 return false;
4897
4898         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4899                 &backlight_enable, 1) != DC_OK)
4900                 return false;
4901
4902         return true;
4903 }
4904
4905 // we read default from 0x320 because we expect BIOS wrote it there
4906 // regular get_backlight_nit reads from panel set at 0x326
4907 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4908 {
4909         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4910                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4911                 return false;
4912
4913         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4914                 (uint8_t *) backlight_millinits,
4915                 sizeof(uint32_t)) != DC_OK)
4916                 return false;
4917
4918         return true;
4919 }
4920
4921 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4922 {
4923         uint32_t default_backlight;
4924
4925         if (link &&
4926                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4927                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4928                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4929                         default_backlight = 150000;
4930                 // if < 5 nits or > 5000, it might be wrong readback
4931                 if (default_backlight < 5000 || default_backlight > 5000000)
4932                         default_backlight = 150000; //
4933
4934                 return dc_link_set_backlight_level_nits(link, true,
4935                                 default_backlight, 0);
4936         }
4937         return false;
4938 }
4939
4940 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4941 {
4942         struct dc_link_settings link_setting;
4943         uint8_t link_bw_set;
4944         uint8_t link_rate_set;
4945         uint32_t req_bw;
4946         union lane_count_set lane_count_set = { {0} };
4947
4948         ASSERT(link || crtc_timing); // invalid input
4949
4950         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4951                         !link->dc->debug.optimize_edp_link_rate)
4952                 return false;
4953
4954
4955         // Read DPCD 00100h to find if standard link rates are set
4956         core_link_read_dpcd(link, DP_LINK_BW_SET,
4957                                 &link_bw_set, sizeof(link_bw_set));
4958
4959         if (link_bw_set) {
4960                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4961                 return true;
4962         }
4963
4964         // Read DPCD 00115h to find the edp link rate set used
4965         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4966                             &link_rate_set, sizeof(link_rate_set));
4967
4968         // Read DPCD 00101h to find out the number of lanes currently set
4969         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4970                                 &lane_count_set.raw, sizeof(lane_count_set));
4971
4972         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4973
4974         decide_edp_link_settings(link, &link_setting, req_bw);
4975
4976         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4977                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4978                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4979                 return true;
4980         }
4981
4982         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4983         return false;
4984 }
4985
4986 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4987 {
4988         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4989                         (link_settings->link_rate <= LINK_RATE_HIGH3))
4990                 return DP_8b_10b_ENCODING;
4991         return DP_UNKNOWN_ENCODING;
4992 }
4993