drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17 #include "inc/link_enc_cfg.h"
  18
  19 /*Travis*/
  20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  21 /*Nutmeg*/
  22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  23
  24 #define DC_LOGGER \
  25         link->ctx->logger
  26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  27
  28 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
  29
  30         /* maximum pre emphasis level allowed for each voltage swing level*/
  31         static const enum dc_pre_emphasis
  32         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  33                                             PRE_EMPHASIS_LEVEL2,
  34                                             PRE_EMPHASIS_LEVEL1,
  35                                             PRE_EMPHASIS_DISABLED };
  36
  37 enum {
  38         POST_LT_ADJ_REQ_LIMIT = 6,
  39         POST_LT_ADJ_REQ_TIMEOUT = 200
  40 };
  41
  42 enum {
  43         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  44         /* to avoid infinite loop where-in the receiver
  45          * switches between different VS
  46          */
  47         LINK_TRAINING_MAX_CR_RETRY = 100
  48 };
  49
  50 static bool decide_fallback_link_setting(
  51                 struct dc_link_settings initial_link_settings,
  52                 struct dc_link_settings *current_link_setting,
  53                 enum link_training_result training_result);
  54 static struct dc_link_settings get_common_supported_link_settings(
  55                 struct dc_link_settings link_setting_a,
  56                 struct dc_link_settings link_setting_b);
  57
  58 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  59                 const struct dc_link_settings *link_settings)
  60 {
  61         union training_aux_rd_interval training_rd_interval;
  62         uint32_t wait_in_micro_secs = 100;
  63
  64         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  65         core_link_read_dpcd(
  66                         link,
  67                         DP_TRAINING_AUX_RD_INTERVAL,
  68                         (uint8_t *)&training_rd_interval,
  69                         sizeof(training_rd_interval));
  70         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  71                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  72         return wait_in_micro_secs;
  73 }
  74
  75 static uint32_t get_eq_training_aux_rd_interval(
  76         struct dc_link *link,
  77         const struct dc_link_settings *link_settings)
  78 {
  79         union training_aux_rd_interval training_rd_interval;
  80         uint32_t wait_in_micro_secs = 400;
  81
  82         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  83         /* overwrite the delay if rev > 1.1*/
  84         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  85                 /* DP 1.2 or later - retrieve delay through
  86                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  87                 core_link_read_dpcd(
  88                         link,
  89                         DP_TRAINING_AUX_RD_INTERVAL,
  90                         (uint8_t *)&training_rd_interval,
  91                         sizeof(training_rd_interval));
  92
  93                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  94                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  95         }
  96
  97         return wait_in_micro_secs;
  98 }
  99
 100 static void wait_for_training_aux_rd_interval(
 101         struct dc_link *link,
 102         uint32_t wait_in_micro_secs)
 103 {
 104         udelay(wait_in_micro_secs);
 105
 106         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 107                 __func__,
 108                 wait_in_micro_secs);
 109 }
 110
 111 static enum dpcd_training_patterns
 112         dc_dp_training_pattern_to_dpcd_training_pattern(
 113         struct dc_link *link,
 114         enum dc_dp_training_pattern pattern)
 115 {
 116         enum dpcd_training_patterns dpcd_tr_pattern =
 117         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 118
 119         switch (pattern) {
 120         case DP_TRAINING_PATTERN_SEQUENCE_1:
 121                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 122                 break;
 123         case DP_TRAINING_PATTERN_SEQUENCE_2:
 124                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 125                 break;
 126         case DP_TRAINING_PATTERN_SEQUENCE_3:
 127                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 128                 break;
 129         case DP_TRAINING_PATTERN_SEQUENCE_4:
 130                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 131                 break;
 132         case DP_TRAINING_PATTERN_VIDEOIDLE:
 133                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 134                 break;
 135         default:
 136                 ASSERT(0);
 137                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 138                         __func__, pattern);
 139                 break;
 140         }
 141
 142         return dpcd_tr_pattern;
 143 }
 144
 145 static void dpcd_set_training_pattern(
 146         struct dc_link *link,
 147         enum dc_dp_training_pattern training_pattern)
 148 {
 149         union dpcd_training_pattern dpcd_pattern = { {0} };
 150
 151         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 152                         dc_dp_training_pattern_to_dpcd_training_pattern(
 153                                         link, training_pattern);
 154
 155         core_link_write_dpcd(
 156                 link,
 157                 DP_TRAINING_PATTERN_SET,
 158                 &dpcd_pattern.raw,
 159                 1);
 160
 161         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 162                 __func__,
 163                 DP_TRAINING_PATTERN_SET,
 164                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 165 }
 166
 167 static enum dc_dp_training_pattern decide_cr_training_pattern(
 168                 const struct dc_link_settings *link_settings)
 169 {
 170         return DP_TRAINING_PATTERN_SEQUENCE_1;
 171 }
 172
 173 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 174                 const struct dc_link_settings *link_settings)
 175 {
 176         struct link_encoder *link_enc;
 177         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 178         struct encoder_feature_support *features;
 179         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 180
 181         /* Access link encoder capability based on whether it is statically
 182          * or dynamically assigned to a link.
 183          */
 184         if (link->is_dig_mapping_flexible &&
 185                         link->dc->res_pool->funcs->link_encs_assign)
 186                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 187         else
 188                 link_enc = link->link_enc;
 189         ASSERT(link_enc);
 190         features = &link_enc->features;
 191
 192         if (features->flags.bits.IS_TPS3_CAPABLE)
 193                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 194
 195         if (features->flags.bits.IS_TPS4_CAPABLE)
 196                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 197
 198         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 199                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 200                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 201
 202         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 203                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 204                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 205
 206         return DP_TRAINING_PATTERN_SEQUENCE_2;
 207 }
 208
 209 static void dpcd_set_link_settings(
 210         struct dc_link *link,
 211         const struct link_training_settings *lt_settings)
 212 {
 213         uint8_t rate;
 214
 215         union down_spread_ctrl downspread = { {0} };
 216         union lane_count_set lane_count_set = { {0} };
 217
 218         downspread.raw = (uint8_t)
 219         (lt_settings->link_settings.link_spread);
 220
 221         lane_count_set.bits.LANE_COUNT_SET =
 222         lt_settings->link_settings.lane_count;
 223
 224         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 225         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 226
 227
 228         if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 229                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 230                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 231         }
 232
 233         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 234                 &downspread.raw, sizeof(downspread));
 235
 236         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 237                 &lane_count_set.raw, 1);
 238
 239         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 240                         lt_settings->link_settings.use_link_rate_set == true) {
 241                 rate = 0;
 242                 /* WA for some MUX chips that will power down with eDP and lose supported
 243                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 244                  * MUX chip gets link rate set back before link training.
 245                  */
 246                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 247                         uint8_t supported_link_rates[16];
 248
 249                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 250                                         supported_link_rates, sizeof(supported_link_rates));
 251                 }
 252                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 253                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 254                                 &lt_settings->link_settings.link_rate_set, 1);
 255         } else {
 256                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 257                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 258         }
 259
 260         if (rate) {
 261                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 262                         __func__,
 263                         DP_LINK_BW_SET,
 264                         lt_settings->link_settings.link_rate,
 265                         DP_LANE_COUNT_SET,
 266                         lt_settings->link_settings.lane_count,
 267                         lt_settings->enhanced_framing,
 268                         DP_DOWNSPREAD_CTRL,
 269                         lt_settings->link_settings.link_spread);
 270         } else {
 271                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 272                         __func__,
 273                         DP_LINK_RATE_SET,
 274                         lt_settings->link_settings.link_rate_set,
 275                         DP_LANE_COUNT_SET,
 276                         lt_settings->link_settings.lane_count,
 277                         lt_settings->enhanced_framing,
 278                         DP_DOWNSPREAD_CTRL,
 279                         lt_settings->link_settings.link_spread);
 280         }
 281 }
 282
 283 static uint8_t dc_dp_initialize_scrambling_data_symbols(
 284         struct dc_link *link,
 285         enum dc_dp_training_pattern pattern)
 286 {
 287         uint8_t disable_scrabled_data_symbols = 0;
 288
 289         switch (pattern) {
 290         case DP_TRAINING_PATTERN_SEQUENCE_1:
 291         case DP_TRAINING_PATTERN_SEQUENCE_2:
 292         case DP_TRAINING_PATTERN_SEQUENCE_3:
 293                 disable_scrabled_data_symbols = 1;
 294                 break;
 295         case DP_TRAINING_PATTERN_SEQUENCE_4:
 296                 disable_scrabled_data_symbols = 0;
 297                 break;
 298         default:
 299                 ASSERT(0);
 300                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 301                         __func__, pattern);
 302                 break;
 303         }
 304         return disable_scrabled_data_symbols;
 305 }
 306
 307 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 308 {
 309         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 310 }
 311
 312 static void dpcd_set_lt_pattern_and_lane_settings(
 313         struct dc_link *link,
 314         const struct link_training_settings *lt_settings,
 315         enum dc_dp_training_pattern pattern,
 316         uint32_t offset)
 317 {
 318         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 319
 320         uint32_t dpcd_base_lt_offset;
 321
 322         uint8_t dpcd_lt_buffer[5] = {0};
 323         union dpcd_training_pattern dpcd_pattern = { {0} };
 324         uint32_t lane;
 325         uint32_t size_in_bytes;
 326         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 327         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 328
 329         if (is_repeater(link, offset))
 330                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 331                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 332
 333         /*****************************************************************
 334         * DpcdAddress_TrainingPatternSet
 335         *****************************************************************/
 336         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 337                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 338
 339         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 340                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 341
 342         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 343                 = dpcd_pattern.raw;
 344
 345         if (is_repeater(link, offset)) {
 346                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 347                         __func__,
 348                         offset,
 349                         dpcd_base_lt_offset,
 350                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 351         } else {
 352                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 353                         __func__,
 354                         dpcd_base_lt_offset,
 355                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 356         }
 357         /*****************************************************************
 358         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 359         *****************************************************************/
 360         for (lane = 0; lane <
 361                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 362
 363                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 364                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 365                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 366                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 367
 368                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 369                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 370                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 371                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 372                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 373                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 374         }
 375
 376         /* concatenate everything into one buffer*/
 377
 378         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 379
 380          // 0x00103 - 0x00102
 381         memmove(
 382                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 383                 dpcd_lane,
 384                 size_in_bytes);
 385
 386         if (is_repeater(link, offset)) {
 387                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 388                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 389                         __func__,
 390                         offset,
 391                         dpcd_base_lt_offset,
 392                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 393                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 394                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 395                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 396         } else {
 397                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 398                         __func__,
 399                         dpcd_base_lt_offset,
 400                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 401                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 402                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 403                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 404         }
 405         if (edp_workaround) {
 406                 /* for eDP write in 2 parts because the 5-byte burst is
 407                 * causing issues on some eDP panels (EPR#366724)
 408                 */
 409                 core_link_write_dpcd(
 410                         link,
 411                         DP_TRAINING_PATTERN_SET,
 412                         &dpcd_pattern.raw,
 413                         sizeof(dpcd_pattern.raw));
 414
 415                 core_link_write_dpcd(
 416                         link,
 417                         DP_TRAINING_LANE0_SET,
 418                         (uint8_t *)(dpcd_lane),
 419                         size_in_bytes);
 420
 421                 } else
 422                 /* write it all in (1 + number-of-lanes)-byte burst*/
 423                         core_link_write_dpcd(
 424                                 link,
 425                                 dpcd_base_lt_offset,
 426                                 dpcd_lt_buffer,
 427                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 428
 429         link->cur_lane_setting = lt_settings->lane_settings[0];
 430 }
 431
 432 static bool is_cr_done(enum dc_lane_count ln_count,
 433         union lane_status *dpcd_lane_status)
 434 {
 435         uint32_t lane;
 436         /*LANEx_CR_DONE bits All 1's?*/
 437         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 438                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 439                         return false;
 440         }
 441         return true;
 442 }
 443
 444 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 445                 union lane_status *dpcd_lane_status)
 446 {
 447         bool done = true;
 448         uint32_t lane;
 449         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 450                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 451                         done = false;
 452         return done;
 453 }
 454
 455 static bool is_symbol_locked(enum dc_lane_count ln_count,
 456                 union lane_status *dpcd_lane_status)
 457 {
 458         bool locked = true;
 459         uint32_t lane;
 460         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 461                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 462                         locked = false;
 463         return locked;
 464 }
 465
 466 static inline bool is_interlane_aligned(union lane_align_status_updated align_status)
 467 {
 468         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 469 }
 470
 471 static void update_drive_settings(
 472                 struct link_training_settings *dest,
 473                 struct link_training_settings src)
 474 {
 475         uint32_t lane;
 476         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 477                 if (dest->voltage_swing == NULL)
 478                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 479                 else
 480                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 481
 482                 if (dest->pre_emphasis == NULL)
 483                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 484                 else
 485                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 486
 487                 if (dest->post_cursor2 == NULL)
 488                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 489                 else
 490                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 491         }
 492 }
 493
 494 static uint8_t get_nibble_at_index(const uint8_t *buf,
 495         uint32_t index)
 496 {
 497         uint8_t nibble;
 498         nibble = buf[index / 2];
 499
 500         if (index % 2)
 501                 nibble >>= 4;
 502         else
 503                 nibble &= 0x0F;
 504
 505         return nibble;
 506 }
 507
 508 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 509         enum dc_voltage_swing voltage)
 510 {
 511         enum dc_pre_emphasis pre_emphasis;
 512         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 513
 514         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 515                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 516
 517         return pre_emphasis;
 518
 519 }
 520
 521 static void find_max_drive_settings(
 522         const struct link_training_settings *link_training_setting,
 523         struct link_training_settings *max_lt_setting)
 524 {
 525         uint32_t lane;
 526         struct dc_lane_settings max_requested;
 527
 528         max_requested.VOLTAGE_SWING =
 529                 link_training_setting->
 530                 lane_settings[0].VOLTAGE_SWING;
 531         max_requested.PRE_EMPHASIS =
 532                 link_training_setting->
 533                 lane_settings[0].PRE_EMPHASIS;
 534         /*max_requested.postCursor2 =
 535          * link_training_setting->laneSettings[0].postCursor2;*/
 536
 537         /* Determine what the maximum of the requested settings are*/
 538         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 539                         lane++) {
 540                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 541                         max_requested.VOLTAGE_SWING)
 542
 543                         max_requested.VOLTAGE_SWING =
 544                         link_training_setting->
 545                         lane_settings[lane].VOLTAGE_SWING;
 546
 547                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 548                                 max_requested.PRE_EMPHASIS)
 549                         max_requested.PRE_EMPHASIS =
 550                         link_training_setting->
 551                         lane_settings[lane].PRE_EMPHASIS;
 552
 553                 /*
 554                 if (link_training_setting->laneSettings[lane].postCursor2 >
 555                  max_requested.postCursor2)
 556                 {
 557                 max_requested.postCursor2 =
 558                 link_training_setting->laneSettings[lane].postCursor2;
 559                 }
 560                 */
 561         }
 562
 563         /* make sure the requested settings are
 564          * not higher than maximum settings*/
 565         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 566                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 567
 568         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 569                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 570         /*
 571         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 572         max_requested.postCursor2 = PostCursor2_MaxLevel;
 573         */
 574
 575         /* make sure the pre-emphasis matches the voltage swing*/
 576         if (max_requested.PRE_EMPHASIS >
 577                 get_max_pre_emphasis_for_voltage_swing(
 578                         max_requested.VOLTAGE_SWING))
 579                 max_requested.PRE_EMPHASIS =
 580                 get_max_pre_emphasis_for_voltage_swing(
 581                         max_requested.VOLTAGE_SWING);
 582
 583         /*
 584          * Post Cursor2 levels are completely independent from
 585          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 586          * can only be applied to each allowable combination of voltage
 587          * swing and pre-emphasis levels */
 588          /* if ( max_requested.postCursor2 >
 589           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 590           *  max_requested.postCursor2 =
 591           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 592           */
 593
 594         max_lt_setting->link_settings.link_rate =
 595                 link_training_setting->link_settings.link_rate;
 596         max_lt_setting->link_settings.lane_count =
 597         link_training_setting->link_settings.lane_count;
 598         max_lt_setting->link_settings.link_spread =
 599                 link_training_setting->link_settings.link_spread;
 600
 601         for (lane = 0; lane <
 602                 link_training_setting->link_settings.lane_count;
 603                 lane++) {
 604                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 605                         max_requested.VOLTAGE_SWING;
 606                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 607                         max_requested.PRE_EMPHASIS;
 608                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 609                  * max_requested.postCursor2;
 610                  */
 611         }
 612
 613 }
 614
 615 static void get_lane_status_and_drive_settings(
 616         struct dc_link *link,
 617         const struct link_training_settings *link_training_setting,
 618         union lane_status *ln_status,
 619         union lane_align_status_updated *ln_status_updated,
 620         struct link_training_settings *req_settings,
 621         uint32_t offset)
 622 {
 623         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 624         uint8_t lane_adjust_offset = 4;
 625         unsigned int lane01_adjust_address;
 626         uint8_t dpcd_buf[6] = {0};
 627         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 628         struct link_training_settings request_settings = { {0} };
 629         uint32_t lane;
 630
 631         memset(req_settings, '\0', sizeof(struct link_training_settings));
 632
 633         if (is_repeater(link, offset)) {
 634                 lane01_status_address =
 635                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 636                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 637                 lane_adjust_offset = 3;
 638         }
 639
 640         core_link_read_dpcd(
 641                 link,
 642                 lane01_status_address,
 643                 (uint8_t *)(dpcd_buf),
 644                 sizeof(dpcd_buf));
 645
 646         for (lane = 0; lane <
 647                 (uint32_t)(link_training_setting->link_settings.lane_count);
 648                 lane++) {
 649
 650                 ln_status[lane].raw =
 651                         get_nibble_at_index(&dpcd_buf[0], lane);
 652                 dpcd_lane_adjust[lane].raw =
 653                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 654         }
 655
 656         ln_status_updated->raw = dpcd_buf[2];
 657
 658         if (is_repeater(link, offset)) {
 659                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 660                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 661                         __func__,
 662                         offset,
 663                         lane01_status_address, dpcd_buf[0],
 664                         lane01_status_address + 1, dpcd_buf[1]);
 665         } else {
 666                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 667                         __func__,
 668                         lane01_status_address, dpcd_buf[0],
 669                         lane01_status_address + 1, dpcd_buf[1]);
 670         }
 671         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 672
 673         if (is_repeater(link, offset))
 674                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 675                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 676
 677         if (is_repeater(link, offset)) {
 678                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 679                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 680                                         __func__,
 681                                         offset,
 682                                         lane01_adjust_address,
 683                                         dpcd_buf[lane_adjust_offset],
 684                                         lane01_adjust_address + 1,
 685                                         dpcd_buf[lane_adjust_offset + 1]);
 686         } else {
 687                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 688                         __func__,
 689                         lane01_adjust_address,
 690                         dpcd_buf[lane_adjust_offset],
 691                         lane01_adjust_address + 1,
 692                         dpcd_buf[lane_adjust_offset + 1]);
 693         }
 694
 695         /*copy to req_settings*/
 696         request_settings.link_settings.lane_count =
 697                 link_training_setting->link_settings.lane_count;
 698         request_settings.link_settings.link_rate =
 699                 link_training_setting->link_settings.link_rate;
 700         request_settings.link_settings.link_spread =
 701                 link_training_setting->link_settings.link_spread;
 702
 703         for (lane = 0; lane <
 704                 (uint32_t)(link_training_setting->link_settings.lane_count);
 705                 lane++) {
 706
 707                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 708                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 709                                 VOLTAGE_SWING_LANE);
 710                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 711                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 712                                 PRE_EMPHASIS_LANE);
 713         }
 714
 715         /*Note: for postcursor2, read adjusted
 716          * postcursor2 settings from*/
 717         /*DpcdAddress_AdjustRequestPostCursor2 =
 718          *0x020C (not implemented yet)*/
 719
 720         /* we find the maximum of the requested settings across all lanes*/
 721         /* and set this maximum for all lanes*/
 722         find_max_drive_settings(&request_settings, req_settings);
 723
 724         /* if post cursor 2 is needed in the future,
 725          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 726          */
 727
 728 }
 729
 730 static void dpcd_set_lane_settings(
 731         struct dc_link *link,
 732         const struct link_training_settings *link_training_setting,
 733         uint32_t offset)
 734 {
 735         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 736         uint32_t lane;
 737         unsigned int lane0_set_address;
 738
 739         lane0_set_address = DP_TRAINING_LANE0_SET;
 740
 741         if (is_repeater(link, offset))
 742                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 743                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 744
 745         for (lane = 0; lane <
 746                 (uint32_t)(link_training_setting->
 747                 link_settings.lane_count);
 748                 lane++) {
 749                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 750                         (uint8_t)(link_training_setting->
 751                         lane_settings[lane].VOLTAGE_SWING);
 752                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 753                         (uint8_t)(link_training_setting->
 754                         lane_settings[lane].PRE_EMPHASIS);
 755                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 756                         (link_training_setting->
 757                         lane_settings[lane].VOLTAGE_SWING ==
 758                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 759                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 760                         (link_training_setting->
 761                         lane_settings[lane].PRE_EMPHASIS ==
 762                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 763         }
 764
 765         core_link_write_dpcd(link,
 766                 lane0_set_address,
 767                 (uint8_t *)(dpcd_lane),
 768                 link_training_setting->link_settings.lane_count);
 769
 770         /*
 771         if (LTSettings.link.rate == LinkRate_High2)
 772         {
 773                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 774                 for ( uint32_t lane = 0;
 775                 lane < lane_count_DPMax; lane++)
 776                 {
 777                         dpcd_lane2[lane].bits.post_cursor2_set =
 778                         static_cast<unsigned char>(
 779                         LTSettings.laneSettings[lane].postCursor2);
 780                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 781                 }
 782                 m_pDpcdAccessSrv->WriteDpcdData(
 783                 DpcdAddress_Lane0Set2,
 784                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 785                 LTSettings.link.lanes);
 786         }
 787         */
 788
 789         if (is_repeater(link, offset)) {
 790                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 791                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 792                         __func__,
 793                         offset,
 794                         lane0_set_address,
 795                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 796                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 797                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 798                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 799
 800         } else {
 801                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 802                         __func__,
 803                         lane0_set_address,
 804                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 805                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 806                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 807                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 808         }
 809         link->cur_lane_setting = link_training_setting->lane_settings[0];
 810
 811 }
 812
 813 static bool is_max_vs_reached(
 814         const struct link_training_settings *lt_settings)
 815 {
 816         uint32_t lane;
 817         for (lane = 0; lane <
 818                 (uint32_t)(lt_settings->link_settings.lane_count);
 819                 lane++) {
 820                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 821                         == VOLTAGE_SWING_MAX_LEVEL)
 822                         return true;
 823         }
 824         return false;
 825
 826 }
 827
 828 static bool perform_post_lt_adj_req_sequence(
 829         struct dc_link *link,
 830         struct link_training_settings *lt_settings)
 831 {
 832         enum dc_lane_count lane_count =
 833         lt_settings->link_settings.lane_count;
 834
 835         uint32_t adj_req_count;
 836         uint32_t adj_req_timer;
 837         bool req_drv_setting_changed;
 838         uint32_t lane;
 839
 840         req_drv_setting_changed = false;
 841         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 842         adj_req_count++) {
 843
 844                 req_drv_setting_changed = false;
 845
 846                 for (adj_req_timer = 0;
 847                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 848                         adj_req_timer++) {
 849
 850                         struct link_training_settings req_settings;
 851                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 852                         union lane_align_status_updated
 853                                 dpcd_lane_status_updated;
 854
 855                         get_lane_status_and_drive_settings(
 856                         link,
 857                         lt_settings,
 858                         dpcd_lane_status,
 859                         &dpcd_lane_status_updated,
 860                         &req_settings,
 861                         DPRX);
 862
 863                         if (dpcd_lane_status_updated.bits.
 864                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 865                                 return true;
 866
 867                         if (!is_cr_done(lane_count, dpcd_lane_status))
 868                                 return false;
 869
 870                         if (!is_ch_eq_done(lane_count, dpcd_lane_status) ||
 871                                         !is_symbol_locked(lane_count, dpcd_lane_status) ||
 872                                         !is_interlane_aligned(dpcd_lane_status_updated))
 873                                 return false;
 874
 875                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 876
 877                                 if (lt_settings->
 878                                 lane_settings[lane].VOLTAGE_SWING !=
 879                                 req_settings.lane_settings[lane].
 880                                 VOLTAGE_SWING ||
 881                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 882                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 883
 884                                         req_drv_setting_changed = true;
 885                                         break;
 886                                 }
 887                         }
 888
 889                         if (req_drv_setting_changed) {
 890                                 update_drive_settings(
 891                                         lt_settings, req_settings);
 892
 893                                 dc_link_dp_set_drive_settings(link,
 894                                                 lt_settings);
 895                                 break;
 896                         }
 897
 898                         msleep(1);
 899                 }
 900
 901                 if (!req_drv_setting_changed) {
 902                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 903                                 __func__);
 904
 905                         ASSERT(0);
 906                         return true;
 907                 }
 908         }
 909         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 910                 __func__);
 911
 912         ASSERT(0);
 913         return true;
 914
 915 }
 916
 917 /* Only used for channel equalization */
 918 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 919 {
 920         unsigned int aux_rd_interval_us = 400;
 921
 922         switch (dpcd_aux_read_interval) {
 923         case 0x01:
 924                 aux_rd_interval_us = 4000;
 925                 break;
 926         case 0x02:
 927                 aux_rd_interval_us = 8000;
 928                 break;
 929         case 0x03:
 930                 aux_rd_interval_us = 12000;
 931                 break;
 932         case 0x04:
 933                 aux_rd_interval_us = 16000;
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return aux_rd_interval_us;
 940 }
 941
 942 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 943                                         union lane_status *dpcd_lane_status)
 944 {
 945         enum link_training_result result = LINK_TRAINING_SUCCESS;
 946
 947         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 948                 result = LINK_TRAINING_CR_FAIL_LANE0;
 949         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 950                 result = LINK_TRAINING_CR_FAIL_LANE1;
 951         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 952                 result = LINK_TRAINING_CR_FAIL_LANE23;
 953         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 954                 result = LINK_TRAINING_CR_FAIL_LANE23;
 955         return result;
 956 }
 957
 958 static enum link_training_result perform_channel_equalization_sequence(
 959         struct dc_link *link,
 960         struct link_training_settings *lt_settings,
 961         uint32_t offset)
 962 {
 963         struct link_training_settings req_settings;
 964         enum dc_dp_training_pattern tr_pattern;
 965         uint32_t retries_ch_eq;
 966         uint32_t wait_time_microsec;
 967         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 968         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 969         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 970
 971         /* Note: also check that TPS4 is a supported feature*/
 972
 973         tr_pattern = lt_settings->pattern_for_eq;
 974
 975         if (is_repeater(link, offset))
 976                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 977
 978         dp_set_hw_training_pattern(link, tr_pattern, offset);
 979
 980         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 981                 retries_ch_eq++) {
 982
 983                 dp_set_hw_lane_settings(link, lt_settings, offset);
 984
 985                 /* 2. update DPCD*/
 986                 if (!retries_ch_eq)
 987                         /* EPR #361076 - write as a 5-byte burst,
 988                          * but only for the 1-st iteration
 989                          */
 990
 991                         dpcd_set_lt_pattern_and_lane_settings(
 992                                 link,
 993                                 lt_settings,
 994                                 tr_pattern, offset);
 995                 else
 996                         dpcd_set_lane_settings(link, lt_settings, offset);
 997
 998                 /* 3. wait for receiver to lock-on*/
 999                 wait_time_microsec = lt_settings->eq_pattern_time;
1000
1001                 if (is_repeater(link, offset))
1002                         wait_time_microsec =
1003                                         translate_training_aux_read_interval(
1004                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1005
1006                 wait_for_training_aux_rd_interval(
1007                                 link,
1008                                 wait_time_microsec);
1009
1010                 /* 4. Read lane status and requested
1011                  * drive settings as set by the sink*/
1012
1013                 get_lane_status_and_drive_settings(
1014                         link,
1015                         lt_settings,
1016                         dpcd_lane_status,
1017                         &dpcd_lane_status_updated,
1018                         &req_settings,
1019                         offset);
1020
1021                 /* 5. check CR done*/
1022                 if (!is_cr_done(lane_count, dpcd_lane_status))
1023                         return LINK_TRAINING_EQ_FAIL_CR;
1024
1025                 /* 6. check CHEQ done*/
1026                 if (is_ch_eq_done(lane_count, dpcd_lane_status) &&
1027                                 is_symbol_locked(lane_count, dpcd_lane_status) &&
1028                                 is_interlane_aligned(dpcd_lane_status_updated))
1029                         return LINK_TRAINING_SUCCESS;
1030
1031                 /* 7. update VS/PE/PC2 in lt_settings*/
1032                 update_drive_settings(lt_settings, req_settings);
1033         }
1034
1035         return LINK_TRAINING_EQ_FAIL_EQ;
1036
1037 }
1038 #define TRAINING_AUX_RD_INTERVAL 100 //us
1039
1040 static void start_clock_recovery_pattern_early(struct dc_link *link,
1041                 struct link_training_settings *lt_settings,
1042                 uint32_t offset)
1043 {
1044         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1045                         __func__);
1046         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1047         dp_set_hw_lane_settings(link, lt_settings, offset);
1048         udelay(400);
1049 }
1050
1051 static enum link_training_result perform_clock_recovery_sequence(
1052         struct dc_link *link,
1053         struct link_training_settings *lt_settings,
1054         uint32_t offset)
1055 {
1056         uint32_t retries_cr;
1057         uint32_t retry_count;
1058         uint32_t wait_time_microsec;
1059         struct link_training_settings req_settings;
1060         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1061         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1062         union lane_align_status_updated dpcd_lane_status_updated;
1063
1064         retries_cr = 0;
1065         retry_count = 0;
1066
1067         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1068                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1069
1070         /* najeeb - The synaptics MST hub can put the LT in
1071         * infinite loop by switching the VS
1072         */
1073         /* between level 0 and level 1 continuously, here
1074         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1075         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1076                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1077
1078                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1079                 memset(&dpcd_lane_status_updated, '\0',
1080                 sizeof(dpcd_lane_status_updated));
1081
1082                 /* 1. call HWSS to set lane settings*/
1083                 dp_set_hw_lane_settings(
1084                                 link,
1085                                 lt_settings,
1086                                 offset);
1087
1088                 /* 2. update DPCD of the receiver*/
1089                 if (!retry_count)
1090                         /* EPR #361076 - write as a 5-byte burst,
1091                          * but only for the 1-st iteration.*/
1092                         dpcd_set_lt_pattern_and_lane_settings(
1093                                         link,
1094                                         lt_settings,
1095                                         lt_settings->pattern_for_cr,
1096                                         offset);
1097                 else
1098                         dpcd_set_lane_settings(
1099                                         link,
1100                                         lt_settings,
1101                                         offset);
1102
1103                 /* 3. wait receiver to lock-on*/
1104                 wait_time_microsec = lt_settings->cr_pattern_time;
1105
1106                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1107                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1108
1109                 wait_for_training_aux_rd_interval(
1110                                 link,
1111                                 wait_time_microsec);
1112
1113                 /* 4. Read lane status and requested drive
1114                 * settings as set by the sink
1115                 */
1116                 get_lane_status_and_drive_settings(
1117                                 link,
1118                                 lt_settings,
1119                                 dpcd_lane_status,
1120                                 &dpcd_lane_status_updated,
1121                                 &req_settings,
1122                                 offset);
1123
1124                 /* 5. check CR done*/
1125                 if (is_cr_done(lane_count, dpcd_lane_status))
1126                         return LINK_TRAINING_SUCCESS;
1127
1128                 /* 6. max VS reached*/
1129                 if (is_max_vs_reached(lt_settings))
1130                         break;
1131
1132                 /* 7. same lane settings*/
1133                 /* Note: settings are the same for all lanes,
1134                  * so comparing first lane is sufficient*/
1135                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1136                         req_settings.lane_settings[0].VOLTAGE_SWING)
1137                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1138                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1139                         retries_cr++;
1140                 else
1141                         retries_cr = 0;
1142
1143                 /* 8. update VS/PE/PC2 in lt_settings*/
1144                 update_drive_settings(lt_settings, req_settings);
1145
1146                 retry_count++;
1147         }
1148
1149         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1150                 ASSERT(0);
1151                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1152                         __func__,
1153                         LINK_TRAINING_MAX_CR_RETRY);
1154
1155         }
1156
1157         return get_cr_failure(lane_count, dpcd_lane_status);
1158 }
1159
1160 static inline enum link_training_result dp_transition_to_video_idle(
1161         struct dc_link *link,
1162         struct link_training_settings *lt_settings,
1163         enum link_training_result status)
1164 {
1165         union lane_count_set lane_count_set = { {0} };
1166
1167         /* 4. mainlink output idle pattern*/
1168         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1169
1170         /*
1171          * 5. post training adjust if required
1172          * If the upstream DPTX and downstream DPRX both support TPS4,
1173          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1174          */
1175         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1176                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
1177                 return status;
1178
1179         if (status == LINK_TRAINING_SUCCESS &&
1180                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1181                 status = LINK_TRAINING_LQA_FAIL;
1182
1183         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1184         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1185         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1186
1187         core_link_write_dpcd(
1188                 link,
1189                 DP_LANE_COUNT_SET,
1190                 &lane_count_set.raw,
1191                 sizeof(lane_count_set));
1192
1193         return status;
1194 }
1195
1196 enum link_training_result dp_check_link_loss_status(
1197         struct dc_link *link,
1198         const struct link_training_settings *link_training_setting)
1199 {
1200         enum link_training_result status = LINK_TRAINING_SUCCESS;
1201         union lane_status lane_status;
1202         uint8_t dpcd_buf[6] = {0};
1203         uint32_t lane;
1204
1205         core_link_read_dpcd(
1206                         link,
1207                         DP_SINK_COUNT,
1208                         (uint8_t *)(dpcd_buf),
1209                         sizeof(dpcd_buf));
1210
1211         /*parse lane status*/
1212         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1213                 /*
1214                  * check lanes status
1215                  */
1216                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1217
1218                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1219                         !lane_status.bits.CR_DONE_0 ||
1220                         !lane_status.bits.SYMBOL_LOCKED_0) {
1221                         /* if one of the channel equalization, clock
1222                          * recovery or symbol lock is dropped
1223                          * consider it as (link has been
1224                          * dropped) dp sink status has changed
1225                          */
1226                         status = LINK_TRAINING_LINK_LOSS;
1227                         break;
1228                 }
1229         }
1230
1231         return status;
1232 }
1233
1234 static inline void decide_8b_10b_training_settings(
1235          struct dc_link *link,
1236         const struct dc_link_settings *link_setting,
1237         const struct dc_link_training_overrides *overrides,
1238         struct link_training_settings *lt_settings)
1239 {
1240         uint32_t lane;
1241
1242         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1243
1244         /* Initialize link settings */
1245         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1246         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1247
1248         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1249                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1250         else
1251                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1252
1253         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1254                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1255         else
1256                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1257
1258         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1259
1260         /* TODO hard coded to SS for now
1261          * lt_settings.link_settings.link_spread =
1262          * dal_display_path_is_ss_supported(
1263          * path_mode->display_path) ?
1264          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1265          * LINK_SPREAD_DISABLED;
1266          */
1267         /* Initialize link spread */
1268         if (link->dp_ss_off)
1269                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1270         else if (overrides->downspread != NULL)
1271                 lt_settings->link_settings.link_spread
1272                         = *overrides->downspread
1273                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1274                         : LINK_SPREAD_DISABLED;
1275         else
1276                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1277
1278         /* Initialize lane settings overrides */
1279         if (overrides->voltage_swing != NULL)
1280                 lt_settings->voltage_swing = overrides->voltage_swing;
1281
1282         if (overrides->pre_emphasis != NULL)
1283                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1284
1285         if (overrides->post_cursor2 != NULL)
1286                 lt_settings->post_cursor2 = overrides->post_cursor2;
1287
1288         /* Initialize lane settings (VS/PE/PC2) */
1289         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1290                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1291                         lt_settings->voltage_swing != NULL ?
1292                         *lt_settings->voltage_swing :
1293                         VOLTAGE_SWING_LEVEL0;
1294                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1295                         lt_settings->pre_emphasis != NULL ?
1296                         *lt_settings->pre_emphasis
1297                         : PRE_EMPHASIS_DISABLED;
1298                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1299                         lt_settings->post_cursor2 != NULL ?
1300                         *lt_settings->post_cursor2
1301                         : POST_CURSOR2_DISABLED;
1302         }
1303
1304         /* Initialize training timings */
1305         if (overrides->cr_pattern_time != NULL)
1306                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1307         else
1308                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1309
1310         if (overrides->eq_pattern_time != NULL)
1311                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1312         else
1313                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1314
1315         if (overrides->pattern_for_cr != NULL)
1316                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1317         else
1318                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1319         if (overrides->pattern_for_eq != NULL)
1320                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1321         else
1322                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1323
1324         if (overrides->enhanced_framing != NULL)
1325                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1326         else
1327                 lt_settings->enhanced_framing = 1;
1328 }
1329
1330 static void decide_training_settings(
1331                 struct dc_link *link,
1332                 const struct dc_link_settings *link_settings,
1333                 const struct dc_link_training_overrides *overrides,
1334                 struct link_training_settings *lt_settings)
1335 {
1336         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1337                 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1338 }
1339
1340
1341 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1342 {
1343         switch (lttpr_repeater_count) {
1344         case 0x80: // 1 lttpr repeater
1345                 return 1;
1346         case 0x40: // 2 lttpr repeaters
1347                 return 2;
1348         case 0x20: // 3 lttpr repeaters
1349                 return 3;
1350         case 0x10: // 4 lttpr repeaters
1351                 return 4;
1352         case 0x08: // 5 lttpr repeaters
1353                 return 5;
1354         case 0x04: // 6 lttpr repeaters
1355                 return 6;
1356         case 0x02: // 7 lttpr repeaters
1357                 return 7;
1358         case 0x01: // 8 lttpr repeaters
1359                 return 8;
1360         default:
1361                 break;
1362         }
1363         return 0; // invalid value
1364 }
1365
1366 static void configure_lttpr_mode_transparent(struct dc_link *link)
1367 {
1368         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1369
1370         core_link_write_dpcd(link,
1371                         DP_PHY_REPEATER_MODE,
1372                         (uint8_t *)&repeater_mode,
1373                         sizeof(repeater_mode));
1374 }
1375
1376 static void configure_lttpr_mode_non_transparent(struct dc_link *link)
1377 {
1378         /* aux timeout is already set to extended */
1379         /* RESET/SET lttpr mode to enable non transparent mode */
1380         uint8_t repeater_cnt;
1381         uint32_t aux_interval_address;
1382         uint8_t repeater_id;
1383         enum dc_status result = DC_ERROR_UNEXPECTED;
1384         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1385
1386         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1387         result = core_link_write_dpcd(link,
1388                         DP_PHY_REPEATER_MODE,
1389                         (uint8_t *)&repeater_mode,
1390                         sizeof(repeater_mode));
1391
1392         if (result == DC_OK) {
1393                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1394         }
1395
1396         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1397
1398                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1399
1400                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1401                 result = core_link_write_dpcd(link,
1402                                 DP_PHY_REPEATER_MODE,
1403                                 (uint8_t *)&repeater_mode,
1404                                 sizeof(repeater_mode));
1405
1406                 if (result == DC_OK) {
1407                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1408                 }
1409
1410                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1411
1412                 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1413                         aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1414                                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1415                         core_link_read_dpcd(
1416                                 link,
1417                                 aux_interval_address,
1418                                 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1419                                 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1420                         link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1421                 }
1422         }
1423 }
1424
1425 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1426 {
1427         union dpcd_training_pattern dpcd_pattern = { {0} };
1428
1429         const uint32_t dpcd_base_lt_offset =
1430                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1431                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1432         /* Set training not in progress*/
1433         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1434
1435         core_link_write_dpcd(
1436                 link,
1437                 dpcd_base_lt_offset,
1438                 &dpcd_pattern.raw,
1439                 1);
1440
1441         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1442                 __func__,
1443                 offset,
1444                 dpcd_base_lt_offset,
1445                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1446 }
1447
1448 static void print_status_message(
1449         struct dc_link *link,
1450         const struct link_training_settings *lt_settings,
1451         enum link_training_result status)
1452 {
1453         char *link_rate = "Unknown";
1454         char *lt_result = "Unknown";
1455         char *lt_spread = "Disabled";
1456
1457         switch (lt_settings->link_settings.link_rate) {
1458         case LINK_RATE_LOW:
1459                 link_rate = "RBR";
1460                 break;
1461         case LINK_RATE_RATE_2:
1462                 link_rate = "R2";
1463                 break;
1464         case LINK_RATE_RATE_3:
1465                 link_rate = "R3";
1466                 break;
1467         case LINK_RATE_HIGH:
1468                 link_rate = "HBR";
1469                 break;
1470         case LINK_RATE_RBR2:
1471                 link_rate = "RBR2";
1472                 break;
1473         case LINK_RATE_RATE_6:
1474                 link_rate = "R6";
1475                 break;
1476         case LINK_RATE_HIGH2:
1477                 link_rate = "HBR2";
1478                 break;
1479         case LINK_RATE_HIGH3:
1480                 link_rate = "HBR3";
1481                 break;
1482         default:
1483                 break;
1484         }
1485
1486         switch (status) {
1487         case LINK_TRAINING_SUCCESS:
1488                 lt_result = "pass";
1489                 break;
1490         case LINK_TRAINING_CR_FAIL_LANE0:
1491                 lt_result = "CR failed lane0";
1492                 break;
1493         case LINK_TRAINING_CR_FAIL_LANE1:
1494                 lt_result = "CR failed lane1";
1495                 break;
1496         case LINK_TRAINING_CR_FAIL_LANE23:
1497                 lt_result = "CR failed lane23";
1498                 break;
1499         case LINK_TRAINING_EQ_FAIL_CR:
1500                 lt_result = "CR failed in EQ";
1501                 break;
1502         case LINK_TRAINING_EQ_FAIL_EQ:
1503                 lt_result = "EQ failed";
1504                 break;
1505         case LINK_TRAINING_LQA_FAIL:
1506                 lt_result = "LQA failed";
1507                 break;
1508         case LINK_TRAINING_LINK_LOSS:
1509                 lt_result = "Link loss";
1510                 break;
1511         default:
1512                 break;
1513         }
1514
1515         switch (lt_settings->link_settings.link_spread) {
1516         case LINK_SPREAD_DISABLED:
1517                 lt_spread = "Disabled";
1518                 break;
1519         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1520                 lt_spread = "0.5% 30KHz";
1521                 break;
1522         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1523                 lt_spread = "0.5% 33KHz";
1524                 break;
1525         default:
1526                 break;
1527         }
1528
1529         /* Connectivity log: link training */
1530         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1531                                 link_rate,
1532                                 lt_settings->link_settings.lane_count,
1533                                 lt_result,
1534                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1535                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1536                                 lt_spread);
1537 }
1538
1539 void dc_link_dp_set_drive_settings(
1540         struct dc_link *link,
1541         struct link_training_settings *lt_settings)
1542 {
1543         /* program ASIC PHY settings*/
1544         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1545
1546         /* Notify DP sink the PHY settings from source */
1547         dpcd_set_lane_settings(link, lt_settings, DPRX);
1548 }
1549
1550 bool dc_link_dp_perform_link_training_skip_aux(
1551         struct dc_link *link,
1552         const struct dc_link_settings *link_setting)
1553 {
1554         struct link_training_settings lt_settings;
1555
1556         decide_training_settings(
1557                         link,
1558                         link_setting,
1559                         &link->preferred_training_settings,
1560                         &lt_settings);
1561
1562         /* 1. Perform_clock_recovery_sequence. */
1563
1564         /* transmit training pattern for clock recovery */
1565         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1566
1567         /* call HWSS to set lane settings*/
1568         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1569
1570         /* wait receiver to lock-on*/
1571         wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1572
1573         /* 2. Perform_channel_equalization_sequence. */
1574
1575         /* transmit training pattern for channel equalization. */
1576         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1577
1578         /* call HWSS to set lane settings*/
1579         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1580
1581         /* wait receiver to lock-on. */
1582         wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1583
1584         /* 3. Perform_link_training_int. */
1585
1586         /* Mainlink output idle pattern. */
1587         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1588
1589         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1590
1591         return true;
1592 }
1593
1594 enum link_training_result dc_link_dp_perform_link_training(
1595         struct dc_link *link,
1596         const struct dc_link_settings *link_setting,
1597         bool skip_video_pattern)
1598 {
1599         enum link_training_result status = LINK_TRAINING_SUCCESS;
1600         struct link_training_settings lt_settings;
1601
1602         bool fec_enable;
1603         uint8_t repeater_cnt;
1604         uint8_t repeater_id;
1605
1606         decide_training_settings(
1607                         link,
1608                         link_setting,
1609                         &link->preferred_training_settings,
1610                         &lt_settings);
1611
1612         /* Configure lttpr mode */
1613         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1614                 configure_lttpr_mode_non_transparent(link);
1615         else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1616                 configure_lttpr_mode_transparent(link);
1617
1618         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1619                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1620
1621         /* 1. set link rate, lane count and spread. */
1622         dpcd_set_link_settings(link, &lt_settings);
1623
1624         if (link->preferred_training_settings.fec_enable != NULL)
1625                 fec_enable = *link->preferred_training_settings.fec_enable;
1626         else
1627                 fec_enable = true;
1628
1629         dp_set_fec_ready(link, fec_enable);
1630
1631         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1632
1633                 /* 2. perform link training (set link training done
1634                  *  to false is done as well)
1635                  */
1636                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1637
1638                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1639                                 repeater_id--) {
1640                         status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1641
1642                         if (status != LINK_TRAINING_SUCCESS)
1643                                 break;
1644
1645                         status = perform_channel_equalization_sequence(link,
1646                                         &lt_settings,
1647                                         repeater_id);
1648
1649                         if (status != LINK_TRAINING_SUCCESS)
1650                                 break;
1651
1652                         repeater_training_done(link, repeater_id);
1653                 }
1654         }
1655
1656         if (status == LINK_TRAINING_SUCCESS) {
1657                 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1658         if (status == LINK_TRAINING_SUCCESS) {
1659                 status = perform_channel_equalization_sequence(link,
1660                                         &lt_settings,
1661                                         DPRX);
1662                 }
1663         }
1664
1665         /* 3. set training not in progress*/
1666         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1667         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1668                 status = dp_transition_to_video_idle(link,
1669                                 &lt_settings,
1670                                 status);
1671         }
1672
1673         /* delay 5ms after Main Link output idle pattern and then check
1674          * DPCD 0202h.
1675          */
1676         if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1677                 msleep(5);
1678                 status = dp_check_link_loss_status(link, &lt_settings);
1679         }
1680
1681         /* 6. print status message*/
1682         print_status_message(link, &lt_settings, status);
1683
1684         if (status != LINK_TRAINING_SUCCESS)
1685                 link->ctx->dc->debug_data.ltFailCount++;
1686
1687         return status;
1688 }
1689
1690 static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1691 {
1692         struct dc_link *link = stream->link;
1693         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1694 #ifdef CONFIG_DRM_AMD_DC_HDCP
1695         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1696 #endif
1697
1698         /* ASSR must be supported on the panel */
1699         if (panel_mode == DP_PANEL_MODE_DEFAULT)
1700                 return panel_mode;
1701
1702         /* eDP or internal DP only */
1703         if (link->connector_signal != SIGNAL_TYPE_EDP &&
1704                 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1705                  link->is_internal_display))
1706                 return DP_PANEL_MODE_DEFAULT;
1707
1708 #ifdef CONFIG_DRM_AMD_DC_HDCP
1709         if (cp_psp && cp_psp->funcs.enable_assr) {
1710                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1711                         /* since eDP implies ASSR on, change panel
1712                          * mode to disable ASSR
1713                          */
1714                         panel_mode = DP_PANEL_MODE_DEFAULT;
1715                 }
1716         } else
1717                 panel_mode = DP_PANEL_MODE_DEFAULT;
1718
1719 #else
1720         /* turn off ASSR if the implementation is not compiled in */
1721         panel_mode = DP_PANEL_MODE_DEFAULT;
1722 #endif
1723         return panel_mode;
1724 }
1725
1726 bool perform_link_training_with_retries(
1727         const struct dc_link_settings *link_setting,
1728         bool skip_video_pattern,
1729         int attempts,
1730         struct pipe_ctx *pipe_ctx,
1731         enum signal_type signal,
1732         bool do_fallback)
1733 {
1734         uint8_t j;
1735         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1736         struct dc_stream_state *stream = pipe_ctx->stream;
1737         struct dc_link *link = stream->link;
1738         enum dp_panel_mode panel_mode;
1739         struct link_encoder *link_enc;
1740         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1741         struct dc_link_settings currnet_setting = *link_setting;
1742
1743         /* Dynamically assigned link encoders associated with stream rather than
1744          * link.
1745          */
1746         if (link->dc->res_pool->funcs->link_encs_assign)
1747                 link_enc = stream->link_enc;
1748         else
1749                 link_enc = link->link_enc;
1750         ASSERT(link_enc);
1751
1752         /* We need to do this before the link training to ensure the idle pattern in SST
1753          * mode will be sent right after the link training
1754          */
1755         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1756                                                         pipe_ctx->stream_res.stream_enc->id, true);
1757
1758         for (j = 0; j < attempts; ++j) {
1759
1760                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1761                         __func__, (unsigned int)j + 1, attempts);
1762
1763                 dp_enable_link_phy(
1764                         link,
1765                         signal,
1766                         pipe_ctx->clock_source->id,
1767                         &currnet_setting);
1768
1769                 if (stream->sink_patches.dppowerup_delay > 0) {
1770                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1771
1772                         msleep(delay_dp_power_up_in_ms);
1773                 }
1774
1775                 panel_mode = try_enable_assr(stream);
1776                 dp_set_panel_mode(link, panel_mode);
1777                 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1778                          link->link_index,
1779                          panel_mode != DP_PANEL_MODE_DEFAULT);
1780
1781                 if (link->aux_access_disabled) {
1782                         dc_link_dp_perform_link_training_skip_aux(link, &currnet_setting);
1783                         return true;
1784                 } else {
1785                                 status = dc_link_dp_perform_link_training(
1786                                                                                 link,
1787                                                                                 &currnet_setting,
1788                                                                                 skip_video_pattern);
1789                         if (status == LINK_TRAINING_SUCCESS)
1790                                 return true;
1791                 }
1792
1793                 /* latest link training still fail, skip delay and keep PHY on
1794                  */
1795                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1796                         break;
1797
1798                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1799                         __func__, (unsigned int)j + 1, attempts);
1800
1801                 dp_disable_link_phy(link, signal);
1802
1803                 /* Abort link training if failure due to sink being unplugged. */
1804                 if (status == LINK_TRAINING_ABORT)
1805                         break;
1806                 else if (do_fallback) {
1807                         decide_fallback_link_setting(*link_setting, &currnet_setting, status);
1808                         /* Fail link training if reduced link bandwidth no longer meets
1809                          * stream requirements.
1810                          */
1811                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1812                                         dc_link_bandwidth_kbps(link, &currnet_setting))
1813                                 break;
1814                 }
1815
1816                 msleep(delay_between_attempts);
1817
1818                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1819         }
1820
1821         return false;
1822 }
1823
1824 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1825 {
1826         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1827         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1828
1829         if (dp_cs != NULL) {
1830                 dp_cs_id = dp_cs->id;
1831         } else {
1832                 /*
1833                  * dp clock source is not initialized for some reason.
1834                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1835                  */
1836                 ASSERT(dp_cs);
1837         }
1838
1839         return dp_cs_id;
1840 }
1841
1842 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1843 {
1844         if (mst_enable == false &&
1845                 link->type == dc_connection_mst_branch) {
1846                 /* Disable MST on link. Use only local sink. */
1847                 dp_disable_link_phy_mst(link, link->connector_signal);
1848
1849                 link->type = dc_connection_single;
1850                 link->local_sink = link->remote_sinks[0];
1851                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1852         } else if (mst_enable == true &&
1853                         link->type == dc_connection_single &&
1854                         link->remote_sinks[0] != NULL) {
1855                 /* Re-enable MST on link. */
1856                 dp_disable_link_phy(link, link->connector_signal);
1857                 dp_enable_mst_on_sink(link, true);
1858
1859                 link->type = dc_connection_mst_branch;
1860                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1861         }
1862 }
1863
1864 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1865 {
1866         /* Begin Sync LT. During this time,
1867          * DPCD:600h must not be powered down.
1868          */
1869         link->sync_lt_in_progress = true;
1870
1871         /*Clear any existing preferred settings.*/
1872         memset(&link->preferred_training_settings, 0,
1873                 sizeof(struct dc_link_training_overrides));
1874         memset(&link->preferred_link_setting, 0,
1875                 sizeof(struct dc_link_settings));
1876
1877         return true;
1878 }
1879
1880 enum link_training_result dc_link_dp_sync_lt_attempt(
1881     struct dc_link *link,
1882     struct dc_link_settings *link_settings,
1883     struct dc_link_training_overrides *lt_overrides)
1884 {
1885         struct link_training_settings lt_settings;
1886         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1887         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1888         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1889         bool fec_enable = false;
1890
1891         decide_training_settings(
1892                 link,
1893                 link_settings,
1894                 lt_overrides,
1895                 &lt_settings);
1896
1897         /* Setup MST Mode */
1898         if (lt_overrides->mst_enable)
1899                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1900
1901         /* Disable link */
1902         dp_disable_link_phy(link, link->connector_signal);
1903
1904         /* Enable link */
1905         dp_cs_id = get_clock_source_id(link);
1906         dp_enable_link_phy(link, link->connector_signal,
1907                 dp_cs_id, link_settings);
1908
1909         /* Set FEC enable */
1910         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1911         dp_set_fec_ready(link, fec_enable);
1912
1913         if (lt_overrides->alternate_scrambler_reset) {
1914                 if (*lt_overrides->alternate_scrambler_reset)
1915                         panel_mode = DP_PANEL_MODE_EDP;
1916                 else
1917                         panel_mode = DP_PANEL_MODE_DEFAULT;
1918         } else
1919                 panel_mode = dp_get_panel_mode(link);
1920
1921         dp_set_panel_mode(link, panel_mode);
1922
1923         /* Attempt to train with given link training settings */
1924         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1925                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1926
1927         /* Set link rate, lane count and spread. */
1928         dpcd_set_link_settings(link, &lt_settings);
1929
1930         /* 2. perform link training (set link training done
1931          *  to false is done as well)
1932          */
1933         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1934         if (lt_status == LINK_TRAINING_SUCCESS) {
1935                 lt_status = perform_channel_equalization_sequence(link,
1936                                                 &lt_settings,
1937                                                 DPRX);
1938         }
1939
1940         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1941         /* 4. print status message*/
1942         print_status_message(link, &lt_settings, lt_status);
1943
1944         return lt_status;
1945 }
1946
1947 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1948 {
1949         /* If input parameter is set, shut down phy.
1950          * Still shouldn't turn off dp_receiver (DPCD:600h)
1951          */
1952         if (link_down == true) {
1953                 dp_disable_link_phy(link, link->connector_signal);
1954                 dp_set_fec_ready(link, false);
1955         }
1956
1957         link->sync_lt_in_progress = false;
1958         return true;
1959 }
1960
1961 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1962 {
1963         struct dc_link_settings max_link_cap = {0};
1964
1965         /* get max link encoder capability */
1966         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1967
1968         /* Lower link settings based on sink's link cap */
1969         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1970                 max_link_cap.lane_count =
1971                                 link->reported_link_cap.lane_count;
1972         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1973                 max_link_cap.link_rate =
1974                                 link->reported_link_cap.link_rate;
1975         if (link->reported_link_cap.link_spread <
1976                         max_link_cap.link_spread)
1977                 max_link_cap.link_spread =
1978                                 link->reported_link_cap.link_spread;
1979         /*
1980          * account for lttpr repeaters cap
1981          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1982          */
1983         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1984                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1985                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1986
1987                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1988                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1989
1990                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
1991                                                 __func__,
1992                                                 max_link_cap.lane_count,
1993                                                 max_link_cap.link_rate);
1994         }
1995         return max_link_cap;
1996 }
1997
1998 enum dc_status read_hpd_rx_irq_data(
1999         struct dc_link *link,
2000         union hpd_irq_data *irq_data)
2001 {
2002         static enum dc_status retval;
2003
2004         /* The HW reads 16 bytes from 200h on HPD,
2005          * but if we get an AUX_DEFER, the HW cannot retry
2006          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2007          * fail, so we now explicitly read 6 bytes which is
2008          * the req from the above mentioned test cases.
2009          *
2010          * For DP 1.4 we need to read those from 2002h range.
2011          */
2012         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2013                 retval = core_link_read_dpcd(
2014                         link,
2015                         DP_SINK_COUNT,
2016                         irq_data->raw,
2017                         sizeof(union hpd_irq_data));
2018         else {
2019                 /* Read 14 bytes in a single read and then copy only the required fields.
2020                  * This is more efficient than doing it in two separate AUX reads. */
2021
2022                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2023
2024                 retval = core_link_read_dpcd(
2025                         link,
2026                         DP_SINK_COUNT_ESI,
2027                         tmp,
2028                         sizeof(tmp));
2029
2030                 if (retval != DC_OK)
2031                         return retval;
2032
2033                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2034                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2035                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2036                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2037                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2038                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2039         }
2040
2041         return retval;
2042 }
2043
2044 static bool hpd_rx_irq_check_link_loss_status(
2045         struct dc_link *link,
2046         union hpd_irq_data *hpd_irq_dpcd_data)
2047 {
2048         uint8_t irq_reg_rx_power_state = 0;
2049         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2050         union lane_status lane_status;
2051         uint32_t lane;
2052         bool sink_status_changed;
2053         bool return_code;
2054
2055         sink_status_changed = false;
2056         return_code = false;
2057
2058         if (link->cur_link_settings.lane_count == 0)
2059                 return return_code;
2060
2061         /*1. Check that Link Status changed, before re-training.*/
2062
2063         /*parse lane status*/
2064         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2065                 /* check status of lanes 0,1
2066                  * changed DpcdAddress_Lane01Status (0x202)
2067                  */
2068                 lane_status.raw = get_nibble_at_index(
2069                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2070                         lane);
2071
2072                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2073                         !lane_status.bits.CR_DONE_0 ||
2074                         !lane_status.bits.SYMBOL_LOCKED_0) {
2075                         /* if one of the channel equalization, clock
2076                          * recovery or symbol lock is dropped
2077                          * consider it as (link has been
2078                          * dropped) dp sink status has changed
2079                          */
2080                         sink_status_changed = true;
2081                         break;
2082                 }
2083         }
2084
2085         /* Check interlane align.*/
2086         if (sink_status_changed ||
2087                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2088
2089                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2090
2091                 return_code = true;
2092
2093                 /*2. Check that we can handle interrupt: Not in FS DOS,
2094                  *  Not in "Display Timeout" state, Link is trained.
2095                  */
2096                 dpcd_result = core_link_read_dpcd(link,
2097                         DP_SET_POWER,
2098                         &irq_reg_rx_power_state,
2099                         sizeof(irq_reg_rx_power_state));
2100
2101                 if (dpcd_result != DC_OK) {
2102                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2103                                 __func__);
2104                 } else {
2105                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2106                                 return_code = false;
2107                 }
2108         }
2109
2110         return return_code;
2111 }
2112
2113 bool dp_verify_link_cap(
2114         struct dc_link *link,
2115         struct dc_link_settings *known_limit_link_setting,
2116         int *fail_count)
2117 {
2118         struct dc_link_settings max_link_cap = {0};
2119         struct dc_link_settings cur_link_setting = {0};
2120         struct dc_link_settings *cur = &cur_link_setting;
2121         struct dc_link_settings initial_link_settings = {0};
2122         bool success;
2123         bool skip_link_training;
2124         bool skip_video_pattern;
2125         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2126         enum link_training_result status;
2127         union hpd_irq_data irq_data;
2128
2129         if (link->dc->debug.skip_detection_link_training) {
2130                 link->verified_link_cap = *known_limit_link_setting;
2131                 return true;
2132         }
2133
2134         memset(&irq_data, 0, sizeof(irq_data));
2135         success = false;
2136         skip_link_training = false;
2137
2138         max_link_cap = get_max_link_cap(link);
2139
2140         /* Grant extended timeout request */
2141         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2142                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2143
2144                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2145         }
2146
2147         /* TODO implement override and monitor patch later */
2148
2149         /* try to train the link from high to low to
2150          * find the physical link capability
2151          */
2152         /* disable PHY done possible by BIOS, will be done by driver itself */
2153         dp_disable_link_phy(link, link->connector_signal);
2154
2155         dp_cs_id = get_clock_source_id(link);
2156
2157         /* link training starts with the maximum common settings
2158          * supported by both sink and ASIC.
2159          */
2160         initial_link_settings = get_common_supported_link_settings(
2161                         *known_limit_link_setting,
2162                         max_link_cap);
2163         cur_link_setting = initial_link_settings;
2164
2165         /* Temporary Renoir-specific workaround for SWDEV-215184;
2166          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2167          * so add extra cycle of enabling and disabling the PHY before first link training.
2168          */
2169         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2170                         link->dc->debug.usbc_combo_phy_reset_wa) {
2171                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2172                 dp_disable_link_phy(link, link->connector_signal);
2173         }
2174
2175         do {
2176                 skip_video_pattern = true;
2177
2178                 if (cur->link_rate == LINK_RATE_LOW)
2179                         skip_video_pattern = false;
2180
2181                 dp_enable_link_phy(
2182                                 link,
2183                                 link->connector_signal,
2184                                 dp_cs_id,
2185                                 cur);
2186
2187
2188                 if (skip_link_training)
2189                         success = true;
2190                 else {
2191                         status = dc_link_dp_perform_link_training(
2192                                                         link,
2193                                                         cur,
2194                                                         skip_video_pattern);
2195                         if (status == LINK_TRAINING_SUCCESS)
2196                                 success = true;
2197                         else
2198                                 (*fail_count)++;
2199                 }
2200
2201                 if (success) {
2202                         link->verified_link_cap = *cur;
2203                         udelay(1000);
2204                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2205                                 if (hpd_rx_irq_check_link_loss_status(
2206                                                 link,
2207                                                 &irq_data))
2208                                         (*fail_count)++;
2209                 }
2210                 /* always disable the link before trying another
2211                  * setting or before returning we'll enable it later
2212                  * based on the actual mode we're driving
2213                  */
2214                 dp_disable_link_phy(link, link->connector_signal);
2215         } while (!success && decide_fallback_link_setting(
2216                         initial_link_settings, cur, status));
2217
2218         /* Link Training failed for all Link Settings
2219          *  (Lane Count is still unknown)
2220          */
2221         if (!success) {
2222                 /* If all LT fails for all settings,
2223                  * set verified = failed safe (1 lane low)
2224                  */
2225                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2226                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2227
2228                 link->verified_link_cap.link_spread =
2229                 LINK_SPREAD_DISABLED;
2230         }
2231
2232
2233         return success;
2234 }
2235
2236 bool dp_verify_link_cap_with_retries(
2237         struct dc_link *link,
2238         struct dc_link_settings *known_limit_link_setting,
2239         int attempts)
2240 {
2241         uint8_t i = 0;
2242         bool success = false;
2243
2244         for (i = 0; i < attempts; i++) {
2245                 int fail_count = 0;
2246                 enum dc_connection_type type = dc_connection_none;
2247
2248                 memset(&link->verified_link_cap, 0,
2249                                 sizeof(struct dc_link_settings));
2250                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2251                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2252                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2253                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2254                         break;
2255                 } else if (dp_verify_link_cap(link,
2256                                 &link->reported_link_cap,
2257                                 &fail_count) && fail_count == 0) {
2258                         success = true;
2259                         break;
2260                 }
2261                 msleep(10);
2262         }
2263         return success;
2264 }
2265
2266 bool dp_verify_mst_link_cap(
2267         struct dc_link *link)
2268 {
2269         struct dc_link_settings max_link_cap = {0};
2270
2271         max_link_cap = get_max_link_cap(link);
2272         link->verified_link_cap = get_common_supported_link_settings(
2273                 link->reported_link_cap,
2274                 max_link_cap);
2275
2276         return true;
2277 }
2278
2279 static struct dc_link_settings get_common_supported_link_settings(
2280                 struct dc_link_settings link_setting_a,
2281                 struct dc_link_settings link_setting_b)
2282 {
2283         struct dc_link_settings link_settings = {0};
2284
2285         link_settings.lane_count =
2286                 (link_setting_a.lane_count <=
2287                         link_setting_b.lane_count) ?
2288                         link_setting_a.lane_count :
2289                         link_setting_b.lane_count;
2290         link_settings.link_rate =
2291                 (link_setting_a.link_rate <=
2292                         link_setting_b.link_rate) ?
2293                         link_setting_a.link_rate :
2294                         link_setting_b.link_rate;
2295         link_settings.link_spread = LINK_SPREAD_DISABLED;
2296
2297         /* in DP compliance test, DPR-120 may have
2298          * a random value in its MAX_LINK_BW dpcd field.
2299          * We map it to the maximum supported link rate that
2300          * is smaller than MAX_LINK_BW in this case.
2301          */
2302         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2303                 link_settings.link_rate = LINK_RATE_HIGH3;
2304         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2305                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2306                 link_settings.link_rate = LINK_RATE_HIGH2;
2307         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2308                         && link_settings.link_rate > LINK_RATE_HIGH) {
2309                 link_settings.link_rate = LINK_RATE_HIGH;
2310         } else if (link_settings.link_rate < LINK_RATE_HIGH
2311                         && link_settings.link_rate > LINK_RATE_LOW) {
2312                 link_settings.link_rate = LINK_RATE_LOW;
2313         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2314                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2315         }
2316
2317         return link_settings;
2318 }
2319
2320 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2321 {
2322         return lane_count <= LANE_COUNT_ONE;
2323 }
2324
2325 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2326 {
2327         return link_rate <= LINK_RATE_LOW;
2328 }
2329
2330 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2331 {
2332         switch (lane_count) {
2333         case LANE_COUNT_FOUR:
2334                 return LANE_COUNT_TWO;
2335         case LANE_COUNT_TWO:
2336                 return LANE_COUNT_ONE;
2337         case LANE_COUNT_ONE:
2338                 return LANE_COUNT_UNKNOWN;
2339         default:
2340                 return LANE_COUNT_UNKNOWN;
2341         }
2342 }
2343
2344 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2345 {
2346         switch (link_rate) {
2347         case LINK_RATE_HIGH3:
2348                 return LINK_RATE_HIGH2;
2349         case LINK_RATE_HIGH2:
2350                 return LINK_RATE_HIGH;
2351         case LINK_RATE_HIGH:
2352                 return LINK_RATE_LOW;
2353         case LINK_RATE_LOW:
2354                 return LINK_RATE_UNKNOWN;
2355         default:
2356                 return LINK_RATE_UNKNOWN;
2357         }
2358 }
2359
2360 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2361 {
2362         switch (lane_count) {
2363         case LANE_COUNT_ONE:
2364                 return LANE_COUNT_TWO;
2365         case LANE_COUNT_TWO:
2366                 return LANE_COUNT_FOUR;
2367         default:
2368                 return LANE_COUNT_UNKNOWN;
2369         }
2370 }
2371
2372 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2373 {
2374         switch (link_rate) {
2375         case LINK_RATE_LOW:
2376                 return LINK_RATE_HIGH;
2377         case LINK_RATE_HIGH:
2378                 return LINK_RATE_HIGH2;
2379         case LINK_RATE_HIGH2:
2380                 return LINK_RATE_HIGH3;
2381         default:
2382                 return LINK_RATE_UNKNOWN;
2383         }
2384 }
2385
2386 /*
2387  * function: set link rate and lane count fallback based
2388  * on current link setting and last link training result
2389  * return value:
2390  *                      true - link setting could be set
2391  *                      false - has reached minimum setting
2392  *                                      and no further fallback could be done
2393  */
2394 static bool decide_fallback_link_setting(
2395                 struct dc_link_settings initial_link_settings,
2396                 struct dc_link_settings *current_link_setting,
2397                 enum link_training_result training_result)
2398 {
2399         if (!current_link_setting)
2400                 return false;
2401
2402         switch (training_result) {
2403         case LINK_TRAINING_CR_FAIL_LANE0:
2404         case LINK_TRAINING_CR_FAIL_LANE1:
2405         case LINK_TRAINING_CR_FAIL_LANE23:
2406         case LINK_TRAINING_LQA_FAIL:
2407         {
2408                 if (!reached_minimum_link_rate
2409                                 (current_link_setting->link_rate)) {
2410                         current_link_setting->link_rate =
2411                                 reduce_link_rate(
2412                                         current_link_setting->link_rate);
2413                 } else if (!reached_minimum_lane_count
2414                                 (current_link_setting->lane_count)) {
2415                         current_link_setting->link_rate =
2416                                 initial_link_settings.link_rate;
2417                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2418                                 return false;
2419                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2420                                 current_link_setting->lane_count =
2421                                                 LANE_COUNT_ONE;
2422                         else if (training_result ==
2423                                         LINK_TRAINING_CR_FAIL_LANE23)
2424                                 current_link_setting->lane_count =
2425                                                 LANE_COUNT_TWO;
2426                         else
2427                                 current_link_setting->lane_count =
2428                                         reduce_lane_count(
2429                                         current_link_setting->lane_count);
2430                 } else {
2431                         return false;
2432                 }
2433                 break;
2434         }
2435         case LINK_TRAINING_EQ_FAIL_EQ:
2436         {
2437                 if (!reached_minimum_lane_count
2438                                 (current_link_setting->lane_count)) {
2439                         current_link_setting->lane_count =
2440                                 reduce_lane_count(
2441                                         current_link_setting->lane_count);
2442                 } else if (!reached_minimum_link_rate
2443                                 (current_link_setting->link_rate)) {
2444                         current_link_setting->link_rate =
2445                                 reduce_link_rate(
2446                                         current_link_setting->link_rate);
2447                 } else {
2448                         return false;
2449                 }
2450                 break;
2451         }
2452         case LINK_TRAINING_EQ_FAIL_CR:
2453         {
2454                 if (!reached_minimum_link_rate
2455                                 (current_link_setting->link_rate)) {
2456                         current_link_setting->link_rate =
2457                                 reduce_link_rate(
2458                                         current_link_setting->link_rate);
2459                 } else {
2460                         return false;
2461                 }
2462                 break;
2463         }
2464         default:
2465                 return false;
2466         }
2467         return true;
2468 }
2469
2470 bool dp_validate_mode_timing(
2471         struct dc_link *link,
2472         const struct dc_crtc_timing *timing)
2473 {
2474         uint32_t req_bw;
2475         uint32_t max_bw;
2476
2477         const struct dc_link_settings *link_setting;
2478
2479         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2480         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2481                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2482                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2483                 return false;
2484
2485         /*always DP fail safe mode*/
2486         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2487                 timing->h_addressable == (uint32_t) 640 &&
2488                 timing->v_addressable == (uint32_t) 480)
2489                 return true;
2490
2491         link_setting = dc_link_get_link_cap(link);
2492
2493         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2494         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2495                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2496                 link_setting = &link->verified_link_cap;
2497         */
2498
2499         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2500         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2501
2502         if (req_bw <= max_bw) {
2503                 /* remember the biggest mode here, during
2504                  * initial link training (to get
2505                  * verified_link_cap), LS sends event about
2506                  * cannot train at reported cap to upper
2507                  * layer and upper layer will re-enumerate modes.
2508                  * this is not necessary if the lower
2509                  * verified_link_cap is enough to drive
2510                  * all the modes */
2511
2512                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2513                 /* if (flags.DYNAMIC_VALIDATION == 1)
2514                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2515                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2516                 return true;
2517         } else
2518                 return false;
2519 }
2520
2521 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2522 {
2523         struct dc_link_settings initial_link_setting = {
2524                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2525         struct dc_link_settings current_link_setting =
2526                         initial_link_setting;
2527         uint32_t link_bw;
2528
2529         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2530                 return false;
2531
2532         /* search for the minimum link setting that:
2533          * 1. is supported according to the link training result
2534          * 2. could support the b/w requested by the timing
2535          */
2536         while (current_link_setting.link_rate <=
2537                         link->verified_link_cap.link_rate) {
2538                 link_bw = dc_link_bandwidth_kbps(
2539                                 link,
2540                                 &current_link_setting);
2541                 if (req_bw <= link_bw) {
2542                         *link_setting = current_link_setting;
2543                         return true;
2544                 }
2545
2546                 if (current_link_setting.lane_count <
2547                                 link->verified_link_cap.lane_count) {
2548                         current_link_setting.lane_count =
2549                                         increase_lane_count(
2550                                                         current_link_setting.lane_count);
2551                 } else {
2552                         current_link_setting.link_rate =
2553                                         increase_link_rate(
2554                                                         current_link_setting.link_rate);
2555                         current_link_setting.lane_count =
2556                                         initial_link_setting.lane_count;
2557                 }
2558         }
2559
2560         return false;
2561 }
2562
2563 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2564 {
2565         struct dc_link_settings initial_link_setting;
2566         struct dc_link_settings current_link_setting;
2567         uint32_t link_bw;
2568
2569         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2570                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2571                 *link_setting = link->verified_link_cap;
2572                 return true;
2573         }
2574
2575         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2576         initial_link_setting.lane_count = LANE_COUNT_ONE;
2577         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2578         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2579         initial_link_setting.use_link_rate_set = true;
2580         initial_link_setting.link_rate_set = 0;
2581         current_link_setting = initial_link_setting;
2582
2583         /* search for the minimum link setting that:
2584          * 1. is supported according to the link training result
2585          * 2. could support the b/w requested by the timing
2586          */
2587         while (current_link_setting.link_rate <=
2588                         link->verified_link_cap.link_rate) {
2589                 link_bw = dc_link_bandwidth_kbps(
2590                                 link,
2591                                 &current_link_setting);
2592                 if (req_bw <= link_bw) {
2593                         *link_setting = current_link_setting;
2594                         return true;
2595                 }
2596
2597                 if (current_link_setting.lane_count <
2598                                 link->verified_link_cap.lane_count) {
2599                         current_link_setting.lane_count =
2600                                         increase_lane_count(
2601                                                         current_link_setting.lane_count);
2602                 } else {
2603                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2604                                 current_link_setting.link_rate_set++;
2605                                 current_link_setting.link_rate =
2606                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2607                                 current_link_setting.lane_count =
2608                                                                         initial_link_setting.lane_count;
2609                         } else
2610                                 break;
2611                 }
2612         }
2613         return false;
2614 }
2615
2616 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2617 {
2618         *link_setting = link->verified_link_cap;
2619         return true;
2620 }
2621
2622 void decide_link_settings(struct dc_stream_state *stream,
2623         struct dc_link_settings *link_setting)
2624 {
2625         struct dc_link *link;
2626         uint32_t req_bw;
2627
2628         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2629
2630         link = stream->link;
2631
2632         /* if preferred is specified through AMDDP, use it, if it's enough
2633          * to drive the mode
2634          */
2635         if (link->preferred_link_setting.lane_count !=
2636                         LANE_COUNT_UNKNOWN &&
2637                         link->preferred_link_setting.link_rate !=
2638                                         LINK_RATE_UNKNOWN) {
2639                 *link_setting =  link->preferred_link_setting;
2640                 return;
2641         }
2642
2643         /* MST doesn't perform link training for now
2644          * TODO: add MST specific link training routine
2645          */
2646         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2647                 if (decide_mst_link_settings(link, link_setting))
2648                         return;
2649         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2650                 if (decide_edp_link_settings(link, link_setting, req_bw))
2651                         return;
2652         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2653                 return;
2654
2655         BREAK_TO_DEBUGGER();
2656         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2657
2658         *link_setting = link->verified_link_cap;
2659 }
2660
2661 /*************************Short Pulse IRQ***************************/
2662 static bool allow_hpd_rx_irq(const struct dc_link *link)
2663 {
2664         /*
2665          * Don't handle RX IRQ unless one of following is met:
2666          * 1) The link is established (cur_link_settings != unknown)
2667          * 2) We know we're dealing with a branch device, SST or MST
2668          */
2669
2670         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2671                 is_dp_branch_device(link))
2672                 return true;
2673
2674         return false;
2675 }
2676
2677 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2678 {
2679         union dpcd_psr_configuration psr_configuration;
2680
2681         if (!link->psr_settings.psr_feature_enabled)
2682                 return false;
2683
2684         dm_helpers_dp_read_dpcd(
2685                 link->ctx,
2686                 link,
2687                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2688                 &psr_configuration.raw,
2689                 sizeof(psr_configuration.raw));
2690
2691
2692         if (psr_configuration.bits.ENABLE) {
2693                 unsigned char dpcdbuf[3] = {0};
2694                 union psr_error_status psr_error_status;
2695                 union psr_sink_psr_status psr_sink_psr_status;
2696
2697                 dm_helpers_dp_read_dpcd(
2698                         link->ctx,
2699                         link,
2700                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2701                         (unsigned char *) dpcdbuf,
2702                         sizeof(dpcdbuf));
2703
2704                 /*DPCD 2006h   ERROR STATUS*/
2705                 psr_error_status.raw = dpcdbuf[0];
2706                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2707                 psr_sink_psr_status.raw = dpcdbuf[2];
2708
2709                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2710                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2711                                 psr_error_status.bits.VSC_SDP_ERROR) {
2712                         /* Acknowledge and clear error bits */
2713                         dm_helpers_dp_write_dpcd(
2714                                 link->ctx,
2715                                 link,
2716                                 8198,/*DpcdAddress_PSR_Error_Status*/
2717                                 &psr_error_status.raw,
2718                                 sizeof(psr_error_status.raw));
2719
2720                         /* PSR error, disable and re-enable PSR */
2721                         dc_link_set_psr_allow_active(link, false, true, false);
2722                         dc_link_set_psr_allow_active(link, true, true, false);
2723
2724                         return true;
2725                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2726                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2727                         /* No error is detect, PSR is active.
2728                          * We should return with IRQ_HPD handled without
2729                          * checking for loss of sync since PSR would have
2730                          * powered down main link.
2731                          */
2732                         return true;
2733                 }
2734         }
2735         return false;
2736 }
2737
2738 static void dp_test_send_link_training(struct dc_link *link)
2739 {
2740         struct dc_link_settings link_settings = {0};
2741
2742         core_link_read_dpcd(
2743                         link,
2744                         DP_TEST_LANE_COUNT,
2745                         (unsigned char *)(&link_settings.lane_count),
2746                         1);
2747         core_link_read_dpcd(
2748                         link,
2749                         DP_TEST_LINK_RATE,
2750                         (unsigned char *)(&link_settings.link_rate),
2751                         1);
2752
2753         /* Set preferred link settings */
2754         link->verified_link_cap.lane_count = link_settings.lane_count;
2755         link->verified_link_cap.link_rate = link_settings.link_rate;
2756
2757         dp_retrain_link_dp_test(link, &link_settings, false);
2758 }
2759
2760 /* TODO Raven hbr2 compliance eye output is unstable
2761  * (toggling on and off) with debugger break
2762  * This caueses intermittent PHY automation failure
2763  * Need to look into the root cause */
2764 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2765 {
2766         union phy_test_pattern dpcd_test_pattern;
2767         union lane_adjust dpcd_lane_adjustment[2];
2768         unsigned char dpcd_post_cursor_2_adjustment = 0;
2769         unsigned char test_pattern_buffer[
2770                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2771                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2772         unsigned int test_pattern_size = 0;
2773         enum dp_test_pattern test_pattern;
2774         struct dc_link_training_settings link_settings;
2775         union lane_adjust dpcd_lane_adjust;
2776         unsigned int lane;
2777         struct link_training_settings link_training_settings;
2778         int i = 0;
2779
2780         dpcd_test_pattern.raw = 0;
2781         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2782         memset(&link_settings, 0, sizeof(link_settings));
2783
2784         /* get phy test pattern and pattern parameters from DP receiver */
2785         core_link_read_dpcd(
2786                         link,
2787                         DP_PHY_TEST_PATTERN,
2788                         &dpcd_test_pattern.raw,
2789                         sizeof(dpcd_test_pattern));
2790         core_link_read_dpcd(
2791                         link,
2792                         DP_ADJUST_REQUEST_LANE0_1,
2793                         &dpcd_lane_adjustment[0].raw,
2794                         sizeof(dpcd_lane_adjustment));
2795
2796         /*get post cursor 2 parameters
2797          * For DP 1.1a or eariler, this DPCD register's value is 0
2798          * For DP 1.2 or later:
2799          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2800          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2801          */
2802         core_link_read_dpcd(
2803                         link,
2804                         DP_ADJUST_REQUEST_POST_CURSOR2,
2805                         &dpcd_post_cursor_2_adjustment,
2806                         sizeof(dpcd_post_cursor_2_adjustment));
2807
2808         /* translate request */
2809         switch (dpcd_test_pattern.bits.PATTERN) {
2810         case PHY_TEST_PATTERN_D10_2:
2811                 test_pattern = DP_TEST_PATTERN_D102;
2812                 break;
2813         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2814                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2815                 break;
2816         case PHY_TEST_PATTERN_PRBS7:
2817                 test_pattern = DP_TEST_PATTERN_PRBS7;
2818                 break;
2819         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2820                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2821                 break;
2822         case PHY_TEST_PATTERN_CP2520_1:
2823                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2824                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2825                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2826                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2827                 break;
2828         case PHY_TEST_PATTERN_CP2520_2:
2829                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2830                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2831                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2832                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2833                 break;
2834         case PHY_TEST_PATTERN_CP2520_3:
2835                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2836                 break;
2837         default:
2838                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2839         break;
2840         }
2841
2842         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2843                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2844                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2845                 core_link_read_dpcd(
2846                                 link,
2847                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2848                                 test_pattern_buffer,
2849                                 test_pattern_size);
2850         }
2851
2852         /* prepare link training settings */
2853         link_settings.link = link->cur_link_settings;
2854
2855         for (lane = 0; lane <
2856                 (unsigned int)(link->cur_link_settings.lane_count);
2857                 lane++) {
2858                 dpcd_lane_adjust.raw =
2859                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2860                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2861                         (enum dc_voltage_swing)
2862                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2863                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2864                         (enum dc_pre_emphasis)
2865                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2866                 link_settings.lane_settings[lane].POST_CURSOR2 =
2867                         (enum dc_post_cursor2)
2868                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2869         }
2870
2871         for (i = 0; i < 4; i++)
2872                 link_training_settings.lane_settings[i] =
2873                                 link_settings.lane_settings[i];
2874         link_training_settings.link_settings = link_settings.link;
2875         link_training_settings.allow_invalid_msa_timing_param = false;
2876         /*Usage: Measure DP physical lane signal
2877          * by DP SI test equipment automatically.
2878          * PHY test pattern request is generated by equipment via HPD interrupt.
2879          * HPD needs to be active all the time. HPD should be active
2880          * all the time. Do not touch it.
2881          * forward request to DS
2882          */
2883         dc_link_dp_set_test_pattern(
2884                 link,
2885                 test_pattern,
2886                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2887                 &link_training_settings,
2888                 test_pattern_buffer,
2889                 test_pattern_size);
2890 }
2891
2892 static void dp_test_send_link_test_pattern(struct dc_link *link)
2893 {
2894         union link_test_pattern dpcd_test_pattern;
2895         union test_misc dpcd_test_params;
2896         enum dp_test_pattern test_pattern;
2897         enum dp_test_pattern_color_space test_pattern_color_space =
2898                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2899         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2900         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2901         struct pipe_ctx *pipe_ctx = NULL;
2902         int i;
2903
2904         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2905         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2906
2907         for (i = 0; i < MAX_PIPES; i++) {
2908                 if (pipes[i].stream == NULL)
2909                         continue;
2910
2911                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2912                         pipe_ctx = &pipes[i];
2913                         break;
2914                 }
2915         }
2916
2917         if (pipe_ctx == NULL)
2918                 return;
2919
2920         /* get link test pattern and pattern parameters */
2921         core_link_read_dpcd(
2922                         link,
2923                         DP_TEST_PATTERN,
2924                         &dpcd_test_pattern.raw,
2925                         sizeof(dpcd_test_pattern));
2926         core_link_read_dpcd(
2927                         link,
2928                         DP_TEST_MISC0,
2929                         &dpcd_test_params.raw,
2930                         sizeof(dpcd_test_params));
2931
2932         switch (dpcd_test_pattern.bits.PATTERN) {
2933         case LINK_TEST_PATTERN_COLOR_RAMP:
2934                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2935         break;
2936         case LINK_TEST_PATTERN_VERTICAL_BARS:
2937                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2938         break; /* black and white */
2939         case LINK_TEST_PATTERN_COLOR_SQUARES:
2940                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2941                                 TEST_DYN_RANGE_VESA ?
2942                                 DP_TEST_PATTERN_COLOR_SQUARES :
2943                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2944         break;
2945         default:
2946                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2947         break;
2948         }
2949
2950         if (dpcd_test_params.bits.CLR_FORMAT == 0)
2951                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2952         else
2953                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2954                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2955                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2956
2957         switch (dpcd_test_params.bits.BPC) {
2958         case 0: // 6 bits
2959                 requestColorDepth = COLOR_DEPTH_666;
2960                 break;
2961         case 1: // 8 bits
2962                 requestColorDepth = COLOR_DEPTH_888;
2963                 break;
2964         case 2: // 10 bits
2965                 requestColorDepth = COLOR_DEPTH_101010;
2966                 break;
2967         case 3: // 12 bits
2968                 requestColorDepth = COLOR_DEPTH_121212;
2969                 break;
2970         default:
2971                 break;
2972         }
2973
2974         switch (dpcd_test_params.bits.CLR_FORMAT) {
2975         case 0:
2976                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
2977                 break;
2978         case 1:
2979                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
2980                 break;
2981         case 2:
2982                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
2983                 break;
2984         default:
2985                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
2986                 break;
2987         }
2988
2989
2990         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
2991                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
2992                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
2993                                 __func__,
2994                                 pipe_ctx->stream->timing.display_color_depth,
2995                                 requestColorDepth);
2996                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
2997         }
2998
2999         dp_update_dsc_config(pipe_ctx);
3000
3001         dc_link_dp_set_test_pattern(
3002                         link,
3003                         test_pattern,
3004                         test_pattern_color_space,
3005                         NULL,
3006                         NULL,
3007                         0);
3008 }
3009
3010 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3011 {
3012         union audio_test_mode            dpcd_test_mode = {0};
3013         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3014         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3015         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3016
3017         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3018         struct pipe_ctx *pipe_ctx = &pipes[0];
3019         unsigned int channel_count;
3020         unsigned int channel = 0;
3021         unsigned int modes = 0;
3022         unsigned int sampling_rate_in_hz = 0;
3023
3024         // get audio test mode and test pattern parameters
3025         core_link_read_dpcd(
3026                 link,
3027                 DP_TEST_AUDIO_MODE,
3028                 &dpcd_test_mode.raw,
3029                 sizeof(dpcd_test_mode));
3030
3031         core_link_read_dpcd(
3032                 link,
3033                 DP_TEST_AUDIO_PATTERN_TYPE,
3034                 &dpcd_pattern_type.value,
3035                 sizeof(dpcd_pattern_type));
3036
3037         channel_count = dpcd_test_mode.bits.channel_count + 1;
3038
3039         // read pattern periods for requested channels when sawTooth pattern is requested
3040         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3041                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3042
3043                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3044                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3045                 // read period for each channel
3046                 for (channel = 0; channel < channel_count; channel++) {
3047                         core_link_read_dpcd(
3048                                                         link,
3049                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3050                                                         &dpcd_pattern_period[channel].raw,
3051                                                         sizeof(dpcd_pattern_period[channel]));
3052                 }
3053         }
3054
3055         // translate sampling rate
3056         switch (dpcd_test_mode.bits.sampling_rate) {
3057         case AUDIO_SAMPLING_RATE_32KHZ:
3058                 sampling_rate_in_hz = 32000;
3059                 break;
3060         case AUDIO_SAMPLING_RATE_44_1KHZ:
3061                 sampling_rate_in_hz = 44100;
3062                 break;
3063         case AUDIO_SAMPLING_RATE_48KHZ:
3064                 sampling_rate_in_hz = 48000;
3065                 break;
3066         case AUDIO_SAMPLING_RATE_88_2KHZ:
3067                 sampling_rate_in_hz = 88200;
3068                 break;
3069         case AUDIO_SAMPLING_RATE_96KHZ:
3070                 sampling_rate_in_hz = 96000;
3071                 break;
3072         case AUDIO_SAMPLING_RATE_176_4KHZ:
3073                 sampling_rate_in_hz = 176400;
3074                 break;
3075         case AUDIO_SAMPLING_RATE_192KHZ:
3076                 sampling_rate_in_hz = 192000;
3077                 break;
3078         default:
3079                 sampling_rate_in_hz = 0;
3080                 break;
3081         }
3082
3083         link->audio_test_data.flags.test_requested = 1;
3084         link->audio_test_data.flags.disable_video = disable_video;
3085         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3086         link->audio_test_data.channel_count = channel_count;
3087         link->audio_test_data.pattern_type = test_pattern;
3088
3089         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3090                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3091                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3092                 }
3093         }
3094 }
3095
3096 static void handle_automated_test(struct dc_link *link)
3097 {
3098         union test_request test_request;
3099         union test_response test_response;
3100
3101         memset(&test_request, 0, sizeof(test_request));
3102         memset(&test_response, 0, sizeof(test_response));
3103
3104         core_link_read_dpcd(
3105                 link,
3106                 DP_TEST_REQUEST,
3107                 &test_request.raw,
3108                 sizeof(union test_request));
3109         if (test_request.bits.LINK_TRAINING) {
3110                 /* ACK first to let DP RX test box monitor LT sequence */
3111                 test_response.bits.ACK = 1;
3112                 core_link_write_dpcd(
3113                         link,
3114                         DP_TEST_RESPONSE,
3115                         &test_response.raw,
3116                         sizeof(test_response));
3117                 dp_test_send_link_training(link);
3118                 /* no acknowledge request is needed again */
3119                 test_response.bits.ACK = 0;
3120         }
3121         if (test_request.bits.LINK_TEST_PATTRN) {
3122                 dp_test_send_link_test_pattern(link);
3123                 test_response.bits.ACK = 1;
3124         }
3125
3126         if (test_request.bits.AUDIO_TEST_PATTERN) {
3127                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3128                 test_response.bits.ACK = 1;
3129         }
3130
3131         if (test_request.bits.PHY_TEST_PATTERN) {
3132                 dp_test_send_phy_test_pattern(link);
3133                 test_response.bits.ACK = 1;
3134         }
3135
3136         /* send request acknowledgment */
3137         if (test_response.bits.ACK)
3138                 core_link_write_dpcd(
3139                         link,
3140                         DP_TEST_RESPONSE,
3141                         &test_response.raw,
3142                         sizeof(test_response));
3143 }
3144
3145 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3146 {
3147         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3148         union device_service_irq device_service_clear = { { 0 } };
3149         enum dc_status result;
3150         bool status = false;
3151         struct pipe_ctx *pipe_ctx;
3152         int i;
3153
3154         if (out_link_loss)
3155                 *out_link_loss = false;
3156         /* For use cases related to down stream connection status change,
3157          * PSR and device auto test, refer to function handle_sst_hpd_irq
3158          * in DAL2.1*/
3159
3160         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3161                 __func__, link->link_index);
3162
3163
3164          /* All the "handle_hpd_irq_xxx()" methods
3165                  * should be called only after
3166                  * dal_dpsst_ls_read_hpd_irq_data
3167                  * Order of calls is important too
3168                  */
3169         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3170         if (out_hpd_irq_dpcd_data)
3171                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3172
3173         if (result != DC_OK) {
3174                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3175                         __func__);
3176                 return false;
3177         }
3178
3179         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3180                 device_service_clear.bits.AUTOMATED_TEST = 1;
3181                 core_link_write_dpcd(
3182                         link,
3183                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3184                         &device_service_clear.raw,
3185                         sizeof(device_service_clear.raw));
3186                 device_service_clear.raw = 0;
3187                 handle_automated_test(link);
3188                 return false;
3189         }
3190
3191         if (!allow_hpd_rx_irq(link)) {
3192                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3193                         __func__, link->link_index);
3194                 return false;
3195         }
3196
3197         if (handle_hpd_irq_psr_sink(link))
3198                 /* PSR-related error was detected and handled */
3199                 return true;
3200
3201         /* If PSR-related error handled, Main link may be off,
3202          * so do not handle as a normal sink status change interrupt.
3203          */
3204
3205         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3206                 return true;
3207
3208         /* check if we have MST msg and return since we poll for it */
3209         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3210                 return false;
3211
3212         /* For now we only handle 'Downstream port status' case.
3213          * If we got sink count changed it means
3214          * Downstream port status changed,
3215          * then DM should call DC to do the detection.
3216          * NOTE: Do not handle link loss on eDP since it is internal link*/
3217         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3218                 hpd_rx_irq_check_link_loss_status(
3219                         link,
3220                         &hpd_irq_dpcd_data)) {
3221                 /* Connectivity log: link loss */
3222                 CONN_DATA_LINK_LOSS(link,
3223                                         hpd_irq_dpcd_data.raw,
3224                                         sizeof(hpd_irq_dpcd_data),
3225                                         "Status: ");
3226
3227                 for (i = 0; i < MAX_PIPES; i++) {
3228                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3229                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3230                                 break;
3231                 }
3232
3233                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3234                         return false;
3235
3236
3237                 for (i = 0; i < MAX_PIPES; i++) {
3238                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3239                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3240                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3241                                 core_link_disable_stream(pipe_ctx);
3242                 }
3243
3244                 for (i = 0; i < MAX_PIPES; i++) {
3245                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3246                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3247                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3248                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3249                 }
3250
3251                 status = false;
3252                 if (out_link_loss)
3253                         *out_link_loss = true;
3254         }
3255
3256         if (link->type == dc_connection_sst_branch &&
3257                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3258                         != link->dpcd_sink_count)
3259                 status = true;
3260
3261         /* reasons for HPD RX:
3262          * 1. Link Loss - ie Re-train the Link
3263          * 2. MST sideband message
3264          * 3. Automated Test - ie. Internal Commit
3265          * 4. CP (copy protection) - (not interesting for DM???)
3266          * 5. DRR
3267          * 6. Downstream Port status changed
3268          * -ie. Detect - this the only one
3269          * which is interesting for DM because
3270          * it must call dc_link_detect.
3271          */
3272         return status;
3273 }
3274
3275 /*query dpcd for version and mst cap addresses*/
3276 bool is_mst_supported(struct dc_link *link)
3277 {
3278         bool mst          = false;
3279         enum dc_status st = DC_OK;
3280         union dpcd_rev rev;
3281         union mstm_cap cap;
3282
3283         if (link->preferred_training_settings.mst_enable &&
3284                 *link->preferred_training_settings.mst_enable == false) {
3285                 return false;
3286         }
3287
3288         rev.raw  = 0;
3289         cap.raw  = 0;
3290
3291         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3292                         sizeof(rev));
3293
3294         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3295
3296                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3297                                 &cap.raw, sizeof(cap));
3298                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3299                         mst = true;
3300         }
3301         return mst;
3302
3303 }
3304
3305 bool is_dp_active_dongle(const struct dc_link *link)
3306 {
3307         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3308                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3309 }
3310
3311 bool is_dp_branch_device(const struct dc_link *link)
3312 {
3313         return link->dpcd_caps.is_branch_dev;
3314 }
3315
3316 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3317 {
3318         switch (bpc) {
3319         case DOWN_STREAM_MAX_8BPC:
3320                 return 8;
3321         case DOWN_STREAM_MAX_10BPC:
3322                 return 10;
3323         case DOWN_STREAM_MAX_12BPC:
3324                 return 12;
3325         case DOWN_STREAM_MAX_16BPC:
3326                 return 16;
3327         default:
3328                 break;
3329         }
3330
3331         return -1;
3332 }
3333
3334 static void read_dp_device_vendor_id(struct dc_link *link)
3335 {
3336         struct dp_device_vendor_id dp_id;
3337
3338         /* read IEEE branch device id */
3339         core_link_read_dpcd(
3340                 link,
3341                 DP_BRANCH_OUI,
3342                 (uint8_t *)&dp_id,
3343                 sizeof(dp_id));
3344
3345         link->dpcd_caps.branch_dev_id =
3346                 (dp_id.ieee_oui[0] << 16) +
3347                 (dp_id.ieee_oui[1] << 8) +
3348                 dp_id.ieee_oui[2];
3349
3350         memmove(
3351                 link->dpcd_caps.branch_dev_name,
3352                 dp_id.ieee_device_id,
3353                 sizeof(dp_id.ieee_device_id));
3354 }
3355
3356
3357
3358 static void get_active_converter_info(
3359         uint8_t data, struct dc_link *link)
3360 {
3361         union dp_downstream_port_present ds_port = { .byte = data };
3362         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3363
3364         /* decode converter info*/
3365         if (!ds_port.fields.PORT_PRESENT) {
3366                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3367                 ddc_service_set_dongle_type(link->ddc,
3368                                 link->dpcd_caps.dongle_type);
3369                 link->dpcd_caps.is_branch_dev = false;
3370                 return;
3371         }
3372
3373         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3374         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3375
3376         switch (ds_port.fields.PORT_TYPE) {
3377         case DOWNSTREAM_VGA:
3378                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3379                 break;
3380         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3381                 /* At this point we don't know is it DVI or HDMI or DP++,
3382                  * assume DVI.*/
3383                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3384                 break;
3385         default:
3386                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3387                 break;
3388         }
3389
3390         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3391                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3392                 union dwnstream_port_caps_byte0 *port_caps =
3393                         (union dwnstream_port_caps_byte0 *)det_caps;
3394                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3395                                 det_caps, sizeof(det_caps)) == DC_OK) {
3396
3397                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3398                         /*Handle DP case as DONGLE_NONE*/
3399                         case DOWN_STREAM_DETAILED_DP:
3400                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3401                                 break;
3402                         case DOWN_STREAM_DETAILED_VGA:
3403                                 link->dpcd_caps.dongle_type =
3404                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3405                                 break;
3406                         case DOWN_STREAM_DETAILED_DVI:
3407                                 link->dpcd_caps.dongle_type =
3408                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3409                                 break;
3410                         case DOWN_STREAM_DETAILED_HDMI:
3411                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3412                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3413                                 link->dpcd_caps.dongle_type =
3414                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3415
3416                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3417                                 if (ds_port.fields.DETAILED_CAPS) {
3418
3419                                         union dwnstream_port_caps_byte3_hdmi
3420                                                 hdmi_caps = {.raw = det_caps[3] };
3421                                         union dwnstream_port_caps_byte2
3422                                                 hdmi_color_caps = {.raw = det_caps[2] };
3423                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3424                                                 det_caps[1] * 2500;
3425
3426                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3427                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3428                                         /*YCBCR capability only for HDMI case*/
3429                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3430                                                         == DOWN_STREAM_DETAILED_HDMI) {
3431                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3432                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3433                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3434                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3435                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3436                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3437                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3438                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3439                                         }
3440
3441                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3442                                                 translate_dpcd_max_bpc(
3443                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3444
3445                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3446                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3447                                 }
3448
3449                                 break;
3450                         }
3451                 }
3452         }
3453
3454         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3455
3456         {
3457                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3458
3459                 core_link_read_dpcd(
3460                         link,
3461                         DP_BRANCH_REVISION_START,
3462                         (uint8_t *)&dp_hw_fw_revision,
3463                         sizeof(dp_hw_fw_revision));
3464
3465                 link->dpcd_caps.branch_hw_revision =
3466                         dp_hw_fw_revision.ieee_hw_rev;
3467
3468                 memmove(
3469                         link->dpcd_caps.branch_fw_revision,
3470                         dp_hw_fw_revision.ieee_fw_rev,
3471                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3472         }
3473 }
3474
3475 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3476                 int length)
3477 {
3478         int retry = 0;
3479
3480         if (!link->dpcd_caps.dpcd_rev.raw) {
3481                 do {
3482                         dp_receiver_power_ctrl(link, true);
3483                         core_link_read_dpcd(link, DP_DPCD_REV,
3484                                                         dpcd_data, length);
3485                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3486                                 DP_DPCD_REV -
3487                                 DP_DPCD_REV];
3488                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3489         }
3490
3491         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3492                 switch (link->dpcd_caps.branch_dev_id) {
3493                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3494                  * all internal circuits including AUX communication preventing
3495                  * reading DPCD table and EDID (spec violation).
3496                  * Encoder will skip DP RX power down on disable_output to
3497                  * keep receiver powered all the time.*/
3498                 case DP_BRANCH_DEVICE_ID_0010FA:
3499                 case DP_BRANCH_DEVICE_ID_0080E1:
3500                 case DP_BRANCH_DEVICE_ID_00E04C:
3501                         link->wa_flags.dp_keep_receiver_powered = true;
3502                         break;
3503
3504                 /* TODO: May need work around for other dongles. */
3505                 default:
3506                         link->wa_flags.dp_keep_receiver_powered = false;
3507                         break;
3508                 }
3509         } else
3510                 link->wa_flags.dp_keep_receiver_powered = false;
3511 }
3512
3513 /* Read additional sink caps defined in source specific DPCD area
3514  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3515  */
3516 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3517 {
3518         uint8_t dpcd_data;
3519
3520         if (!link)
3521                 return false;
3522
3523         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3524                 return false;
3525
3526         link->dpcd_sink_ext_caps.raw = dpcd_data;
3527         return true;
3528 }
3529
3530 static bool retrieve_link_cap(struct dc_link *link)
3531 {
3532         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3533          * which means size 16 will be good for both of those DPCD register block reads
3534          */
3535         uint8_t dpcd_data[16];
3536         uint8_t lttpr_dpcd_data[6];
3537
3538         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3539          */
3540         uint8_t dpcd_dprx_data = '\0';
3541         uint8_t dpcd_power_state = '\0';
3542
3543         struct dp_device_vendor_id sink_id;
3544         union down_stream_port_count down_strm_port_count;
3545         union edp_configuration_cap edp_config_cap;
3546         union dp_downstream_port_present ds_port = { 0 };
3547         enum dc_status status = DC_ERROR_UNEXPECTED;
3548         uint32_t read_dpcd_retry_cnt = 3;
3549         int i;
3550         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3551         bool is_lttpr_present = false;
3552         const uint32_t post_oui_delay = 30; // 30ms
3553         bool vbios_lttpr_enable = false;
3554         bool vbios_lttpr_interop = false;
3555         struct dc_bios *bios = link->dc->ctx->dc_bios;
3556
3557         memset(dpcd_data, '\0', sizeof(dpcd_data));
3558         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3559         memset(&down_strm_port_count,
3560                 '\0', sizeof(union down_stream_port_count));
3561         memset(&edp_config_cap, '\0',
3562                 sizeof(union edp_configuration_cap));
3563
3564         /* if extended timeout is supported in hardware,
3565          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3566          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3567          */
3568         dc_link_aux_try_to_configure_timeout(link->ddc,
3569                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3570
3571         status = core_link_read_dpcd(link, DP_SET_POWER,
3572                                 &dpcd_power_state, sizeof(dpcd_power_state));
3573
3574         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3575          * section 2.3.1.2, if AUX CH may be powered down due to
3576          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3577          * signal and may need up to 1 ms before being able to reply.
3578          */
3579         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3580                 udelay(1000);
3581
3582         dpcd_set_source_specific_data(link);
3583         /* Sink may need to configure internals based on vendor, so allow some
3584          * time before proceeding with possibly vendor specific transactions
3585          */
3586         msleep(post_oui_delay);
3587
3588         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3589                 status = core_link_read_dpcd(
3590                                 link,
3591                                 DP_DPCD_REV,
3592                                 dpcd_data,
3593                                 sizeof(dpcd_data));
3594                 if (status == DC_OK)
3595                         break;
3596         }
3597
3598         if (status != DC_OK) {
3599                 dm_error("%s: Read dpcd data failed.\n", __func__);
3600                 return false;
3601         }
3602
3603         /* Query BIOS to determine if LTTPR functionality is forced on by system */
3604         if (bios->funcs->get_lttpr_caps) {
3605                 enum bp_result bp_query_result;
3606                 uint8_t is_vbios_lttpr_enable = 0;
3607
3608                 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3609                 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3610         }
3611
3612         if (bios->funcs->get_lttpr_interop) {
3613                 enum bp_result bp_query_result;
3614                 uint8_t is_vbios_interop_enabled = 0;
3615
3616                 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3617                 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3618         }
3619
3620         /*
3621          * Logic to determine LTTPR mode
3622          */
3623         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3624         if (vbios_lttpr_enable && vbios_lttpr_interop)
3625                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3626         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3627                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3628                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3629                 else
3630                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3631         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3632                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3633                         || !link->dc->caps.extended_aux_timeout_support)
3634                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3635                 else
3636                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3637         }
3638
3639         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3640                 /* By reading LTTPR capability, RX assumes that we will enable
3641                  * LTTPR extended aux timeout if LTTPR is present.
3642                  */
3643                 status = core_link_read_dpcd(
3644                                 link,
3645                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3646                                 lttpr_dpcd_data,
3647                                 sizeof(lttpr_dpcd_data));
3648
3649                 link->dpcd_caps.lttpr_caps.revision.raw =
3650                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3651                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3652
3653                 link->dpcd_caps.lttpr_caps.max_link_rate =
3654                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3655                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3656
3657                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3658                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3659                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3660
3661                 link->dpcd_caps.lttpr_caps.max_lane_count =
3662                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3663                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3664
3665                 link->dpcd_caps.lttpr_caps.mode =
3666                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3667                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3668
3669                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3670                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3671                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3672
3673                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3674                 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3675                                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
3676                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3677                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3678                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3679                 if (is_lttpr_present)
3680                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3681                 else
3682                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3683         }
3684
3685         if (!is_lttpr_present)
3686                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3687
3688
3689         {
3690                 union training_aux_rd_interval aux_rd_interval;
3691
3692                 aux_rd_interval.raw =
3693                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3694
3695                 link->dpcd_caps.ext_receiver_cap_field_present =
3696                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3697
3698                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3699                         uint8_t ext_cap_data[16];
3700
3701                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3702                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3703                                 status = core_link_read_dpcd(
3704                                 link,
3705                                 DP_DP13_DPCD_REV,
3706                                 ext_cap_data,
3707                                 sizeof(ext_cap_data));
3708                                 if (status == DC_OK) {
3709                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3710                                         break;
3711                                 }
3712                         }
3713                         if (status != DC_OK)
3714                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3715                 }
3716         }
3717
3718         link->dpcd_caps.dpcd_rev.raw =
3719                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3720
3721         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3722                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3723                         status = core_link_read_dpcd(
3724                                         link,
3725                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3726                                         &dpcd_dprx_data,
3727                                         sizeof(dpcd_dprx_data));
3728                         if (status == DC_OK)
3729                                 break;
3730                 }
3731
3732                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3733
3734                 if (status != DC_OK)
3735                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3736         }
3737
3738         else {
3739                 link->dpcd_caps.dprx_feature.raw = 0;
3740         }
3741
3742
3743         /* Error condition checking...
3744          * It is impossible for Sink to report Max Lane Count = 0.
3745          * It is possible for Sink to report Max Link Rate = 0, if it is
3746          * an eDP device that is reporting specialized link rates in the
3747          * SUPPORTED_LINK_RATE table.
3748          */
3749         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3750                 return false;
3751
3752         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3753                                  DP_DPCD_REV];
3754
3755         read_dp_device_vendor_id(link);
3756
3757         get_active_converter_info(ds_port.byte, link);
3758
3759         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3760
3761         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3762                                  DP_DPCD_REV];
3763
3764         link->dpcd_caps.allow_invalid_MSA_timing_param =
3765                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3766
3767         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3768                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3769
3770         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3771                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3772
3773         link->reported_link_cap.lane_count =
3774                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3775         link->reported_link_cap.link_rate = dpcd_data[
3776                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3777         link->reported_link_cap.link_spread =
3778                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3779                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3780
3781         edp_config_cap.raw = dpcd_data[
3782                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3783         link->dpcd_caps.panel_mode_edp =
3784                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3785         link->dpcd_caps.dpcd_display_control_capable =
3786                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3787
3788         link->test_pattern_enabled = false;
3789         link->compliance_test_state.raw = 0;
3790
3791         /* read sink count */
3792         core_link_read_dpcd(link,
3793                         DP_SINK_COUNT,
3794                         &link->dpcd_caps.sink_count.raw,
3795                         sizeof(link->dpcd_caps.sink_count.raw));
3796
3797         /* read sink ieee oui */
3798         core_link_read_dpcd(link,
3799                         DP_SINK_OUI,
3800                         (uint8_t *)(&sink_id),
3801                         sizeof(sink_id));
3802
3803         link->dpcd_caps.sink_dev_id =
3804                         (sink_id.ieee_oui[0] << 16) +
3805                         (sink_id.ieee_oui[1] << 8) +
3806                         (sink_id.ieee_oui[2]);
3807
3808         memmove(
3809                 link->dpcd_caps.sink_dev_id_str,
3810                 sink_id.ieee_device_id,
3811                 sizeof(sink_id.ieee_device_id));
3812
3813         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3814         {
3815                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3816
3817                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3818                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3819                             sizeof(str_mbp_2017))) {
3820                         link->reported_link_cap.link_rate = 0x0c;
3821                 }
3822         }
3823
3824         core_link_read_dpcd(
3825                 link,
3826                 DP_SINK_HW_REVISION_START,
3827                 (uint8_t *)&dp_hw_fw_revision,
3828                 sizeof(dp_hw_fw_revision));
3829
3830         link->dpcd_caps.sink_hw_revision =
3831                 dp_hw_fw_revision.ieee_hw_rev;
3832
3833         memmove(
3834                 link->dpcd_caps.sink_fw_revision,
3835                 dp_hw_fw_revision.ieee_fw_rev,
3836                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3837
3838         memset(&link->dpcd_caps.dsc_caps, '\0',
3839                         sizeof(link->dpcd_caps.dsc_caps));
3840         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3841         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3842         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3843                 status = core_link_read_dpcd(
3844                                 link,
3845                                 DP_FEC_CAPABILITY,
3846                                 &link->dpcd_caps.fec_cap.raw,
3847                                 sizeof(link->dpcd_caps.fec_cap.raw));
3848                 status = core_link_read_dpcd(
3849                                 link,
3850                                 DP_DSC_SUPPORT,
3851                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3852                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3853                 status = core_link_read_dpcd(
3854                                 link,
3855                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3856                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3857                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3858         }
3859
3860         if (!dpcd_read_sink_ext_caps(link))
3861                 link->dpcd_sink_ext_caps.raw = 0;
3862
3863         /* Connectivity log: detection */
3864         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3865
3866         return true;
3867 }
3868
3869 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3870 {
3871         uint8_t dpcd_data[16];
3872         uint32_t read_dpcd_retry_cnt = 3;
3873         enum dc_status status = DC_ERROR_UNEXPECTED;
3874         union dp_downstream_port_present ds_port = { 0 };
3875         union down_stream_port_count down_strm_port_count;
3876         union edp_configuration_cap edp_config_cap;
3877
3878         int i;
3879
3880         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3881                 status = core_link_read_dpcd(
3882                                 link,
3883                                 DP_DPCD_REV,
3884                                 dpcd_data,
3885                                 sizeof(dpcd_data));
3886                 if (status == DC_OK)
3887                         break;
3888         }
3889
3890         link->dpcd_caps.dpcd_rev.raw =
3891                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3892
3893         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3894                 return false;
3895
3896         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3897                         DP_DPCD_REV];
3898
3899         get_active_converter_info(ds_port.byte, link);
3900
3901         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3902                         DP_DPCD_REV];
3903
3904         link->dpcd_caps.allow_invalid_MSA_timing_param =
3905                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3906
3907         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3908                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3909
3910         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3911                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3912
3913         link->reported_link_cap.lane_count =
3914                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3915         link->reported_link_cap.link_rate = dpcd_data[
3916                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3917         link->reported_link_cap.link_spread =
3918                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3919                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3920
3921         edp_config_cap.raw = dpcd_data[
3922                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3923         link->dpcd_caps.panel_mode_edp =
3924                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3925         link->dpcd_caps.dpcd_display_control_capable =
3926                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3927
3928         return true;
3929 }
3930
3931 bool detect_dp_sink_caps(struct dc_link *link)
3932 {
3933         return retrieve_link_cap(link);
3934
3935         /* dc init_hw has power encoder using default
3936          * signal for connector. For native DP, no
3937          * need to power up encoder again. If not native
3938          * DP, hw_init may need check signal or power up
3939          * encoder here.
3940          */
3941         /* TODO save sink caps in link->sink */
3942 }
3943
3944 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3945 {
3946         enum dc_link_rate link_rate;
3947         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3948         switch (link_rate_in_khz) {
3949         case 1620000:
3950                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
3951                 break;
3952         case 2160000:
3953                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
3954                 break;
3955         case 2430000:
3956                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
3957                 break;
3958         case 2700000:
3959                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
3960                 break;
3961         case 3240000:
3962                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
3963                 break;
3964         case 4320000:
3965                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
3966                 break;
3967         case 5400000:
3968                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
3969                 break;
3970         case 8100000:
3971                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
3972                 break;
3973         default:
3974                 link_rate = LINK_RATE_UNKNOWN;
3975                 break;
3976         }
3977         return link_rate;
3978 }
3979
3980 void detect_edp_sink_caps(struct dc_link *link)
3981 {
3982         uint8_t supported_link_rates[16];
3983         uint32_t entry;
3984         uint32_t link_rate_in_khz;
3985         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3986         uint8_t backlight_adj_cap;
3987
3988         retrieve_link_cap(link);
3989         link->dpcd_caps.edp_supported_link_rates_count = 0;
3990         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3991
3992         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3993                         (link->dc->debug.optimize_edp_link_rate ||
3994                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3995                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3996                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3997                                                         supported_link_rates, sizeof(supported_link_rates));
3998
3999                 for (entry = 0; entry < 16; entry += 2) {
4000                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4001                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4002                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4003                                                                                 supported_link_rates[entry]) * 200;
4004
4005                         if (link_rate_in_khz != 0) {
4006                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4007                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4008                                 link->dpcd_caps.edp_supported_link_rates_count++;
4009
4010                                 if (link->reported_link_cap.link_rate < link_rate)
4011                                         link->reported_link_cap.link_rate = link_rate;
4012                         }
4013                 }
4014         }
4015         link->verified_link_cap = link->reported_link_cap;
4016
4017         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4018                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4019
4020         link->dpcd_caps.dynamic_backlight_capable_edp =
4021                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4022
4023         dc_link_set_default_brightness_aux(link);
4024 }
4025
4026 void dc_link_dp_enable_hpd(const struct dc_link *link)
4027 {
4028         struct link_encoder *encoder = link->link_enc;
4029
4030         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4031                 encoder->funcs->enable_hpd(encoder);
4032 }
4033
4034 void dc_link_dp_disable_hpd(const struct dc_link *link)
4035 {
4036         struct link_encoder *encoder = link->link_enc;
4037
4038         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4039                 encoder->funcs->disable_hpd(encoder);
4040 }
4041
4042 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4043 {
4044         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4045                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4046                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4047                 return true;
4048         else
4049                 return false;
4050 }
4051
4052 static void set_crtc_test_pattern(struct dc_link *link,
4053                                 struct pipe_ctx *pipe_ctx,
4054                                 enum dp_test_pattern test_pattern,
4055                                 enum dp_test_pattern_color_space test_pattern_color_space)
4056 {
4057         enum controller_dp_test_pattern controller_test_pattern;
4058         enum dc_color_depth color_depth = pipe_ctx->
4059                 stream->timing.display_color_depth;
4060         struct bit_depth_reduction_params params;
4061         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4062         int width = pipe_ctx->stream->timing.h_addressable +
4063                 pipe_ctx->stream->timing.h_border_left +
4064                 pipe_ctx->stream->timing.h_border_right;
4065         int height = pipe_ctx->stream->timing.v_addressable +
4066                 pipe_ctx->stream->timing.v_border_bottom +
4067                 pipe_ctx->stream->timing.v_border_top;
4068
4069         memset(&params, 0, sizeof(params));
4070
4071         switch (test_pattern) {
4072         case DP_TEST_PATTERN_COLOR_SQUARES:
4073                 controller_test_pattern =
4074                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4075         break;
4076         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4077                 controller_test_pattern =
4078                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4079         break;
4080         case DP_TEST_PATTERN_VERTICAL_BARS:
4081                 controller_test_pattern =
4082                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4083         break;
4084         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4085                 controller_test_pattern =
4086                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4087         break;
4088         case DP_TEST_PATTERN_COLOR_RAMP:
4089                 controller_test_pattern =
4090                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4091         break;
4092         default:
4093                 controller_test_pattern =
4094                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4095         break;
4096         }
4097
4098         switch (test_pattern) {
4099         case DP_TEST_PATTERN_COLOR_SQUARES:
4100         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4101         case DP_TEST_PATTERN_VERTICAL_BARS:
4102         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4103         case DP_TEST_PATTERN_COLOR_RAMP:
4104         {
4105                 /* disable bit depth reduction */
4106                 pipe_ctx->stream->bit_depth_params = params;
4107                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4108                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4109                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4110                                 controller_test_pattern, color_depth);
4111                 else if (link->dc->hwss.set_disp_pattern_generator) {
4112                         struct pipe_ctx *odm_pipe;
4113                         enum controller_dp_color_space controller_color_space;
4114                         int opp_cnt = 1;
4115                         int offset = 0;
4116                         int dpg_width = width;
4117
4118                         switch (test_pattern_color_space) {
4119                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4120                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4121                                 break;
4122                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4123                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4124                                 break;
4125                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4126                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4127                                 break;
4128                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4129                         default:
4130                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4131                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4132                                 ASSERT(0);
4133                                 break;
4134                         }
4135
4136                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4137                                 opp_cnt++;
4138                         dpg_width = width / opp_cnt;
4139                         offset = dpg_width;
4140
4141                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4142                                         pipe_ctx,
4143                                         controller_test_pattern,
4144                                         controller_color_space,
4145                                         color_depth,
4146                                         NULL,
4147                                         dpg_width,
4148                                         height,
4149                                         0);
4150
4151                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4152                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4153
4154                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4155                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4156                                                 odm_pipe,
4157                                                 controller_test_pattern,
4158                                                 controller_color_space,
4159                                                 color_depth,
4160                                                 NULL,
4161                                                 dpg_width,
4162                                                 height,
4163                                                 offset);
4164                                 offset += offset;
4165                         }
4166                 }
4167         }
4168         break;
4169         case DP_TEST_PATTERN_VIDEO_MODE:
4170         {
4171                 /* restore bitdepth reduction */
4172                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4173                 pipe_ctx->stream->bit_depth_params = params;
4174                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4175                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4176                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4177                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4178                                 color_depth);
4179                 else if (link->dc->hwss.set_disp_pattern_generator) {
4180                         struct pipe_ctx *odm_pipe;
4181                         int opp_cnt = 1;
4182                         int dpg_width = width;
4183
4184                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4185                                 opp_cnt++;
4186
4187                         dpg_width = width / opp_cnt;
4188                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4189                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4190
4191                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4192                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4193                                                 odm_pipe,
4194                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4195                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4196                                                 color_depth,
4197                                                 NULL,
4198                                                 dpg_width,
4199                                                 height,
4200                                                 0);
4201                         }
4202                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4203                                         pipe_ctx,
4204                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4205                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4206                                         color_depth,
4207                                         NULL,
4208                                         dpg_width,
4209                                         height,
4210                                         0);
4211                 }
4212         }
4213         break;
4214
4215         default:
4216         break;
4217         }
4218 }
4219
4220 bool dc_link_dp_set_test_pattern(
4221         struct dc_link *link,
4222         enum dp_test_pattern test_pattern,
4223         enum dp_test_pattern_color_space test_pattern_color_space,
4224         const struct link_training_settings *p_link_settings,
4225         const unsigned char *p_custom_pattern,
4226         unsigned int cust_pattern_size)
4227 {
4228         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4229         struct pipe_ctx *pipe_ctx = NULL;
4230         unsigned int lane;
4231         unsigned int i;
4232         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4233         union dpcd_training_pattern training_pattern;
4234         enum dpcd_phy_test_patterns pattern;
4235
4236         memset(&training_pattern, 0, sizeof(training_pattern));
4237
4238         for (i = 0; i < MAX_PIPES; i++) {
4239                 if (pipes[i].stream == NULL)
4240                         continue;
4241
4242                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4243                         pipe_ctx = &pipes[i];
4244                         break;
4245                 }
4246         }
4247
4248         if (pipe_ctx == NULL)
4249                 return false;
4250
4251         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4252         if (link->test_pattern_enabled && test_pattern ==
4253                         DP_TEST_PATTERN_VIDEO_MODE) {
4254                 /* Set CRTC Test Pattern */
4255                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4256                 dp_set_hw_test_pattern(link, test_pattern,
4257                                 (uint8_t *)p_custom_pattern,
4258                                 (uint32_t)cust_pattern_size);
4259
4260                 /* Unblank Stream */
4261                 link->dc->hwss.unblank_stream(
4262                         pipe_ctx,
4263                         &link->verified_link_cap);
4264                 /* TODO:m_pHwss->MuteAudioEndpoint
4265                  * (pPathMode->pDisplayPath, false);
4266                  */
4267
4268                 /* Reset Test Pattern state */
4269                 link->test_pattern_enabled = false;
4270
4271                 return true;
4272         }
4273
4274         /* Check for PHY Test Patterns */
4275         if (is_dp_phy_pattern(test_pattern)) {
4276                 /* Set DPCD Lane Settings before running test pattern */
4277                 if (p_link_settings != NULL) {
4278                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4279                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4280                 }
4281
4282                 /* Blank stream if running test pattern */
4283                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4284                         /*TODO:
4285                          * m_pHwss->
4286                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4287                          */
4288                         /* Blank stream */
4289                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4290                 }
4291
4292                 dp_set_hw_test_pattern(link, test_pattern,
4293                                 (uint8_t *)p_custom_pattern,
4294                                 (uint32_t)cust_pattern_size);
4295
4296                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4297                         /* Set Test Pattern state */
4298                         link->test_pattern_enabled = true;
4299                         if (p_link_settings != NULL)
4300                                 dpcd_set_link_settings(link,
4301                                                 p_link_settings);
4302                 }
4303
4304                 switch (test_pattern) {
4305                 case DP_TEST_PATTERN_VIDEO_MODE:
4306                         pattern = PHY_TEST_PATTERN_NONE;
4307                         break;
4308                 case DP_TEST_PATTERN_D102:
4309                         pattern = PHY_TEST_PATTERN_D10_2;
4310                         break;
4311                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4312                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4313                         break;
4314                 case DP_TEST_PATTERN_PRBS7:
4315                         pattern = PHY_TEST_PATTERN_PRBS7;
4316                         break;
4317                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4318                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4319                         break;
4320                 case DP_TEST_PATTERN_CP2520_1:
4321                         pattern = PHY_TEST_PATTERN_CP2520_1;
4322                         break;
4323                 case DP_TEST_PATTERN_CP2520_2:
4324                         pattern = PHY_TEST_PATTERN_CP2520_2;
4325                         break;
4326                 case DP_TEST_PATTERN_CP2520_3:
4327                         pattern = PHY_TEST_PATTERN_CP2520_3;
4328                         break;
4329                 default:
4330                         return false;
4331                 }
4332
4333                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4334                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4335                         return false;
4336
4337                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4338                         /* tell receiver that we are sending qualification
4339                          * pattern DP 1.2 or later - DP receiver's link quality
4340                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4341                          * register (0x10B~0x10E)\
4342                          */
4343                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4344                                 link_qual_pattern[lane] =
4345                                                 (unsigned char)(pattern);
4346
4347                         core_link_write_dpcd(link,
4348                                         DP_LINK_QUAL_LANE0_SET,
4349                                         link_qual_pattern,
4350                                         sizeof(link_qual_pattern));
4351                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4352                            link->dpcd_caps.dpcd_rev.raw == 0) {
4353                         /* tell receiver that we are sending qualification
4354                          * pattern DP 1.1a or earlier - DP receiver's link
4355                          * quality pattern is set using
4356                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4357                          * register (0x102). We will use v_1.3 when we are
4358                          * setting test pattern for DP 1.1.
4359                          */
4360                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4361                                             &training_pattern.raw,
4362                                             sizeof(training_pattern));
4363                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4364                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4365                                              &training_pattern.raw,
4366                                              sizeof(training_pattern));
4367                 }
4368         } else {
4369                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4370
4371                 switch (test_pattern_color_space) {
4372                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4373                         color_space = COLOR_SPACE_SRGB;
4374                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4375                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4376                         break;
4377
4378                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4379                         color_space = COLOR_SPACE_YCBCR601;
4380                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4381                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4382                         break;
4383                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4384                         color_space = COLOR_SPACE_YCBCR709;
4385                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4386                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4387                         break;
4388                 default:
4389                         break;
4390                 }
4391
4392                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4393                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4394                                 union dmub_hw_lock_flags hw_locks = { 0 };
4395                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4396
4397                                 hw_locks.bits.lock_dig = 1;
4398                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4399
4400                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4401                                                         true,
4402                                                         &hw_locks,
4403                                                         &inst_flags);
4404                         } else
4405                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4406                                                 pipe_ctx->stream_res.tg);
4407                 }
4408
4409                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4410                 /* update MSA to requested color space */
4411                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4412                                 &pipe_ctx->stream->timing,
4413                                 color_space,
4414                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4415                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4416
4417                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4418                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4419                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4420                         else
4421                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4422                         resource_build_info_frame(pipe_ctx);
4423                         link->dc->hwss.update_info_frame(pipe_ctx);
4424                 }
4425
4426                 /* CRTC Patterns */
4427                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4428                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4429                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4430                                 CRTC_STATE_VACTIVE);
4431                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4432                                 CRTC_STATE_VBLANK);
4433                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4434                                 CRTC_STATE_VACTIVE);
4435
4436                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4437                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4438                                 union dmub_hw_lock_flags hw_locks = { 0 };
4439                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4440
4441                                 hw_locks.bits.lock_dig = 1;
4442                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4443
4444                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4445                                                         false,
4446                                                         &hw_locks,
4447                                                         &inst_flags);
4448                         } else
4449                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4450                                                 pipe_ctx->stream_res.tg);
4451                 }
4452
4453                 /* Set Test Pattern state */
4454                 link->test_pattern_enabled = true;
4455         }
4456
4457         return true;
4458 }
4459
4460 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4461 {
4462         unsigned char mstmCntl;
4463
4464         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4465         if (enable)
4466                 mstmCntl |= DP_MST_EN;
4467         else
4468                 mstmCntl &= (~DP_MST_EN);
4469
4470         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4471 }
4472
4473 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4474 {
4475         union dpcd_edp_config edp_config_set;
4476         bool panel_mode_edp = false;
4477
4478         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4479
4480         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4481
4482                 switch (panel_mode) {
4483                 case DP_PANEL_MODE_EDP:
4484                 case DP_PANEL_MODE_SPECIAL:
4485                         panel_mode_edp = true;
4486                         break;
4487
4488                 default:
4489                                 break;
4490                 }
4491
4492                 /*set edp panel mode in receiver*/
4493                 core_link_read_dpcd(
4494                         link,
4495                         DP_EDP_CONFIGURATION_SET,
4496                         &edp_config_set.raw,
4497                         sizeof(edp_config_set.raw));
4498
4499                 if (edp_config_set.bits.PANEL_MODE_EDP
4500                         != panel_mode_edp) {
4501                         enum dc_status result;
4502
4503                         edp_config_set.bits.PANEL_MODE_EDP =
4504                         panel_mode_edp;
4505                         result = core_link_write_dpcd(
4506                                 link,
4507                                 DP_EDP_CONFIGURATION_SET,
4508                                 &edp_config_set.raw,
4509                                 sizeof(edp_config_set.raw));
4510
4511                         ASSERT(result == DC_OK);
4512                 }
4513         }
4514         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4515                  "eDP panel mode enabled: %d \n",
4516                  link->link_index,
4517                  link->dpcd_caps.panel_mode_edp,
4518                  panel_mode_edp);
4519 }
4520
4521 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4522 {
4523         /* We need to explicitly check that connector
4524          * is not DP. Some Travis_VGA get reported
4525          * by video bios as DP.
4526          */
4527         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4528
4529                 switch (link->dpcd_caps.branch_dev_id) {
4530                 case DP_BRANCH_DEVICE_ID_0022B9:
4531                         /* alternate scrambler reset is required for Travis
4532                          * for the case when external chip does not
4533                          * provide sink device id, alternate scrambler
4534                          * scheme will  be overriden later by querying
4535                          * Encoder features
4536                          */
4537                         if (strncmp(
4538                                 link->dpcd_caps.branch_dev_name,
4539                                 DP_VGA_LVDS_CONVERTER_ID_2,
4540                                 sizeof(
4541                                 link->dpcd_caps.
4542                                 branch_dev_name)) == 0) {
4543                                         return DP_PANEL_MODE_SPECIAL;
4544                         }
4545                         break;
4546                 case DP_BRANCH_DEVICE_ID_00001A:
4547                         /* alternate scrambler reset is required for Travis
4548                          * for the case when external chip does not provide
4549                          * sink device id, alternate scrambler scheme will
4550                          * be overriden later by querying Encoder feature
4551                          */
4552                         if (strncmp(link->dpcd_caps.branch_dev_name,
4553                                 DP_VGA_LVDS_CONVERTER_ID_3,
4554                                 sizeof(
4555                                 link->dpcd_caps.
4556                                 branch_dev_name)) == 0) {
4557                                         return DP_PANEL_MODE_SPECIAL;
4558                         }
4559                         break;
4560                 default:
4561                         break;
4562                 }
4563         }
4564
4565         if (link->dpcd_caps.panel_mode_edp) {
4566                 return DP_PANEL_MODE_EDP;
4567         }
4568
4569         return DP_PANEL_MODE_DEFAULT;
4570 }
4571
4572 void dp_set_fec_ready(struct dc_link *link, bool ready)
4573 {
4574         /* FEC has to be "set ready" before the link training.
4575          * The policy is to always train with FEC
4576          * if the sink supports it and leave it enabled on link.
4577          * If FEC is not supported, disable it.
4578          */
4579         struct link_encoder *link_enc = link->link_enc;
4580         uint8_t fec_config = 0;
4581
4582         if (!dc_link_should_enable_fec(link))
4583                 return;
4584
4585         if (link_enc->funcs->fec_set_ready &&
4586                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4587                 if (ready) {
4588                         fec_config = 1;
4589                         if (core_link_write_dpcd(link,
4590                                         DP_FEC_CONFIGURATION,
4591                                         &fec_config,
4592                                         sizeof(fec_config)) == DC_OK) {
4593                                 link_enc->funcs->fec_set_ready(link_enc, true);
4594                                 link->fec_state = dc_link_fec_ready;
4595                         } else {
4596                                 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4597                                 link->fec_state = dc_link_fec_not_ready;
4598                                 dm_error("dpcd write failed to set fec_ready");
4599                         }
4600                 } else if (link->fec_state == dc_link_fec_ready) {
4601                         fec_config = 0;
4602                         core_link_write_dpcd(link,
4603                                         DP_FEC_CONFIGURATION,
4604                                         &fec_config,
4605                                         sizeof(fec_config));
4606                         link->link_enc->funcs->fec_set_ready(
4607                                         link->link_enc, false);
4608                         link->fec_state = dc_link_fec_not_ready;
4609                 }
4610         }
4611 }
4612
4613 void dp_set_fec_enable(struct dc_link *link, bool enable)
4614 {
4615         struct link_encoder *link_enc = link->link_enc;
4616
4617         if (!dc_link_should_enable_fec(link))
4618                 return;
4619
4620         if (link_enc->funcs->fec_set_enable &&
4621                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4622                 if (link->fec_state == dc_link_fec_ready && enable) {
4623                         /* Accord to DP spec, FEC enable sequence can first
4624                          * be transmitted anytime after 1000 LL codes have
4625                          * been transmitted on the link after link training
4626                          * completion. Using 1 lane RBR should have the maximum
4627                          * time for transmitting 1000 LL codes which is 6.173 us.
4628                          * So use 7 microseconds delay instead.
4629                          */
4630                         udelay(7);
4631                         link_enc->funcs->fec_set_enable(link_enc, true);
4632                         link->fec_state = dc_link_fec_enabled;
4633                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4634                         link_enc->funcs->fec_set_enable(link_enc, false);
4635                         link->fec_state = dc_link_fec_ready;
4636                 }
4637         }
4638 }
4639
4640 void dpcd_set_source_specific_data(struct dc_link *link)
4641 {
4642         if (!link->dc->vendor_signature.is_valid) {
4643                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4644                 struct dpcd_amd_signature amd_signature = {0};
4645                 struct dpcd_amd_device_id amd_device_id = {0};
4646
4647                 amd_device_id.device_id_byte1 =
4648                                 (uint8_t)(link->ctx->asic_id.chip_id);
4649                 amd_device_id.device_id_byte2 =
4650                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4651                 amd_device_id.dce_version =
4652                                 (uint8_t)(link->ctx->dce_version);
4653                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4654                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4655
4656                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4657                                 (uint8_t *)(&amd_signature),
4658                                 sizeof(amd_signature));
4659
4660                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4661                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4662                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4663
4664                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4665                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4666                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4667
4668                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4669                                 (uint8_t *)(&amd_signature),
4670                                 sizeof(amd_signature));
4671                 }
4672
4673                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4674                                 (uint8_t *)(&amd_device_id),
4675                                 sizeof(amd_device_id));
4676
4677                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4678                         link->dc->caps.min_horizontal_blanking_period != 0) {
4679
4680                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4681
4682                         result_write_min_hblank = core_link_write_dpcd(link,
4683                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4684                                 sizeof(hblank_size));
4685                 }
4686                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4687                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4688                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4689                                                         result_write_min_hblank,
4690                                                         link->link_index,
4691                                                         link->ctx->dce_version,
4692                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4693                                                         link->dc->caps.min_horizontal_blanking_period,
4694                                                         link->dpcd_caps.branch_dev_id,
4695                                                         link->dpcd_caps.branch_dev_name[0],
4696                                                         link->dpcd_caps.branch_dev_name[1],
4697                                                         link->dpcd_caps.branch_dev_name[2],
4698                                                         link->dpcd_caps.branch_dev_name[3],
4699                                                         link->dpcd_caps.branch_dev_name[4],
4700                                                         link->dpcd_caps.branch_dev_name[5]);
4701         } else {
4702                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4703                                 link->dc->vendor_signature.data.raw,
4704                                 sizeof(link->dc->vendor_signature.data.raw));
4705         }
4706 }
4707
4708 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4709                 bool isHDR,
4710                 uint32_t backlight_millinits,
4711                 uint32_t transition_time_in_ms)
4712 {
4713         struct dpcd_source_backlight_set dpcd_backlight_set;
4714         uint8_t backlight_control = isHDR ? 1 : 0;
4715
4716         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4717                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4718                 return false;
4719
4720         // OLEDs have no PWM, they can only use AUX
4721         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4722                 backlight_control = 1;
4723
4724         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4725         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4726
4727
4728         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4729                         (uint8_t *)(&dpcd_backlight_set),
4730                         sizeof(dpcd_backlight_set)) != DC_OK)
4731                 return false;
4732
4733         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4734                         &backlight_control, 1) != DC_OK)
4735                 return false;
4736
4737         return true;
4738 }
4739
4740 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4741                 uint32_t *backlight_millinits_avg,
4742                 uint32_t *backlight_millinits_peak)
4743 {
4744         union dpcd_source_backlight_get dpcd_backlight_get;
4745
4746         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4747
4748         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4749                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4750                 return false;
4751
4752         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4753                         dpcd_backlight_get.raw,
4754                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4755                 return false;
4756
4757         *backlight_millinits_avg =
4758                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4759         *backlight_millinits_peak =
4760                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4761
4762         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4763         if (*backlight_millinits_avg == 0 ||
4764                         *backlight_millinits_avg > *backlight_millinits_peak)
4765                 return false;
4766
4767         return true;
4768 }
4769
4770 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4771 {
4772         uint8_t backlight_enable = enable ? 1 : 0;
4773
4774         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4775                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4776                 return false;
4777
4778         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4779                 &backlight_enable, 1) != DC_OK)
4780                 return false;
4781
4782         return true;
4783 }
4784
4785 // we read default from 0x320 because we expect BIOS wrote it there
4786 // regular get_backlight_nit reads from panel set at 0x326
4787 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4788 {
4789         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4790                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4791                 return false;
4792
4793         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4794                 (uint8_t *) backlight_millinits,
4795                 sizeof(uint32_t)) != DC_OK)
4796                 return false;
4797
4798         return true;
4799 }
4800
4801 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4802 {
4803         uint32_t default_backlight;
4804
4805         if (link &&
4806                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4807                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4808                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4809                         default_backlight = 150000;
4810                 // if < 5 nits or > 5000, it might be wrong readback
4811                 if (default_backlight < 5000 || default_backlight > 5000000)
4812                         default_backlight = 150000; //
4813
4814                 return dc_link_set_backlight_level_nits(link, true,
4815                                 default_backlight, 0);
4816         }
4817         return false;
4818 }
4819
4820 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4821 {
4822         struct dc_link_settings link_setting;
4823         uint8_t link_bw_set;
4824         uint8_t link_rate_set;
4825         uint32_t req_bw;
4826         union lane_count_set lane_count_set = { {0} };
4827
4828         ASSERT(link || crtc_timing); // invalid input
4829
4830         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4831                         !link->dc->debug.optimize_edp_link_rate)
4832                 return false;
4833
4834
4835         // Read DPCD 00100h to find if standard link rates are set
4836         core_link_read_dpcd(link, DP_LINK_BW_SET,
4837                                 &link_bw_set, sizeof(link_bw_set));
4838
4839         if (link_bw_set) {
4840                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4841                 return true;
4842         }
4843
4844         // Read DPCD 00115h to find the edp link rate set used
4845         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4846                             &link_rate_set, sizeof(link_rate_set));
4847
4848         // Read DPCD 00101h to find out the number of lanes currently set
4849         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4850                                 &lane_count_set.raw, sizeof(lane_count_set));
4851
4852         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4853
4854         decide_edp_link_settings(link, &link_setting, req_bw);
4855
4856         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4857                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4858                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4859                 return true;
4860         }
4861
4862         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4863         return false;
4864 }
4865
4866 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4867 {
4868         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4869                         (link_settings->link_rate <= LINK_RATE_HIGH3))
4870                 return DP_8b_10b_ENCODING;
4871         return DP_UNKNOWN_ENCODING;
4872 }
4873